X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=src%2Fedu%2Fberkeley%2Ffleet%2Ffpga%2FFpgaShip.java;h=072aae45196f64e00974a552c1c042f5e0e43d9a;hb=75c6a5bd47f04b052a57e5ef1f5d1fe64ada7d9e;hp=332970ea19bdbd0e7a0b433684ccb1e9beecee6b;hpb=682bd33874c48bf8d20225fbbffa3a7b5c38d059;p=fleet.git

diff --git a/src/edu/berkeley/fleet/fpga/FpgaShip.java b/src/edu/berkeley/fleet/fpga/FpgaShip.java
index 332970e..072aae4 100644
--- a/src/edu/berkeley/fleet/fpga/FpgaShip.java
+++ b/src/edu/berkeley/fleet/fpga/FpgaShip.java
@@ -12,19 +12,23 @@ public class FpgaShip extends FleetTwoShip {
     private Module module;
     private Module.InstantiatedModule instance;
     private LinkedHashMap<String,FpgaDock> ports = new LinkedHashMap<String,FpgaDock>();
+    LinkedHashMap<String,Module.SourcePort> docklessPorts = new LinkedHashMap<String,Module.SourcePort>();
 
     /** You should instantiate a bunch of Inboxes and Outboxes in your constructor */
     public FpgaShip(Fpga fleet, ShipDescription sd) {
         super(fleet, sd);
         this.module = new Module(getType().toLowerCase());
         this.instance = new Module.InstantiatedModule(fleet.getVerilogModule(), module);
-        for(DockDescription sdbb : sd) {
-            if (sdbb.isInputDock()) module.createInputPort(sdbb.getName(), getFleet().getWordWidth()+1);
-            else                module.createOutputPort(sdbb.getName(), getFleet().getWordWidth()+1, "");
-            ports.put(sdbb.getName(), new FpgaDock(this, sdbb));
+        for(DockDescription sdbb : sd.ports()) {
+            if (sdbb.isDockless()) {
+                module.createOutputPort(sdbb.getName(), fleet.WIDTH_PACKET);
+                docklessPorts.put(sdbb.getName(), instance.getOutputPort(sdbb.getName()));
+            } else {
+                if (sdbb.isInputDock()) module.createInputPort(sdbb.getName(), getFleet().getWordWidth()+1);
+                else                    module.createOutputPort(sdbb.getName(), getFleet().getWordWidth()+1);
+                ports.put(sdbb.getName(), new FpgaDock(this, sdbb));
+            }
         }
-        if (getType().toLowerCase().equals("debug"))
-            module.createOutputPort("debug_out", getFleet().getWordWidth(), "");
         for(PercolatedPort pp : sd.percolatedPorts)
             this.module.percolatedPorts.add(pp);
     }