have break signal flush input/output fifos
authoradam <adam@megacz.com>
Mon, 11 Feb 2008 13:07:41 +0000 (14:07 +0100)
committeradam <adam@megacz.com>
Mon, 11 Feb 2008 13:07:41 +0000 (14:07 +0100)
commit0ceebe5773c9552152f7686f9529f2b0eb5e1846
tree5d16519ff15c90b932802c7e437fd67becf98fa5
parent3becc5182ccad8ed38ce1a96dfe4807f3e6c720a
have break signal flush input/output fifos
src/edu/berkeley/fleet/fpga/main.v
src/edu/berkeley/fleet/fpga/sasc_fifo4.v
src/edu/berkeley/fleet/fpga/sasc_top.v