add additional masterClear() code for Verilog simulations
authorAdam Megacz <adam.megacz@sun.com>
Mon, 20 Apr 2009 22:26:22 +0000 (22:26 +0000)
committerAdam Megacz <adam.megacz@sun.com>
Mon, 20 Apr 2009 22:26:22 +0000 (22:26 +0000)
commit55673a7abfb1513b501a96e3ec489eaa72a0b805
treea88b0110bd00c4f004dbfdaca0546fa4c2f067b4
parent98d72439f08da504be879152a3e58771fe1b0e07
add additional masterClear() code for Verilog simulations
testCode/com/sun/vlsi/chips/marina/test/Marina.java