added code to implement REVERSE_LATENCY using srl16
authormegacz <adam@megacz.com>
Thu, 26 Feb 2009 23:02:07 +0000 (15:02 -0800)
committermegacz <adam@megacz.com>
Thu, 26 Feb 2009 23:02:07 +0000 (15:02 -0800)
commit5c8f4a2a8fbf62f3780ae1aa1035c0b51ad6d111
treea5ce878215195b9ce1e612b0695de11508eafac5
parent3f0c967c3d51ba37c7496c948321a502e9b3259e
added code to implement REVERSE_LATENCY using srl16
src/edu/berkeley/fleet/fpga/verilog/Verilog.java