use getReq()/getAck() in isFull()
authormegacz <adam@megacz.com>
Thu, 26 Feb 2009 22:00:55 +0000 (14:00 -0800)
committermegacz <adam@megacz.com>
Thu, 26 Feb 2009 22:00:55 +0000 (14:00 -0800)
commit6b8f4312934b0e9ffa14da21331e737cfc251564
tree8f12a1c22fb35edc00630fe4dcf91f64f2d85729
parent1b6b3c57aae3baeadd8251e61e767e58f93ec486
use getReq()/getAck() in isFull()
src/edu/berkeley/fleet/fpga/verilog/Verilog.java