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(parent: 3516d1f) | patch
move to ml505, import Greg\'s memory controller
authormegacz <adam@megacz.com>
Tue, 30 Dec 2008 01:47:51 +0000 (17:47 -0800)
committermegacz <adam@megacz.com>
Tue, 30 Dec 2008 01:47:51 +0000 (17:47 -0800)
commitae942d8f10fe85af7b22221952c70bf919a72232
tree8bf64b2b03a4b0d6dcf8e5cf80d1619be57d36a4tree | snapshot
parent3516d1f4ad38ecc44a6d12b8035d2804f9f18fb0commit | diff
move to ml505, import Greg\'s memory controller
31 files changed:
Makefile diff | blob | history
misc/program.sh diff | blob | history
ships/DDR2.ship [new file with mode: 0644] blob
ships/Debug.ship diff | blob | history
src/edu/berkeley/fleet/fpga/greg/Const.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/DDR2SDRAM.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/Readme.txt [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/asyncfifo_dmem_1b.ngc [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/asyncfifo_dmem_1b.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_ctrl.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_idelay_ctrl.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_infrastructure.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_mem_if_top.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_phy_calib.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_phy_ctl_io.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_phy_dm_iob.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_phy_dq_iob.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_phy_dqs_iob.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_phy_init.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_phy_io.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_phy_top.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_phy_write.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_sdram.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_top.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_usr_addr_fifo.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_usr_rd.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_usr_top.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/greg/ddr2_usr_wr.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/main-ml410.ucf [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/main-ml50x.ucf [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/main.ucf diff | blob | history
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