synth:
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
synth:
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
| grep --line-buffered -v 'been backward balanced into' \
| grep --line-buffered -v 'IDDR has been replaced by IDDR_2CLK' \
| grep --line-buffered -v 'WARNING:Xst:616 - Invalid property'
| grep --line-buffered -v 'been backward balanced into' \
| grep --line-buffered -v 'IDDR has been replaced by IDDR_2CLK' \
| grep --line-buffered -v 'WARNING:Xst:616 - Invalid property'
cat build/fpga/*.ucf > build/fpga/main.ucf
$(xilinx_ise)ngdbuild ${intstyle} -aul -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
$(xilinx_ise)map ${intstyle} -ol ${effort} -p $(device) -pr b -cm ${opt_for} -o main_map.ncd main.ngd main.pcf
cat build/fpga/*.ucf > build/fpga/main.ucf
$(xilinx_ise)ngdbuild ${intstyle} -aul -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
$(xilinx_ise)map ${intstyle} -ol ${effort} -p $(device) -pr b -cm ${opt_for} -o main_map.ncd main.ngd main.pcf
$(xilinx_ise)trce ${intstyle} -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
$(xilinx_ise)bitgen ${intstyle} -f main.ut main.ncd
# $(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
$(xilinx_ise)trce ${intstyle} -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
$(xilinx_ise)bitgen ${intstyle} -f main.ut main.ncd
# $(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace