+
+
+
+## DDR ##############################################################################
+
+
+## IO Devices constraints
+
+#### Module ORGate_1 constraints
+
+# Net fpga_0_ORGate_1_Res_pin LOC=AE18;
+# Net fpga_0_ORGate_1_Res_pin TIG;
+# Net fpga_0_ORGate_1_Res_1_pin LOC=AE17;
+# Net fpga_0_ORGate_1_Res_1_pin TIG;
+# Net fpga_0_ORGate_1_Res_2_pin LOC=R11;
+# Net fpga_0_ORGate_1_Res_2_pin IOSTANDARD = PCI33_3;
+
+#### Module DDR2_SDRAM constraints
+
+# Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin LOC=AA25;
+# Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<0> LOC=H28;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<0> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<1> LOC=K28;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<1> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<2> LOC=L28;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<2> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<3> LOC=M25;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<3> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<4> LOC=Y24;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<4> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<5> LOC=N27;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<5> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<6> LOC=AD26;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<6> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<7> LOC=AC25;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<7> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<8> LOC=R26;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<8> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<9> LOC=R28;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<9> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<10> LOC=T26;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<10> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<11> LOC=T28;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<11> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<12> LOC=U27;
+# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<12> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<0> LOC=V28;
+# Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<0> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<1> LOC=W26;
+# Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<1> IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin LOC=R31;
+# Net fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_CE_pin LOC=AJ31;
+# Net fpga_0_DDR2_SDRAM_DDR2_CE_pin IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin LOC=AJ30;
+# Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin LOC=R32;
+# Net fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_WE_n_pin LOC=T31;
+# Net fpga_0_DDR2_SDRAM_DDR2_WE_n_pin IOSTANDARD = SSTL18_I;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=AH30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=M31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> LOC=T30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> LOC=U28;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=AJ32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=AG31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=AG30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=AF29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<0> LOC=F29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<0> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<1> LOC=K29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<1> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<2> LOC=P27;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<2> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<3> LOC=P32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<3> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<4> LOC=W27;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<4> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<5> LOC=W31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<5> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<6> LOC=AG32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<6> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<7> LOC=AE32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS<7> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<0> LOC=E29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<0> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<1> LOC=J29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<1> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<2> LOC=P26;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<2> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<3> LOC=N32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<3> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<4> LOC=V27;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<4> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<5> LOC=W30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<5> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<6> LOC=AH32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<6> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<7> LOC=AE31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<7> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<0> LOC=C32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<0> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<1> LOC=D32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<1> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<2> LOC=E32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<2> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<3> LOC=G32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<3> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<4> LOC=H32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<4> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<5> LOC=J32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<5> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<6> LOC=K32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<6> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<7> LOC=M32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<7> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<8> LOC=N28;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<8> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<9> LOC=D31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<9> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<10> LOC=E31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<10> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<11> LOC=F31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<11> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<12> LOC=G31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<12> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<13> LOC=J31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<13> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<14> LOC=K31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<14> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<15> LOC=L31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<15> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<16> LOC=C30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<16> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<17> LOC=D30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<17> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<18> LOC=F30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<18> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<19> LOC=G30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<19> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<20> LOC=Y28;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<20> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<21> LOC=Y27;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<21> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<22> LOC=L30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<22> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<23> LOC=M30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<23> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<24> LOC=N30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<24> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<25> LOC=C29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<25> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<26> LOC=D29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<26> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<27> LOC=J30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<27> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<28> LOC=L29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<28> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<29> LOC=N29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<29> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<30> LOC=P29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<30> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<31> LOC=R29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<31> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<32> LOC=T29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<32> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<33> LOC=U32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<33> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<34> LOC=V32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<34> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<35> LOC=W32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<35> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<36> LOC=Y32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<36> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<37> LOC=AB32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<37> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<38> LOC=AC32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<38> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<39> LOC=AD32;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<39> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<40> LOC=AB27;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<40> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<41> LOC=U31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<41> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<42> LOC=W25;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<42> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<43> LOC=Y31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<43> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<44> LOC=AA31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<44> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<45> LOC=AB31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<45> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<46> LOC=AD31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<46> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<47> LOC=AB28;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<47> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<48> LOC=AF31;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<48> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<49> LOC=U30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<49> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<50> LOC=V30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<50> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<51> LOC=Y26;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<51> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<52> LOC=AA30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<52> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<53> LOC=AB30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<53> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<54> LOC=AC30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<54> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<55> LOC=AD30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<55> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<56> LOC=AF30;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<56> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<57> LOC=V29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<57> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<58> LOC=W29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<58> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<59> LOC=Y29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<59> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<60> LOC=AA29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<60> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<61> LOC=AC29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<61> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<62> LOC=AD29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<62> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<63> LOC=AE29;
+# Net fpga_0_DDR2_SDRAM_DDR2_DQ<63> IOSTANDARD = SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin LOC=H30;
+# Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin IOSTANDARD = DIFF_SSTL18_II;
+# Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin LOC=H29;
+# Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin IOSTANDARD = DIFF_SSTL18_II;
+
+#### Module DDR_SDRAM constraints
+
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=J24;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=K26;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=K24;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=K23;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=L26;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=L25;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=L24;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=M23;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=N24;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=N23;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=N22;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=P22;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=P24;
+Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=J26;
+Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=J25;
+Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=D26;
+Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=H14;
+Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=C27;
+Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=D27;
+Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=E27;
+Net fpga_0_DDR_SDRAM_DDR_WE_n_pin IOSTANDARD = SSTL2_I;
+Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=F21;
+Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=G22;
+Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> LOC=E23;
+Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> LOC=G23;
+Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQS<0> LOC=F20;
+Net fpga_0_DDR_SDRAM_DDR_DQS<0> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQS<1> LOC=G20;
+Net fpga_0_DDR_SDRAM_DDR_DQS<1> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQS<2> LOC=G25;
+Net fpga_0_DDR_SDRAM_DDR_DQS<2> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQS<3> LOC=F25;
+Net fpga_0_DDR_SDRAM_DDR_DQS<3> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<0> LOC=E17;
+Net fpga_0_DDR_SDRAM_DDR_DQ<0> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<1> LOC=E18;
+Net fpga_0_DDR_SDRAM_DDR_DQ<1> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<2> LOC=F18;
+Net fpga_0_DDR_SDRAM_DDR_DQ<2> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<3> LOC=G18;
+Net fpga_0_DDR_SDRAM_DDR_DQ<3> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<4> LOC=F19;
+Net fpga_0_DDR_SDRAM_DDR_DQ<4> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<5> LOC=E19;
+Net fpga_0_DDR_SDRAM_DDR_DQ<5> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<6> LOC=D21;
+Net fpga_0_DDR_SDRAM_DDR_DQ<6> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<7> LOC=E21;
+Net fpga_0_DDR_SDRAM_DDR_DQ<7> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<8> LOC=G21;
+Net fpga_0_DDR_SDRAM_DDR_DQ<8> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<9> LOC=H20;
+Net fpga_0_DDR_SDRAM_DDR_DQ<9> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<10> LOC=J20;
+Net fpga_0_DDR_SDRAM_DDR_DQ<10> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<11> LOC=J21;
+Net fpga_0_DDR_SDRAM_DDR_DQ<11> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<12> LOC=K21;
+Net fpga_0_DDR_SDRAM_DDR_DQ<12> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<13> LOC=L21;
+Net fpga_0_DDR_SDRAM_DDR_DQ<13> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<14> LOC=J22;
+Net fpga_0_DDR_SDRAM_DDR_DQ<14> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<15> LOC=H22;
+Net fpga_0_DDR_SDRAM_DDR_DQ<15> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<16> LOC=C22;
+Net fpga_0_DDR_SDRAM_DDR_DQ<16> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<17> LOC=C23;
+Net fpga_0_DDR_SDRAM_DDR_DQ<17> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<18> LOC=C24;
+Net fpga_0_DDR_SDRAM_DDR_DQ<18> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<19> LOC=C25;
+Net fpga_0_DDR_SDRAM_DDR_DQ<19> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<20> LOC=D22;
+Net fpga_0_DDR_SDRAM_DDR_DQ<20> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<21> LOC=D24;
+Net fpga_0_DDR_SDRAM_DDR_DQ<21> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<22> LOC=D25;
+Net fpga_0_DDR_SDRAM_DDR_DQ<22> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<23> LOC=C28;
+Net fpga_0_DDR_SDRAM_DDR_DQ<23> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<24> LOC=F23;
+Net fpga_0_DDR_SDRAM_DDR_DQ<24> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<25> LOC=F24;
+Net fpga_0_DDR_SDRAM_DDR_DQ<25> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<26> LOC=F26;
+Net fpga_0_DDR_SDRAM_DDR_DQ<26> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<27> LOC=G26;
+Net fpga_0_DDR_SDRAM_DDR_DQ<27> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<28> LOC=H25;
+Net fpga_0_DDR_SDRAM_DDR_DQ<28> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<29> LOC=H24;
+Net fpga_0_DDR_SDRAM_DDR_DQ<29> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<30> LOC=E24;
+Net fpga_0_DDR_SDRAM_DDR_DQ<30> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_DQ<31> LOC=E22;
+Net fpga_0_DDR_SDRAM_DDR_DQ<31> IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=F28;
+Net fpga_0_DDR_SDRAM_DDR_Clk_pin IOSTANDARD = SSTL2_II;
+Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=E28;
+Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin IOSTANDARD = SSTL2_II;