+ if (filename.equals("fifo")) {
+ pw.println(" wire in_a__;");
+ pw.println(" wire out_r__;");
+ pw.println(" fifo8x37 fifo8x37(clk, rst,");
+ pw.println(" in_r, in_a__, in_d,");
+ pw.println(" out_r__, out_a, out_d_);");
+ pw.println(" always @(posedge clk) begin");
+ pw.println(" if (!rst) begin");
+ pw.println(" `reset");
+ pw.println(" end else begin");
+ pw.println(" `flush");
+ pw.println(" out_r <= out_r__;");
+ pw.println(" in_a <= in_a__;");
+ pw.println(" end");
+ pw.println(" end");
+ } else {
+ pw.println(sd.getSection("fpga"));
+ }