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set C-flag on Memory ship out port
author
adam
<adam@megacz.com>
Mon, 3 Nov 2008 13:32:20 +0000
(14:32 +0100)
committer
adam
<adam@megacz.com>
Mon, 3 Nov 2008 13:32:20 +0000
(14:32 +0100)
ships/Memory.ship
patch
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diff --git
a/ships/Memory.ship
b/ships/Memory.ship
index
5395cb3
..
29f0888
100644
(file)
--- a/
ships/Memory.ship
+++ b/
ships/Memory.ship
@@
-170,6
+170,7
@@
sequence guarantee problem mentioned in the previous paragraph.
initial counter = 0;
reg write_flag;
initial counter = 0;
reg write_flag;
+ reg out_w;
reg dispatching_cbd;
initial write_flag = 0;
initial dispatching_cbd = 0;
reg dispatching_cbd;
initial write_flag = 0;
initial dispatching_cbd = 0;
@@
-178,7
+179,7
@@
sequence guarantee problem mentioned in the previous paragraph.
assign addr1 = write_flag ? inAddrWrite_d[(`DATAWIDTH-1):0] : inAddrRead_d[(`DATAWIDTH-1):0];
bram14 mybram(clk, rst, write_flag, addr1, cursor, inDataWrite_d, out1, out2);
assign addr1 = write_flag ? inAddrWrite_d[(`DATAWIDTH-1):0] : inAddrRead_d[(`DATAWIDTH-1):0];
bram14 mybram(clk, rst, write_flag, addr1, cursor, inDataWrite_d, out1, out2);
- assign out_d_ = dispatching_cbd ? out2 : out1;
+ assign out_d_ = { out_w , (dispatching_cbd ? out2 : out1) };
always @(posedge clk) begin
always @(posedge clk) begin
@@
-207,8
+208,9
@@
sequence guarantee problem mentioned in the previous paragraph.
dispatching_cbd <= 1;
end
out_r <= 1;
dispatching_cbd <= 1;
end
out_r <= 1;
- end else if (inCBD_r && out_r && out_a) begin
- out_r <= 0;
+ out_w <= 0;
+ end else if (inCBD_r && out_r && out_a) begin
+ out_r <= 0;
if (counter != inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin
cursor <= cursor + 1;
counter <= counter + 1;
if (counter != inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin
cursor <= cursor + 1;
counter <= counter + 1;
@@
-221,7
+223,8
@@
sequence guarantee problem mentioned in the previous paragraph.
end else if (!dispatching_cbd && !out_r && !out_a && inAddrRead_r && !inAddrRead_a) begin
inAddrRead_a <= 1;
out_r <= 1;
end else if (!dispatching_cbd && !out_r && !out_a && inAddrRead_r && !inAddrRead_a) begin
inAddrRead_a <= 1;
out_r <= 1;
-
+ out_w <= 0;
+
end else if (!dispatching_cbd && !out_r && !out_a && inAddrWrite_r && inDataWrite_r) begin
// timing note: it's okay to set the *_a flags here because *_d will still
// be valid on the *next* cycle, which is all we care about
end else if (!dispatching_cbd && !out_r && !out_a && inAddrWrite_r && inDataWrite_r) begin
// timing note: it's okay to set the *_a flags here because *_d will still
// be valid on the *next* cycle, which is all we care about
@@
-229,6
+232,7
@@
sequence guarantee problem mentioned in the previous paragraph.
inDataWrite_a <= 1;
out_r <= 1;
write_flag <= 1;
inDataWrite_a <= 1;
out_r <= 1;
write_flag <= 1;
+ out_w <= 1;
end
end
end
end
end
end