-/* Verilog for cell 'marinaOutDock{sch}' from library 'aMarinaM' */
-/* Created on Mon Nov 17, 2008 08:47:24 */
-/* Last revised on Sat May 02, 2009 06:16:53 */
-/* Written on Sat May 16, 2009 16:19:19 by Electric VLSI Design System, version 8.08k */
-
-module orangeTSMC090nm__wire(a);
- input a;
-
- supply0 gnd;
-endmodule /* orangeTSMC090nm__wire */
-
-module orangeTSMC090nm__wire90(a);
- inout a;
-
- supply0 gnd;
- orangeTSMC090nm__wire wire_0(.a(a));
-endmodule /* orangeTSMC090nm__wire90 */
-
-module countersL__cntShift(ctgLO, myp1p, myp2p, sid, sod);
- input ctgLO;
- output myp1p;
- output myp2p;
- inout [1:9] sid;
- inout [1:1] sod;
-
- supply1 vdd;
- supply0 gnd;
- wire net_97, net_99;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (myp1p, net_97);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (myp2p, net_99);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_4 (net_99, ctgLO, sid[2]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_5 (net_97, ctgLO, sid[3]);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_9(.a(net_97));
- orangeTSMC090nm__wire90 wire90_10(.a(net_99));
-endmodule /* countersL__cntShift */
-
-module countersL__cntFreq(count, fin, myFin, ctgLO, fout);
- input count;
- input fin;
- input myFin;
- output ctgLO;
- output fout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_17, net_33, net_39;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_17, ctgLO);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (ctgLO, count);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_39, net_17, myFin);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_33, ctgLO, fin);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (fout, net_33, net_39);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_2(.a(net_17));
- orangeTSMC090nm__wire90 wire90_4(.a(net_33));
- orangeTSMC090nm__wire90 wire90_5(.a(net_39));
-endmodule /* countersL__cntFreq */
-
-module orangeTSMC090nm__NMOSxwk(g, d, s);
- input g;
- inout d;
- inout s;
-
- supply0 gnd;
- /* begin Verilog_template for orangeTSMC090nm:NMOSfwk{sch}*/
- rtranif1 #(100) NMOSfwk_0 (d, s, g);
- // end Verilog_template
-endmodule /* orangeTSMC090nm__NMOSxwk */
-
-module orangeTSMC090nm__PMOSxwk(g, d, s);
- input g;
- inout d;
- inout s;
-
- supply1 vdd;
- /* begin Verilog_template for orangeTSMC090nm:PMOSfwk{sch}*/
- rtranif0 #(100) PMOSfwk_0 (d, s, g);
- // end Verilog_template
-endmodule /* orangeTSMC090nm__PMOSxwk */
-
-module latchPartsK__latchKeep(out_B_, out_s_);
- output out_B_;
- output out_s_;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__NMOSxwk NMOSxwk_0(.g(out_B_), .d(out_s_), .s(gnd));
- orangeTSMC090nm__NMOSxwk NMOSxwk_1(.g(out_s_), .d(out_B_), .s(gnd));
- orangeTSMC090nm__PMOSxwk PMOSxwk_0(.g(out_B_), .d(out_s_), .s(vdd));
- orangeTSMC090nm__PMOSxwk PMOSxwk_1(.g(out_s_), .d(out_B_), .s(vdd));
-endmodule /* latchPartsK__latchKeep */
-
-module orangeTSMC090nm__NMOSx(g, d, s);
- input g;
- inout d;
- inout s;
-
- supply0 gnd;
- /* begin Verilog_template for orangeTSMC090nm:NMOSf{sch}*/
- tranif1 #(100) NMOSf_0 (d, s, g);
- // end Verilog_template
-endmodule /* orangeTSMC090nm__NMOSx */
-
-module latchPartsK__latchPointF(hcl, in, x_F_, x_T_);
- input hcl;
- input [1:1] in;
- output x_F_;
- output x_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- orangeTSMC090nm__NMOSx PMOSx_0(.g(hcl), .d(in[1]), .s(x_T_));
- orangeTSMC090nm__NMOSx PMOSx_1(.g(hcl), .d(net_8), .s(x_F_));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_8, in[1]);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
-endmodule /* latchPartsK__latchPointF */
-
-module latchesK__raw2inLatchF(hcl_A_, hcl_B_, inA, inB, out_F_);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output out_F_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_45;
-
- latchPartsK__latchKeep latchKee_0(.out_B_(out_F_), .out_s_(net_45));
- latchPartsK__latchPointF latchPoi_0(.hcl(hcl_A_), .in(inA[1:1]),
- .x_F_(out_F_), .x_T_(net_45));
- latchPartsK__latchPointF latchPoi_1(.hcl(hcl_B_), .in(inB[1:1]),
- .x_F_(out_F_), .x_T_(net_45));
- orangeTSMC090nm__wire90 wire90_0(.a(net_45));
-endmodule /* latchesK__raw2inLatchF */
-
-module latchesK__latch2in10A(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire dataBar;
-
- latchesK__raw2inLatchF hi2inLat_0(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:1]), .inB(inB[1:1]), .out_F_(dataBar));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_1 (out[1], dataBar);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_1(.a(dataBar));
-endmodule /* latchesK__latch2in10A */
-
-module redFive__nor2n_sy(ina, inb, out);
- input ina;
- input inb;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
- // end Verilog_template
-endmodule /* redFive__nor2n_sy */
-
-module countersL__cntScnOne(cin, ctgLO, p1p, p2p, sin, out);
- input cin;
- input ctgLO;
- input p1p;
- input p2p;
- input sin;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire cA, cB, net_14, net_3;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_14, out);
- // end Verilog_template
- latchesK__latch2in10A latch2in_0(.hcl_A_(cB), .hcl_B_(p1p), .inA({net_3}),
- .inB({net_3}), .out({out}));
- latchesK__latch2in10A latch2in_1(.hcl_A_(cA), .hcl_B_(p2p), .inA({net_14}),
- .inB({sin}), .out({net_3}));
- redFive__nor2n_sy nor2n_sy_0(.ina(ctgLO), .inb(cB), .out(cA));
- redFive__nor2n_sy nor2n_sy_2(.ina(ctgLO), .inb(cin), .out(cB));
- orangeTSMC090nm__wire90 wire90_0(.a(net_14));
- orangeTSMC090nm__wire90 wire90_1(.a(net_3));
- orangeTSMC090nm__wire90 wire90_2(.a(cA));
- orangeTSMC090nm__wire90 wire90_3(.a(cB));
-endmodule /* countersL__cntScnOne */
-
-module countersL__cntScnFour(cin, ctgLO, p1p, p2p, sin, out);
- input cin;
- input ctgLO;
- input p1p;
- input p2p;
- input sin;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_40, net_43, net_46;
-
- countersL__cntScnOne cntScnOn_0(.cin(net_46), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_46), .out(net_40));
- countersL__cntScnOne cntScnOn_1(.cin(cin), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(sin), .out(net_43));
- countersL__cntScnOne cntScnOn_2(.cin(net_43), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_43), .out(net_46));
- countersL__cntScnOne cntScnOn_3(.cin(net_40), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_40), .out(out));
- orangeTSMC090nm__wire90 wire90_4(.a(net_40));
- orangeTSMC090nm__wire90 wire90_5(.a(net_43));
- orangeTSMC090nm__wire90 wire90_6(.a(net_46));
-endmodule /* countersL__cntScnFour */
-
-module countersL__cntScnThree(cin, ctgLO, p1p, p2p, sin, out);
- input cin;
- input ctgLO;
- input p1p;
- input p2p;
- input sin;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_43, net_46;
-
- countersL__cntScnOne cntScnOn_0(.cin(net_46), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_46), .out(out));
- countersL__cntScnOne cntScnOn_1(.cin(cin), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(sin), .out(net_43));
- countersL__cntScnOne cntScnOn_2(.cin(net_43), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_43), .out(net_46));
- orangeTSMC090nm__wire90 wire90_5(.a(net_43));
- orangeTSMC090nm__wire90 wire90_6(.a(net_46));
-endmodule /* countersL__cntScnThree */
-
-module countersL__cntScnTwelve(cin, ctgLO, p1p, p2p, sin, out);
- input cin;
- input ctgLO;
- input p1p;
- input p2p;
- input sin;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_43, net_46;
-
- countersL__cntScnFour cntScnFo_0(.cin(net_46), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_46), .out(out));
- countersL__cntScnFour cntScnFo_1(.cin(cin), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(sin), .out(net_43));
- countersL__cntScnFour cntScnFo_2(.cin(net_43), .ctgLO(ctgLO), .p1p(p1p),
- .p2p(p2p), .sin(net_43), .out(net_46));
- orangeTSMC090nm__wire90 wire90_5(.a(net_43));
- orangeTSMC090nm__wire90 wire90_6(.a(net_46));
-endmodule /* countersL__cntScnTwelve */
-
-module countersL__instructionCount(cin, count, fin, fout, sid, sod);
- input cin;
- input count;
- input fin;
- output fout;
- inout [1:9] sid;
- inout [1:1] sod;
-
- supply1 vdd;
- supply0 gnd;
- wire ctgLO, myp1p, myp2p, net_1, net_77, net_78;
-
- countersL__cntShift cntContr_0(.ctgLO(ctgLO), .myp1p(myp1p), .myp2p(myp2p),
- .sid(sid[1:9]), .sod(sod[1:1]));
- countersL__cntFreq cntFreq_0(.count(count), .fin(fin), .myFin(net_77),
- .ctgLO(ctgLO), .fout(fout));
- countersL__cntScnFour cntScnFo_1(.cin(cin), .ctgLO(ctgLO), .p1p(myp1p),
- .p2p(myp2p), .sin(sid[1]), .out(net_1));
- countersL__cntScnThree cntScnTh_0(.cin(net_77), .ctgLO(ctgLO), .p1p(myp1p),
- .p2p(myp2p), .sin(net_77), .out(net_78));
- countersL__cntScnTwelve cntScnTw_3(.cin(net_1), .ctgLO(ctgLO), .p1p(myp1p),
- .p2p(myp2p), .sin(net_1), .out(net_77));
- countersL__cntScnTwelve cntScnTw_5(.cin(net_78), .ctgLO(ctgLO), .p1p(myp1p),
- .p2p(myp2p), .sin(net_78), .out(sod[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_1));
- orangeTSMC090nm__wire90 wire90_1(.a(net_77));
- orangeTSMC090nm__wire90 wire90_2(.a(net_78));
- orangeTSMC090nm__wire90 wire90_3(.a(sod[1]));
-endmodule /* countersL__instructionCount */
-
-module latchesK__raw1inLatchF(hcl, in, out_F_);
- input hcl;
- input [1:1] in;
- output out_F_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_45;
-
- latchPartsK__latchKeep latchFlo_0(.out_B_(out_F_), .out_s_(net_45));
- latchPartsK__latchPointF latchPoi_0(.hcl(hcl), .in(in[1:1]), .x_F_(out_F_),
- .x_T_(net_45));
- orangeTSMC090nm__wire90 wire90_0(.a(net_45));
-endmodule /* latchesK__raw1inLatchF */
-
-module latchesK__latch1in60C(hcl, inS, outS);
- input hcl;
- input [1:1] inS;
- output [1:1] outS;
-
- supply1 vdd;
- supply0 gnd;
- wire net_14, net_16, net_17;
-
- latchesK__raw1inLatchF hi2inLat_0(.hcl(hcl), .in(inS[1:1]),
- .out_F_(net_14));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_16, net_14);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_1 (net_17, net_16);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_2 (outS[1], net_17);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_14));
- orangeTSMC090nm__wire90 wire90_1(.a(net_16));
- orangeTSMC090nm__wire90 wire90_2(.a(net_17));
-endmodule /* latchesK__latch1in60C */
-
-module registersM__addr1in60Cx7(ain, fire, aout);
- input [1:7] ain;
- input fire;
- output [1:7] aout;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch1in60C lat_1_(.hcl(fire), .inS({ain[1]}), .outS({aout[1]}));
- latchesK__latch1in60C lat_2_(.hcl(fire), .inS({ain[2]}), .outS({aout[2]}));
- latchesK__latch1in60C lat_3_(.hcl(fire), .inS({ain[3]}), .outS({aout[3]}));
- latchesK__latch1in60C lat_4_(.hcl(fire), .inS({ain[4]}), .outS({aout[4]}));
- latchesK__latch1in60C lat_5_(.hcl(fire), .inS({ain[5]}), .outS({aout[5]}));
- latchesK__latch1in60C lat_6_(.hcl(fire), .inS({ain[6]}), .outS({aout[6]}));
- latchesK__latch1in60C lat_7_(.hcl(fire), .inS({ain[7]}), .outS({aout[7]}));
-endmodule /* registersM__addr1in60Cx7 */
-
-module registersM__addr1in60Cx15(ain, ain_TT_, fire, aout, aout_TT_);
- input [1:14] ain;
- input ain_TT_;
- input fire;
- output [1:14] aout;
- output aout_TT_;
-
- supply1 vdd;
- supply0 gnd;
- registersM__addr1in60Cx7 addr1in6_0(.ain(ain[8:14]), .fire(fire),
- .aout(aout[8:14]));
- registersM__addr1in60Cx7 addr1in6_1(.ain(ain[1:7]), .fire(fire),
- .aout(aout[1:7]));
- latchesK__latch1in60C latch1in_0(.hcl(fire), .inS({ain_TT_}),
- .outS({aout_TT_}));
- orangeTSMC090nm__wire90 wire90_0(.a(fire));
- orangeTSMC090nm__wire90 wire90_1(.a(fire));
-endmodule /* registersM__addr1in60Cx15 */
-
-module registersM__data1in60Cx18(dcl, in, out);
- input dcl;
- input [1:18] in;
- output [1:18] out;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch1in60C lat_1_(.hcl(dcl), .inS({in[1]}), .outS({out[1]}));
- latchesK__latch1in60C lat_2_(.hcl(dcl), .inS({in[2]}), .outS({out[2]}));
- latchesK__latch1in60C lat_3_(.hcl(dcl), .inS({in[3]}), .outS({out[3]}));
- latchesK__latch1in60C lat_4_(.hcl(dcl), .inS({in[4]}), .outS({out[4]}));
- latchesK__latch1in60C lat_5_(.hcl(dcl), .inS({in[5]}), .outS({out[5]}));
- latchesK__latch1in60C lat_6_(.hcl(dcl), .inS({in[6]}), .outS({out[6]}));
- latchesK__latch1in60C lat_7_(.hcl(dcl), .inS({in[7]}), .outS({out[7]}));
- latchesK__latch1in60C lat_8_(.hcl(dcl), .inS({in[8]}), .outS({out[8]}));
- latchesK__latch1in60C lat_9_(.hcl(dcl), .inS({in[9]}), .outS({out[9]}));
- latchesK__latch1in60C lat_10_(.hcl(dcl), .inS({in[10]}), .outS({out[10]}));
- latchesK__latch1in60C lat_11_(.hcl(dcl), .inS({in[11]}), .outS({out[11]}));
- latchesK__latch1in60C lat_12_(.hcl(dcl), .inS({in[12]}), .outS({out[12]}));
- latchesK__latch1in60C lat_13_(.hcl(dcl), .inS({in[13]}), .outS({out[13]}));
- latchesK__latch1in60C lat_14_(.hcl(dcl), .inS({in[14]}), .outS({out[14]}));
- latchesK__latch1in60C lat_15_(.hcl(dcl), .inS({in[15]}), .outS({out[15]}));
- latchesK__latch1in60C lat_16_(.hcl(dcl), .inS({in[16]}), .outS({out[16]}));
- latchesK__latch1in60C lat_17_(.hcl(dcl), .inS({in[17]}), .outS({out[17]}));
- latchesK__latch1in60C lat_18_(.hcl(dcl), .inS({in[18]}), .outS({out[18]}));
-endmodule /* registersM__data1in60Cx18 */
-
-module registersM__data1in60Cx37(in, take, out);
- input [1:37] in;
- input take;
- output [1:37] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__data1in60Cx18 data1in6_1(.dcl(take), .in(in[1:18]),
- .out(out[1:18]));
- registersM__data1in60Cx18 data1in6_2(.dcl(take), .in(in[20:37]),
- .out(out[20:37]));
- latchesK__latch1in60C latch1in_0(.hcl(take), .inS({in[19]}),
- .outS({out[19]}));
- orangeTSMC090nm__wire90 wire90_2(.a(take));
- orangeTSMC090nm__wire90 wire90_3(.a(take));
-endmodule /* registersM__data1in60Cx37 */
-
-module orangeTSMC090nm__PMOSx(g, d, s);
- input g;
- inout d;
- inout s;
-
- supply1 vdd;
- /* begin Verilog_template for orangeTSMC090nm:PMOSf{sch}*/
- tranif0 #(100) PMOSf_0 (d, s, g);
- // end Verilog_template
-endmodule /* orangeTSMC090nm__PMOSx */
-
-module arbiterM__half2inArb(inA, req_B_, cross, grant_B_);
- input inA;
- input req_B_;
- output cross;
- output grant_B_; trireg grant_B_;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__PMOSx NMOSx_0(.g(req_B_), .d(vdd), .s(grant_B_));
- orangeTSMC090nm__NMOSx PMOSx_0(.g(inA), .d(cross), .s(grant_B_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nor2n_0 (cross, inA, req_B_);
- // end Verilog_template
-endmodule /* arbiterM__half2inArb */
-
-module arbiterM__arbiter2(req_A_, req_B_, grant_A_, grant_B_);
- input req_A_;
- input req_B_;
- output grant_A_;
- output grant_B_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_5, net_8;
-
- arbiterM__half2inArb halfArb_2(.inA(net_5), .req_B_(req_A_), .cross(net_8),
- .grant_B_(grant_A_));
- arbiterM__half2inArb halfArb_3(.inA(net_8), .req_B_(req_B_), .cross(net_5),
- .grant_B_(grant_B_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
- orangeTSMC090nm__wire90 wire90_1(.a(net_5));
-endmodule /* arbiterM__arbiter2 */
-
-module centersJ__ctrAND2in100LT(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_135, net_139, net_144;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_8 (net_135, inB);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_9 (net_139, inA);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_10 (out, net_144);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2LT_sy{sch}*/
- nand (strong0, strong1) #(100) nand2LT__0 (net_144, net_139, net_135);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_4(.a(net_135));
- orangeTSMC090nm__wire90 wire90_5(.a(net_144));
- orangeTSMC090nm__wire90 wire90_6(.a(net_139));
-endmodule /* centersJ__ctrAND2in100LT */
-
-module driversM__dataDriver60(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_7;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out, net_7);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_7, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_7));
-endmodule /* driversM__dataDriver60 */
-
-module redFive__pms3(g, g2, g3, d);
- input g;
- input g2;
- input g3;
- output d;
-
- supply1 vdd;
- wire net_2, net_5;
-
- orangeTSMC090nm__PMOSx PMOS_0(.g(g3), .d(d), .s(net_2));
- orangeTSMC090nm__PMOSx PMOS_1(.g(g2), .d(net_2), .s(net_5));
- orangeTSMC090nm__PMOSx PMOS_2(.g(g), .d(net_5), .s(vdd));
-endmodule /* redFive__pms3 */
-
-module driversM__predDri60wMC(in, mc, pred);
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(in), .d(pred), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(pred), .s(gnd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_145, pred);
- // end Verilog_template
- redFive__pms3 pms3_0(.g(mc), .g2(in), .g3(net_145), .d(pred));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
-endmodule /* driversM__predDri60wMC */
-
-module redFive__nms2(g, g2, d);
- input g;
- input g2;
- output d;
-
- supply0 gnd;
- wire net_0;
-
- orangeTSMC090nm__NMOSx NMOS_0(.g(g2), .d(d), .s(net_0));
- orangeTSMC090nm__NMOSx NMOS_1(.g(g), .d(net_0), .s(gnd));
-endmodule /* redFive__nms2 */
-
-module driversM__sucANDdri60(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_51, inA, inB);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_51), .g2(net_71), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__sucANDdri60 */
-
-module wiresL__tranCap();
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for orangeTSMC090nm:NMOSf{sch}*/
- tranif1 #(100) NMOSf_1 (gnd, gnd, vdd);
- // end Verilog_template
- /* begin Verilog_template for orangeTSMC090nm:PMOSf{sch}*/
- tranif0 #(100) PMOSf_2 (vdd, vdd, gnd);
- // end Verilog_template
-endmodule /* wiresL__tranCap */
-
-module gaspM__gaspDrain(clear, go, pred, silent, tok, fire, s, succ, take);
- input clear;
- input go;
- input pred;
- input silent;
- input tok;
- output fire;
- output [1:2] s;
- output succ;
- output take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_241, net_353, net_360, net_463, net_472;
-
- arbiterM__arbiter2 arbiter2_0(.req_A_(pred), .req_B_(net_360),
- .grant_A_(net_241), .grant_B_(net_353));
- centersJ__ctrAND2in100LT ctrAND2i_5(.inA(net_241), .inB(succ), .out(fire));
- driversM__dataDriver60 dataDriv_0(.inA(tok), .inB(fire), .out(take));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_360, go);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_472, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_463, silent);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[2], net_353);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (s[1], net_472);
- // end Verilog_template
- driversM__predDri60wMC predDri6_1(.in(fire), .mc(clear), .pred(pred));
- driversM__sucANDdri60 sucANDdr_4(.inA(net_463), .inB(fire), .succ(succ));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- orangeTSMC090nm__wire90 wire90_1(.a(net_241));
- orangeTSMC090nm__wire90 wire90_7(.a(net_360));
- orangeTSMC090nm__wire90 wire90_10(.a(net_353));
- orangeTSMC090nm__wire90 wire90_11(.a(s[2]));
- orangeTSMC090nm__wire90 wire90_15(.a(net_472));
- orangeTSMC090nm__wire90 wire90_16(.a(net_463));
-endmodule /* gaspM__gaspDrain */
-
-module latchesK__latch1in10A(hcl, in, out);
- input hcl;
- input [1:1] in;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18;
-
- latchesK__raw1inLatchF hi2inLat_0(.hcl(hcl), .in(in[1:1]), .out_F_(net_18));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (out[1], net_18);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
-endmodule /* latchesK__latch1in10A */
-
-module latchesK__latch2in10Alo(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire dataBar;
-
- latchesK__raw2inLatchF hi2inLat_0(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:1]), .inB(inB[1:1]), .out_F_(dataBar));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (out[1], dataBar);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(dataBar));
-endmodule /* latchesK__latch2in10Alo */
-
-module scanM__scanCellE(dIn, p1p, p2p, rd, sin, sout);
- input [1:1] dIn;
- input p1p;
- input p2p;
- input rd;
- input sin;
- output sout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_2;
-
- latchesK__latch1in10A latch1in_0(.hcl(p2p), .in({sin}), .out({net_2}));
- latchesK__latch2in10Alo latch2in_0(.hcl_A_(p1p), .hcl_B_(rd), .inA({net_2}),
- .inB(dIn[1:1]), .out({sout}));
- orangeTSMC090nm__wire90 wire90_0(.a(net_2));
-endmodule /* scanM__scanCellE */
-
-module scanM__scanEx2(dIn, sir, sor);
- input [1:2] dIn;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_26;
-
- scanM__scanCellE scanCell_3(.dIn({dIn[1]}), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(sir[1]), .sout(net_26));
- scanM__scanCellE scanCell_4(.dIn({dIn[2]}), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(net_26), .sout(sor[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_26));
-endmodule /* scanM__scanEx2 */
-
-module latchPartsK__latchPointFmcHI(mc, x_F_, x_T_);
- input mc;
- output x_F_;
- output x_T_;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__NMOSx PMOSx_0(.g(mc), .d(gnd), .s(x_T_));
- orangeTSMC090nm__NMOSx PMOSx_1(.g(mc), .d(vdd), .s(x_F_));
-endmodule /* latchPartsK__latchPointFmcHI */
-
-module latchesK__raw2inLatchFmc(hcl, inA, mc, out_F_);
- input hcl;
- input [1:1] inA;
- input mc;
- output out_F_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_45;
-
- latchPartsK__latchKeep latchKee_0(.out_B_(out_F_), .out_s_(net_45));
- latchPartsK__latchPointF latchPoi_0(.hcl(hcl), .in(inA[1:1]), .x_F_(out_F_),
- .x_T_(net_45));
- latchPartsK__latchPointFmcHI latchPoi_1(.mc(mc), .x_F_(out_F_),
- .x_T_(net_45));
- orangeTSMC090nm__wire90 wire90_0(.a(net_45));
-endmodule /* latchesK__raw2inLatchFmc */
-
-module latchesK__latch2in10Alomc(hcl, inA, mc, out);
- input hcl;
- input [1:1] inA;
- input mc;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire dataBar;
-
- latchesK__raw2inLatchFmc hi2inLat_0(.hcl(hcl), .inA(inA[1:1]), .mc(mc),
- .out_F_(dataBar));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (out[1], dataBar);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(dataBar));
-endmodule /* latchesK__latch2in10Alomc */
-
-module scanM__scanCellF(mc, p1p, p2p, rd, sin, wr, dout, sout);
- input mc;
- input p1p;
- input p2p;
- input rd;
- input sin;
- input wr;
- output [1:1] dout;
- output sout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_2;
-
- latchesK__latch1in10A latch1in_0(.hcl(p2p), .in({sin}), .out({net_2}));
- latchesK__latch2in10Alo latch2in_0(.hcl_A_(p1p), .hcl_B_(rd), .inA({net_2}),
- .inB(dout[1:1]), .out({sout}));
- latchesK__latch2in10Alomc latch2in_1(.hcl(wr), .inA({sout}), .mc(mc),
- .out(dout[1:1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_2));
-endmodule /* scanM__scanCellF */
-
-module scanM__scanCellFtall(mc, p1p, p2p, rd, sin, wr, dout, sout);
- input mc;
- input p1p;
- input p2p;
- input rd;
- input sin;
- input wr;
- output [1:1] dout;
- output sout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_2;
-
- latchesK__latch1in10A latch1in_0(.hcl(p2p), .in({sin}), .out({net_2}));
- latchesK__latch2in10Alo latch2in_0(.hcl_A_(p1p), .hcl_B_(rd), .inA({net_2}),
- .inB(dout[1:1]), .out({sout}));
- latchesK__latch2in10Alomc latch2in_1(.hcl(wr), .inA({sout}), .mc(mc),
- .out(dout[1:1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_2));
-endmodule /* scanM__scanCellFtall */
-
-module scanM__scanFx3tallL(dout, dout_1, dout_2, sic, soc);
- output [1:1] dout;
- output [2:2] dout_1;
- output [3:3] dout_2;
- inout [1:9] sic;
- inout [1:1] soc;
-
- supply1 vdd;
- supply0 gnd;
- wire net_30, net_31;
-
- scanM__scanCellF scanCell_5(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_30), .wr(sic[4]), .dout(dout_1[2:2]),
- .sout(net_31));
- scanM__scanCellF scanCell_6(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_31), .wr(sic[4]), .dout(dout_2[3:3]),
- .sout(soc[1]));
- scanM__scanCellFtall scanCell_7(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(sic[1]), .wr(sic[4]), .dout(dout[1:1]),
- .sout(net_30));
- orangeTSMC090nm__wire90 wire90_0(.a(net_30));
- orangeTSMC090nm__wire90 wire90_1(.a(net_31));
-endmodule /* scanM__scanFx3tallL */
-
-module stagesM__drainStage(ain, ain_TT_, in, pred, aout, aout_TT_, out, succ,
- sic, sir, soc, sor);
- input [14:1] ain;
- input ain_TT_;
- input [1:37] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output [1:37] out;
- output succ;
- inout [1:9] sic;
- inout [1:9] sir;
- inout [1:1] soc;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire clear, go, net_4, net_5, silent;
- wire [1:0] net_17;
-
- registersM__addr1in60Cx15 addr1in6_0(.ain({ain[1], ain[2], ain[3], ain[4],
- ain[5], ain[6], ain[7], ain[8], ain[9], ain[10], ain[11], ain[12],
- ain[13], ain[14]}), .ain_TT_(ain_TT_), .fire(net_4), .aout({aout[1],
- aout[2], aout[3], aout[4], aout[5], aout[6], aout[7], aout[8], aout[9],
- aout[10], aout[11], aout[12], aout[13], aout[14]}),
- .aout_TT_(aout_TT_));
- registersM__data1in60Cx37 data1in6_0(.in(in[1:37]), .take(net_5),
- .out(out[1:37]));
- gaspM__gaspDrain gaspDrai_0(.clear(clear), .go(go), .pred(pred),
- .silent(silent), .tok(ain_TT_), .fire(net_4), .s({net_17[1], net_17[0]}),
- .succ(succ), .take(net_5));
- scanM__scanEx2 scanEx2v_1(.dIn({net_17[1], net_17[0]}), .sir(sir[1:9]),
- .sor(sor[1:1]));
- scanM__scanFx3tallL scanFx3t_1(.dout({go}), .dout_1({clear}),
- .dout_2({silent}), .sic(sic[1:9]), .soc(soc[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
-endmodule /* stagesM__drainStage */
-
-module latchesK__latch2in60C(hcl_A_, hcl_B_, inA, inB, outS);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output [1:1] outS;
-
- supply1 vdd;
- supply0 gnd;
- wire net_14, net_16, net_17;
-
- latchesK__raw2inLatchF hi2inLat_0(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:1]), .inB(inB[1:1]), .out_F_(net_14));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_16, net_14);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_1 (net_17, net_16);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_2 (outS[1], net_17);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_14));
- orangeTSMC090nm__wire90 wire90_1(.a(net_16));
- orangeTSMC090nm__wire90 wire90_2(.a(net_17));
-endmodule /* latchesK__latch2in60C */
-
-module latchGroupsK__latchWscM2(hcl, in, sin, out, sout, p1p, p2p, rd, wr);
- input hcl;
- input [1:1] in;
- input sin;
- output [1:1] out;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
- inout wr;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch2in60C hi2inLat_1(.hcl_A_(hcl), .hcl_B_(wr), .inA(in[1:1]),
- .inB({sout}), .outS(out[1:1]));
- scanM__scanCellE scanCell_3(.dIn(out[1:1]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(sout));
-endmodule /* latchGroupsK__latchWscM2 */
-
-module registersM__addr1in60Cx7scan(ain, fire, sin, aout, sout, p1p, p2p, rd,
- wr_A_);
- input [1:7] ain;
- input fire;
- input sin;
- output [1:7] aout;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
- inout wr_A_;
-
- supply1 vdd;
- supply0 gnd;
- wire [2:7] xin;
-
- latchGroupsK__latchWscM2 la_1_(.hcl(fire), .in({ain[1]}), .sin(sin),
- .out({aout[1]}), .sout(xin[2]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_2_(.hcl(fire), .in({ain[2]}), .sin(xin[2]),
- .out({aout[2]}), .sout(xin[3]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_3_(.hcl(fire), .in({ain[3]}), .sin(xin[3]),
- .out({aout[3]}), .sout(xin[4]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_4_(.hcl(fire), .in({ain[4]}), .sin(xin[4]),
- .out({aout[4]}), .sout(xin[5]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_5_(.hcl(fire), .in({ain[5]}), .sin(xin[5]),
- .out({aout[5]}), .sout(xin[6]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_6_(.hcl(fire), .in({ain[6]}), .sin(xin[6]),
- .out({aout[6]}), .sout(xin[7]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
- latchGroupsK__latchWscM2 la_7_(.hcl(fire), .in({ain[7]}), .sin(xin[7]),
- .out({aout[7]}), .sout(sout), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_A_));
-endmodule /* registersM__addr1in60Cx7scan */
-
-module registersM__data1in60Cx18scan(dcl, in, sin, out, sout, p1p, p2p, rd,
- wr_D_);
- input dcl;
- input [1:18] in;
- input sin;
- output [1:18] out;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
- inout wr_D_;
-
- supply1 vdd;
- supply0 gnd;
- wire [2:18] xin;
-
- latchGroupsK__latchWscM2 la_1_(.hcl(dcl), .in({in[1]}), .sin(sin),
- .out({out[1]}), .sout(xin[2]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_2_(.hcl(dcl), .in({in[2]}), .sin(xin[2]),
- .out({out[2]}), .sout(xin[3]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_3_(.hcl(dcl), .in({in[3]}), .sin(xin[3]),
- .out({out[3]}), .sout(xin[4]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_4_(.hcl(dcl), .in({in[4]}), .sin(xin[4]),
- .out({out[4]}), .sout(xin[5]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_5_(.hcl(dcl), .in({in[5]}), .sin(xin[5]),
- .out({out[5]}), .sout(xin[6]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_6_(.hcl(dcl), .in({in[6]}), .sin(xin[6]),
- .out({out[6]}), .sout(xin[7]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_7_(.hcl(dcl), .in({in[7]}), .sin(xin[7]),
- .out({out[7]}), .sout(xin[8]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_8_(.hcl(dcl), .in({in[8]}), .sin(xin[8]),
- .out({out[8]}), .sout(xin[9]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_9_(.hcl(dcl), .in({in[9]}), .sin(xin[9]),
- .out({out[9]}), .sout(xin[10]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_10_(.hcl(dcl), .in({in[10]}), .sin(xin[10]),
- .out({out[10]}), .sout(xin[11]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_11_(.hcl(dcl), .in({in[11]}), .sin(xin[11]),
- .out({out[11]}), .sout(xin[12]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_12_(.hcl(dcl), .in({in[12]}), .sin(xin[12]),
- .out({out[12]}), .sout(xin[13]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_13_(.hcl(dcl), .in({in[13]}), .sin(xin[13]),
- .out({out[13]}), .sout(xin[14]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_14_(.hcl(dcl), .in({in[14]}), .sin(xin[14]),
- .out({out[14]}), .sout(xin[15]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_15_(.hcl(dcl), .in({in[15]}), .sin(xin[15]),
- .out({out[15]}), .sout(xin[16]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_16_(.hcl(dcl), .in({in[16]}), .sin(xin[16]),
- .out({out[16]}), .sout(xin[17]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_17_(.hcl(dcl), .in({in[17]}), .sin(xin[17]),
- .out({out[17]}), .sout(xin[18]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
- latchGroupsK__latchWscM2 la_18_(.hcl(dcl), .in({in[18]}), .sin(xin[18]),
- .out({out[18]}), .sout(sout), .p1p(p1p), .p2p(p2p), .rd(rd),
- .wr(wr_D_));
-endmodule /* registersM__data1in60Cx18scan */
-
-module centersJ__ctrAND3in30(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_19, net_6, net_9;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_19, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (out, net_9);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_9, net_19, net_6);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_0 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
- orangeTSMC090nm__wire90 wire90_1(.a(net_9));
- orangeTSMC090nm__wire90 wire90_2(.a(net_19));
-endmodule /* centersJ__ctrAND3in30 */
-
-module centersJ__ctrAND3in100A(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_19, net_6, net_9;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_19, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (out, net_9);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_9, net_19, net_6);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_0 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
- orangeTSMC090nm__wire90 wire90_1(.a(net_9));
- orangeTSMC090nm__wire90 wire90_2(.a(net_19));
-endmodule /* centersJ__ctrAND3in100A */
-
-module gaspM__fillScanControl(wr_A_, wr_D_, si, so);
- output wr_A_;
- output wr_D_;
- inout [1:9] si;
- inout [1:1] so;
-
- supply1 vdd;
- supply0 gnd;
- wire net_4;
- wire [1:1] scanCell_2_dIn;
- wire [1:1] scanCell_3_dIn;
-
- driversM__dataDriver60 dataDriv_2(.inA(so[1]), .inB(si[4]), .out(wr_D_));
- driversM__dataDriver60 dataDriv_3(.inA(net_4), .inB(si[4]), .out(wr_A_));
- scanM__scanCellE scanCell_2(.dIn(scanCell_2_dIn[1:1]), .p1p(si[3]),
- .p2p(si[2]), .rd(si[5]), .sin(si[1]), .sout(net_4));
- scanM__scanCellE scanCell_3(.dIn(scanCell_3_dIn[1:1]), .p1p(si[3]),
- .p2p(si[2]), .rd(si[5]), .sin(net_4), .sout(so[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_4));
- orangeTSMC090nm__wire90 wire90_1(.a(si[4]));
-endmodule /* gaspM__fillScanControl */
-
-module driversM__latchDriver60(in, out);
- input in;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_16;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_16, in);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (out, net_16);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_16));
-endmodule /* driversM__latchDriver60 */
-
-module driversM__sucORdri60(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_51), .g2(net_71), .d(succ));
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_0 (net_51, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__sucORdri60 */
-
-module gaspM__gaspFill(block, fill, pred, fire, s, succ, take, wr_A_, wr_D_,
- si, so);
- input block;
- input fill;
- input pred;
- output fire;
- output [1:2] s;
- output succ;
- output take;
- output wr_A_;
- output wr_D_;
- inout [1:9] si;
- inout [1:1] so;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_B_, net_454, net_537;
-
- centersJ__ctrAND3in30 ctrAND3i_1(.inA(net_537), .inB(succ), .inC(fire),
- .out(fire_B_));
- centersJ__ctrAND3in100A ctrAND3i_3(.inA(net_454), .inB(succ), .inC(block),
- .out(fire));
- gaspM__fillScanControl fillScan_1(.wr_A_(wr_A_), .wr_D_(wr_D_), .si(si[1:9]),
- .so(so[1:1]));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_454, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_537, fill);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_454);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (s[2], net_537);
- // end Verilog_template
- driversM__latchDriver60 latchDri_1(.in(fire), .out(take));
- driversM__predDri60wMC predDri6_2(.in(fire), .mc(si[9]), .pred(pred));
- driversM__sucORdri60 sucORdri_2(.inA(fire), .inB(fire_B_), .succ(succ));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- orangeTSMC090nm__wire90 wire90_1(.a(net_537));
- orangeTSMC090nm__wire90 wire90_12(.a(net_454));
- orangeTSMC090nm__wire90 wire90_15(.a(fire_B_));
-endmodule /* gaspM__gaspFill */
-
-module scanM__scanAmp(in, out);
- inout [1:1] in;
- inout [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_1;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_1, in[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (out[1], net_1);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_1));
-endmodule /* scanM__scanAmp */
-
-module scanM__scanAMPx5(si, so);
- input [1:9] si;
- output [1:5] so;
-
- supply1 vdd;
- supply0 gnd;
- scanM__scanAmp sa_1_(.in({si[1]}), .out({so[1]}));
- scanM__scanAmp sa_2_(.in({si[2]}), .out({so[2]}));
- scanM__scanAmp sa_3_(.in({si[3]}), .out({so[3]}));
- scanM__scanAmp sa_4_(.in({si[4]}), .out({so[4]}));
- scanM__scanAmp sa_5_(.in({si[5]}), .out({so[5]}));
-endmodule /* scanM__scanAMPx5 */
-
-module scanM__scanFx3(dout, dout_1, dout_2, sic, soc);
- output [1:1] dout;
- output [2:2] dout_1;
- output [3:3] dout_2;
- inout [1:9] sic;
- inout [1:1] soc;
-
- supply1 vdd;
- supply0 gnd;
- wire net_30, net_31;
-
- scanM__scanCellF scanCell_4(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(sic[1]), .wr(sic[4]), .dout(dout[1:1]),
- .sout(net_30));
- scanM__scanCellF scanCell_5(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_30), .wr(sic[4]), .dout(dout_1[2:2]),
- .sout(net_31));
- scanM__scanCellF scanCell_6(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_31), .wr(sic[4]), .dout(dout_2[3:3]),
- .sout(soc[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_30));
- orangeTSMC090nm__wire90 wire90_1(.a(net_31));
-endmodule /* scanM__scanFx3 */
-
-module stagesM__fillStage(ain, ain_TT_, \in[1] , \in[2] , \in[3] , \in[4] ,
- \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12]
- , \in[13] , \in[14] , \in[15] , \in[16] , \in[17] , \in[18] , \in[20] ,
- \in[21] , \in[22] , \in[23] , \in[24] , \in[25] , \in[26] , \in[27] ,
- \in[28] , \in[29] , \in[30] , \in[31] , \in[32] , \in[33] , \in[34] ,
- \in[35] , \in[36] , \in[37] , in_1, pred, aout, aout_TT_, extra, fire,
- \out[1] , \out[2] , \out[3] , \out[4] , \out[5] , \out[6] , \out[7] ,
- \out[8] , \out[9] , \out[10] , \out[11] , \out[12] , \out[13] , \out[14]
- , \out[15] , \out[16] , \out[17] , \out[18] , \out[20] , \out[21] ,
- \out[22] , \out[23] , \out[24] , \out[25] , \out[26] , \out[27] ,
- \out[28] , \out[29] , \out[30] , \out[31] , \out[32] , \out[33] ,
- \out[34] , \out[35] , \out[36] , \out[37] , out_1, succ, sic, sid, sir,
- soc, sod, sor);
- input [1:14] ain;
- input ain_TT_;
- input \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] ,
- \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , \in[15] ,
- \in[16] , \in[17] , \in[18] , \in[20] , \in[21] , \in[22] , \in[23] ,
- \in[24] , \in[25] , \in[26] , \in[27] , \in[28] , \in[29] , \in[30] ,
- \in[31] , \in[32] , \in[33] , \in[34] , \in[35] , \in[36] , \in[37] ;
- input [19:19] in_1;
- input pred;
- output [1:14] aout;
- output aout_TT_;
- output extra;
- output fire;
- output \out[1] , \out[2] , \out[3] , \out[4] , \out[5] , \out[6] , \out[7] ,
- \out[8] , \out[9] , \out[10] , \out[11] , \out[12] , \out[13] , \out[14]
- , \out[15] , \out[16] , \out[17] , \out[18] , \out[20] , \out[21] ,
- \out[22] , \out[23] , \out[24] , \out[25] , \out[26] , \out[27] ,
- \out[28] , \out[29] , \out[30] , \out[31] , \out[32] , \out[33] ,
- \out[34] , \out[35] , \out[36] , \out[37] ;
- output [19:19] out_1;
- output succ;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire block, fill, net_0, net_61, net_62, net_64, net_65, net_66, sx_A_, sx_D_;
- wire [8:8] net_139;
- wire [8:8] net_142;
- wire [1:2] s;
- wire [1:5] sx;
- wire [1:1] sy;
- wire [1:1] sz;
-
- registersM__addr1in60Cx7scan addr1in6_0(.ain(ain[1:7]), .fire(fire),
- .sin(net_61), .aout(aout[1:7]), .sout(net_62), .p1p(sx[3]), .p2p(sx[2]),
- .rd(sx[5]), .wr_A_(sx_A_));
- registersM__addr1in60Cx7scan addr1in6_1(.ain(ain[8:14]), .fire(fire),
- .sin(net_62), .aout(aout[8:14]), .sout(net_66), .p1p(sx[3]), .p2p(sx[2]),
- .rd(sx[5]), .wr_A_(sx_A_));
- registersM__data1in60Cx18scan data1in6_0(.dcl(net_0), .in({ \in[1] , \in[2]
- , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] ,
- \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , \in[15] , \in[16]
- , \in[17] , \in[18] }), .sin(net_66), .out({ \out[1] , \out[2] ,
- \out[3] , \out[4] , \out[5] , \out[6] , \out[7] , \out[8] , \out[9]
- , \out[10] , \out[11] , \out[12] , \out[13] , \out[14] , \out[15] ,
- \out[16] , \out[17] , \out[18] }), .sout(net_65), .p1p(sx[3]),
- .p2p(sx[2]), .rd(sx[5]), .wr_D_(sx_D_));
- registersM__data1in60Cx18scan data1in6_1(.dcl(net_0), .in({ \in[20] ,
- \in[21] , \in[22] , \in[23] , \in[24] , \in[25] , \in[26] , \in[27]
- , \in[28] , \in[29] , \in[30] , \in[31] , \in[32] , \in[33] ,
- \in[34] , \in[35] , \in[36] , \in[37] }), .sin(net_64), .out({
- \out[20] , \out[21] , \out[22] , \out[23] , \out[24] , \out[25] ,
- \out[26] , \out[27] , \out[28] , \out[29] , \out[30] , \out[31] ,
- \out[32] , \out[33] , \out[34] , \out[35] , \out[36] , \out[37] }),
- .sout(sz[1]), .p1p(sx[3]), .p2p(sx[2]), .rd(sx[5]), .wr_D_(sx_D_));
- gaspM__gaspFill gaspFill_0(.block(block), .fill(fill), .pred(pred),
- .fire(fire), .s(s[1:2]), .succ(succ), .take(net_0), .wr_A_(sx_A_),
- .wr_D_(sx_D_), .si({sx[1], sx[2], sx[3], sx[4], sx[5], sid[6], sid[7],
- sid[8], sid[9]}), .so(sy[1:1]));
- latchGroupsK__latchWscM2 latchWsc_0(.hcl(net_0), .in(in_1[19:19]),
- .sin(net_65), .out(out_1[19:19]), .sout(net_64), .p1p(sx[3]),
- .p2p(sx[2]), .rd(sx[5]), .wr(sx_D_));
- latchGroupsK__latchWscM2 latchWsc_1(.hcl(fire), .in({ain_TT_}), .sin(sy[1]),
- .out({aout_TT_}), .sout(net_61), .p1p(sx[3]), .p2p(sx[2]), .rd(sx[5]),
- .wr(sx_A_));
- scanM__scanAMPx5 scanAMPx_2(.si(sid[1:9]), .so(sx[1:5]));
- scanM__scanAMPx5 scanAMPx_3(.si({sz[1], sx[2], sx[3], sx[4], sx[5], sid[6],
- sid[7], sid[8], sid[9]}), .so(sod[1:5]));
- scanM__scanAMPx5 scanAMPx_4(.si(sic[1:9]), .so({net_139[8], soc[2], soc[3],
- soc[4], soc[5]}));
- scanM__scanAMPx5 scanAMPx_5(.si(sir[1:9]), .so({net_142[8], sor[2], sor[3],
- sor[4], sor[5]}));
- scanM__scanEx2 scanEx2_0(.dIn(s[1:2]), .sir({net_142[8], sor[2], sor[3],
- sor[4], sor[5], sir[6], sir[7], sir[8], sir[9]}), .sor(sor[1:1]));
- scanM__scanFx3 scanFx3_0(.dout({block}), .dout_1({extra}), .dout_2({fill}),
- .sic({net_139[8], soc[2], soc[3], soc[4], soc[5], sic[6], sic[7], sic[8],
- sic[9]}), .soc(soc[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- orangeTSMC090nm__wire90 wire90_1(.a(net_0));
- orangeTSMC090nm__wire90 wire90_3(.a(fire));
- orangeTSMC090nm__wire90 wire90_4(.a(net_0));
- orangeTSMC090nm__wire90 wire90_5(.a(fire));
-endmodule /* stagesM__fillStage */
-
-module stageGroupsM__properStopper(ain, ain_TT_, in, pred, aout, aout_TT_,
- extra, fire, out, succ, sic, sid, sir, soc, sod, sor);
- input [14:1] ain;
- input ain_TT_;
- input [37:1] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output extra;
- output fire;
- output [37:1] out;
- output succ;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_41;
- wire [8:8] net_2;
- wire [8:8] net_3;
- wire [51:0] net_65;
-
- stagesM__drainStage drainSta_1(.ain({net_65[37], net_65[38], net_65[39],
- net_65[40], net_65[41], net_65[42], net_65[43], net_65[44], net_65[45],
- net_65[46], net_65[47], net_65[48], net_65[49], net_65[50]}),
- .ain_TT_(net_65[51]), .in({net_65[36], net_65[35], net_65[34],
- net_65[33], net_65[32], net_65[31], net_65[30], net_65[29], net_65[28],
- net_65[27], net_65[26], net_65[25], net_65[24], net_65[23], net_65[22],
- net_65[21], net_65[20], net_65[19], net_65[18], net_65[17], net_65[16],
- net_65[15], net_65[14], net_65[13], net_65[12], net_65[11], net_65[10],
- net_65[9], net_65[8], net_65[7], net_65[6], net_65[5], net_65[4],
- net_65[3], net_65[2], net_65[1], net_65[0]}), .pred(net_41),
- .aout(aout[14:1]), .aout_TT_(aout_TT_), .out({out[1], out[2], out[3],
- out[4], out[5], out[6], out[7], out[8], out[9], out[10], out[11],
- out[12], out[13], out[14], out[15], out[16], out[17], out[18], out[19],
- out[20], out[21], out[22], out[23], out[24], out[25], out[26], out[27],
- out[28], out[29], out[30], out[31], out[32], out[33], out[34], out[35],
- out[36], out[37]}), .succ(succ), .sic({net_3[8], soc[2], soc[3], soc[4],
- soc[5], sic[6], sic[7], sic[8], sic[9]}), .sir({net_2[8], sor[2], sor[3],
- sor[4], sor[5], sir[6], sir[7], sir[8], sir[9]}), .soc(soc[1:1]),
- .sor(sor[1:1]));
- stagesM__fillStage fillStag_1(.ain({ain[1], ain[2], ain[3], ain[4], ain[5],
- ain[6], ain[7], ain[8], ain[9], ain[10], ain[11], ain[12], ain[13],
- ain[14]}), .ain_TT_(ain_TT_), .\in[1] (in[1]), .\in[2] (in[2]), .\in[3]
- (in[3]), .\in[4] (in[4]), .\in[5] (in[5]), .\in[6] (in[6]), .\in[7]
- (in[7]), .\in[8] (in[8]), .\in[9] (in[9]), .\in[10] (in[10]), .\in[11]
- (in[11]), .\in[12] (in[12]), .\in[13] (in[13]), .\in[14] (in[14]),
- .\in[15] (in[15]), .\in[16] (in[16]), .\in[17] (in[17]), .\in[18]
- (in[18]), .\in[20] (in[20]), .\in[21] (in[21]), .\in[22] (in[22]),
- .\in[23] (in[23]), .\in[24] (in[24]), .\in[25] (in[25]), .\in[26]
- (in[26]), .\in[27] (in[27]), .\in[28] (in[28]), .\in[29] (in[29]),
- .\in[30] (in[30]), .\in[31] (in[31]), .\in[32] (in[32]), .\in[33]
- (in[33]), .\in[34] (in[34]), .\in[35] (in[35]), .\in[36] (in[36]),
- .\in[37] (in[37]), .in_1(in[19:19]), .pred(pred), .aout({net_65[50],
- net_65[49], net_65[48], net_65[47], net_65[46], net_65[45], net_65[44],
- net_65[43], net_65[42], net_65[41], net_65[40], net_65[39], net_65[38],
- net_65[37]}), .aout_TT_(net_65[51]), .extra(extra), .fire(fire), .\out[1]
- (net_65[36]), .\out[2] (net_65[35]), .\out[3] (net_65[34]), .\out[4]
- (net_65[33]), .\out[5] (net_65[32]), .\out[6] (net_65[31]), .\out[7]
- (net_65[30]), .\out[8] (net_65[29]), .\out[9] (net_65[28]), .\out[10]
- (net_65[27]), .\out[11] (net_65[26]), .\out[12] (net_65[25]), .\out[13]
- (net_65[24]), .\out[14] (net_65[23]), .\out[15] (net_65[22]), .\out[16]
- (net_65[21]), .\out[17] (net_65[20]), .\out[18] (net_65[19]), .\out[20]
- (net_65[17]), .\out[21] (net_65[16]), .\out[22] (net_65[15]), .\out[23]
- (net_65[14]), .\out[24] (net_65[13]), .\out[25] (net_65[12]), .\out[26]
- (net_65[11]), .\out[27] (net_65[10]), .\out[28] (net_65[9]), .\out[29]
- (net_65[8]), .\out[30] (net_65[7]), .\out[31] (net_65[6]), .\out[32]
- (net_65[5]), .\out[33] (net_65[4]), .\out[34] (net_65[3]), .\out[35]
- (net_65[2]), .\out[36] (net_65[1]), .\out[37] (net_65[0]),
- .out_1(net_65[18:18]), .succ(net_41), .sic(sic[1:9]), .sid(sid[1:9]),
- .sir(sir[1:9]), .soc({net_3[8], soc[2], soc[3], soc[4], soc[5]}),
- .sod(sod[1:5]), .sor({net_2[8], sor[2], sor[3], sor[4], sor[5]}));
- orangeTSMC090nm__wire90 wire90_0(.a(net_41));
-endmodule /* stageGroupsM__properStopper */
-
-module stageGroupsM__fillDrainCount(ain, ain_TT_, fin, in, pred, aout,
- aout_TT_, fout, out, succ, sic, sid, sir, soc, sod, sor);
- input [14:1] ain;
- input ain_TT_;
- input fin;
- input [37:1] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output fout;
- output [37:1] out;
- output succ;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_48, net_53;
- wire [8:8] net_61;
-
- countersL__instructionCount instruct_0(.cin(net_53), .count(net_48),
- .fin(fin), .fout(fout), .sid({net_61[8], sod[2], sod[3], sod[4], sod[5],
- sid[6], sid[7], sid[8], sid[9]}), .sod(sod[1:1]));
- stageGroupsM__properStopper properSt_1(.ain(ain[14:1]), .ain_TT_(ain_TT_),
- .in(in[37:1]), .pred(pred), .aout(aout[14:1]), .aout_TT_(aout_TT_),
- .extra(net_48), .fire(net_53), .out(out[37:1]), .succ(succ),
- .sic(sic[1:9]), .sid(sid[1:9]), .sir(sir[1:9]), .soc(soc[1:5]),
- .sod({net_61[8], sod[2], sod[3], sod[4], sod[5]}), .sor(sor[1:5]));
- orangeTSMC090nm__wire90 wire90_1(.a(net_48));
-endmodule /* stageGroupsM__fillDrainCount */
-
-module scanM__scanCap(si);
- inout [4:9] si;
-
-endmodule /* scanM__scanCap */
-
-module latchPartsK__latchPointT(hcl, in, x_F_, x_T_);
- input hcl;
- input [1:1] in;
- output x_F_;
- output x_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- orangeTSMC090nm__NMOSx PMOSx_0(.g(hcl), .d(in[1]), .s(x_T_));
- orangeTSMC090nm__NMOSx PMOSx_1(.g(hcl), .d(net_8), .s(x_F_));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_8, in[1]);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
-endmodule /* latchPartsK__latchPointT */
-
-module latchesK__raw1inLatchT(hcl_A_, inA, out_T_);
- input hcl_A_;
- input [1:1] inA;
- output out_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_7;
-
- latchPartsK__latchKeep latchFlo_0(.out_B_(out_T_), .out_s_(net_7));
- latchPartsK__latchPointT latchPoi_0(.hcl(hcl_A_), .in(inA[1:1]),
- .x_F_(net_7), .x_T_(out_T_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_7));
-endmodule /* latchesK__raw1inLatchT */
-
-module latchesK__latch1in20B(hcl, in, out);
- input hcl;
- input [1:1] in;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_23;
-
- latchesK__raw1inLatchT hi2inLat_0(.hcl_A_(hcl), .inA(in[1:1]),
- .out_T_(net_18));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out[1], net_23);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_23, net_18);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
- orangeTSMC090nm__wire90 wire90_1(.a(net_23));
-endmodule /* latchesK__latch1in20B */
-
-module registersM__addr1in20Bx7(ain, fire, aout);
- input [1:7] ain;
- input fire;
- output [1:7] aout;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch1in20B lat_1_(.hcl(fire), .in({ain[1]}), .out({aout[1]}));
- latchesK__latch1in20B lat_2_(.hcl(fire), .in({ain[2]}), .out({aout[2]}));
- latchesK__latch1in20B lat_3_(.hcl(fire), .in({ain[3]}), .out({aout[3]}));
- latchesK__latch1in20B lat_4_(.hcl(fire), .in({ain[4]}), .out({aout[4]}));
- latchesK__latch1in20B lat_5_(.hcl(fire), .in({ain[5]}), .out({aout[5]}));
- latchesK__latch1in20B lat_6_(.hcl(fire), .in({ain[6]}), .out({aout[6]}));
- latchesK__latch1in20B lat_7_(.hcl(fire), .in({ain[7]}), .out({aout[7]}));
-endmodule /* registersM__addr1in20Bx7 */
-
-module registersM__addr1in20Bx15(ain, ain_TT_, fire, aout, aout_TT_);
- input [1:14] ain;
- input ain_TT_;
- input fire;
- output [1:14] aout;
- output aout_TT_;
-
- supply1 vdd;
- supply0 gnd;
- registersM__addr1in20Bx7 addr1in2_1(.ain(ain[8:14]), .fire(fire),
- .aout(aout[8:14]));
- registersM__addr1in20Bx7 addr1in2_2(.ain(ain[1:7]), .fire(fire),
- .aout(aout[1:7]));
- latchesK__latch1in20B latch1in_1(.hcl(fire), .in({ain_TT_}),
- .out({aout_TT_}));
- orangeTSMC090nm__wire90 wire90_0(.a(fire));
- orangeTSMC090nm__wire90 wire90_1(.a(fire));
-endmodule /* registersM__addr1in20Bx15 */
-
-module registersM__ins1in20Bx18(hcl, in, out);
- input hcl;
- input [1:18] in;
- output [1:18] out;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch1in20B lx_1_(.hcl(hcl), .in({in[1]}), .out({out[1]}));
- latchesK__latch1in20B lx_2_(.hcl(hcl), .in({in[2]}), .out({out[2]}));
- latchesK__latch1in20B lx_3_(.hcl(hcl), .in({in[3]}), .out({out[3]}));
- latchesK__latch1in20B lx_4_(.hcl(hcl), .in({in[4]}), .out({out[4]}));
- latchesK__latch1in20B lx_5_(.hcl(hcl), .in({in[5]}), .out({out[5]}));
- latchesK__latch1in20B lx_6_(.hcl(hcl), .in({in[6]}), .out({out[6]}));
- latchesK__latch1in20B lx_7_(.hcl(hcl), .in({in[7]}), .out({out[7]}));
- latchesK__latch1in20B lx_8_(.hcl(hcl), .in({in[8]}), .out({out[8]}));
- latchesK__latch1in20B lx_9_(.hcl(hcl), .in({in[9]}), .out({out[9]}));
- latchesK__latch1in20B lx_10_(.hcl(hcl), .in({in[10]}), .out({out[10]}));
- latchesK__latch1in20B lx_11_(.hcl(hcl), .in({in[11]}), .out({out[11]}));
- latchesK__latch1in20B lx_12_(.hcl(hcl), .in({in[12]}), .out({out[12]}));
- latchesK__latch1in20B lx_13_(.hcl(hcl), .in({in[13]}), .out({out[13]}));
- latchesK__latch1in20B lx_14_(.hcl(hcl), .in({in[14]}), .out({out[14]}));
- latchesK__latch1in20B lx_15_(.hcl(hcl), .in({in[15]}), .out({out[15]}));
- latchesK__latch1in20B lx_16_(.hcl(hcl), .in({in[16]}), .out({out[16]}));
- latchesK__latch1in20B lx_17_(.hcl(hcl), .in({in[17]}), .out({out[17]}));
- latchesK__latch1in20B lx_18_(.hcl(hcl), .in({in[18]}), .out({out[18]}));
-endmodule /* registersM__ins1in20Bx18 */
-
-module registersM__data1in20Bx37(in, take, out);
- input [1:37] in;
- input take;
- output [1:37] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__ins1in20Bx18 ins1in20_0(.hcl(take), .in(in[20:37]),
- .out(out[20:37]));
- registersM__ins1in20Bx18 ins1in20_1(.hcl(take), .in(in[1:18]),
- .out(out[1:18]));
- latchesK__latch1in20B latch1in_1(.hcl(take), .in({in[19]}),
- .out({out[19]}));
- orangeTSMC090nm__wire90 wire90_2(.a(take));
- orangeTSMC090nm__wire90 wire90_3(.a(take));
-endmodule /* registersM__data1in20Bx37 */
-
-module driversM__predDri20wMC(in, mc, pred);
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(in), .d(pred), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(pred), .s(gnd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_145, pred);
- // end Verilog_template
- redFive__pms3 pms3_0(.g(net_145), .g2(in), .g3(mc), .d(pred));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
-endmodule /* driversM__predDri20wMC */
-
-module redFive__pms1(g, d);
- input g;
- output d;
-
- supply1 vdd;
- orangeTSMC090nm__PMOSx PMOS_0(.g(g), .d(d), .s(vdd));
-endmodule /* redFive__pms1 */
-
-module driversM__sucDri20(in, succ);
- input in;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_109, net_94;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_94, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_109, in);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_94), .g2(net_109), .d(succ));
- redFive__pms1 pms1_0(.g(net_109), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_94));
- orangeTSMC090nm__wire90 wire90_1(.a(net_109));
-endmodule /* driversM__sucDri20 */
-
-module gaspM__gaspWeak(mc, pred, tok, fire, s, succ, take);
- input mc;
- input pred;
- input tok;
- output fire;
- output [1:1] s;
- output succ;
- output take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- centersJ__ctrAND2in100LT ctrAND2i_0(.inA(net_8), .inB(succ), .out(fire));
- driversM__dataDriver60 dataDriv_0(.inA(tok), .inB(fire), .out(take));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_8, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_8);
- // end Verilog_template
- driversM__predDri20wMC predDri2_0(.in(fire), .mc(mc), .pred(pred));
- driversM__sucDri20 sucDri20_0(.in(fire), .succ(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
- orangeTSMC090nm__wire90 wire90_1(.a(fire));
-endmodule /* gaspM__gaspWeak */
-
-module scanM__scanEx1(dIn, sir, sor);
- input [1:1] dIn;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- scanM__scanCellE scanCell_1(.dIn(dIn[1:1]), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(sir[1]), .sout(sor[1]));
-endmodule /* scanM__scanEx1 */
-
-module stagesM__weakStage(ain, ain_TT_, in, pred, aout, aout_TT_, out, succ,
- sir, sor);
- input [14:1] ain;
- input ain_TT_;
- input [1:37] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output [1:37] out;
- output succ;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_39, net_47, net_59;
-
- registersM__addr1in20Bx15 addr1in2_0(.ain({ain[1], ain[2], ain[3], ain[4],
- ain[5], ain[6], ain[7], ain[8], ain[9], ain[10], ain[11], ain[12],
- ain[13], ain[14]}), .ain_TT_(ain_TT_), .fire(net_59), .aout({aout[1],
- aout[2], aout[3], aout[4], aout[5], aout[6], aout[7], aout[8], aout[9],
- aout[10], aout[11], aout[12], aout[13], aout[14]}),
- .aout_TT_(aout_TT_));
- registersM__data1in20Bx37 data1in2_0(.in(in[1:37]), .take(net_47),
- .out(out[1:37]));
- gaspM__gaspWeak gaspWeak_0(.mc(sir[9]), .pred(pred), .tok(ain_TT_),
- .fire(net_59), .s({net_39}), .succ(succ), .take(net_47));
- scanM__scanEx1 scanEx1_0(.dIn({net_39}), .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
-endmodule /* stagesM__weakStage */
-
-module stageGroupsM__upDown8weak(ainD, ainD_TT_, ainU, ainU_TT_, inD, inU,
- predD, predU, aoutD, aoutD_TT_, aoutU, aoutU_TT_, outD, outU, succD,
- succU, sir, sor);
- input [14:1] ainD;
- input ainD_TT_;
- input [14:1] ainU;
- input ainU_TT_;
- input [37:1] inD;
- input [37:1] inU;
- input predD;
- input predU;
- output [14:1] aoutD;
- output aoutD_TT_;
- output [14:1] aoutU;
- output aoutU_TT_;
- output [37:1] outD;
- output [37:1] outU;
- output succD;
- output succU;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_28, net_43, net_50, net_52, net_62, net_64;
- wire [8:8] net_117;
- wire [8:8] net_120;
- wire [8:8] net_123;
- wire [8:8] net_126;
- wire [8:8] net_129;
- wire [8:8] net_132;
- wire [8:8] net_135;
- wire [51:0] net_189;
- wire [51:0] net_190;
- wire [51:0] net_191;
- wire [51:0] net_192;
- wire [51:0] net_193;
- wire [51:0] net_194;
-
- stagesM__weakStage weakStag_18(.ain(ainU[14:1]), .ain_TT_(ainU_TT_),
- .in({inU[1], inU[2], inU[3], inU[4], inU[5], inU[6], inU[7], inU[8],
- inU[9], inU[10], inU[11], inU[12], inU[13], inU[14], inU[15], inU[16],
- inU[17], inU[18], inU[19], inU[20], inU[21], inU[22], inU[23], inU[24],
- inU[25], inU[26], inU[27], inU[28], inU[29], inU[30], inU[31], inU[32],
- inU[33], inU[34], inU[35], inU[36], inU[37]}), .pred(predU),
- .aout({net_189[37], net_189[38], net_189[39], net_189[40], net_189[41],
- net_189[42], net_189[43], net_189[44], net_189[45], net_189[46],
- net_189[47], net_189[48], net_189[49], net_189[50]}),
- .aout_TT_(net_189[51]), .out({net_189[36], net_189[35], net_189[34],
- net_189[33], net_189[32], net_189[31], net_189[30], net_189[29],
- net_189[28], net_189[27], net_189[26], net_189[25], net_189[24],
- net_189[23], net_189[22], net_189[21], net_189[20], net_189[19],
- net_189[18], net_189[17], net_189[16], net_189[15], net_189[14],
- net_189[13], net_189[12], net_189[11], net_189[10], net_189[9],
- net_189[8], net_189[7], net_189[6], net_189[5], net_189[4], net_189[3],
- net_189[2], net_189[1], net_189[0]}), .succ(net_28), .sir(sir[1:9]),
- .sor({net_117[8]}));
- stagesM__weakStage weakStag_19(.ain({net_189[37], net_189[38], net_189[39],
- net_189[40], net_189[41], net_189[42], net_189[43], net_189[44],
- net_189[45], net_189[46], net_189[47], net_189[48], net_189[49],
- net_189[50]}), .ain_TT_(net_189[51]), .in({net_189[36], net_189[35],
- net_189[34], net_189[33], net_189[32], net_189[31], net_189[30],
- net_189[29], net_189[28], net_189[27], net_189[26], net_189[25],
- net_189[24], net_189[23], net_189[22], net_189[21], net_189[20],
- net_189[19], net_189[18], net_189[17], net_189[16], net_189[15],
- net_189[14], net_189[13], net_189[12], net_189[11], net_189[10],
- net_189[9], net_189[8], net_189[7], net_189[6], net_189[5], net_189[4],
- net_189[3], net_189[2], net_189[1], net_189[0]}), .pred(net_28),
- .aout({net_190[37], net_190[38], net_190[39], net_190[40], net_190[41],
- net_190[42], net_190[43], net_190[44], net_190[45], net_190[46],
- net_190[47], net_190[48], net_190[49], net_190[50]}),
- .aout_TT_(net_190[51]), .out({net_190[36], net_190[35], net_190[34],
- net_190[33], net_190[32], net_190[31], net_190[30], net_190[29],
- net_190[28], net_190[27], net_190[26], net_190[25], net_190[24],
- net_190[23], net_190[22], net_190[21], net_190[20], net_190[19],
- net_190[18], net_190[17], net_190[16], net_190[15], net_190[14],
- net_190[13], net_190[12], net_190[11], net_190[10], net_190[9],
- net_190[8], net_190[7], net_190[6], net_190[5], net_190[4], net_190[3],
- net_190[2], net_190[1], net_190[0]}), .succ(net_62), .sir({net_120[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor({net_123[8]}));
- stagesM__weakStage weakStag_20(.ain({net_190[37], net_190[38], net_190[39],
- net_190[40], net_190[41], net_190[42], net_190[43], net_190[44],
- net_190[45], net_190[46], net_190[47], net_190[48], net_190[49],
- net_190[50]}), .ain_TT_(net_190[51]), .in({net_190[36], net_190[35],
- net_190[34], net_190[33], net_190[32], net_190[31], net_190[30],
- net_190[29], net_190[28], net_190[27], net_190[26], net_190[25],
- net_190[24], net_190[23], net_190[22], net_190[21], net_190[20],
- net_190[19], net_190[18], net_190[17], net_190[16], net_190[15],
- net_190[14], net_190[13], net_190[12], net_190[11], net_190[10],
- net_190[9], net_190[8], net_190[7], net_190[6], net_190[5], net_190[4],
- net_190[3], net_190[2], net_190[1], net_190[0]}), .pred(net_62),
- .aout({net_191[37], net_191[38], net_191[39], net_191[40], net_191[41],
- net_191[42], net_191[43], net_191[44], net_191[45], net_191[46],
- net_191[47], net_191[48], net_191[49], net_191[50]}),
- .aout_TT_(net_191[51]), .out({net_191[36], net_191[35], net_191[34],
- net_191[33], net_191[32], net_191[31], net_191[30], net_191[29],
- net_191[28], net_191[27], net_191[26], net_191[25], net_191[24],
- net_191[23], net_191[22], net_191[21], net_191[20], net_191[19],
- net_191[18], net_191[17], net_191[16], net_191[15], net_191[14],
- net_191[13], net_191[12], net_191[11], net_191[10], net_191[9],
- net_191[8], net_191[7], net_191[6], net_191[5], net_191[4], net_191[3],
- net_191[2], net_191[1], net_191[0]}), .succ(net_64), .sir({net_126[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor({net_129[8]}));
- stagesM__weakStage weakStag_21(.ain({net_191[37], net_191[38], net_191[39],
- net_191[40], net_191[41], net_191[42], net_191[43], net_191[44],
- net_191[45], net_191[46], net_191[47], net_191[48], net_191[49],
- net_191[50]}), .ain_TT_(net_191[51]), .in({net_191[36], net_191[35],
- net_191[34], net_191[33], net_191[32], net_191[31], net_191[30],
- net_191[29], net_191[28], net_191[27], net_191[26], net_191[25],
- net_191[24], net_191[23], net_191[22], net_191[21], net_191[20],
- net_191[19], net_191[18], net_191[17], net_191[16], net_191[15],
- net_191[14], net_191[13], net_191[12], net_191[11], net_191[10],
- net_191[9], net_191[8], net_191[7], net_191[6], net_191[5], net_191[4],
- net_191[3], net_191[2], net_191[1], net_191[0]}), .pred(net_64),
- .aout(aoutU[14:1]), .aout_TT_(aoutU_TT_), .out({outU[1], outU[2],
- outU[3], outU[4], outU[5], outU[6], outU[7], outU[8], outU[9], outU[10],
- outU[11], outU[12], outU[13], outU[14], outU[15], outU[16], outU[17],
- outU[18], outU[19], outU[20], outU[21], outU[22], outU[23], outU[24],
- outU[25], outU[26], outU[27], outU[28], outU[29], outU[30], outU[31],
- outU[32], outU[33], outU[34], outU[35], outU[36], outU[37]}),
- .succ(succU), .sir({net_132[8], sir[2], sir[3], sir[4], sir[5], sir[6],
- sir[7], sir[8], sir[9]}), .sor({net_135[8]}));
- stagesM__weakStage weakStag_22(.ain({net_192[37], net_192[38], net_192[39],
- net_192[40], net_192[41], net_192[42], net_192[43], net_192[44],
- net_192[45], net_192[46], net_192[47], net_192[48], net_192[49],
- net_192[50]}), .ain_TT_(net_192[51]), .in({net_192[36], net_192[35],
- net_192[34], net_192[33], net_192[32], net_192[31], net_192[30],
- net_192[29], net_192[28], net_192[27], net_192[26], net_192[25],
- net_192[24], net_192[23], net_192[22], net_192[21], net_192[20],
- net_192[19], net_192[18], net_192[17], net_192[16], net_192[15],
- net_192[14], net_192[13], net_192[12], net_192[11], net_192[10],
- net_192[9], net_192[8], net_192[7], net_192[6], net_192[5], net_192[4],
- net_192[3], net_192[2], net_192[1], net_192[0]}), .pred(net_50),
- .aout(aoutD[14:1]), .aout_TT_(aoutD_TT_), .out({outD[1], outD[2],
- outD[3], outD[4], outD[5], outD[6], outD[7], outD[8], outD[9], outD[10],
- outD[11], outD[12], outD[13], outD[14], outD[15], outD[16], outD[17],
- outD[18], outD[19], outD[20], outD[21], outD[22], outD[23], outD[24],
- outD[25], outD[26], outD[27], outD[28], outD[29], outD[30], outD[31],
- outD[32], outD[33], outD[34], outD[35], outD[36], outD[37]}),
- .succ(succD), .sir({net_117[8], sir[2], sir[3], sir[4], sir[5], sir[6],
- sir[7], sir[8], sir[9]}), .sor({net_120[8]}));
- stagesM__weakStage weakStag_23(.ain({net_193[37], net_193[38], net_193[39],
- net_193[40], net_193[41], net_193[42], net_193[43], net_193[44],
- net_193[45], net_193[46], net_193[47], net_193[48], net_193[49],
- net_193[50]}), .ain_TT_(net_193[51]), .in({net_193[36], net_193[35],
- net_193[34], net_193[33], net_193[32], net_193[31], net_193[30],
- net_193[29], net_193[28], net_193[27], net_193[26], net_193[25],
- net_193[24], net_193[23], net_193[22], net_193[21], net_193[20],
- net_193[19], net_193[18], net_193[17], net_193[16], net_193[15],
- net_193[14], net_193[13], net_193[12], net_193[11], net_193[10],
- net_193[9], net_193[8], net_193[7], net_193[6], net_193[5], net_193[4],
- net_193[3], net_193[2], net_193[1], net_193[0]}), .pred(net_43),
- .aout({net_192[37], net_192[38], net_192[39], net_192[40], net_192[41],
- net_192[42], net_192[43], net_192[44], net_192[45], net_192[46],
- net_192[47], net_192[48], net_192[49], net_192[50]}),
- .aout_TT_(net_192[51]), .out({net_192[36], net_192[35], net_192[34],
- net_192[33], net_192[32], net_192[31], net_192[30], net_192[29],
- net_192[28], net_192[27], net_192[26], net_192[25], net_192[24],
- net_192[23], net_192[22], net_192[21], net_192[20], net_192[19],
- net_192[18], net_192[17], net_192[16], net_192[15], net_192[14],
- net_192[13], net_192[12], net_192[11], net_192[10], net_192[9],
- net_192[8], net_192[7], net_192[6], net_192[5], net_192[4], net_192[3],
- net_192[2], net_192[1], net_192[0]}), .succ(net_50), .sir({net_123[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor({net_126[8]}));
- stagesM__weakStage weakStag_24(.ain({net_194[37], net_194[38], net_194[39],
- net_194[40], net_194[41], net_194[42], net_194[43], net_194[44],
- net_194[45], net_194[46], net_194[47], net_194[48], net_194[49],
- net_194[50]}), .ain_TT_(net_194[51]), .in({net_194[36], net_194[35],
- net_194[34], net_194[33], net_194[32], net_194[31], net_194[30],
- net_194[29], net_194[28], net_194[27], net_194[26], net_194[25],
- net_194[24], net_194[23], net_194[22], net_194[21], net_194[20],
- net_194[19], net_194[18], net_194[17], net_194[16], net_194[15],
- net_194[14], net_194[13], net_194[12], net_194[11], net_194[10],
- net_194[9], net_194[8], net_194[7], net_194[6], net_194[5], net_194[4],
- net_194[3], net_194[2], net_194[1], net_194[0]}), .pred(net_52),
- .aout({net_193[37], net_193[38], net_193[39], net_193[40], net_193[41],
- net_193[42], net_193[43], net_193[44], net_193[45], net_193[46],
- net_193[47], net_193[48], net_193[49], net_193[50]}),
- .aout_TT_(net_193[51]), .out({net_193[36], net_193[35], net_193[34],
- net_193[33], net_193[32], net_193[31], net_193[30], net_193[29],
- net_193[28], net_193[27], net_193[26], net_193[25], net_193[24],
- net_193[23], net_193[22], net_193[21], net_193[20], net_193[19],
- net_193[18], net_193[17], net_193[16], net_193[15], net_193[14],
- net_193[13], net_193[12], net_193[11], net_193[10], net_193[9],
- net_193[8], net_193[7], net_193[6], net_193[5], net_193[4], net_193[3],
- net_193[2], net_193[1], net_193[0]}), .succ(net_43), .sir({net_129[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor({net_132[8]}));
- stagesM__weakStage weakStag_25(.ain(ainD[14:1]), .ain_TT_(ainD_TT_),
- .in({inD[1], inD[2], inD[3], inD[4], inD[5], inD[6], inD[7], inD[8],
- inD[9], inD[10], inD[11], inD[12], inD[13], inD[14], inD[15], inD[16],
- inD[17], inD[18], inD[19], inD[20], inD[21], inD[22], inD[23], inD[24],
- inD[25], inD[26], inD[27], inD[28], inD[29], inD[30], inD[31], inD[32],
- inD[33], inD[34], inD[35], inD[36], inD[37]}), .pred(predD),
- .aout({net_194[37], net_194[38], net_194[39], net_194[40], net_194[41],
- net_194[42], net_194[43], net_194[44], net_194[45], net_194[46],
- net_194[47], net_194[48], net_194[49], net_194[50]}),
- .aout_TT_(net_194[51]), .out({net_194[36], net_194[35], net_194[34],
- net_194[33], net_194[32], net_194[31], net_194[30], net_194[29],
- net_194[28], net_194[27], net_194[26], net_194[25], net_194[24],
- net_194[23], net_194[22], net_194[21], net_194[20], net_194[19],
- net_194[18], net_194[17], net_194[16], net_194[15], net_194[14],
- net_194[13], net_194[12], net_194[11], net_194[10], net_194[9],
- net_194[8], net_194[7], net_194[6], net_194[5], net_194[4], net_194[3],
- net_194[2], net_194[1], net_194[0]}), .succ(net_52), .sir({net_135[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .sor(sor[1:1]));
- orangeTSMC090nm__wire90 wire90_1(.a(net_43));
- orangeTSMC090nm__wire90 wire90_2(.a(net_28));
- orangeTSMC090nm__wire90 wire90_3(.a(net_62));
- orangeTSMC090nm__wire90 wire90_4(.a(net_64));
- orangeTSMC090nm__wire90 wire90_5(.a(net_50));
- orangeTSMC090nm__wire90 wire90_6(.a(net_52));
-endmodule /* stageGroupsM__upDown8weak */
-
-module stageGroupsM__northFifo(ainU, ainU_TT_, fin, inU, predU, aoutD,
- aoutD_TT_, fout, outD, succD, sic, sid, sir);
- input [14:1] ainU;
- input ainU_TT_;
- input fin;
- input [37:1] inU;
- input predU;
- output [14:1] aoutD;
- output aoutD_TT_;
- output fout;
- output [37:1] outD;
- output succD;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
-
- supply1 vdd;
- supply0 gnd;
- wire net_229, net_263;
- wire [5:4] net_235;
- wire [5:4] net_236;
- wire [8:8] net_254;
- wire [51:0] net_256;
- wire [51:0] net_259;
- wire [5:4] net_262;
-
- stageGroupsM__fillDrainCount fillDrai_1(.ain({net_256[37], net_256[38],
- net_256[39], net_256[40], net_256[41], net_256[42], net_256[43],
- net_256[44], net_256[45], net_256[46], net_256[47], net_256[48],
- net_256[49], net_256[50]}), .ain_TT_(net_256[51]), .fin(fin),
- .in({net_256[0], net_256[1], net_256[2], net_256[3], net_256[4],
- net_256[5], net_256[6], net_256[7], net_256[8], net_256[9], net_256[10],
- net_256[11], net_256[12], net_256[13], net_256[14], net_256[15],
- net_256[16], net_256[17], net_256[18], net_256[19], net_256[20],
- net_256[21], net_256[22], net_256[23], net_256[24], net_256[25],
- net_256[26], net_256[27], net_256[28], net_256[29], net_256[30],
- net_256[31], net_256[32], net_256[33], net_256[34], net_256[35],
- net_256[36]}), .pred(net_263), .aout({net_259[37], net_259[38],
- net_259[39], net_259[40], net_259[41], net_259[42], net_259[43],
- net_259[44], net_259[45], net_259[46], net_259[47], net_259[48],
- net_259[49], net_259[50]}), .aout_TT_(net_259[51]), .fout(fout),
- .out({net_259[0], net_259[1], net_259[2], net_259[3], net_259[4],
- net_259[5], net_259[6], net_259[7], net_259[8], net_259[9], net_259[10],
- net_259[11], net_259[12], net_259[13], net_259[14], net_259[15],
- net_259[16], net_259[17], net_259[18], net_259[19], net_259[20],
- net_259[21], net_259[22], net_259[23], net_259[24], net_259[25],
- net_259[26], net_259[27], net_259[28], net_259[29], net_259[30],
- net_259[31], net_259[32], net_259[33], net_259[34], net_259[35],
- net_259[36]}), .succ(net_229), .sic(sic[1:9]), .sid(sid[1:9]),
- .sir({net_254[8], sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8],
- sir[9]}), .soc({sic[8], sic[7], sic[6], net_236[5], net_236[4]}),
- .sod({sid[8], sid[7], sid[6], net_235[5], net_235[4]}), .sor({sir[8],
- sir[7], sir[6], net_262[5], net_262[4]}));
- scanM__scanCap scanCap_5(.si({net_235[5], net_235[4], sid[6], sid[7], sid[8],
- sid[9]}));
- scanM__scanCap scanCap_6(.si({net_236[5], net_236[4], sic[6], sic[7], sic[8],
- sic[9]}));
- scanM__scanCap scanCap_7(.si({net_262[5], net_262[4], sir[6], sir[7], sir[8],
- sir[9]}));
- stageGroupsM__upDown8weak upDown8w_2(.ainD({net_259[37], net_259[38],
- net_259[39], net_259[40], net_259[41], net_259[42], net_259[43],
- net_259[44], net_259[45], net_259[46], net_259[47], net_259[48],
- net_259[49], net_259[50]}), .ainD_TT_(net_259[51]), .ainU(ainU[14:1]),
- .ainU_TT_(ainU_TT_), .inD({net_259[0], net_259[1], net_259[2],
- net_259[3], net_259[4], net_259[5], net_259[6], net_259[7], net_259[8],
- net_259[9], net_259[10], net_259[11], net_259[12], net_259[13],
- net_259[14], net_259[15], net_259[16], net_259[17], net_259[18],
- net_259[19], net_259[20], net_259[21], net_259[22], net_259[23],
- net_259[24], net_259[25], net_259[26], net_259[27], net_259[28],
- net_259[29], net_259[30], net_259[31], net_259[32], net_259[33],
- net_259[34], net_259[35], net_259[36]}), .inU(inU[37:1]),
- .predD(net_229), .predU(predU), .aoutD(aoutD[14:1]),
- .aoutD_TT_(aoutD_TT_), .aoutU({net_256[37], net_256[38], net_256[39],
- net_256[40], net_256[41], net_256[42], net_256[43], net_256[44],
- net_256[45], net_256[46], net_256[47], net_256[48], net_256[49],
- net_256[50]}), .aoutU_TT_(net_256[51]), .outD(outD[37:1]),
- .outU({net_256[0], net_256[1], net_256[2], net_256[3], net_256[4],
- net_256[5], net_256[6], net_256[7], net_256[8], net_256[9], net_256[10],
- net_256[11], net_256[12], net_256[13], net_256[14], net_256[15],
- net_256[16], net_256[17], net_256[18], net_256[19], net_256[20],
- net_256[21], net_256[22], net_256[23], net_256[24], net_256[25],
- net_256[26], net_256[27], net_256[28], net_256[29], net_256[30],
- net_256[31], net_256[32], net_256[33], net_256[34], net_256[35],
- net_256[36]}), .succD(succD), .succU(net_263), .sir(sir[1:9]),
- .sor({net_254[8]}));
- orangeTSMC090nm__wire90 wire90_6(.a(net_229));
- orangeTSMC090nm__wire90 wire90_18(.a(net_263));
-endmodule /* stageGroupsM__northFifo */
-
-module redFive__nor2n(ina, inb, out);
- input ina;
- input inb;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nor2{sch}*/
- nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
- // end Verilog_template
-endmodule /* redFive__nor2n */
-
-module centersJ__ctrAND4in30(inA, inB, inC, inD, out);
- input inA;
- input inB;
- input inC;
- input inD;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_3, net_43, net_58;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (out, net_3);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_3, net_43, net_58);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_1 (net_58, inA, inB);
- // end Verilog_template
- redFive__nor2n nor2n_0(.ina(inD), .inb(inC), .out(net_43));
- orangeTSMC090nm__wire90 wire90_0(.a(net_43));
- orangeTSMC090nm__wire90 wire90_1(.a(net_3));
- orangeTSMC090nm__wire90 wire90_2(.a(net_58));
-endmodule /* centersJ__ctrAND4in30 */
-
-module latchesK__rsLatchA(mc, reset, set, out, outBar);
- input mc;
- input reset;
- input set;
- output out;
- output outBar;
-
- supply1 vdd;
- supply0 gnd;
- wire net_177, net_188;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(reset), .d(net_188), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(net_188), .s(gnd));
- orangeTSMC090nm__PMOSx PMOSx_3(.g(net_177), .d(net_188), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (outBar, net_188);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_177, set);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (out, outBar);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(outBar), .g2(net_177), .d(net_188));
- redFive__pms3 pms3_0(.g(mc), .g2(outBar), .g3(reset), .d(net_188));
- orangeTSMC090nm__wire90 wire90_0(.a(net_177));
- orangeTSMC090nm__wire90 wire90_1(.a(net_188));
-endmodule /* latchesK__rsLatchA */
-
-module driversM__sucORdri20(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_71), .g2(net_51), .d(succ));
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_0 (net_51, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__sucORdri20 */
-
-module gaspM__anAltEnd(mc, predA, predB, fire_A_, fire_B_, s, succ);
- input mc;
- input predA;
- input predB;
- output fire_A_;
- output fire_B_;
- output [1:3] s;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_1040, net_1082, net_822, net_824;
-
- centersJ__ctrAND4in30 ctrAND4i_2(.inA(net_822), .inB(succ), .inC(net_1040),
- .inD(fire_B_), .out(fire_A_));
- centersJ__ctrAND4in30 ctrAND4i_3(.inA(net_824), .inB(succ), .inC(fire_A_),
- .inD(net_1082), .out(fire_B_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (s[1], net_822);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (s[3], net_824);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_822, predA);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_6 (net_824, predB);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_7 (s[2], net_1040);
- // end Verilog_template
- driversM__predDri20wMC predDri2_0(.in(fire_A_), .mc(mc), .pred(predA));
- driversM__predDri20wMC predDri2_1(.in(fire_B_), .mc(mc), .pred(predB));
- latchesK__rsLatchA rsLatchA_1(.mc(mc), .reset(fire_B_), .set(fire_A_),
- .out(net_1040), .outBar(net_1082));
- driversM__sucORdri20 sucORdri_0(.inA(fire_A_), .inB(fire_B_), .succ(succ));
- orangeTSMC090nm__wire90 wire90_34(.a(net_824));
- orangeTSMC090nm__wire90 wire90_35(.a(net_822));
- orangeTSMC090nm__wire90 wire90_36(.a(net_1082));
- orangeTSMC090nm__wire90 wire90_37(.a(net_1040));
-endmodule /* gaspM__anAltEnd */
-
-module latchesK__latch2in20A(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:1] inA;
- input [1:1] inB;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_16;
-
- latchesK__raw2inLatchF hi2inLat_0(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:1]), .inB(inB[1:1]), .out_F_(net_16));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_1 (out[1], net_16);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_1(.a(net_16));
-endmodule /* latchesK__latch2in20A */
-
-module registersM__ins2in20Ax18(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:18] inA;
- input [1:18] inB;
- output [1:18] out;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch2in20A lx_1_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[1]}),
- .inB({inB[1]}), .out({out[1]}));
- latchesK__latch2in20A lx_2_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[2]}),
- .inB({inB[2]}), .out({out[2]}));
- latchesK__latch2in20A lx_3_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[3]}),
- .inB({inB[3]}), .out({out[3]}));
- latchesK__latch2in20A lx_4_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[4]}),
- .inB({inB[4]}), .out({out[4]}));
- latchesK__latch2in20A lx_5_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[5]}),
- .inB({inB[5]}), .out({out[5]}));
- latchesK__latch2in20A lx_6_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[6]}),
- .inB({inB[6]}), .out({out[6]}));
- latchesK__latch2in20A lx_7_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[7]}),
- .inB({inB[7]}), .out({out[7]}));
- latchesK__latch2in20A lx_8_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[8]}),
- .inB({inB[8]}), .out({out[8]}));
- latchesK__latch2in20A lx_9_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_), .inA({inA[9]}),
- .inB({inB[9]}), .out({out[9]}));
- latchesK__latch2in20A lx_10_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[10]}), .inB({inB[10]}), .out({out[10]}));
- latchesK__latch2in20A lx_11_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[11]}), .inB({inB[11]}), .out({out[11]}));
- latchesK__latch2in20A lx_12_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[12]}), .inB({inB[12]}), .out({out[12]}));
- latchesK__latch2in20A lx_13_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[13]}), .inB({inB[13]}), .out({out[13]}));
- latchesK__latch2in20A lx_14_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[14]}), .inB({inB[14]}), .out({out[14]}));
- latchesK__latch2in20A lx_15_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[15]}), .inB({inB[15]}), .out({out[15]}));
- latchesK__latch2in20A lx_16_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[16]}), .inB({inB[16]}), .out({out[16]}));
- latchesK__latch2in20A lx_17_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[17]}), .inB({inB[17]}), .out({out[17]}));
- latchesK__latch2in20A lx_18_(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA({inA[18]}), .inB({inB[18]}), .out({out[18]}));
-endmodule /* registersM__ins2in20Ax18 */
-
-module registersM__ins2in20Ax36(hcl_A_, hcl_B_, inA, inB, out);
- input hcl_A_;
- input hcl_B_;
- input [1:36] inA;
- input [1:36] inB;
- output [1:36] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__ins2in20Ax18 ins2in20_2(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[19:36]), .inB(inB[19:36]), .out(out[19:36]));
- registersM__ins2in20Ax18 ins2in20_3(.hcl_A_(hcl_A_), .hcl_B_(hcl_B_),
- .inA(inA[1:18]), .inB(inB[1:18]), .out(out[1:18]));
- orangeTSMC090nm__wire90 wire90_0(.a(hcl_A_));
- orangeTSMC090nm__wire90 wire90_1(.a(hcl_A_));
- orangeTSMC090nm__wire90 wire90_2(.a(hcl_B_));
- orangeTSMC090nm__wire90 wire90_3(.a(hcl_B_));
-endmodule /* registersM__ins2in20Ax36 */
-
-module scanM__scanEx3(dIn, dIn_1, dIn_2, sir, sor);
- input [1:1] dIn;
- input [2:2] dIn_1;
- input [3:3] dIn_2;
- input [1:9] sir;
- output [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_26, net_45;
-
- scanM__scanCellE scanCell_1(.dIn(dIn[1:1]), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(sir[1]), .sout(net_26));
- scanM__scanCellE scanCell_2(.dIn(dIn_1[2:2]), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(net_26), .sout(net_45));
- scanM__scanCellE scanCell_3(.dIn(dIn_2[3:3]), .p1p(sir[3]), .p2p(sir[2]),
- .rd(sir[5]), .sin(net_45), .sout(sor[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_26));
- orangeTSMC090nm__wire90 wire90_1(.a(net_45));
-endmodule /* scanM__scanEx3 */
-
-module stagesM__altEndDockStage(inA, inB, predA, predB, sir, out, sor, succ);
- input [1:36] inA;
- input [1:36] inB;
- input predA;
- input predB;
- input [1:9] sir;
- output [1:36] out;
- output [1:1] sor;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_A_, fire_B_, take_A_, take_B_;
- wire [1:3] s;
-
- gaspM__anAltEnd anAltEnd_1(.mc(sir[9]), .predA(predA), .predB(predB),
- .fire_A_(fire_A_), .fire_B_(fire_B_), .s(s[1:3]), .succ(succ));
- registersM__ins2in20Ax36 ins2in20_0(.hcl_A_(take_A_), .hcl_B_(take_B_),
- .inA(inA[1:36]), .inB(inB[1:36]), .out(out[1:36]));
- driversM__latchDriver60 latchDri_2(.in(fire_A_), .out(take_A_));
- driversM__latchDriver60 latchDri_3(.in(fire_B_), .out(take_B_));
- scanM__scanEx3 scanEx3_0(.dIn({s[1]}), .dIn_1({s[2]}), .dIn_2({s[3]}),
- .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- wiresL__tranCap tc_12_();
- wiresL__tranCap tc_13_();
- wiresL__tranCap tc_14_();
- wiresL__tranCap tc_15_();
- wiresL__tranCap tc_16_();
- wiresL__tranCap tc_17_();
- wiresL__tranCap tc_18_();
- wiresL__tranCap tc_19_();
- wiresL__tranCap tc_20_();
- wiresL__tranCap tc_21_();
- orangeTSMC090nm__wire90 wire90_0(.a(fire_B_));
- orangeTSMC090nm__wire90 wire90_1(.a(fire_A_));
- orangeTSMC090nm__wire90 wire90_2(.a(take_B_));
- orangeTSMC090nm__wire90 wire90_3(.a(take_A_));
-endmodule /* stagesM__altEndDockStage */
-
-module centersJ__ctrAND4in30M(inA, inB, inC, inD, out, outM);
- input inA;
- input inB;
- input inC;
- input inD;
- output out;
- output outM;
-
- supply1 vdd;
- supply0 gnd;
- wire net_43, net_58;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (out, outM);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (outM, net_43, net_58);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_1 (net_58, inA, inB);
- // end Verilog_template
- redFive__nor2n nor2n_0(.ina(inD), .inb(inC), .out(net_43));
- orangeTSMC090nm__wire90 wire90_0(.a(net_43));
- orangeTSMC090nm__wire90 wire90_2(.a(net_58));
-endmodule /* centersJ__ctrAND4in30M */
-
-module redFive__nand2n_sy(ina, inb, out);
- input ina;
- input inb;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (out, ina, inb);
- // end Verilog_template
-endmodule /* redFive__nand2n_sy */
-
-module gaspM__anAltStart(mc, pred, fire_A_, fire_B_, s, succA, succB);
- input mc;
- input pred;
- output fire_A_;
- output fire_B_;
- output [1:2] s;
- output succA;
- output succB;
-
- supply1 vdd;
- supply0 gnd;
- wire net_143, net_410, net_422, net_634, net_905, net_909;
-
- centersJ__ctrAND4in30M ctrAND4i_1(.inA(net_634), .inB(succA), .inC(fire_B_),
- .inD(net_905), .out(fire_A_), .outM(net_410));
- centersJ__ctrAND4in30M ctrAND4i_3(.inA(net_634), .inB(succB), .inC(net_909),
- .inD(fire_A_), .out(fire_B_), .outM(net_143));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (s[1], net_634);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_634, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (s[2], net_905);
- // end Verilog_template
- redFive__nand2n_sy nand2n_s_0(.ina(net_143), .inb(net_410), .out(net_422));
- driversM__predDri20wMC predDri2_0(.in(net_422), .mc(mc), .pred(pred));
- latchesK__rsLatchA rsLatchA_1(.mc(mc), .reset(fire_B_), .set(fire_A_),
- .out(net_905), .outBar(net_909));
- driversM__sucDri20 sucDri20_0(.in(fire_A_), .succ(succA));
- driversM__sucDri20 sucDri20_1(.in(fire_B_), .succ(succB));
- orangeTSMC090nm__wire90 wire90_16(.a(net_410));
- orangeTSMC090nm__wire90 wire90_17(.a(net_143));
- orangeTSMC090nm__wire90 wire90_19(.a(net_905));
- orangeTSMC090nm__wire90 wire90_20(.a(net_422));
- orangeTSMC090nm__wire90 wire90_27(.a(net_909));
- orangeTSMC090nm__wire90 wire90_28(.a(net_634));
-endmodule /* gaspM__anAltStart */
-
-module registersM__ins1in20Bx36(hcl, in, out);
- input [1:1] hcl;
- input [1:36] in;
- output [1:36] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__ins1in20Bx18 ins1in20_0(.hcl(hcl[1]), .in(in[1:18]),
- .out(out[1:18]));
- registersM__ins1in20Bx18 ins1in20_1(.hcl(hcl[1]), .in(in[19:36]),
- .out(out[19:36]));
- orangeTSMC090nm__wire90 wire90_0(.a(hcl[1]));
- orangeTSMC090nm__wire90 wire90_1(.a(hcl[1]));
-endmodule /* registersM__ins1in20Bx36 */
-
-module stagesM__altStartDockStage(in, pred, sir, outA, outB, sor, succA,
- succB);
- input [1:36] in;
- input pred;
- input [1:9] sir;
- output [1:36] outA;
- output [1:36] outB;
- output [1:1] sor;
- output succA;
- output succB;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_A_, fire_B_, net_20, net_22;
- wire [1:0] net_48;
-
- gaspM__anAltStart anAltSta_1(.mc(sir[9]), .pred(pred), .fire_A_(fire_A_),
- .fire_B_(fire_B_), .s({net_48[1], net_48[0]}), .succA(succA),
- .succB(succB));
- registersM__ins1in20Bx36 ins1in20_0(.hcl({net_20}), .in(in[1:36]),
- .out(outA[1:36]));
- registersM__ins1in20Bx36 ins1in20_1(.hcl({net_22}), .in(in[1:36]),
- .out(outB[1:36]));
- driversM__latchDriver60 latchDri_2(.in(fire_A_), .out(net_20));
- driversM__latchDriver60 latchDri_3(.in(fire_B_), .out(net_22));
- scanM__scanEx2 scanEx2v_1(.dIn({net_48[1], net_48[0]}), .sir(sir[1:9]),
- .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- orangeTSMC090nm__wire90 wire90_0(.a(fire_A_));
- orangeTSMC090nm__wire90 wire90_1(.a(fire_B_));
- orangeTSMC090nm__wire90 wire90_2(.a(net_20));
- orangeTSMC090nm__wire90 wire90_3(.a(net_22));
-endmodule /* stagesM__altStartDockStage */
-
-module centersJ__ctrAND2in30(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_6, net_8;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (out, net_8);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (net_8, net_6);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_1 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
- orangeTSMC090nm__wire90 wire90_1(.a(net_8));
-endmodule /* centersJ__ctrAND2in30 */
-
-module gaspM__aStage(mc, pred, fire, s, succ);
- input mc;
- input pred;
- output fire;
- output [1:1] s;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_494;
-
- centersJ__ctrAND2in30 ctrAND2i_4(.inA(net_494), .inB(succ), .out(fire));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (s[1], net_494);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_494, pred);
- // end Verilog_template
- driversM__predDri20wMC predDri2_1(.in(fire), .mc(mc), .pred(pred));
- driversM__sucDri20 sucDri20_1(.in(fire), .succ(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_494));
-endmodule /* gaspM__aStage */
-
-module stagesM__plainDockStage(in, pred, sir, out, sor, succ, take);
- input [1:36] in;
- input pred;
- input [1:9] sir;
- output [1:36] out;
- output [1:1] sor;
- output succ;
- output [1:1] take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_41;
- wire [1:1] fire;
-
- gaspM__aStage aStage_1(.mc(sir[9]), .pred(pred), .fire(fire[1]),
- .s({net_41}), .succ(succ));
- registersM__ins1in20Bx36 ins1in20_0(.hcl(take[1:1]), .in(in[1:36]),
- .out(out[1:36]));
- driversM__latchDriver60 latchDri_1(.in(fire[1]), .out(take[1]));
- scanM__scanEx1 scanEx1_0(.dIn({net_41}), .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- orangeTSMC090nm__wire90 wire90_1(.a(fire[1]));
-endmodule /* stagesM__plainDockStage */
-
-module stageGroupsM__dockWagNine(in, pred, sir, out, sor, succ, take);
- input [1:36] in;
- input pred;
- input [1:9] sir;
- output [1:36] out;
- output [1:1] sor;
- output succ;
- output [4:4] take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_105, net_107, net_109, net_111, net_58, net_60, net_64, net_69;
- wire [35:0] net_0;
- wire [35:0] net_1;
- wire [8:8] net_116;
- wire [8:8] net_125;
- wire [8:8] net_127;
- wire [8:8] net_128;
- wire [8:8] net_130;
- wire [8:8] net_134;
- wire [8:8] net_136;
- wire [35:0] net_16;
- wire [35:0] net_19;
- wire [35:0] net_2;
- wire [35:0] net_20;
- wire [35:0] net_21;
- wire [35:0] net_3;
- wire \take_1[6] ;
- wire \take_1[5] ;
- wire \take_1[3] ;
- wire \take_1[2] ;
- wire \take_1[1] ;
-
- stagesM__altEndDockStage altEndDo_0(.inA({net_16[35], net_16[34], net_16[33],
- net_16[32], net_16[31], net_16[30], net_16[29], net_16[28], net_16[27],
- net_16[26], net_16[25], net_16[24], net_16[23], net_16[22], net_16[21],
- net_16[20], net_16[19], net_16[18], net_16[17], net_16[16], net_16[15],
- net_16[14], net_16[13], net_16[12], net_16[11], net_16[10], net_16[9],
- net_16[8], net_16[7], net_16[6], net_16[5], net_16[4], net_16[3],
- net_16[2], net_16[1], net_16[0]}), .inB({net_19[35], net_19[34],
- net_19[33], net_19[32], net_19[31], net_19[30], net_19[29], net_19[28],
- net_19[27], net_19[26], net_19[25], net_19[24], net_19[23], net_19[22],
- net_19[21], net_19[20], net_19[19], net_19[18], net_19[17], net_19[16],
- net_19[15], net_19[14], net_19[13], net_19[12], net_19[11], net_19[10],
- net_19[9], net_19[8], net_19[7], net_19[6], net_19[5], net_19[4],
- net_19[3], net_19[2], net_19[1], net_19[0]}), .predA(net_69),
- .predB(net_58), .sir({net_134[8], sir[2], sir[3], sir[4], sir[5], sir[6],
- sir[7], sir[8], sir[9]}), .out(out[1:36]), .sor(sor[1:1]), .succ(succ));
- stagesM__altStartDockStage altStart_0(.in(in[1:36]), .pred(pred),
- .sir(sir[1:9]), .outA({net_21[35], net_21[34], net_21[33], net_21[32],
- net_21[31], net_21[30], net_21[29], net_21[28], net_21[27], net_21[26],
- net_21[25], net_21[24], net_21[23], net_21[22], net_21[21], net_21[20],
- net_21[19], net_21[18], net_21[17], net_21[16], net_21[15], net_21[14],
- net_21[13], net_21[12], net_21[11], net_21[10], net_21[9], net_21[8],
- net_21[7], net_21[6], net_21[5], net_21[4], net_21[3], net_21[2],
- net_21[1], net_21[0]}), .outB({net_20[35], net_20[34], net_20[33],
- net_20[32], net_20[31], net_20[30], net_20[29], net_20[28], net_20[27],
- net_20[26], net_20[25], net_20[24], net_20[23], net_20[22], net_20[21],
- net_20[20], net_20[19], net_20[18], net_20[17], net_20[16], net_20[15],
- net_20[14], net_20[13], net_20[12], net_20[11], net_20[10], net_20[9],
- net_20[8], net_20[7], net_20[6], net_20[5], net_20[4], net_20[3],
- net_20[2], net_20[1], net_20[0]}), .sor({net_116[8]}), .succA(net_64),
- .succB(net_60));
- stagesM__plainDockStage plainDoc_0(.in({net_2[35], net_2[34], net_2[33],
- net_2[32], net_2[31], net_2[30], net_2[29], net_2[28], net_2[27],
- net_2[26], net_2[25], net_2[24], net_2[23], net_2[22], net_2[21],
- net_2[20], net_2[19], net_2[18], net_2[17], net_2[16], net_2[15],
- net_2[14], net_2[13], net_2[12], net_2[11], net_2[10], net_2[9],
- net_2[8], net_2[7], net_2[6], net_2[5], net_2[4], net_2[3], net_2[2],
- net_2[1], net_2[0]}), .pred(net_107), .sir({net_136[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .out({net_3[35],
- net_3[34], net_3[33], net_3[32], net_3[31], net_3[30], net_3[29],
- net_3[28], net_3[27], net_3[26], net_3[25], net_3[24], net_3[23],
- net_3[22], net_3[21], net_3[20], net_3[19], net_3[18], net_3[17],
- net_3[16], net_3[15], net_3[14], net_3[13], net_3[12], net_3[11],
- net_3[10], net_3[9], net_3[8], net_3[7], net_3[6], net_3[5], net_3[4],
- net_3[3], net_3[2], net_3[1], net_3[0]}), .sor({net_130[8]}),
- .succ(net_105), .take({ \take_1[5] }));
- stagesM__plainDockStage plainDoc_1(.in({net_20[35], net_20[34], net_20[33],
- net_20[32], net_20[31], net_20[30], net_20[29], net_20[28], net_20[27],
- net_20[26], net_20[25], net_20[24], net_20[23], net_20[22], net_20[21],
- net_20[20], net_20[19], net_20[18], net_20[17], net_20[16], net_20[15],
- net_20[14], net_20[13], net_20[12], net_20[11], net_20[10], net_20[9],
- net_20[8], net_20[7], net_20[6], net_20[5], net_20[4], net_20[3],
- net_20[2], net_20[1], net_20[0]}), .pred(net_60), .sir({net_125[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .out({net_2[35], net_2[34], net_2[33], net_2[32], net_2[31], net_2[30],
- net_2[29], net_2[28], net_2[27], net_2[26], net_2[25], net_2[24],
- net_2[23], net_2[22], net_2[21], net_2[20], net_2[19], net_2[18],
- net_2[17], net_2[16], net_2[15], net_2[14], net_2[13], net_2[12],
- net_2[11], net_2[10], net_2[9], net_2[8], net_2[7], net_2[6], net_2[5],
- net_2[4], net_2[3], net_2[2], net_2[1], net_2[0]}), .sor({net_136[8]}),
- .succ(net_107), .take(take[4:4]));
- stagesM__plainDockStage plainDoc_2(.in({net_3[35], net_3[34], net_3[33],
- net_3[32], net_3[31], net_3[30], net_3[29], net_3[28], net_3[27],
- net_3[26], net_3[25], net_3[24], net_3[23], net_3[22], net_3[21],
- net_3[20], net_3[19], net_3[18], net_3[17], net_3[16], net_3[15],
- net_3[14], net_3[13], net_3[12], net_3[11], net_3[10], net_3[9],
- net_3[8], net_3[7], net_3[6], net_3[5], net_3[4], net_3[3], net_3[2],
- net_3[1], net_3[0]}), .pred(net_105), .sir({net_130[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .out({net_19[35],
- net_19[34], net_19[33], net_19[32], net_19[31], net_19[30], net_19[29],
- net_19[28], net_19[27], net_19[26], net_19[25], net_19[24], net_19[23],
- net_19[22], net_19[21], net_19[20], net_19[19], net_19[18], net_19[17],
- net_19[16], net_19[15], net_19[14], net_19[13], net_19[12], net_19[11],
- net_19[10], net_19[9], net_19[8], net_19[7], net_19[6], net_19[5],
- net_19[4], net_19[3], net_19[2], net_19[1], net_19[0]}),
- .sor({net_134[8]}), .succ(net_58), .take({ \take_1[6] }));
- stagesM__plainDockStage plainDoc_3(.in({net_0[35], net_0[34], net_0[33],
- net_0[32], net_0[31], net_0[30], net_0[29], net_0[28], net_0[27],
- net_0[26], net_0[25], net_0[24], net_0[23], net_0[22], net_0[21],
- net_0[20], net_0[19], net_0[18], net_0[17], net_0[16], net_0[15],
- net_0[14], net_0[13], net_0[12], net_0[11], net_0[10], net_0[9],
- net_0[8], net_0[7], net_0[6], net_0[5], net_0[4], net_0[3], net_0[2],
- net_0[1], net_0[0]}), .pred(net_109), .sir({net_127[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .out({net_1[35],
- net_1[34], net_1[33], net_1[32], net_1[31], net_1[30], net_1[29],
- net_1[28], net_1[27], net_1[26], net_1[25], net_1[24], net_1[23],
- net_1[22], net_1[21], net_1[20], net_1[19], net_1[18], net_1[17],
- net_1[16], net_1[15], net_1[14], net_1[13], net_1[12], net_1[11],
- net_1[10], net_1[9], net_1[8], net_1[7], net_1[6], net_1[5], net_1[4],
- net_1[3], net_1[2], net_1[1], net_1[0]}), .sor({net_128[8]}),
- .succ(net_111), .take({ \take_1[2] }));
- stagesM__plainDockStage plainDoc_4(.in({net_21[35], net_21[34], net_21[33],
- net_21[32], net_21[31], net_21[30], net_21[29], net_21[28], net_21[27],
- net_21[26], net_21[25], net_21[24], net_21[23], net_21[22], net_21[21],
- net_21[20], net_21[19], net_21[18], net_21[17], net_21[16], net_21[15],
- net_21[14], net_21[13], net_21[12], net_21[11], net_21[10], net_21[9],
- net_21[8], net_21[7], net_21[6], net_21[5], net_21[4], net_21[3],
- net_21[2], net_21[1], net_21[0]}), .pred(net_64), .sir({net_116[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .out({net_0[35], net_0[34], net_0[33], net_0[32], net_0[31], net_0[30],
- net_0[29], net_0[28], net_0[27], net_0[26], net_0[25], net_0[24],
- net_0[23], net_0[22], net_0[21], net_0[20], net_0[19], net_0[18],
- net_0[17], net_0[16], net_0[15], net_0[14], net_0[13], net_0[12],
- net_0[11], net_0[10], net_0[9], net_0[8], net_0[7], net_0[6], net_0[5],
- net_0[4], net_0[3], net_0[2], net_0[1], net_0[0]}), .sor({net_127[8]}),
- .succ(net_109), .take({ \take_1[1] }));
- stagesM__plainDockStage plainDoc_5(.in({net_1[35], net_1[34], net_1[33],
- net_1[32], net_1[31], net_1[30], net_1[29], net_1[28], net_1[27],
- net_1[26], net_1[25], net_1[24], net_1[23], net_1[22], net_1[21],
- net_1[20], net_1[19], net_1[18], net_1[17], net_1[16], net_1[15],
- net_1[14], net_1[13], net_1[12], net_1[11], net_1[10], net_1[9],
- net_1[8], net_1[7], net_1[6], net_1[5], net_1[4], net_1[3], net_1[2],
- net_1[1], net_1[0]}), .pred(net_111), .sir({net_128[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .out({net_16[35],
- net_16[34], net_16[33], net_16[32], net_16[31], net_16[30], net_16[29],
- net_16[28], net_16[27], net_16[26], net_16[25], net_16[24], net_16[23],
- net_16[22], net_16[21], net_16[20], net_16[19], net_16[18], net_16[17],
- net_16[16], net_16[15], net_16[14], net_16[13], net_16[12], net_16[11],
- net_16[10], net_16[9], net_16[8], net_16[7], net_16[6], net_16[5],
- net_16[4], net_16[3], net_16[2], net_16[1], net_16[0]}),
- .sor({net_125[8]}), .succ(net_69), .take({ \take_1[3] }));
- orangeTSMC090nm__wire90 wire90_0(.a(net_64));
- orangeTSMC090nm__wire90 wire90_1(.a(net_60));
- orangeTSMC090nm__wire90 wire90_2(.a(net_109));
- orangeTSMC090nm__wire90 wire90_3(.a(net_105));
- orangeTSMC090nm__wire90 wire90_4(.a(net_111));
- orangeTSMC090nm__wire90 wire90_5(.a(net_58));
- orangeTSMC090nm__wire90 wire90_6(.a(net_107));
- orangeTSMC090nm__wire90 wire90_7(.a(net_69));
-endmodule /* stageGroupsM__dockWagNine */
-
-module centersJ__ctrAND3in30A(inA, inB, inC, out, outM);
- input inA;
- input inB;
- input inC;
- output out;
- output outM;
-
- supply1 vdd;
- supply0 gnd;
- wire net_6;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (out, outM);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (outM, net_6, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2HT_sy{sch}*/
- nor (strong0, strong1) #(100) nor2HT_s_0 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
-endmodule /* centersJ__ctrAND3in30A */
-
-module driversM__suc3ANDdri20(inA, inB, inC, succ);
- input inA;
- input inB;
- input inC;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_0 (net_51, inA, inB, inC);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_71), .g2(net_51), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__suc3ANDdri20 */
-
-module driversM__sucANDdri20(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_51, net_71;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_51), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_71, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_51, inA, inB);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_71), .g2(net_51), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_51));
- orangeTSMC090nm__wire90 wire90_1(.a(net_71));
-endmodule /* driversM__sucANDdri20 */
-
-module gaspM__gaspEpi(mc, pred, tailBit, tokenLO, epi_OTHER_, epi_TAIL_,
- epi_TORP_, fire, s);
- input mc;
- input pred;
- input tailBit;
- input tokenLO;
- output epi_OTHER_;
- output epi_TAIL_;
- output epi_TORP_;
- output fire;
- output [1:1] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_1079, net_1119, net_1139, net_1147, net_987;
-
- centersJ__ctrAND3in30A ctrAND3i_3(.inA(net_987), .inB(epi_TORP_),
- .inC(net_1079), .out(fire), .outM(net_1119));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_987, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_987);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (net_1139, tokenLO);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_3 (net_1147, tailBit);
- // end Verilog_template
- redFive__nor2n_sy nor2n_sy_0(.ina(epi_TAIL_), .inb(epi_OTHER_),
- .out(net_1079));
- driversM__predDri20wMC predDri2_0(.in(fire), .mc(mc), .pred(pred));
- driversM__suc3ANDdri20 suc3ANDd_0(.inA(tokenLO), .inB(net_1147), .inC(fire),
- .succ(epi_OTHER_));
- driversM__suc3ANDdri20 suc3ANDd_1(.inA(tokenLO), .inB(tailBit), .inC(fire),
- .succ(epi_TAIL_));
- driversM__sucANDdri20 sucANDdr_1(.inA(net_1139), .inB(fire),
- .succ(epi_TORP_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_987));
- orangeTSMC090nm__wire90 wire90_3(.a(net_1079));
- orangeTSMC090nm__wire90 wire90_4(.a(net_1139));
- orangeTSMC090nm__wire90 wire90_6(.a(net_1147));
-endmodule /* gaspM__gaspEpi */
-
-module stagesM__epiDockStage(do_epi_, in, in_T_, sir, epi, epi_OTHER_,
- epi_TAIL_, epi_TORP_, sor, take_epi_);
- input do_epi_;
- input [1:36] in;
- input in_T_;
- input [1:9] sir;
- output [1:36] epi;
- output epi_OTHER_;
- output epi_TAIL_;
- output epi_TORP_;
- output [1:1] sor;
- output take_epi_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_0, net_47;
-
- gaspM__gaspEpi anEpiSta_1(.mc(sir[9]), .pred(do_epi_), .tailBit(in[28]),
- .tokenLO(in_T_), .epi_OTHER_(epi_OTHER_), .epi_TAIL_(epi_TAIL_),
- .epi_TORP_(epi_TORP_), .fire(net_0), .s({net_47}));
- registersM__ins1in20Bx36 ins1in20_0(.hcl({take_epi_}), .in(in[1:36]),
- .out(epi[1:36]));
- driversM__latchDriver60 latchDri_1(.in(net_0), .out(take_epi_));
- scanM__scanEx1 scanEx1_0(.dIn({net_47}), .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tranCap_0();
- orangeTSMC090nm__wire90 wire90_0(.a(net_0));
-endmodule /* stagesM__epiDockStage */
-
-module gates3inM__nor3in6_6sym(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__NMOSx NMOSx_0(.g(inC), .d(out), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_7(.g(inB), .d(out), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_8(.g(inA), .d(out), .s(gnd));
- redFive__pms3 pms3_0(.g(inA), .g2(inB), .g3(inC), .d(out));
- redFive__pms3 pms3_1(.g(inC), .g2(inB), .g3(inA), .d(out));
-endmodule /* gates3inM__nor3in6_6sym */
-
-module oneHotM__onDeck(bits_ABORT_, bits_HEAD_, flag_A__clr_, flag_A__set_,
- flag_D__clr_, flag_D__set_, mc, pred, fire_od_, od_ABORT_, od_HEAD_,
- od_OTHER_, s);
- input bits_ABORT_;
- input bits_HEAD_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input mc;
- input pred;
- output fire_od_;
- output od_ABORT_;
- output od_HEAD_;
- output od_OTHER_;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_297, net_305, net_314, net_322, net_367, net_371, net_438, net_463;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_8 (net_314, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_9 (net_438, bits_HEAD_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_10 (net_463, bits_ABORT_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (s[2], net_297);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_5 (fire_od_, net_367);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_6 (s[1], net_314);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2LT_sy{sch}*/
- nand (strong0, strong1) #(100) nand2LT__2 (net_367, net_371, net_322);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_7 (net_305, flag_A__set_,
- flag_A__clr_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_8 (net_297, flag_D__set_,
- flag_D__clr_);
- // end Verilog_template
- gates3inM__nor3in6_6sym nor3in3__2(.inA(net_297), .inB(net_305),
- .inC(net_314), .out(net_322));
- gates3inM__nor3in6_6sym nor3in3__5(.inA(od_ABORT_), .inB(od_OTHER_),
- .inC(od_HEAD_), .out(net_371));
- driversM__predDri20wMC predDri2_2(.in(fire_od_), .mc(mc), .pred(pred));
- driversM__suc3ANDdri20 suc3ANDd_1(.inA(net_438), .inB(net_463),
- .inC(fire_od_), .succ(od_OTHER_));
- driversM__sucANDdri20 sucANDdr_0(.inA(bits_HEAD_), .inB(fire_od_),
- .succ(od_HEAD_));
- driversM__sucANDdri20 sucANDdr_4(.inA(bits_ABORT_), .inB(fire_od_),
- .succ(od_ABORT_));
- orangeTSMC090nm__wire90 wire90_10(.a(fire_od_));
- orangeTSMC090nm__wire90 wire90_11(.a(net_322));
- orangeTSMC090nm__wire90 wire90_13(.a(net_297));
- orangeTSMC090nm__wire90 wire90_15(.a(net_305));
- orangeTSMC090nm__wire90 wire90_16(.a(net_314));
- orangeTSMC090nm__wire90 wire90_18(.a(net_371));
- orangeTSMC090nm__wire90 wire90_19(.a(net_367));
- orangeTSMC090nm__wire90 wire90_20(.a(net_438));
- orangeTSMC090nm__wire90 wire90_21(.a(net_463));
-endmodule /* oneHotM__onDeck */
-
-module stagesM__onDeckDockStage(do_od_, flag_A__clr_, flag_A__set_,
- flag_D__clr_, flag_D__set_, m1, sir, od, od_ABORT_, od_HEAD_, od_OTHER_,
- sor, take_od_);
- input do_od_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input [1:36] m1;
- input [1:9] sir;
- output [1:36] od;
- output od_ABORT_;
- output od_HEAD_;
- output od_OTHER_;
- output [1:1] sor;
- output take_od_;
-
- supply1 vdd;
- supply0 gnd;
- wire [1:1] fire;
- wire [1:0] net_62;
-
- registersM__ins1in20Bx36 ins1in20_0(.hcl({take_od_}), .in(m1[1:36]),
- .out(od[1:36]));
- driversM__latchDriver60 latchDri_1(.in(fire[1]), .out(take_od_));
- oneHotM__onDeck onDeck_0(.bits_ABORT_(m1[29]), .bits_HEAD_(m1[30]),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .mc(sir[9]),
- .pred(do_od_), .fire_od_(fire[1]), .od_ABORT_(od_ABORT_),
- .od_HEAD_(od_HEAD_), .od_OTHER_(od_OTHER_), .s({net_62[1], net_62[0]}));
- scanM__scanEx2 scanEx2v_2(.dIn({net_62[1], net_62[0]}), .sir(sir[1:9]),
- .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- orangeTSMC090nm__wire90 wire90_1(.a(fire[1]));
-endmodule /* stagesM__onDeckDockStage */
-
-module centersJ__ctrAND1in30(in, out);
- input in;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_101, net_82;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_11 (net_82, net_101);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (out, net_82);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (net_101, in);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_1(.a(net_101));
- orangeTSMC090nm__wire90 wire90_2(.a(net_82));
-endmodule /* centersJ__ctrAND1in30 */
-
-module oneHotM__reQueueB(epi_TAIL_, mc, od_HEAD_, circulate, s);
- input epi_TAIL_;
- input mc;
- input od_HEAD_;
- output circulate;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_0, net_125, net_127, net_7;
-
- centersJ__ctrAND1in30 ctrAND1i_0(.in(net_0), .out(net_7));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_127, od_HEAD_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (net_125, epi_TAIL_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_3 (s[1], net_127);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_4 (s[2], net_125);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_0, od_HEAD_, epi_TAIL_);
- // end Verilog_template
- driversM__predDri20wMC predDri2_1(.in(net_7), .mc(mc), .pred(epi_TAIL_));
- driversM__predDri20wMC predDri2_2(.in(net_7), .mc(mc), .pred(od_HEAD_));
- driversM__sucDri20 sucDri20_0(.in(net_7), .succ(circulate));
- orangeTSMC090nm__wire90 wire90_0(.a(net_0));
- orangeTSMC090nm__wire90 wire90_1(.a(net_7));
- orangeTSMC090nm__wire90 wire90_2(.a(net_125));
- orangeTSMC090nm__wire90 wire90_3(.a(net_127));
-endmodule /* oneHotM__reQueueB */
-
-module redFive__nand2n(ina, inb, out);
- input ina;
- input inb;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
- // end Verilog_template
-endmodule /* redFive__nand2n */
-
-module redFive__nms3(g, g2, g3, d);
- input g;
- input g2;
- input g3;
- output d;
-
- supply0 gnd;
- wire net_6, net_7;
-
- orangeTSMC090nm__NMOSx NMOS_0(.g(g3), .d(d), .s(net_6));
- orangeTSMC090nm__NMOSx NMOS_1(.g(g), .d(net_7), .s(gnd));
- orangeTSMC090nm__NMOSx NMOS_2(.g(g2), .d(net_6), .s(net_7));
-endmodule /* redFive__nms3 */
-
-module gates3inM__nand3in6_6sym(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__PMOSx PMOSx_1(.g(inA), .d(out), .s(vdd));
- orangeTSMC090nm__PMOSx PMOSx_3(.g(inC), .d(out), .s(vdd));
- orangeTSMC090nm__PMOSx PMOSx_4(.g(inB), .d(out), .s(vdd));
- redFive__nms3 nms3_0(.g(inA), .g2(inB), .g3(inC), .d(out));
- redFive__nms3 nms3_2(.g(inC), .g2(inB), .g3(inA), .d(out));
-endmodule /* gates3inM__nand3in6_6sym */
-
-module oneHotM__reQueueC(circulate, epi_OTHER_, mc, od_ABORT_, od_OTHER_,
- ps_do_, ps_skip_, fire_E_, fire_R_, s, succ);
- input circulate;
- input epi_OTHER_;
- input mc;
- input od_ABORT_;
- input od_OTHER_;
- input ps_do_;
- input ps_skip_;
- output fire_E_;
- output fire_R_;
- output [1:2] s;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire abortLO, fire_C_, net_274, net_277, net_280, net_283, net_311, net_313;
- wire net_320, net_324, net_361, net_376, net_396;
-
- centersJ__ctrAND3in30 ctrAND3i_0(.inA(succ), .inB(net_361), .inC(circulate),
- .out(fire_E_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_12 (abortLO, net_376);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_13 (net_361, epi_OTHER_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_14 (net_320, circulate);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_10 (net_376, net_283);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_11 (net_396, abortLO);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_12 (s[2], net_361);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_13 (s[1], net_320);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_1 (net_274, od_OTHER_, ps_skip_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_2 (net_277, od_ABORT_, ps_skip_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_3 (net_280, od_OTHER_, ps_do_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_4 (net_283, od_ABORT_, ps_do_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_5 (net_324, net_313, net_311);
- // end Verilog_template
- redFive__nand2n nand2n_0(.ina(circulate), .inb(succ), .out(net_313));
- redFive__nand2n_sy nand2n_s_0(.ina(net_324), .inb(abortLO), .out(fire_C_));
- gates3inM__nand3in6_6sym nand3in6_1(.inA(net_274), .inB(net_277),
- .inC(net_280), .out(net_311));
- redFive__nor2n nor2n_1(.ina(net_324), .inb(net_320), .out(fire_R_));
- driversM__predDri20wMC predDri2_2(.in(fire_C_), .mc(mc), .pred(od_ABORT_));
- driversM__predDri20wMC predDri2_3(.in(fire_C_), .mc(mc), .pred(od_OTHER_));
- driversM__predDri20wMC predDri2_4(.in(fire_C_), .mc(mc), .pred(ps_do_));
- driversM__predDri20wMC predDri2_5(.in(fire_C_), .mc(mc), .pred(ps_skip_));
- driversM__predDri20wMC predDri2_6(.in(fire_E_), .mc(mc), .pred(epi_OTHER_));
- driversM__predDri20wMC predDri2_7(.in(net_396), .mc(mc), .pred(circulate));
- driversM__sucORdri20 sucORdri_0(.inA(fire_R_), .inB(fire_E_), .succ(succ));
- orangeTSMC090nm__wire90 wire90_12(.a(net_274));
- orangeTSMC090nm__wire90 wire90_13(.a(net_277));
- orangeTSMC090nm__wire90 wire90_14(.a(net_280));
- orangeTSMC090nm__wire90 wire90_15(.a(net_283));
- orangeTSMC090nm__wire90 wire90_16(.a(net_311));
- orangeTSMC090nm__wire90 wire90_17(.a(net_313));
- orangeTSMC090nm__wire90 wire90_18(.a(net_320));
- orangeTSMC090nm__wire90 wire90_19(.a(net_324));
- orangeTSMC090nm__wire90 wire90_20(.a(fire_C_));
- orangeTSMC090nm__wire90 wire90_23(.a(net_376));
- orangeTSMC090nm__wire90 wire90_24(.a(abortLO));
- orangeTSMC090nm__wire90 wire90_25(.a(net_396));
- orangeTSMC090nm__wire90 wire90_27(.a(net_361));
-endmodule /* oneHotM__reQueueC */
-
-module oneHotM__reQueue(epi_OTHER_, epi_TAIL_, mc, od_ABORT_, od_HEAD_,
- od_OTHER_, ps_do_, ps_skip_, fire_E_, fire_R_, rq_succ_, s);
- input epi_OTHER_;
- input epi_TAIL_;
- input mc;
- input od_ABORT_;
- input od_HEAD_;
- input od_OTHER_;
- input ps_do_;
- input ps_skip_;
- output fire_E_;
- output fire_R_;
- output rq_succ_;
- output [1:4] s;
-
- supply1 vdd;
- supply0 gnd;
- wire circulate;
-
- oneHotM__reQueueB reQueueB_1(.epi_TAIL_(epi_TAIL_), .mc(mc),
- .od_HEAD_(od_HEAD_), .circulate(circulate), .s(s[1:2]));
- oneHotM__reQueueC reQueueC_0(.circulate(circulate), .epi_OTHER_(epi_OTHER_),
- .mc(mc), .od_ABORT_(od_ABORT_), .od_OTHER_(od_OTHER_), .ps_do_(ps_do_),
- .ps_skip_(ps_skip_), .fire_E_(fire_E_), .fire_R_(fire_R_), .s(s[3:4]),
- .succ(rq_succ_));
- orangeTSMC090nm__wire90 wire90_0(.a(circulate));
-endmodule /* oneHotM__reQueue */
-
-module scanM__scanEx3plain(dIn, dIn_1, dIn_2, sin, \sir[2] , \sir[3] , \sir[5]
- , sout);
- input [1:1] dIn;
- input [2:2] dIn_1;
- input [3:3] dIn_2;
- input sin;
- input \sir[2] , \sir[3] , \sir[5] ;
- output sout;
-
- supply1 vdd;
- supply0 gnd;
- wire net_26, net_45;
-
- scanM__scanCellE scanCell_1(.dIn(dIn[1:1]), .p1p( \sir[3] ), .p2p( \sir[2] ),
- .rd( \sir[5] ), .sin(sin), .sout(net_26));
- scanM__scanCellE scanCell_2(.dIn(dIn_1[2:2]), .p1p( \sir[3] ), .p2p( \sir[2]
- ), .rd( \sir[5] ), .sin(net_26), .sout(net_45));
- scanM__scanCellE scanCell_3(.dIn(dIn_2[3:3]), .p1p( \sir[3] ), .p2p( \sir[2]
- ), .rd( \sir[5] ), .sin(net_45), .sout(sout));
- orangeTSMC090nm__wire90 wire90_0(.a(net_26));
- orangeTSMC090nm__wire90 wire90_1(.a(net_45));
-endmodule /* scanM__scanEx3plain */
-
-module stagesM__rqDockStage(epi_OTHER_, epi_TAIL_, inE, inP, od_ABORT_,
- od_HEAD_, od_OTHER_, ps_do_, ps_skip_, sir, rq, rq_succ_, sor, take_E_,
- take_P_);
- input epi_OTHER_;
- input epi_TAIL_;
- input [1:36] inE;
- input [1:36] inP;
- input od_ABORT_;
- input od_HEAD_;
- input od_OTHER_;
- input ps_do_;
- input ps_skip_;
- input [1:9] sir;
- output [1:36] rq;
- output rq_succ_;
- output [1:1] sor;
- output take_E_;
- output take_P_;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_E_, fire_R_, sin;
- wire [1:4] s;
-
- registersM__ins2in20Ax36 ins2in20_0(.hcl_A_(take_E_), .hcl_B_(take_P_),
- .inA(inE[1:36]), .inB(inP[1:36]), .out(rq[1:36]));
- driversM__latchDriver60 latchDri_2(.in(fire_E_), .out(take_E_));
- driversM__latchDriver60 latchDri_3(.in(fire_R_), .out(take_P_));
- oneHotM__reQueue reQueue_0(.epi_OTHER_(epi_OTHER_), .epi_TAIL_(epi_TAIL_),
- .mc(sir[9]), .od_ABORT_(od_ABORT_), .od_HEAD_(od_HEAD_),
- .od_OTHER_(od_OTHER_), .ps_do_(ps_do_), .ps_skip_(ps_skip_),
- .fire_E_(fire_E_), .fire_R_(fire_R_), .rq_succ_(rq_succ_), .s(s[1:4]));
- scanM__scanEx1 scanEx1_0(.dIn({s[1]}), .sir(sir[1:9]), .sor({sin}));
- scanM__scanEx3plain scanEx3p_1(.dIn({s[2]}), .dIn_1({s[3]}), .dIn_2({s[4]}),
- .sin(sin), .\sir[2] (sir[2]), .\sir[3] (sir[3]), .\sir[5] (sir[5]),
- .sout(sor[1]));
- wiresL__tranCap tranCap_0();
- orangeTSMC090nm__wire90 wire90_0(.a(fire_R_));
- orangeTSMC090nm__wire90 wire90_1(.a(fire_E_));
-endmodule /* stagesM__rqDockStage */
-
-module stageGroupsM__epiRQod(do_epi_, do_od_, flag_A__clr_, flag_A__set_,
- flag_D__clr_, flag_D__set_, in, in_T_, m1, ps_do_, ps_skip_, sir,
- epi_TORP_, rq, rq_succ_, sor);
- input do_epi_;
- input do_od_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input [1:36] in;
- input in_T_;
- input [1:36] m1;
- input ps_do_;
- input ps_skip_;
- input [1:9] sir;
- output epi_TORP_;
- output [1:36] rq;
- output rq_succ_;
- output [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire epi_OTHER_, epi_TAIL_, od_ABORT_, od_HEAD_, od_OTHER_, take_E_, take_P_;
- wire take_epi_, take_od_;
- wire [8:8] net_0;
- wire [8:8] net_36;
- wire [35:0] net_45;
- wire [35:0] net_46;
-
- stagesM__epiDockStage epiDockS_0(.do_epi_(do_epi_), .in(in[1:36]),
- .in_T_(in_T_), .sir(sir[1:9]), .epi({net_45[35], net_45[34], net_45[33],
- net_45[32], net_45[31], net_45[30], net_45[29], net_45[28], net_45[27],
- net_45[26], net_45[25], net_45[24], net_45[23], net_45[22], net_45[21],
- net_45[20], net_45[19], net_45[18], net_45[17], net_45[16], net_45[15],
- net_45[14], net_45[13], net_45[12], net_45[11], net_45[10], net_45[9],
- net_45[8], net_45[7], net_45[6], net_45[5], net_45[4], net_45[3],
- net_45[2], net_45[1], net_45[0]}), .epi_OTHER_(epi_OTHER_),
- .epi_TAIL_(epi_TAIL_), .epi_TORP_(epi_TORP_), .sor({net_0[8]}),
- .take_epi_(take_epi_));
- stagesM__onDeckDockStage onDeckDo_0(.do_od_(do_od_),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .m1(m1[1:36]),
- .sir({net_36[8], sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8],
- sir[9]}), .od({net_46[35], net_46[34], net_46[33], net_46[32],
- net_46[31], net_46[30], net_46[29], net_46[28], net_46[27], net_46[26],
- net_46[25], net_46[24], net_46[23], net_46[22], net_46[21], net_46[20],
- net_46[19], net_46[18], net_46[17], net_46[16], net_46[15], net_46[14],
- net_46[13], net_46[12], net_46[11], net_46[10], net_46[9], net_46[8],
- net_46[7], net_46[6], net_46[5], net_46[4], net_46[3], net_46[2],
- net_46[1], net_46[0]}), .od_ABORT_(od_ABORT_), .od_HEAD_(od_HEAD_),
- .od_OTHER_(od_OTHER_), .sor(sor[1:1]), .take_od_(take_od_));
- stagesM__rqDockStage rqDockSt_0(.epi_OTHER_(epi_OTHER_),
- .epi_TAIL_(epi_TAIL_), .inE({net_45[35], net_45[34], net_45[33],
- net_45[32], net_45[31], net_45[30], net_45[29], net_45[28], net_45[27],
- net_45[26], net_45[25], net_45[24], net_45[23], net_45[22], net_45[21],
- net_45[20], net_45[19], net_45[18], net_45[17], net_45[16], net_45[15],
- net_45[14], net_45[13], net_45[12], net_45[11], net_45[10], net_45[9],
- net_45[8], net_45[7], net_45[6], net_45[5], net_45[4], net_45[3],
- net_45[2], net_45[1], net_45[0]}), .inP({net_46[35], net_46[34],
- net_46[33], net_46[32], net_46[31], net_46[30], net_46[29], net_46[28],
- net_46[27], net_46[26], net_46[25], net_46[24], net_46[23], net_46[22],
- net_46[21], net_46[20], net_46[19], net_46[18], net_46[17], net_46[16],
- net_46[15], net_46[14], net_46[13], net_46[12], net_46[11], net_46[10],
- net_46[9], net_46[8], net_46[7], net_46[6], net_46[5], net_46[4],
- net_46[3], net_46[2], net_46[1], net_46[0]}), .od_ABORT_(od_ABORT_),
- .od_HEAD_(od_HEAD_), .od_OTHER_(od_OTHER_), .ps_do_(ps_do_),
- .ps_skip_(ps_skip_), .sir({net_0[8], sir[2], sir[3], sir[4], sir[5],
- sir[6], sir[7], sir[8], sir[9]}), .rq(rq[1:36]), .rq_succ_(rq_succ_),
- .sor({net_36[8]}), .take_E_(take_E_), .take_P_(take_P_));
-endmodule /* stageGroupsM__epiRQod */
-
-module wiresL__bitAssignments();
-endmodule /* wiresL__bitAssignments */
-
-module centersJ__ctrAND3in60(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_6, net_9;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (out, net_9);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (net_9, net_6, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2{sch}*/
- nor (strong0, strong1) #(100) nor2nn_0 (net_6, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_6));
- orangeTSMC090nm__wire90 wire90_1(.a(net_9));
-endmodule /* centersJ__ctrAND3in60 */
-
-module driversM__predDri40(in, pred);
- input in;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- orangeTSMC090nm__NMOSx NMOSx_0(.g(in), .d(pred), .s(gnd));
-endmodule /* driversM__predDri40 */
-
-module gaspM__gaspLit(do_ins_, ready, sel_Lt_, fire_L_);
- input do_ins_;
- input ready;
- input sel_Lt_;
- output fire_L_;
-
- supply1 vdd;
- supply0 gnd;
- wire invI_1_out, net_233, net_248, net_251;
-
- centersJ__ctrAND3in60 ctrAND3i_0(.inA(net_248), .inB(net_233), .inC(ready),
- .out(fire_L_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_251, fire_L_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (net_248, net_251);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (invI_1_out, net_251);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_233, sel_Lt_, do_ins_);
- // end Verilog_template
- driversM__predDri40 predDri4_0(.in(net_248), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_1(.a(net_233));
- orangeTSMC090nm__wire90 wire90_2(.a(net_251));
- orangeTSMC090nm__wire90 wire90_3(.a(net_248));
-endmodule /* gaspM__gaspLit */
-
-module driversM__latchAndDriver60(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out, net_8);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_8, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
-endmodule /* driversM__latchAndDriver60 */
-
-module stagesM__litDrivers(fire_M_, sel_Dc_, sel_Do_, sel_To_, ready, succ_D_,
- succ_T_, take_A_, take_C_);
- input fire_M_;
- input sel_Dc_;
- input sel_Do_;
- input sel_To_;
- output ready;
- output succ_D_;
- output succ_T_;
- output take_A_;
- output take_C_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_56, net_59;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_56, sel_Dc_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (take_C_, net_59);
- // end Verilog_template
- driversM__latchAndDriver60 latchAnd_1(.inA(sel_Dc_), .inB(fire_M_),
- .out(take_A_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_59, fire_M_, net_56);
- // end Verilog_template
- redFive__nor2n_sy nor2n_sy_0(.ina(succ_T_), .inb(succ_D_), .out(ready));
- driversM__sucANDdri60 sucANDdr_0(.inA(sel_Do_), .inB(fire_M_),
- .succ(succ_D_));
- driversM__sucANDdri60 sucANDdr_1(.inA(sel_To_), .inB(fire_M_),
- .succ(succ_T_));
- orangeTSMC090nm__wire90 wire90_2(.a(net_56));
- orangeTSMC090nm__wire90 wire90_3(.a(net_59));
-endmodule /* stagesM__litDrivers */
-
-module registersM__data2in60Cx18(dcl_A_, dcl_B_, inA, inB, out);
- input dcl_A_;
- input dcl_B_;
- input [1:18] inA;
- input [1:18] inB;
- output [1:18] out;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch2in60C hiL_1_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[1]}), .inB({inB[1]}), .outS({out[1]}));
- latchesK__latch2in60C hiL_2_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[2]}), .inB({inB[2]}), .outS({out[2]}));
- latchesK__latch2in60C hiL_3_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[3]}), .inB({inB[3]}), .outS({out[3]}));
- latchesK__latch2in60C hiL_4_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[4]}), .inB({inB[4]}), .outS({out[4]}));
- latchesK__latch2in60C hiL_5_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[5]}), .inB({inB[5]}), .outS({out[5]}));
- latchesK__latch2in60C hiL_6_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[6]}), .inB({inB[6]}), .outS({out[6]}));
- latchesK__latch2in60C hiL_7_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[7]}), .inB({inB[7]}), .outS({out[7]}));
- latchesK__latch2in60C hiL_8_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[8]}), .inB({inB[8]}), .outS({out[8]}));
- latchesK__latch2in60C hiL_9_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[9]}), .inB({inB[9]}), .outS({out[9]}));
- latchesK__latch2in60C hiL_10_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[10]}), .inB({inB[10]}), .outS({out[10]}));
- latchesK__latch2in60C hiL_11_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[11]}), .inB({inB[11]}), .outS({out[11]}));
- latchesK__latch2in60C hiL_12_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[12]}), .inB({inB[12]}), .outS({out[12]}));
- latchesK__latch2in60C hiL_13_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[13]}), .inB({inB[13]}), .outS({out[13]}));
- latchesK__latch2in60C hiL_14_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[14]}), .inB({inB[14]}), .outS({out[14]}));
- latchesK__latch2in60C hiL_15_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[15]}), .inB({inB[15]}), .outS({out[15]}));
- latchesK__latch2in60C hiL_16_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[16]}), .inB({inB[16]}), .outS({out[16]}));
- latchesK__latch2in60C hiL_17_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[17]}), .inB({inB[17]}), .outS({out[17]}));
- latchesK__latch2in60C hiL_18_(.hcl_A_(dcl_A_), .hcl_B_(dcl_B_),
- .inA({inA[18]}), .inB({inB[18]}), .outS({out[18]}));
-endmodule /* registersM__data2in60Cx18 */
-
-module registersM__data2in60Cx37(inA, inB, take_A_, take_B_, out);
- input [1:37] inA;
- input [1:37] inB;
- input take_A_;
- input take_B_;
- output [1:37] out;
-
- supply1 vdd;
- supply0 gnd;
- registersM__data2in60Cx18 data2in6_1(.dcl_A_(take_A_), .dcl_B_(take_B_),
- .inA(inA[1:18]), .inB(inB[1:18]), .out(out[1:18]));
- registersM__data2in60Cx18 data2in6_2(.dcl_A_(take_A_), .dcl_B_(take_B_),
- .inA(inA[20:37]), .inB(inB[20:37]), .out(out[20:37]));
- latchesK__latch2in60C latch2in_4(.hcl_A_(take_A_), .hcl_B_(take_B_),
- .inA({inA[19]}), .inB({inB[19]}), .outS({out[19]}));
- orangeTSMC090nm__wire90 wire90_0(.a(take_A_));
- orangeTSMC090nm__wire90 wire90_4(.a(take_B_));
- orangeTSMC090nm__wire90 wire90_5(.a(take_B_));
- orangeTSMC090nm__wire90 wire90_6(.a(take_A_));
-endmodule /* registersM__data2in60Cx37 */
-
-module latchesK__latch1in09_6Bi(hcl, in, out);
- input hcl;
- input [1:1] in;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_23;
-
- latchesK__raw1inLatchF hi2inLat_0(.hcl(hcl), .in(in[1:1]), .out_F_(net_18));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out[1], net_23);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_23, net_18);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
- orangeTSMC090nm__wire90 wire90_1(.a(net_23));
-endmodule /* latchesK__latch1in09_6Bi */
-
-module redFive__pms2(g, g2, d);
- input g;
- input g2;
- output d;
-
- supply1 vdd;
- wire net_2;
-
- orangeTSMC090nm__PMOSx PMOS_0(.g(g), .d(net_2), .s(vdd));
- orangeTSMC090nm__PMOSx PMOS_1(.g(g2), .d(d), .s(net_2));
-endmodule /* redFive__pms2 */
-
-module redFive__triInv(en, enB, in, out);
- input en;
- input enB;
- input in;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms2 nms2_0(.g(in), .g2(en), .d(out));
- redFive__pms2 pms2_0(.g(in), .g2(enB), .d(out));
-endmodule /* redFive__triInv */
-
-module gates2inM__mux5(inA, inB, s_F_, s_T_, out);
- input [1:1] inA;
- input [1:1] inB;
- input s_F_;
- input s_T_;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__triInv triInv_0(.en(s_T_), .enB(s_F_), .in(inA[1]), .out(out[1]));
- redFive__triInv triInv_1(.en(s_F_), .enB(s_T_), .in(inB[1]), .out(out[1]));
-endmodule /* gates2inM__mux5 */
-
-module latchGroupsK__dataMux(hcl, in, inB, s_F_, s_T_, out);
- input hcl;
- input [1:1] in;
- input [1:1] inB;
- input s_F_;
- input s_T_;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_5;
-
- latchesK__latch1in09_6Bi latch1in_1(.hcl(hcl), .in(in[1:1]), .out({net_5}));
- gates2inM__mux5 mux5_0(.inA({net_5}), .inB(inB[1:1]), .s_F_(s_F_),
- .s_T_(s_T_), .out(out[1:1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_5));
-endmodule /* latchGroupsK__dataMux */
-
-module registersM__shadowMux4(in, s_F_, s_T_, sign, out);
- input [1:4] in;
- input s_F_;
- input s_T_;
- input sign;
- output [1:4] out;
-
- supply1 vdd;
- supply0 gnd;
- wire [1:4] x;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) i_1_ (x[1], in[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) i_2_ (x[2], in[2]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) i_3_ (x[3], in[3]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) i_4_ (x[4], in[4]);
- // end Verilog_template
- gates2inM__mux5 m_1_(.inA({x[1]}), .inB({sign}), .s_F_(s_F_), .s_T_(s_T_),
- .out({out[1]}));
- gates2inM__mux5 m_2_(.inA({x[2]}), .inB({sign}), .s_F_(s_F_), .s_T_(s_T_),
- .out({out[2]}));
- gates2inM__mux5 m_3_(.inA({x[3]}), .inB({sign}), .s_F_(s_F_), .s_T_(s_T_),
- .out({out[3]}));
- gates2inM__mux5 m_4_(.inA({x[4]}), .inB({sign}), .s_F_(s_F_), .s_T_(s_T_),
- .out({out[4]}));
- orangeTSMC090nm__wire90 wire90_0(.a(x[1]));
- orangeTSMC090nm__wire90 wire90_1(.a(x[2]));
- orangeTSMC090nm__wire90 wire90_2(.a(x[3]));
- orangeTSMC090nm__wire90 wire90_3(.a(x[4]));
-endmodule /* registersM__shadowMux4 */
-
-module registersM__signLogic( \inB[15] , \inB[20] , s_F_, s_T_, sign);
- input \inB[15] , \inB[20] ;
- output s_F_;
- output s_T_;
- output sign;
-
- supply1 vdd;
- supply0 gnd;
- wire net_12, net_14, net_7;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (sign, net_12);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_7, \inB[20] );
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (s_T_, net_7);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (s_F_, s_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_12, net_14);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (net_14, net_7, \inB[15] );
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_2(.a(net_12));
- orangeTSMC090nm__wire90 wire90_4(.a(net_7));
- orangeTSMC090nm__wire90 wire90_5(.a(net_14));
-endmodule /* registersM__signLogic */
-
-module registersM__shadow(hcl, inB, inn, outt);
- input hcl;
- input [15:20] inB;
- input [1:18] inn;
- output [16:37] outt;
-
- supply1 vdd;
- supply0 gnd;
- wire s_F_, s_T_, sign;
-
- latchGroupsK__dataMux dl_1_(.hcl(hcl), .in({inn[1]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[20]}));
- latchGroupsK__dataMux dl_2_(.hcl(hcl), .in({inn[2]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[21]}));
- latchGroupsK__dataMux dl_3_(.hcl(hcl), .in({inn[3]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[22]}));
- latchGroupsK__dataMux dl_4_(.hcl(hcl), .in({inn[4]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[23]}));
- latchGroupsK__dataMux dl_5_(.hcl(hcl), .in({inn[5]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[24]}));
- latchGroupsK__dataMux dl_6_(.hcl(hcl), .in({inn[6]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[25]}));
- latchGroupsK__dataMux dl_7_(.hcl(hcl), .in({inn[7]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[26]}));
- latchGroupsK__dataMux dl_8_(.hcl(hcl), .in({inn[8]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[27]}));
- latchGroupsK__dataMux dl_9_(.hcl(hcl), .in({inn[9]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[28]}));
- latchGroupsK__dataMux dr_1_(.hcl(hcl), .in({inn[18]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[37]}));
- latchGroupsK__dataMux dr_2_(.hcl(hcl), .in({inn[17]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[36]}));
- latchGroupsK__dataMux dr_3_(.hcl(hcl), .in({inn[16]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[35]}));
- latchGroupsK__dataMux dr_4_(.hcl(hcl), .in({inn[15]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[34]}));
- latchGroupsK__dataMux dr_5_(.hcl(hcl), .in({inn[14]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[33]}));
- latchGroupsK__dataMux dr_6_(.hcl(hcl), .in({inn[13]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[32]}));
- latchGroupsK__dataMux dr_7_(.hcl(hcl), .in({inn[12]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[31]}));
- latchGroupsK__dataMux dr_8_(.hcl(hcl), .in({inn[11]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[30]}));
- latchGroupsK__dataMux dr_9_(.hcl(hcl), .in({inn[10]}), .inB({sign}),
- .s_F_(s_F_), .s_T_(s_T_), .out({outt[29]}));
- registersM__shadowMux4 shadowMu_1(.in(inB[16:19]), .s_F_(s_F_), .s_T_(s_T_),
- .sign(sign), .out(outt[16:19]));
- registersM__signLogic signLogi_0(.\inB[15] (inB[15]), .\inB[20] (inB[20]),
- .s_F_(s_F_), .s_T_(s_T_), .sign(sign));
- orangeTSMC090nm__wire90 wire90_1(.a(s_F_));
- orangeTSMC090nm__wire90 wire90_2(.a(s_T_));
- orangeTSMC090nm__wire90 wire90_3(.a(sign));
-endmodule /* registersM__shadow */
-
-module registersM__newDregister(dp, ps, take_A_, take_B_, out);
- input [1:37] dp;
- input [1:20] ps;
- input take_A_;
- input take_B_;
- output [1:37] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_66;
- wire [16:37] ss;
-
- registersM__data2in60Cx37 data2in6_0(.inA(dp[1:37]), .inB({ps[1], ps[2],
- ps[3], ps[4], ps[5], ps[6], ps[7], ps[8], ps[9], ps[10], ps[11], ps[12],
- ps[13], ps[14], ps[15], ss[16], ss[17], ss[18], ss[19], ss[20], ss[21],
- ss[22], ss[23], ss[24], ss[25], ss[26], ss[27], ss[28], ss[29], ss[30],
- ss[31], ss[32], ss[33], ss[34], ss[35], ss[36], ss[37]}),
- .take_A_(take_A_), .take_B_(take_B_), .out(out[1:37]));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_66, take_B_);
- // end Verilog_template
- registersM__shadow shadow_0(.hcl(net_66), .inB(ps[15:20]), .inn(out[1:18]),
- .outt(ss[16:37]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_66));
-endmodule /* registersM__newDregister */
-
-module registersM__addr2in60Cx7(ainA, ainB, fire_A_, fire_B_, aout);
- input [1:7] ainA;
- input [1:7] ainB;
- input fire_A_;
- input fire_B_;
- output [1:7] aout;
-
- supply1 vdd;
- supply0 gnd;
- latchesK__latch2in60C hiL_1_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[1]}), .inB({ainB[1]}), .outS({aout[1]}));
- latchesK__latch2in60C hiL_2_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[2]}), .inB({ainB[2]}), .outS({aout[2]}));
- latchesK__latch2in60C hiL_3_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[3]}), .inB({ainB[3]}), .outS({aout[3]}));
- latchesK__latch2in60C hiL_4_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[4]}), .inB({ainB[4]}), .outS({aout[4]}));
- latchesK__latch2in60C hiL_5_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[5]}), .inB({ainB[5]}), .outS({aout[5]}));
- latchesK__latch2in60C hiL_6_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[6]}), .inB({ainB[6]}), .outS({aout[6]}));
- latchesK__latch2in60C hiL_7_(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA[7]}), .inB({ainB[7]}), .outS({aout[7]}));
-endmodule /* registersM__addr2in60Cx7 */
-
-module registersM__addr2in60Cx15(ainA, ainA_TT_, ainB, ainB_TT_, fire_A_,
- fire_B_, aout, aout_TT_);
- input [1:14] ainA;
- input ainA_TT_;
- input [1:14] ainB;
- input ainB_TT_;
- input fire_A_;
- input fire_B_;
- output [1:14] aout;
- output aout_TT_;
-
- supply1 vdd;
- supply0 gnd;
- registersM__addr2in60Cx7 addr2in6_1(.ainA(ainA[1:7]), .ainB(ainB[1:7]),
- .fire_A_(fire_A_), .fire_B_(fire_B_), .aout(aout[1:7]));
- registersM__addr2in60Cx7 addr2in6_2(.ainA(ainA[8:14]), .ainB(ainB[8:14]),
- .fire_A_(fire_A_), .fire_B_(fire_B_), .aout(aout[8:14]));
- latchesK__latch2in60C latch2in_4(.hcl_A_(fire_A_), .hcl_B_(fire_B_),
- .inA({ainA_TT_}), .inB({ainB_TT_}), .outS({aout_TT_}));
- orangeTSMC090nm__wire90 wire90_3(.a(fire_A_));
- orangeTSMC090nm__wire90 wire90_4(.a(fire_B_));
- orangeTSMC090nm__wire90 wire90_5(.a(fire_B_));
- orangeTSMC090nm__wire90 wire90_6(.a(fire_A_));
-endmodule /* registersM__addr2in60Cx15 */
-
-module driversM__latchAndDriver30(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_8;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (out, net_8);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_8, inA, inB);
- // end Verilog_template
- orangeTSMC090nm__wire90 wire90_0(.a(net_8));
-endmodule /* driversM__latchAndDriver30 */
-
-module registersM__newPathReg(dp, fire_M_, ps, aout, aout_TT_);
- input [1:12] dp;
- input fire_M_;
- input [1:15] ps;
- output [14:1] aout;
- output aout_TT_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_25, net_28, net_58, ps_15not_, take_dp_, take_ps_;
-
- registersM__addr2in60Cx15 addr2in6_0(.ainA({dp[1], dp[2], dp[3], dp[4],
- dp[5], dp[6], dp[7], dp[8], dp[9], dp[10], dp[11], dp[12], dp[12],
- dp[12]}), .ainA_TT_(ps_15not_), .ainB({ps[1], ps[2], ps[3], ps[4], ps[5],
- ps[6], ps[7], ps[8], ps[9], ps[10], ps[11], ps[12], ps[13], ps[13]}),
- .ainB_TT_(ps_15not_), .fire_A_(take_dp_), .fire_B_(take_ps_),
- .aout({aout[1], aout[2], aout[3], aout[4], aout[5], aout[6], aout[7],
- aout[8], aout[9], aout[10], aout[11], aout[12], aout[13], aout[14]}),
- .aout_TT_(aout_TT_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_28, ps[13]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_25, ps[14]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (ps_15not_, ps[15]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (take_dp_, net_58);
- // end Verilog_template
- driversM__latchAndDriver30 latchAnd_1(.inA(ps[14]), .inB(fire_M_),
- .out(take_ps_));
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_1 (net_58, net_25, net_28, fire_M_);
- // end Verilog_template
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- orangeTSMC090nm__wire90 wire90_0(.a(take_ps_));
- orangeTSMC090nm__wire90 wire90_1(.a(take_dp_));
- orangeTSMC090nm__wire90 wire90_3(.a(net_28));
- orangeTSMC090nm__wire90 wire90_4(.a(net_25));
- orangeTSMC090nm__wire90 wire90_5(.a(ps_15not_));
- orangeTSMC090nm__wire90 wire90_6(.a(net_58));
-endmodule /* registersM__newPathReg */
-
-module stagesM__litDandP(do_ins_, dp, dp_B_, fire_M_, \ps[1] , \ps[2] , \ps[3]
- , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8] , \ps[9] , \ps[10] , \ps[11]
- , \ps[12] , \ps[13] , \ps[14] , \ps[15] , \ps[16] , \ps[17] , \ps[18] ,
- \ps[19] , \ps[20] , \ps[27] , signalBitFromInboundSwitchFabric, dsA,
- dsA_TT_, dsD, flag_C_, succ_D_, succ_T_);
- input do_ins_;
- input [1:37] dp;
- input dp_B_;
- input fire_M_;
- input \ps[1] , \ps[2] , \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8] ,
- \ps[9] , \ps[10] , \ps[11] , \ps[12] , \ps[13] , \ps[14] , \ps[15] ,
- \ps[16] , \ps[17] , \ps[18] , \ps[19] , \ps[20] , \ps[27] ;
- input signalBitFromInboundSwitchFabric;
- output [14:1] dsA;
- output dsA_TT_;
- output [1:37] dsD;
- output flag_C_;
- output succ_D_;
- output succ_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_108, net_140, take_A_, take_B_;
-
- wiresL__bitAssignments bitAssig_0();
- gaspM__gaspLit gaspLit_1(.do_ins_(do_ins_), .ready(net_108), .sel_Lt_(
- \ps[27] ), .fire_L_(take_B_));
- latchesK__latch2in60C latch2in_0(.hcl_A_(take_A_), .hcl_B_(net_140),
- .inA({dp_B_}), .inB({signalBitFromInboundSwitchFabric}),
- .outS({flag_C_}));
- stagesM__litDrivers litDrive_0(.fire_M_(fire_M_), .sel_Dc_( \ps[17] ),
- .sel_Do_( \ps[16] ), .sel_To_( \ps[15] ), .ready(net_108),
- .succ_D_(succ_D_), .succ_T_(succ_T_), .take_A_(take_A_),
- .take_C_(net_140));
- registersM__newDregister newDregi_0(.dp(dp[1:37]), .ps({ \ps[1] , \ps[2] ,
- \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8] , \ps[9] ,
- \ps[10] , \ps[11] , \ps[12] , \ps[13] , \ps[14] , \ps[15] , \ps[16]
- , \ps[17] , \ps[18] , \ps[19] , \ps[20] }), .take_A_(take_A_),
- .take_B_(take_B_), .out(dsD[1:37]));
- registersM__newPathReg newPathR_0(.dp(dp[26:37]), .fire_M_(fire_M_), .ps({
- \ps[1] , \ps[2] , \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] ,
- \ps[8] , \ps[9] , \ps[10] , \ps[11] , \ps[12] , \ps[13] , \ps[14] ,
- \ps[15] }), .aout(dsA[14:1]), .aout_TT_(dsA_TT_));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- orangeTSMC090nm__wire90 wire90_1(.a(net_108));
- orangeTSMC090nm__wire90 wire90_4(.a(net_140));
-endmodule /* stagesM__litDandP */
-
-module redFive__nms1(g, d);
- input g;
- output d;
-
- supply0 gnd;
- orangeTSMC090nm__NMOSx NMOS_1(.g(g), .d(d), .s(gnd));
-endmodule /* redFive__nms1 */
-
-module redFive__pms2_sy(g, g2, d);
- input g;
- input g2;
- output d;
-
- supply1 vdd;
- redFive__pms2 pms2_0(.g(g), .g2(g2), .d(d));
- redFive__pms2 pms2_1(.g(g2), .g2(g), .d(d));
-endmodule /* redFive__pms2_sy */
-
-module oneHotM__sucDri10Pair(bit, when, out_1__F_, out_1__T_);
- input [1:1] bit;
- input when;
- output out_1__F_;
- output out_1__T_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_112, net_139, net_4, net_66, net_92;
-
- orangeTSMC090nm__NMOSx NMOSx_2(.g(net_66), .d(out_1__F_), .s(net_139));
- orangeTSMC090nm__NMOSx NMOSx_3(.g(bit[1]), .d(out_1__F_), .s(net_139));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_66, when);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5 (net_92, out_1__F_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_6 (net_112, out_1__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_4, when, bit[1]);
- // end Verilog_template
- redFive__nms1 nms1_2(.g(net_92), .d(net_139));
- redFive__nms2 nms2b_0(.g(net_112), .g2(net_4), .d(out_1__T_));
- redFive__pms1 pms1_0(.g(net_4), .d(out_1__T_));
- redFive__pms2_sy pms2_sy_0(.g(net_66), .g2(bit[1]), .d(out_1__F_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_4));
- orangeTSMC090nm__wire90 wire90_1(.a(net_66));
- orangeTSMC090nm__wire90 wire90_3(.a(net_112));
- orangeTSMC090nm__wire90 wire90_4(.a(net_92));
- orangeTSMC090nm__wire90 wire90_5(.a(net_139));
-endmodule /* oneHotM__sucDri10Pair */
-
-module oneHotM__sucDri10Pairx6(bit, when, m1cate_1__F_, m1cate_1__T_,
- m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_, m1cate_4__F_,
- m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_, m1cate_6__T_,
- ready);
- input [1:6] bit;
- input when;
- output m1cate_1__F_;
- output m1cate_1__T_;
- output m1cate_2__F_;
- output m1cate_2__T_;
- output m1cate_3__F_;
- output m1cate_3__T_;
- output m1cate_4__F_;
- output m1cate_4__T_;
- output m1cate_5__F_;
- output m1cate_5__T_;
- output m1cate_6__F_;
- output m1cate_6__T_;
- output ready;
-
- supply1 vdd;
- supply0 gnd;
- oneHotM__sucDri10Pair dd_1_(.bit({bit[1]}), .when(when),
- .out_1__F_(m1cate_1__F_), .out_1__T_(m1cate_1__T_));
- oneHotM__sucDri10Pair dd_2_(.bit({bit[2]}), .when(when),
- .out_1__F_(m1cate_2__F_), .out_1__T_(m1cate_2__T_));
- oneHotM__sucDri10Pair dd_3_(.bit({bit[3]}), .when(when),
- .out_1__F_(m1cate_3__F_), .out_1__T_(m1cate_3__T_));
- oneHotM__sucDri10Pair dd_4_(.bit({bit[4]}), .when(when),
- .out_1__F_(m1cate_4__F_), .out_1__T_(m1cate_4__T_));
- oneHotM__sucDri10Pair dd_5_(.bit({bit[5]}), .when(when),
- .out_1__F_(m1cate_5__F_), .out_1__T_(m1cate_5__T_));
- oneHotM__sucDri10Pair dd_6_(.bit({bit[6]}), .when(when),
- .out_1__F_(m1cate_6__F_), .out_1__T_(m1cate_6__T_));
- redFive__nor2n_sy nor2n_sy_0(.ina(m1cate_1__T_), .inb(m1cate_1__F_),
- .out(ready));
-endmodule /* oneHotM__sucDri10Pairx6 */
-
-module oneHotM__minusOne(bit, headBit, mc, pred, fire_m1_, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, s, succ_m1_);
- input [1:6] bit;
- input headBit;
- input mc;
- input pred;
- output fire_m1_;
- output m1cate_1__F_;
- output m1cate_1__T_;
- output m1cate_2__F_;
- output m1cate_2__T_;
- output m1cate_3__F_;
- output m1cate_3__T_;
- output m1cate_4__F_;
- output m1cate_4__T_;
- output m1cate_5__F_;
- output m1cate_5__T_;
- output m1cate_6__F_;
- output m1cate_6__T_;
- output [1:1] s;
- output succ_m1_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_235, net_391, net_398, net_406, net_414;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_7 (net_235, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_235);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (fire_m1_, net_398);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_398, net_414, net_391);
- // end Verilog_template
- redFive__nor2n nor2n_0(.ina(headBit), .inb(net_398), .out(net_406));
- redFive__nor2n_sy nor2n_sy_1(.ina(succ_m1_), .inb(net_235), .out(net_391));
- driversM__predDri20wMC predDri2_0(.in(fire_m1_), .mc(mc), .pred(pred));
- oneHotM__sucDri10Pairx6 sucDri10_1(.bit(bit[1:6]), .when(net_406),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_),
- .ready(net_414));
- driversM__sucDri20 sucDri20_1(.in(fire_m1_), .succ(succ_m1_));
- orangeTSMC090nm__wire90 wire90_10(.a(fire_m1_));
- orangeTSMC090nm__wire90 wire90_11(.a(net_235));
- orangeTSMC090nm__wire90 wire90_12(.a(net_414));
- orangeTSMC090nm__wire90 wire90_13(.a(net_391));
- orangeTSMC090nm__wire90 wire90_14(.a(net_398));
- orangeTSMC090nm__wire90 wire90_15(.a(net_406));
-endmodule /* oneHotM__minusOne */
-
-module stagesM__mOneDockStage(pred_R_, ring, sir, m1, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, sor, succ_m1_, take_m1_);
- input pred_R_;
- input [1:36] ring;
- input [1:9] sir;
- output [1:36] m1;
- output m1cate_1__F_;
- output m1cate_1__T_;
- output m1cate_2__F_;
- output m1cate_2__T_;
- output m1cate_3__F_;
- output m1cate_3__T_;
- output m1cate_4__F_;
- output m1cate_4__T_;
- output m1cate_5__F_;
- output m1cate_5__T_;
- output m1cate_6__F_;
- output m1cate_6__T_;
- output [1:1] sor;
- output succ_m1_;
- output take_m1_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_47;
- wire [1:1] fire;
-
- registersM__ins1in20Bx36 ins1in20_0(.hcl({take_m1_}), .in(ring[1:36]),
- .out(m1[1:36]));
- driversM__latchDriver60 latchDri_1(.in(fire[1]), .out(take_m1_));
- oneHotM__minusOne minusOne_0(.bit(ring[31:36]), .headBit(ring[30]),
- .mc(sir[9]), .pred(pred_R_), .fire_m1_(fire[1]),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_), .s({net_47}),
- .succ_m1_(succ_m1_));
- scanM__scanEx1 scanEx1_0(.dIn({net_47}), .sir(sir[1:9]), .sor(sor[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- wiresL__tranCap tc_12_();
- wiresL__tranCap tc_13_();
- wiresL__tranCap tc_14_();
- wiresL__tranCap tc_15_();
- wiresL__tranCap tc_16_();
- wiresL__tranCap tc_17_();
- wiresL__tranCap tc_18_();
- wiresL__tranCap tc_19_();
- orangeTSMC090nm__wire90 wire90_1(.a(fire[1]));
-endmodule /* stagesM__mOneDockStage */
-
-module loopCountM__mux10_2(in, sF, sT, out);
- input [1:1] in;
- input sF;
- input sT;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms2 nms2b_0(.g(sT), .g2(in[1]), .d(out[1]));
- redFive__pms2 pms2_0(.g(sF), .g2(in[1]), .d(out[1]));
-endmodule /* loopCountM__mux10_2 */
-
-module loopCountM__mux10_2x7(in, sF, sT, out);
- input [1:7] in;
- input sF;
- input sT;
- output [1:7] out;
-
- supply1 vdd;
- supply0 gnd;
- loopCountM__mux10_2 mux10_2_0(.in({in[1]}), .sF(sF), .sT(sT),
- .out({out[1]}));
- loopCountM__mux10_2 mux10_2_1(.in({in[2]}), .sF(sF), .sT(sT),
- .out({out[2]}));
- loopCountM__mux10_2 mux10_2_2(.in({in[3]}), .sF(sF), .sT(sT),
- .out({out[3]}));
- loopCountM__mux10_2 mux10_2_3(.in({in[4]}), .sF(sF), .sT(sT),
- .out({out[4]}));
- loopCountM__mux10_2 mux10_2_4(.in({in[5]}), .sF(sF), .sT(sT),
- .out({out[5]}));
- loopCountM__mux10_2 mux10_2_5(.in({in[6]}), .sF(sF), .sT(sT),
- .out({out[6]}));
- loopCountM__mux10_2 mux10_2_6(.in({in[7]}), .sF(sF), .sT(sT),
- .out({out[7]}));
-endmodule /* loopCountM__mux10_2x7 */
-
-module loopCountM__muxForPS(in, sel, out);
- input [1:7] in;
- input sel;
- output [1:7] out;
-
- supply1 vdd;
- supply0 gnd;
- wire sF, sT;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (sT, sel);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_1 (sF, sT);
- // end Verilog_template
- loopCountM__mux10_2x7 mux10_2x_0(.in(in[1:7]), .sF(sF), .sT(sT),
- .out(out[1:7]));
- orangeTSMC090nm__wire90 wire90_0(.a(sT));
- orangeTSMC090nm__wire90 wire90_1(.a(sF));
-endmodule /* loopCountM__muxForPS */
-
-module registersM__dockPSreg(do_ins_, m1, outLO, ps);
- input do_ins_;
- input [1:27] m1;
- output [1:7] outLO;
- output [1:27] ps;
-
- supply1 vdd;
- supply0 gnd;
- wire [1:1] hold;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (hold[1], do_ins_);
- // end Verilog_template
- latchesK__latch1in20B lx_1_(.hcl(hold[1]), .in({m1[1]}), .out({ps[1]}));
- latchesK__latch1in20B lx_2_(.hcl(hold[1]), .in({m1[2]}), .out({ps[2]}));
- latchesK__latch1in20B lx_3_(.hcl(hold[1]), .in({m1[3]}), .out({ps[3]}));
- latchesK__latch1in20B lx_4_(.hcl(hold[1]), .in({m1[4]}), .out({ps[4]}));
- latchesK__latch1in20B lx_5_(.hcl(hold[1]), .in({m1[5]}), .out({ps[5]}));
- latchesK__latch1in20B lx_6_(.hcl(hold[1]), .in({m1[6]}), .out({ps[6]}));
- latchesK__latch1in20B lx_7_(.hcl(hold[1]), .in({m1[7]}), .out({ps[7]}));
- latchesK__latch1in20B lx_8_(.hcl(hold[1]), .in({m1[8]}), .out({ps[8]}));
- latchesK__latch1in20B lx_9_(.hcl(hold[1]), .in({m1[9]}), .out({ps[9]}));
- latchesK__latch1in20B lx_10_(.hcl(hold[1]), .in({m1[10]}), .out({ps[10]}));
- latchesK__latch1in20B lx_11_(.hcl(hold[1]), .in({m1[11]}), .out({ps[11]}));
- latchesK__latch1in20B lx_12_(.hcl(hold[1]), .in({m1[12]}), .out({ps[12]}));
- latchesK__latch1in20B lx_13_(.hcl(hold[1]), .in({m1[13]}), .out({ps[13]}));
- latchesK__latch1in20B lx_14_(.hcl(hold[1]), .in({m1[14]}), .out({ps[14]}));
- latchesK__latch1in20B lx_15_(.hcl(hold[1]), .in({m1[15]}), .out({ps[15]}));
- latchesK__latch1in20B lx_16_(.hcl(hold[1]), .in({m1[16]}), .out({ps[16]}));
- latchesK__latch1in20B lx_17_(.hcl(hold[1]), .in({m1[17]}), .out({ps[17]}));
- latchesK__latch1in20B lx_18_(.hcl(hold[1]), .in({m1[18]}), .out({ps[18]}));
- latchesK__latch1in20B lx_19_(.hcl(hold[1]), .in({m1[19]}), .out({ps[19]}));
- latchesK__latch1in20B lx_20_(.hcl(hold[1]), .in({m1[20]}), .out({ps[20]}));
- latchesK__latch1in20B lx_21_(.hcl(hold[1]), .in({m1[21]}), .out({ps[21]}));
- latchesK__latch1in20B lx_22_(.hcl(hold[1]), .in({m1[22]}), .out({ps[22]}));
- latchesK__latch1in20B lx_23_(.hcl(hold[1]), .in({m1[23]}), .out({ps[23]}));
- latchesK__latch1in20B lx_24_(.hcl(hold[1]), .in({m1[24]}), .out({ps[24]}));
- latchesK__latch1in20B lx_25_(.hcl(hold[1]), .in({m1[25]}), .out({ps[25]}));
- latchesK__latch1in20B lx_26_(.hcl(hold[1]), .in({m1[26]}), .out({ps[26]}));
- latchesK__latch1in20B lx_27_(.hcl(hold[1]), .in({m1[27]}), .out({ps[27]}));
- loopCountM__muxForPS muxForOD_0(.in({ps[1], ps[2], ps[3], ps[4], ps[5],
- ps[6], ps[8]}), .sel(ps[20]), .out(outLO[1:7]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- orangeTSMC090nm__wire90 wire90_0(.a(hold[1]));
-endmodule /* registersM__dockPSreg */
-
-module redFive__xor2(ina, inaB, inb, inbB, out);
- input ina;
- input inaB;
- input inb;
- input inbB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms2 nms2_0(.g(inb), .g2(ina), .d(out));
- redFive__nms2 nms2_1(.g(inbB), .g2(inaB), .d(out));
- redFive__pms2 pms2_0(.g(inbB), .g2(ina), .d(out));
- redFive__pms2 pms2_1(.g(inb), .g2(inaB), .d(out));
-endmodule /* redFive__xor2 */
-
-module oneHotM__ohXor(flag_F_, flag_T_, in_1__F_, in_1__T_, out);
- input flag_F_;
- input flag_T_;
- input in_1__F_;
- input in_1__T_;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__xor2 xor2_0(.ina(in_1__T_), .inaB(in_1__F_), .inb(flag_T_),
- .inbB(flag_F_), .out(out));
-endmodule /* oneHotM__ohXor */
-
-module oneHotM__xor6x12(flag_1__F_, flag_1__T_, flag_2__F_, flag_2__T_,
- flag_3__F_, flag_3__T_, in_1__F_, in_1__T_, in_2__F_, in_2__T_, in_3__F_,
- in_3__T_, in_4__F_, in_4__T_, in_5__F_, in_5__T_, in_6__F_, in_6__T_,
- all, any);
- input flag_1__F_;
- input flag_1__T_;
- input flag_2__F_;
- input flag_2__T_;
- input flag_3__F_;
- input flag_3__T_;
- input in_1__F_;
- input in_1__T_;
- input in_2__F_;
- input in_2__T_;
- input in_3__F_;
- input in_3__T_;
- input in_4__F_;
- input in_4__T_;
- input in_5__F_;
- input in_5__T_;
- input in_6__F_;
- input in_6__T_;
- output all;
- output any;
-
- supply1 vdd;
- supply0 gnd;
- wire match_12F_, match_12T_, match_34F_, match_34T_, match_56F_, match_56T_;
-
- gates3inM__nand3in6_6sym nand3in6_2(.inA(match_12T_), .inB(match_34T_),
- .inC(match_56T_), .out(any));
- gates3inM__nor3in6_6sym nor3in3__1(.inA(match_56F_), .inB(match_34F_),
- .inC(match_12F_), .out(all));
- oneHotM__ohXor ohMux_6(.flag_F_(flag_1__F_), .flag_T_(flag_1__T_),
- .in_1__F_(in_2__F_), .in_1__T_(in_1__F_), .out(match_12F_));
- oneHotM__ohXor ohMux_7(.flag_F_(flag_1__F_), .flag_T_(flag_1__T_),
- .in_1__F_(in_2__T_), .in_1__T_(in_1__T_), .out(match_12T_));
- oneHotM__ohXor ohMux_8(.flag_F_(flag_2__F_), .flag_T_(flag_2__T_),
- .in_1__F_(in_4__F_), .in_1__T_(in_3__F_), .out(match_34F_));
- oneHotM__ohXor ohMux_9(.flag_F_(flag_2__F_), .flag_T_(flag_2__T_),
- .in_1__F_(in_4__T_), .in_1__T_(in_3__T_), .out(match_34T_));
- oneHotM__ohXor ohMux_10(.flag_F_(flag_3__F_), .flag_T_(flag_3__T_),
- .in_1__F_(in_6__F_), .in_1__T_(in_5__F_), .out(match_56F_));
- oneHotM__ohXor ohMux_11(.flag_F_(flag_3__F_), .flag_T_(flag_3__T_),
- .in_1__F_(in_6__T_), .in_1__T_(in_5__T_), .out(match_56T_));
- orangeTSMC090nm__wire90 wire90_0(.a(match_34F_));
- orangeTSMC090nm__wire90 wire90_1(.a(match_34T_));
- orangeTSMC090nm__wire90 wire90_2(.a(match_56F_));
- orangeTSMC090nm__wire90 wire90_3(.a(match_56T_));
- orangeTSMC090nm__wire90 wire90_4(.a(match_12F_));
- orangeTSMC090nm__wire90 wire90_5(.a(match_12T_));
-endmodule /* oneHotM__xor6x12 */
-
-module oneHotM__aFlag(flag_1__clr_, flag_1__set_, flag_A__F_, flag_A__T_,
- flag_B__F_, flag_B__T_, flag_C__F_, flag_C__T_, in_1__T_, in_2__T_,
- in_3__T_, in_4__T_, in_5__T_, in_6__T_, mc, flag_1__F_, flag_1__T_);
- input flag_1__clr_;
- input flag_1__set_;
- input flag_A__F_;
- input flag_A__T_;
- input flag_B__F_;
- input flag_B__T_;
- input flag_C__F_;
- input flag_C__T_;
- input in_1__T_;
- input in_2__T_;
- input in_3__T_;
- input in_4__T_;
- input in_5__T_;
- input in_6__T_;
- input mc;
- output flag_1__F_;
- output flag_1__T_;
-
- supply1 vdd;
- supply0 gnd;
- wire in_1__F_, in_2__F_, in_3__F_, in_4__F_, in_5__F_, in_6__F_, net_172;
- wire net_2, net_22, net_234, net_235, net_236, net_240, net_265, net_305;
- wire net_306, net_308, net_5, net_50, net_68, net_9;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (flag_1__T_, net_235);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (flag_1__F_, net_234);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (net_265, net_2);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_305, mc);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_10 (net_308, net_9);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_11 (net_306, net_172);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1_ (in_1__F_, in_1__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2_ (in_2__F_, in_2__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3_ (in_3__F_, in_3__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4_ (in_4__F_, in_4__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_5_ (in_5__F_, in_5__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_6_ (in_6__F_, in_6__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_9, net_5, net_2);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_172, net_68, net_2);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_236, net_50, net_265);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_3 (net_240, net_22, net_265);
- // end Verilog_template
- redFive__nand2n nand2n_0(.ina(net_9), .inb(net_22), .out(net_50));
- redFive__nand2n nand2n_1(.ina(net_172), .inb(net_50), .out(net_22));
- redFive__nand2n nand2n_2(.ina(net_236), .inb(net_235), .out(net_234));
- redFive__nand2n nand2n_3(.ina(net_240), .inb(net_234), .out(net_235));
- redFive__nor2n_sy nor2n_sy_0(.ina(flag_1__clr_), .inb(flag_1__set_),
- .out(net_2));
- driversM__sucANDdri20 sucANDdr_0(.inA(net_305), .inB(net_308),
- .succ(flag_1__set_));
- driversM__sucANDdri20 sucANDdr_3(.inA(net_305), .inB(net_306),
- .succ(flag_1__clr_));
- orangeTSMC090nm__wire90 wire90_1(.a(net_5));
- orangeTSMC090nm__wire90 wire90_4(.a(net_22));
- orangeTSMC090nm__wire90 wire90_5(.a(net_50));
- orangeTSMC090nm__wire90 wire90_6(.a(net_9));
- orangeTSMC090nm__wire90 wire90_8(.a(net_68));
- orangeTSMC090nm__wire90 wire90_19(.a(net_172));
- orangeTSMC090nm__wire90 wire90_22(.a(net_240));
- orangeTSMC090nm__wire90 wire90_23(.a(net_236));
- orangeTSMC090nm__wire90 wire90_24(.a(net_235));
- orangeTSMC090nm__wire90 wire90_25(.a(net_234));
- orangeTSMC090nm__wire90 wire90_26(.a(net_2));
- orangeTSMC090nm__wire90 wire90_27(.a(net_265));
- orangeTSMC090nm__wire90 wire90_28(.a(net_305));
- oneHotM__xor6x12 xor6x12_0(.flag_1__F_(flag_A__F_), .flag_1__T_(flag_A__T_),
- .flag_2__F_(flag_B__F_), .flag_2__T_(flag_B__T_),
- .flag_3__F_(flag_C__F_), .flag_3__T_(flag_C__T_), .in_1__F_(in_1__F_),
- .in_1__T_(in_1__T_), .in_2__F_(in_2__F_), .in_2__T_(in_2__T_),
- .in_3__F_(in_3__F_), .in_3__T_(in_3__T_), .in_4__F_(in_4__F_),
- .in_4__T_(in_4__T_), .in_5__F_(in_5__F_), .in_5__T_(in_5__T_),
- .in_6__F_(in_6__F_), .in_6__T_(in_6__T_), .all(net_68), .any(net_5));
-endmodule /* oneHotM__aFlag */
-
-module scanM__scanEx3h(dIn, sin, mc, sout, p1p, p2p, rd);
- input [1:3] dIn;
- input sin;
- output mc;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_20;
-
- scanM__scanCellE scanCell_10(.dIn({dIn[1]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(net_18));
- scanM__scanCellE scanCell_11(.dIn({dIn[2]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_18), .sout(net_20));
- scanM__scanCellE scanCell_12(.dIn({dIn[3]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_20), .sout(sout));
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
- orangeTSMC090nm__wire90 wire90_1(.a(net_20));
-endmodule /* scanM__scanEx3h */
-
-module oneHotM__flags(flag_A__clr_, flag_A__set_, flag_B__clr_, flag_B__set_,
- flag_C__T_, m1, sin, sout, mc, p1p, p2p, rd);
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_C__T_;
- input [1:12] m1;
- input sin;
- output sout;
- inout mc;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire flag_A__F_, flag_A__T_, flag_B__F_, flag_B__T_, flag_C__F_;
- wire [1:3] s;
-
- oneHotM__aFlag aFlag_0(.flag_1__clr_(flag_A__clr_),
- .flag_1__set_(flag_A__set_), .flag_A__F_(flag_A__F_),
- .flag_A__T_(flag_A__T_), .flag_B__F_(flag_B__F_),
- .flag_B__T_(flag_B__T_), .flag_C__F_(flag_C__F_),
- .flag_C__T_(flag_C__T_), .in_1__T_(m1[1]), .in_2__T_(m1[2]),
- .in_3__T_(m1[3]), .in_4__T_(m1[4]), .in_5__T_(m1[5]), .in_6__T_(m1[6]),
- .mc(mc), .flag_1__F_(flag_A__F_), .flag_1__T_(flag_A__T_));
- oneHotM__aFlag aFlag_1(.flag_1__clr_(flag_B__clr_),
- .flag_1__set_(flag_B__set_), .flag_A__F_(flag_A__F_),
- .flag_A__T_(flag_A__T_), .flag_B__F_(flag_B__F_),
- .flag_B__T_(flag_B__T_), .flag_C__F_(flag_C__F_),
- .flag_C__T_(flag_C__T_), .in_1__T_(m1[7]), .in_2__T_(m1[8]),
- .in_3__T_(m1[9]), .in_4__T_(m1[10]), .in_5__T_(m1[11]),
- .in_6__T_(m1[12]), .mc(mc), .flag_1__F_(flag_B__F_),
- .flag_1__T_(flag_B__T_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (flag_C__F_, flag_C__T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], flag_A__F_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (s[2], flag_B__F_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (s[3], flag_C__F_);
- // end Verilog_template
- scanM__scanEx3h scanEx3h_0(.dIn(s[1:3]), .sin(sin), .mc(mc), .sout(sout),
- .p1p(p1p), .p2p(p2p), .rd(rd));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
-endmodule /* oneHotM__flags */
-
-module loopCountM__calculate(bit, bit_1, bit_2, bit_3, bit_4, bit_5, do, do_1,
- do_2, do_3, do_4, zero, zoo);
- input [1:1] bit;
- input [2:2] bit_1;
- input [3:3] bit_2;
- input [4:4] bit_3;
- input [5:5] bit_4;
- input [6:6] bit_5;
- output [2:2] do;
- output [3:3] do_1;
- output [4:4] do_2;
- output [5:5] do_3;
- output [6:6] do_4;
- output zero;
- output zoo;
-
- supply1 vdd;
- supply0 gnd;
- wire net_128, net_198, net_221, net_257, net_267, net_56, net_58;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (do[2], net_257);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_128, bit_1[2]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_257, bit[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_58, bit_2[3], bit[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_56, bit_3[4], bit_1[2]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_267, bit_2[3], bit_4[5]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_0 (net_221, bit_4[5], bit_2[3],
- bit[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_1 (net_198, bit_5[6], bit_3[4],
- bit_1[2]);
- // end Verilog_template
- redFive__nor2n nor2n_1(.ina(net_128), .inb(net_257), .out(do_1[3]));
- redFive__nor2n nor2n_2(.ina(net_58), .inb(net_128), .out(do_2[4]));
- redFive__nor2n nor2n_3(.ina(net_56), .inb(net_58), .out(do_3[5]));
- redFive__nor2n nor2n_4(.ina(net_221), .inb(net_56), .out(do_4[6]));
- redFive__nor2n nor2n_5(.ina(net_198), .inb(net_267), .out(zoo));
- redFive__nor2n nor2n_6(.ina(net_198), .inb(net_221), .out(zero));
- orangeTSMC090nm__wire90 wire90_0(.a(net_221));
- orangeTSMC090nm__wire90 wire90_1(.a(net_58));
- orangeTSMC090nm__wire90 wire90_3(.a(net_56));
- orangeTSMC090nm__wire90 wire90_5(.a(net_198));
- orangeTSMC090nm__wire90 wire90_6(.a(net_128));
- orangeTSMC090nm__wire90 wire90_8(.a(net_267));
-endmodule /* loopCountM__calculate */
-
-module latchesK__mlat1in5s(c_F_, c_T_, in, inC, out);
- input c_F_;
- input c_T_;
- input in;
- input inC;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_166;
-
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (out[1], net_166, inC);
- // end Verilog_template
- redFive__nms2 nms2_2(.g(in), .g2(c_T_), .d(net_166));
- redFive__nms2 nms2_3(.g(out[1]), .g2(c_F_), .d(net_166));
- redFive__pms2 pms2_0(.g(out[1]), .g2(c_T_), .d(net_166));
- redFive__pms2 pms2_1(.g(in), .g2(c_F_), .d(net_166));
- orangeTSMC090nm__wire90 wire90_19(.a(net_166));
-endmodule /* latchesK__mlat1in5s */
-
-module latchesK__mlat1in5i(c_F_, c_T_, in, out);
- input c_F_;
- input c_T_;
- input in;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_114;
-
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_114, out);
- // end Verilog_template
- redFive__nms2 nms2_2(.g(in), .g2(c_T_), .d(out));
- redFive__nms2 nms2_3(.g(net_114), .g2(c_F_), .d(out));
- redFive__pms2 pms2_0(.g(net_114), .g2(c_T_), .d(out));
- redFive__pms2 pms2_1(.g(in), .g2(c_F_), .d(out));
- orangeTSMC090nm__wire90 wire90_19(.a(net_114));
-endmodule /* latchesK__mlat1in5i */
-
-module latchesK__mlat2in10i(clA_F_, clA_T_, clB_F_, clB_T_, inA, inB, out);
- input clA_F_;
- input clA_T_;
- input clB_F_;
- input clB_T_;
- input inA;
- input inB;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_33;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_33, out[1]);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(inB), .g2(clB_T_), .d(out[1]));
- redFive__nms2 nms2_1(.g(inA), .g2(clA_T_), .d(out[1]));
- redFive__nms3 nms3_0(.g(clB_F_), .g2(clA_F_), .g3(net_33), .d(out[1]));
- redFive__pms2 pms2_0(.g(inB), .g2(clB_F_), .d(out[1]));
- redFive__pms2 pms2_1(.g(inA), .g2(clA_F_), .d(out[1]));
- redFive__pms3 pms3_0(.g(clA_T_), .g2(clB_T_), .g3(net_33), .d(out[1]));
- orangeTSMC090nm__wire90 wire90_1(.a(net_33));
-endmodule /* latchesK__mlat2in10i */
-
-module loopCountM__ringB(count_F_, count_T_, do, inLO, load_F_, load_T_, bit);
- input count_F_;
- input count_T_;
- input [1:1] do;
- input [1:1] inLO;
- input load_F_;
- input load_T_;
- output [1:1] bit;
-
- supply1 vdd;
- supply0 gnd;
- wire net_60, net_65, net_67, net_77, net_9, xx_F_, xx_T_;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (bit[1], net_60);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_67, bit[1]);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_65, net_67);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_3 (xx_F_, xx_T_);
- // end Verilog_template
- latchesK__mlat1in5i mlat1in5_0(.c_F_(xx_T_), .c_T_(xx_F_), .in(net_65),
- .out(net_9));
- latchesK__mlat1in5i mlat1in5_1(.c_F_(count_T_), .c_T_(count_F_), .in(do[1]),
- .out(net_77));
- latchesK__mlat2in10i mlat2in1_0(.clA_F_(load_F_), .clA_T_(load_T_),
- .clB_F_(xx_F_), .clB_T_(xx_T_), .inA(inLO[1]), .inB(net_9),
- .out({net_60}));
- redFive__nor2n nor2n_0(.ina(net_77), .inb(count_F_), .out(xx_T_));
- orangeTSMC090nm__wire90 wire90_1(.a(net_67));
- orangeTSMC090nm__wire90 wire90_2(.a(net_65));
- orangeTSMC090nm__wire90 wire90_3(.a(net_60));
- orangeTSMC090nm__wire90 wire90_5(.a(net_9));
- orangeTSMC090nm__wire90 wire90_6(.a(xx_F_));
- orangeTSMC090nm__wire90 wire90_7(.a(net_77));
- orangeTSMC090nm__wire90 wire90_8(.a(xx_T_));
-endmodule /* loopCountM__ringB */
-
-module loopCountM__ilcEven(do, do_1, do_2, ilc_decLO_, ilc_torpLO_, \inLO[2] ,
- \inLO[4] , \inLO[6] , \inLO[8] , load_T_, zero, \bitt[2] , \bitt[4] ,
- \bitt[6] , \bitt[8] );
- input [2:2] do;
- input [4:4] do_1;
- input [6:6] do_2;
- input ilc_decLO_;
- input ilc_torpLO_;
- input \inLO[2] , \inLO[4] , \inLO[6] , \inLO[8] ;
- input load_T_;
- input zero;
- output \bitt[2] , \bitt[4] , \bitt[6] , \bitt[8] ;
-
- supply1 vdd;
- supply0 gnd;
- wire count_F_, count_T_, load_F_;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_7 (count_F_, count_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_8 (load_F_, load_T_);
- // end Verilog_template
- latchesK__mlat1in5s mlat1in5_1(.c_F_(load_F_), .c_T_(load_T_), .in( \inLO[8]
- ), .inC(ilc_torpLO_), .out({ \bitt[8] }));
- redFive__nor2n nor2n_0(.ina(zero), .inb(ilc_decLO_), .out(count_T_));
- loopCountM__ringB ringB_3(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_2[6:6]), .inLO({ \inLO[6] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[6] }));
- loopCountM__ringB ringB_4(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_1[4:4]), .inLO({ \inLO[4] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[4] }));
- loopCountM__ringB ringB_5(.count_F_(count_F_), .count_T_(count_T_),
- .do(do[2:2]), .inLO({ \inLO[2] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[2] }));
- orangeTSMC090nm__wire90 wire90_8(.a(count_F_));
- orangeTSMC090nm__wire90 wire90_9(.a(load_F_));
- orangeTSMC090nm__wire90 wire90_10(.a(count_T_));
-endmodule /* loopCountM__ilcEven */
-
-module latchesK__mlat2in5s(clA_F_, clA_T_, clB_F_, clB_T_, inA, inB, inC,
- out);
- input clA_F_;
- input clA_T_;
- input clB_F_;
- input clB_T_;
- input inA;
- input inB;
- input inC;
- output [1:1] out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_4;
-
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (out[1], net_4, inC);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(inB), .g2(clB_T_), .d(net_4));
- redFive__nms2 nms2_1(.g(inA), .g2(clA_T_), .d(net_4));
- redFive__nms3 nms3_0(.g(clA_F_), .g2(out[1]), .g3(clB_F_), .d(net_4));
- redFive__pms2 pms2_0(.g(inB), .g2(clB_F_), .d(net_4));
- redFive__pms2 pms2_1(.g(inA), .g2(clA_F_), .d(net_4));
- redFive__pms3 pms3_0(.g(clA_T_), .g2(out[1]), .g3(clB_T_), .d(net_4));
- orangeTSMC090nm__wire90 wire90_0(.a(net_4));
-endmodule /* latchesK__mlat2in5s */
-
-module loopCountM__ilcOdd(do, do_1, do_2, ilc_decLO_, ilc_torpLO_, \inLO[1] ,
- \inLO[3] , \inLO[5] , load_T_, zero, \bitt[1] , \bitt[3] , \bitt[5] ,
- \bitt[7] );
- input [3:3] do;
- input [5:5] do_1;
- input [7:7] do_2;
- input ilc_decLO_;
- input ilc_torpLO_;
- input \inLO[1] , \inLO[3] , \inLO[5] ;
- input load_T_;
- input zero;
- output \bitt[1] , \bitt[3] , \bitt[5] , \bitt[7] ;
-
- supply1 vdd;
- supply0 gnd;
- wire check_F_, check_T_, count_F_, count_T_, load_F_, net_511;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_5 (count_F_, count_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_6 (load_F_, load_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_7 (check_F_, check_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_8 (check_T_, ilc_decLO_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_12 ( \bitt[7] , net_511);
- // end Verilog_template
- latchesK__mlat2in5s mlat2in5_4(.clA_F_(load_F_), .clA_T_(load_T_),
- .clB_F_(check_F_), .clB_T_(check_T_), .inA(gnd), .inB(do_2[7]),
- .inC(ilc_torpLO_), .out({net_511}));
- redFive__nor2n nor2n_0(.ina(zero), .inb(ilc_decLO_), .out(count_T_));
- loopCountM__ringB ringB_3(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_1[5:5]), .inLO({ \inLO[5] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[5] }));
- loopCountM__ringB ringB_4(.count_F_(count_F_), .count_T_(count_T_),
- .do(do[3:3]), .inLO({ \inLO[3] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[3] }));
- loopCountM__ringB ringB_5(.count_F_(count_F_), .count_T_(count_T_),
- .do({vdd}), .inLO({ \inLO[1] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[1] }));
- orangeTSMC090nm__wire90 wire90_4(.a(count_F_));
- orangeTSMC090nm__wire90 wire90_5(.a(load_F_));
- orangeTSMC090nm__wire90 wire90_6(.a(check_F_));
- orangeTSMC090nm__wire90 wire90_7(.a(count_T_));
- orangeTSMC090nm__wire90 wire90_8(.a(check_T_));
- orangeTSMC090nm__wire90 wire90_9(.a(net_511));
-endmodule /* loopCountM__ilcOdd */
-
-module gates3inM__orNand10(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_14;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(inC), .d(out), .s(net_14));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(inB), .d(out), .s(net_14));
- redFive__nms1 nms1_0(.g(inA), .d(net_14));
- redFive__pms1 pms1_0(.g(inA), .d(net_14));
- redFive__pms2 pms2_0(.g(inC), .g2(inB), .d(out));
-endmodule /* gates3inM__orNand10 */
-
-module loopCountM__ilc(ilc_decLO_, ilc_load_, ilc_torpLO_, \inLO[1] , \inLO[2]
- , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8] , bitt, ilc_do_,
- ilc_mo_);
- input ilc_decLO_;
- input ilc_load_;
- input ilc_torpLO_;
- input \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] ,
- \inLO[8] ;
- output [1:8] bitt;
- output ilc_do_;
- output ilc_mo_;
-
- supply1 vdd;
- supply0 gnd;
- wire ovf, zero;
- wire [7:2] do;
-
- loopCountM__calculate calculat_0(.bit({bitt[1]}), .bit_1({bitt[2]}),
- .bit_2({bitt[3]}), .bit_3({bitt[4]}), .bit_4({bitt[5]}),
- .bit_5({bitt[6]}), .do(do[2:2]), .do_1(do[3:3]), .do_2(do[4:4]),
- .do_3(do[5:5]), .do_4(do[6:6]), .zero(zero), .zoo(do[7]));
- loopCountM__ilcEven ilcEven_0(.do(do[2:2]), .do_1(do[4:4]), .do_2(do[6:6]),
- .ilc_decLO_(ilc_decLO_), .ilc_torpLO_(ilc_torpLO_), .\inLO[2] ( \inLO[2]
- ), .\inLO[4] ( \inLO[4] ), .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8]
- ), .load_T_(ilc_load_), .zero(zero), .\bitt[2] (bitt[2]), .\bitt[4]
- (bitt[4]), .\bitt[6] (bitt[6]), .\bitt[8] (bitt[8]));
- loopCountM__ilcOdd ilcOdd_0(.do(do[3:3]), .do_1(do[5:5]), .do_2(do[7:7]),
- .ilc_decLO_(ilc_decLO_), .ilc_torpLO_(ilc_torpLO_), .\inLO[1] ( \inLO[1]
- ), .\inLO[3] ( \inLO[3] ), .\inLO[5] ( \inLO[5] ), .load_T_(ilc_load_),
- .zero(zero), .\bitt[1] (bitt[1]), .\bitt[3] (bitt[3]), .\bitt[5]
- (bitt[5]), .\bitt[7] (bitt[7]));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (ovf, bitt[7]);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_0 (ilc_do_, bitt[8], bitt[7], zero);
- // end Verilog_template
- gates3inM__orNand10 orNand10_0(.inA(bitt[8]), .inB(ovf), .inC(do[7]),
- .out(ilc_mo_));
- orangeTSMC090nm__wire90 wire90_1(.a(do[2]));
- orangeTSMC090nm__wire90 wire90_2(.a(do[3]));
- orangeTSMC090nm__wire90 wire90_3(.a(do[4]));
- orangeTSMC090nm__wire90 wire90_4(.a(do[5]));
- orangeTSMC090nm__wire90 wire90_5(.a(do[6]));
- orangeTSMC090nm__wire90 wire90_48(.a(bitt[7]));
- orangeTSMC090nm__wire90 wire90_49(.a(bitt[8]));
- orangeTSMC090nm__wire90 wire90_51(.a(zero));
-endmodule /* loopCountM__ilc */
-
-module gates3inM__nand3in44s(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_0 (out, inA, inB, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand3{sch}*/
- nand (strong0, strong1) #(100) nand3_1 (out, inB, inA, inC);
- // end Verilog_template
-endmodule /* gates3inM__nand3in44s */
-
-module moveM__moveRepeat(do_ins_, in_D_, in_T_, sel_Di_, sel_Mv_, sel_Ti_,
- sel_Tp_, succ_sf_, torp, fire_T_, winLO_M_);
- input do_ins_;
- input in_D_;
- input in_T_;
- input sel_Di_;
- input sel_Mv_;
- input sel_Ti_;
- input sel_Tp_;
- input succ_sf_;
- input torp;
- output fire_T_;
- output winLO_M_;
-
- supply1 vdd;
- supply0 gnd;
- wire invI_7_out, net_11, net_12, net_150, net_217, net_221, net_32, net_38;
- wire net_43, net_44, net_53, net_57, net_60, net_86, net_98;
-
- arbiterM__arbiter2 arbiter2_0(.req_A_(torp), .req_B_(in_D_),
- .grant_A_(net_12), .grant_B_(net_11));
- arbiterM__arbiter2 arbiter2_1(.req_A_(torp), .req_B_(in_T_),
- .grant_A_(net_32), .grant_B_(net_53));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (fire_T_, net_150);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_6 (net_217, net_221);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_7 (invI_7_out, net_217);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_86, net_217, do_ins_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_5 (net_221, winLO_M_, sel_Mv_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_6 (net_38, sel_Tp_, do_ins_);
- // end Verilog_template
- redFive__nand2n nand2n_0(.ina(sel_Di_), .inb(net_11), .out(net_57));
- redFive__nand2n nand2n_1(.ina(sel_Ti_), .inb(net_53), .out(net_60));
- gates3inM__nand3in44s nand3in4_0(.inA(net_57), .inB(net_60), .inC(net_98),
- .out(winLO_M_));
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_0 (net_150, net_43, net_44);
- // end Verilog_template
- redFive__nor2n nor2n_0(.ina(net_38), .inb(net_12), .out(net_44));
- redFive__nor2n nor2n_1(.ina(net_38), .inb(net_32), .out(net_43));
- redFive__nor2n nor2n_2(.ina(succ_sf_), .inb(net_86), .out(net_98));
- orangeTSMC090nm__wire90 wire90_0(.a(net_12));
- orangeTSMC090nm__wire90 wire90_1(.a(net_32));
- orangeTSMC090nm__wire90 wire90_2(.a(net_53));
- orangeTSMC090nm__wire90 wire90_3(.a(net_11));
- orangeTSMC090nm__wire90 wire90_4(.a(net_38));
- orangeTSMC090nm__wire90 wire90_6(.a(net_44));
- orangeTSMC090nm__wire90 wire90_7(.a(net_43));
- orangeTSMC090nm__wire90 wire90_8(.a(net_60));
- orangeTSMC090nm__wire90 wire90_9(.a(net_57));
- orangeTSMC090nm__wire90 wire90_11(.a(net_86));
- orangeTSMC090nm__wire90 wire90_13(.a(net_98));
- orangeTSMC090nm__wire90 wire90_15(.a(net_150));
- orangeTSMC090nm__wire90 wire90_19(.a(net_217));
- orangeTSMC090nm__wire90 wire90_20(.a(net_221));
-endmodule /* moveM__moveRepeat */
-
-module moveM__moveOut(do_ins_, epi_torp_, ilc_do_, ilc_mo_, mc, pred_D_,
- pred_T_, sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, succ_sf_, doneLO_M_,
- fire_M_, flag_D__set_, ilc_decLO_, ilc_torpLO_, s);
- input do_ins_;
- input epi_torp_;
- input ilc_do_;
- input ilc_mo_;
- input mc;
- input pred_D_;
- input pred_T_;
- input sel_Di_;
- input sel_Mv_;
- input sel_Ti_;
- input sel_Tp_;
- input succ_sf_;
- output doneLO_M_;
- output fire_M_;
- output flag_D__set_;
- output ilc_decLO_;
- output ilc_torpLO_;
- output [1:3] s;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_T_, net_194, net_200, net_201, net_205, net_206, net_220, net_227;
- wire net_250, net_29, net_326;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_9 (net_326, fire_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_10 (net_220, ilc_do_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_13 (net_194, pred_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_14 (net_227, pred_D_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_15 (net_29, epi_torp_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_16 (ilc_torpLO_, fire_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_9 (s[1], net_194);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_10 (s[2], net_227);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_11 (s[3], net_29);
- // end Verilog_template
- moveM__moveRepeat moveRepe_0(.do_ins_(do_ins_), .in_D_(pred_D_),
- .in_T_(pred_T_), .sel_Di_(sel_Di_), .sel_Mv_(sel_Mv_), .sel_Ti_(sel_Ti_),
- .sel_Tp_(sel_Tp_), .succ_sf_(succ_sf_), .torp(epi_torp_),
- .fire_T_(fire_T_), .winLO_M_(ilc_decLO_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_206, ilc_do_, sel_Di_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_3 (net_205, ilc_do_, sel_Ti_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_4 (doneLO_M_, sel_Tp_, net_250);
- // end Verilog_template
- redFive__nor2n nor2n_1(.ina(ilc_mo_), .inb(ilc_decLO_), .out(net_250));
- redFive__nor2n nor2n_5(.ina(net_206), .inb(ilc_decLO_), .out(net_201));
- redFive__nor2n nor2n_6(.ina(net_205), .inb(ilc_decLO_), .out(net_200));
- redFive__nor2n nor2n_7(.ina(net_220), .inb(ilc_decLO_), .out(fire_M_));
- redFive__pms1 pms1_0(.g(net_326), .d(flag_D__set_));
- driversM__predDri20wMC predDri2_0(.in(fire_T_), .mc(mc), .pred(epi_torp_));
- driversM__predDri20wMC predDri2_3(.in(net_201), .mc(mc), .pred(pred_D_));
- driversM__predDri20wMC predDri2_4(.in(net_200), .mc(mc), .pred(pred_T_));
- driversM__predDri40 predDri4_0(.in(net_250), .pred(do_ins_));
- driversM__predDri40 predDri4_1(.in(fire_T_), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_9(.a(net_206));
- orangeTSMC090nm__wire90 wire90_10(.a(net_220));
- orangeTSMC090nm__wire90 wire90_11(.a(net_200));
- orangeTSMC090nm__wire90 wire90_12(.a(net_201));
- orangeTSMC090nm__wire90 wire90_13(.a(net_205));
- orangeTSMC090nm__wire90 wire90_15(.a(net_250));
- orangeTSMC090nm__wire90 wire90_16(.a(fire_T_));
- orangeTSMC090nm__wire90 wire90_17(.a(net_326));
-endmodule /* moveM__moveOut */
-
-module scanM__scanEx1h(dIn, sin, mc, sout, p1p, p2p, rd);
- input [1:1] dIn;
- input sin;
- output mc;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- scanM__scanCellE scanCell_10(.dIn(dIn[1:1]), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(sout));
-endmodule /* scanM__scanEx1h */
-
-module scanM__scanEx2h(dIn, sin, mc, sout, p1p, p2p, rd);
- input [1:2] dIn;
- input sin;
- output mc;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18;
-
- scanM__scanCellE scanCell_10(.dIn({dIn[1]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(net_18));
- scanM__scanCellE scanCell_11(.dIn({dIn[2]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_18), .sout(sout));
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
-endmodule /* scanM__scanEx2h */
-
-module scanM__scanEx4h(dIn, sin, mc, sout, p1p, p2p, rd);
- input [1:4] dIn;
- input sin;
- output mc;
- output sout;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_20, net_24;
-
- scanM__scanCellE scanCell_10(.dIn({dIn[1]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(sin), .sout(net_18));
- scanM__scanCellE scanCell_11(.dIn({dIn[2]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_18), .sout(net_20));
- scanM__scanCellE scanCell_12(.dIn({dIn[3]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_20), .sout(net_24));
- scanM__scanCellE scanCell_13(.dIn({dIn[4]}), .p1p(p1p), .p2p(p2p), .rd(rd),
- .sin(net_24), .sout(sout));
- orangeTSMC090nm__wire90 wire90_0(.a(net_18));
- orangeTSMC090nm__wire90 wire90_1(.a(net_20));
- orangeTSMC090nm__wire90 wire90_2(.a(net_24));
-endmodule /* scanM__scanEx4h */
-
-module moveM__ilcMoveOut(do_ins_, epi_torp_, ilc_load_, \inLO[1] , \inLO[2] ,
- \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8] , pred_D_, pred_T_,
- sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, sin, succ_sf_, doneLO_M_, fire_M_,
- flag_D__set_, sout, mc, p1p, p2p, rd);
- input do_ins_;
- input epi_torp_;
- input ilc_load_;
- input \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] ,
- \inLO[8] ;
- input pred_D_;
- input pred_T_;
- input sel_Di_;
- input sel_Mv_;
- input sel_Ti_;
- input sel_Tp_;
- input sin;
- input succ_sf_;
- output doneLO_M_;
- output fire_M_;
- output flag_D__set_;
- output sout;
- inout mc;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire ilc_decLO_, ilc_do_, ilc_mo_, ilc_torpLO_, net_50, net_84, net_85;
- wire [1:8] bitt;
- wire [1:3] s;
-
- loopCountM__ilc ilc_0(.ilc_decLO_(ilc_decLO_), .ilc_load_(ilc_load_),
- .ilc_torpLO_(ilc_torpLO_), .\inLO[1] ( \inLO[1] ), .\inLO[2] ( \inLO[2]
- ), .\inLO[3] ( \inLO[3] ), .\inLO[4] ( \inLO[4] ), .\inLO[5] ( \inLO[5]
- ), .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8] ), .bitt(bitt[1:8]),
- .ilc_do_(ilc_do_), .ilc_mo_(ilc_mo_));
- moveM__moveOut outDockM_0(.do_ins_(do_ins_), .epi_torp_(epi_torp_),
- .ilc_do_(ilc_do_), .ilc_mo_(ilc_mo_), .mc(mc), .pred_D_(pred_D_),
- .pred_T_(pred_T_), .sel_Di_(sel_Di_), .sel_Mv_(sel_Mv_),
- .sel_Ti_(sel_Ti_), .sel_Tp_(sel_Tp_), .succ_sf_(succ_sf_),
- .doneLO_M_(doneLO_M_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_),
- .ilc_decLO_(ilc_decLO_), .ilc_torpLO_(ilc_torpLO_), .s(s[1:3]));
- scanM__scanEx1h scanEx1h_0(.dIn({s[3]}), .sin(net_84), .mc(mc), .sout(sout),
- .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx2h scanEx2h_0(.dIn(s[1:2]), .sin(net_85), .mc(mc),
- .sout(net_84), .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx4h scanEx4h_0(.dIn({bitt[1], bitt[3], bitt[5], bitt[7]}),
- .sin(sin), .mc(mc), .sout(net_50), .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx4h scanEx4h_1(.dIn({bitt[2], bitt[4], bitt[6], bitt[8]}),
- .sin(net_50), .mc(mc), .sout(net_85), .p1p(p1p), .p2p(p2p), .rd(rd));
- orangeTSMC090nm__wire90 wire90_1(.a(ilc_mo_));
- orangeTSMC090nm__wire90 wire90_2(.a(ilc_do_));
- orangeTSMC090nm__wire90 wire90_3(.a(bitt[8]));
- orangeTSMC090nm__wire90 wire90_4(.a(bitt[1]));
- orangeTSMC090nm__wire90 wire90_5(.a(bitt[2]));
- orangeTSMC090nm__wire90 wire90_6(.a(bitt[3]));
- orangeTSMC090nm__wire90 wire90_7(.a(bitt[4]));
- orangeTSMC090nm__wire90 wire90_8(.a(bitt[5]));
- orangeTSMC090nm__wire90 wire90_9(.a(bitt[6]));
- orangeTSMC090nm__wire90 wire90_10(.a(bitt[7]));
- orangeTSMC090nm__wire90 wire90_11(.a(ilc_decLO_));
- orangeTSMC090nm__wire90 wire90_12(.a(ilc_torpLO_));
-endmodule /* moveM__ilcMoveOut */
-
-module loopCountM__muxForD(in, sel, outLO);
- input [1:6] in;
- input sel;
- output [1:7] outLO;
-
- supply1 vdd;
- supply0 gnd;
- wire sF, sT;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (sF, sel);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_1 (sT, sF);
- // end Verilog_template
- loopCountM__mux10_2x7 mux10_2x_0(.in({in[1], in[2], in[3], in[4], in[5],
- in[6], gnd}), .sF(sF), .sT(sT), .out(outLO[1:7]));
- orangeTSMC090nm__wire90 wire90_0(.a(sF));
- orangeTSMC090nm__wire90 wire90_1(.a(sT));
-endmodule /* loopCountM__muxForD */
-
-module predicateM__nand3in20sr(inA, inB, inC, resetLO, out);
- input inA;
- input inB;
- input inC;
- input resetLO;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms3 nms3a_0(.g(inA), .g2(inB), .g3(inC), .d(out));
- redFive__pms1 pms1_0(.g(inC), .d(out));
- redFive__pms1 pms1_1(.g(inB), .d(out));
- redFive__pms1 pms1_2(.g(inA), .d(out));
- redFive__pms1 pms1_3(.g(resetLO), .d(out));
-endmodule /* predicateM__nand3in20sr */
-
-module predicateM__flagNOP(do_ins_, ps_Fl_);
- input do_ins_;
- input ps_Fl_;
-
- supply1 vdd;
- supply0 gnd;
- wire invI_2_out, invI_3_out, net_0, net_15, net_22, net_4;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_22, net_15);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (net_4, net_22);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (net_15, net_0);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (invI_2_out, net_15);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_3 (invI_3_out, net_22);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_0, ps_Fl_, do_ins_);
- // end Verilog_template
- driversM__predDri40 predDri4_0(.in(net_4), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_0));
- orangeTSMC090nm__wire90 wire90_1(.a(net_15));
- orangeTSMC090nm__wire90 wire90_2(.a(net_4));
- orangeTSMC090nm__wire90 wire90_3(.a(net_22));
-endmodule /* predicateM__flagNOP */
-
-module driversM__predCond20wMC(cond, in, mc, pred);
- input cond;
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145, net_210;
-
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(pred), .s(gnd));
- orangeTSMC090nm__PMOSx PMOSx_0(.g(in), .d(pred), .s(net_210));
- orangeTSMC090nm__PMOSx PMOSx_1(.g(cond), .d(pred), .s(net_210));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_145, pred);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(cond), .g2(in), .d(pred));
- redFive__pms2 pms2a_0(.g(mc), .g2(net_145), .d(net_210));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
- orangeTSMC090nm__wire90 wire90_1(.a(net_210));
-endmodule /* driversM__predCond20wMC */
-
-module driversM__predCond20wMS(cond, in, mc, pred);
- input cond;
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145, net_210, net_240;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(cond), .d(pred), .s(net_210));
- orangeTSMC090nm__PMOSx PMOSx_1(.g(in), .d(pred), .s(net_210));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_145, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_240, mc);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(cond), .g2(in), .d(pred));
- redFive__pms1 pms1_0(.g(net_240), .d(pred));
- redFive__pms2 pms2a_0(.g(mc), .g2(net_145), .d(net_210));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
- orangeTSMC090nm__wire90 wire90_1(.a(net_210));
-endmodule /* driversM__predCond20wMS */
-
-module predicateM__predFlagDri(fire_do_, flag_A__clr_, flag_A__set_,
- flag_B__clr_, flag_B__set_, flag_D__clr_, flag_D__set_, mc, sel_Fl_,
- sel_rD_);
- input fire_do_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input mc;
- input sel_Fl_;
- input sel_rD_;
-
- supply1 vdd;
- supply0 gnd;
- wiresL__bitAssignments bitAssig_0();
- driversM__predCond20wMC pc_1_(.cond(sel_Fl_), .in(fire_do_), .mc(mc),
- .pred(flag_A__set_));
- driversM__predCond20wMC pc_2_(.cond(sel_Fl_), .in(fire_do_), .mc(mc),
- .pred(flag_A__clr_));
- driversM__predCond20wMC pc_3_(.cond(sel_Fl_), .in(fire_do_), .mc(mc),
- .pred(flag_B__set_));
- driversM__predCond20wMC pc_4_(.cond(sel_Fl_), .in(fire_do_), .mc(mc),
- .pred(flag_B__clr_));
- driversM__predCond20wMC predCond_0(.cond(sel_rD_), .in(fire_do_), .mc(mc),
- .pred(flag_D__clr_));
- driversM__predCond20wMS predCond_1(.cond(sel_rD_), .in(fire_do_), .mc(mc),
- .pred(flag_D__set_));
-endmodule /* predicateM__predFlagDri */
-
-module driversM__sucDri40keep(in, mc, succ);
- input in;
- input mc;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_110, net_113;
-
- orangeTSMC090nm__PMOSx PMOSx_0(.g(net_110), .d(succ), .s(vdd));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_110, in);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (net_113, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:invK{sch}*/
- not (weak0, weak1) #(100) invK_0 (succ, net_113);
- // end Verilog_template
- redFive__nms1 nms1_0(.g(mc), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_113));
- orangeTSMC090nm__wire90 wire90_1(.a(net_110));
-endmodule /* driversM__sucDri40keep */
-
-module predicateM__ohPredDo(fire_do_, fire_skip_, flag_A__clr_, flag_A__set_,
- flag_B__clr_, flag_B__set_, flag_D__clr_, flag_D__set_, m1_Fl_, m1_rD_,
- mc, ps_Fl_, do_ins_, ps_do_, ps_skip_, s);
- input fire_do_;
- input fire_skip_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input m1_Fl_;
- input m1_rD_;
- input mc;
- input ps_Fl_;
- output do_ins_;
- output ps_do_;
- output ps_skip_;
- output [3:3] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_156;
-
- wiresL__bitAssignments bitAssig_0();
- predicateM__flagNOP flagNOP_0(.do_ins_(do_ins_), .ps_Fl_(ps_Fl_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_156, do_ins_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[3], net_156);
- // end Verilog_template
- predicateM__predFlagDri predFlag_1(.fire_do_(fire_do_),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .mc(mc),
- .sel_Fl_(m1_Fl_), .sel_rD_(m1_rD_));
- driversM__sucDri20 sucDri20_0(.in(fire_skip_), .succ(ps_skip_));
- driversM__sucDri20 sucDri20_1(.in(fire_do_), .succ(ps_do_));
- driversM__sucDri40keep sucDri40_0(.in(fire_do_), .mc(mc), .succ(do_ins_));
- orangeTSMC090nm__wire90 wire90_2(.a(fire_skip_));
- orangeTSMC090nm__wire90 wire90_3(.a(net_156));
-endmodule /* predicateM__ohPredDo */
-
-module predicateM__ohSRxor(flag_F_, flag_T_, resetLO, sel, out);
- input flag_F_;
- input flag_T_;
- input resetLO;
- input [1:2] sel;
- output out; trireg out;
-
- supply1 vdd;
- supply0 gnd;
- redFive__nms2 nms2b_4(.g(flag_T_), .g2(sel[1]), .d(out));
- redFive__nms2 nms2b_5(.g(flag_F_), .g2(sel[2]), .d(out));
- redFive__pms1 pms1_0(.g(resetLO), .d(out));
- redFive__pms2 pms2_0(.g(flag_T_), .g2(sel[2]), .d(out));
- redFive__pms2 pms2_1(.g(flag_F_), .g2(sel[1]), .d(out));
-endmodule /* predicateM__ohSRxor */
-
-module predicateM__ohSRxor6x12(flag_A__clr_, flag_A__set_, flag_B__clr_,
- flag_B__set_, flag_D__clr_, flag_D__set_, in_1__F_, in_1__T_, in_2__F_,
- in_2__T_, in_3__F_, in_3__T_, in_4__F_, in_4__T_, in_5__F_, in_5__T_,
- in_6__F_, in_6__T_, resetLO, all, any);
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input in_1__F_;
- input in_1__T_;
- input in_2__F_;
- input in_2__T_;
- input in_3__F_;
- input in_3__T_;
- input in_4__F_;
- input in_4__T_;
- input in_5__F_;
- input in_5__T_;
- input in_6__F_;
- input in_6__T_;
- input resetLO;
- output all;
- output any;
-
- supply1 vdd;
- supply0 gnd;
- wire match_12F_, match_12T_, match_34F_, match_34T_, match_56F_, match_56T_;
-
- gates3inM__nand3in6_6sym nand3in6_3(.inA(match_12T_), .inB(match_34T_),
- .inC(match_56T_), .out(any));
- gates3inM__nor3in6_6sym nor3in3__2(.inA(match_12F_), .inB(match_34F_),
- .inC(match_56F_), .out(all));
- predicateM__ohSRxor ohSRxor_6(.flag_F_(flag_A__clr_), .flag_T_(flag_A__set_),
- .resetLO(resetLO), .sel({in_1__T_, in_2__T_}), .out(match_12T_));
- predicateM__ohSRxor ohSRxor_7(.flag_F_(flag_A__clr_), .flag_T_(flag_A__set_),
- .resetLO(resetLO), .sel({in_1__F_, in_2__F_}), .out(match_12F_));
- predicateM__ohSRxor ohSRxor_8(.flag_F_(flag_B__clr_), .flag_T_(flag_B__set_),
- .resetLO(resetLO), .sel({in_3__F_, in_4__F_}), .out(match_34F_));
- predicateM__ohSRxor ohSRxor_9(.flag_F_(flag_B__clr_), .flag_T_(flag_B__set_),
- .resetLO(resetLO), .sel({in_3__T_, in_4__T_}), .out(match_34T_));
- predicateM__ohSRxor ohSRxor_10(.flag_F_(flag_D__clr_),
- .flag_T_(flag_D__set_), .resetLO(resetLO), .sel({in_5__F_, in_6__F_}),
- .out(match_56F_));
- predicateM__ohSRxor ohSRxor_11(.flag_F_(flag_D__clr_),
- .flag_T_(flag_D__set_), .resetLO(resetLO), .sel({in_5__T_, in_6__T_}),
- .out(match_56T_));
- orangeTSMC090nm__wire90 wire90_1(.a(match_34T_));
- orangeTSMC090nm__wire90 wire90_3(.a(match_56T_));
- orangeTSMC090nm__wire90 wire90_4(.a(match_12F_));
- orangeTSMC090nm__wire90 wire90_5(.a(match_12T_));
- orangeTSMC090nm__wire90 wire90_6(.a(match_34F_));
- orangeTSMC090nm__wire90 wire90_7(.a(match_56F_));
-endmodule /* predicateM__ohSRxor6x12 */
-
-module predicateM__ohPredPred(fire_both_, flag_A__clr_, flag_A__set_,
- flag_B__clr_, flag_B__set_, flag_D__clr_, flag_D__set_, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, mc, any, do, resetLO, s);
- input fire_both_;
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input m1cate_1__F_;
- input m1cate_1__T_;
- input m1cate_2__F_;
- input m1cate_2__T_;
- input m1cate_3__F_;
- input m1cate_3__T_;
- input m1cate_4__F_;
- input m1cate_4__T_;
- input m1cate_5__F_;
- input m1cate_5__T_;
- input m1cate_6__F_;
- input m1cate_6__T_;
- input mc;
- output any;
- output do;
- output resetLO;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_18, net_49, net_62, net_67;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (resetLO, net_49);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_18, fire_both_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (net_49, net_18);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_4 (s[1], net_62);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_5 (s[2], net_67);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_5 (net_67, flag_A__clr_,
- flag_A__set_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nor2_sy{sch}*/
- nor (strong0, strong1) #(100) nor2_sy_6 (net_62, m1cate_1__F_,
- m1cate_1__T_);
- // end Verilog_template
- predicateM__ohSRxor6x12 ohSRxor6_1(.flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_B__clr_(flag_B__clr_),
- .flag_B__set_(flag_B__set_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .in_1__F_(m1cate_1__F_),
- .in_1__T_(m1cate_1__T_), .in_2__F_(m1cate_2__F_),
- .in_2__T_(m1cate_2__T_), .in_3__F_(m1cate_3__F_),
- .in_3__T_(m1cate_3__T_), .in_4__F_(m1cate_4__F_),
- .in_4__T_(m1cate_4__T_), .in_5__F_(m1cate_5__F_),
- .in_5__T_(m1cate_5__T_), .in_6__F_(m1cate_6__F_),
- .in_6__T_(m1cate_6__T_), .resetLO(net_18), .all(do), .any(any));
- driversM__predDri20wMC pp_1_(.in(fire_both_), .mc(mc), .pred(m1cate_1__T_));
- driversM__predDri20wMC pp_2_(.in(fire_both_), .mc(mc), .pred(m1cate_1__F_));
- driversM__predDri20wMC pp_3_(.in(fire_both_), .mc(mc), .pred(m1cate_2__T_));
- driversM__predDri20wMC pp_4_(.in(fire_both_), .mc(mc), .pred(m1cate_2__F_));
- driversM__predDri20wMC pp_5_(.in(fire_both_), .mc(mc), .pred(m1cate_3__T_));
- driversM__predDri20wMC pp_6_(.in(fire_both_), .mc(mc), .pred(m1cate_3__F_));
- driversM__predDri20wMC pp_7_(.in(fire_both_), .mc(mc), .pred(m1cate_4__T_));
- driversM__predDri20wMC pp_8_(.in(fire_both_), .mc(mc), .pred(m1cate_4__F_));
- driversM__predDri20wMC pp_9_(.in(fire_both_), .mc(mc), .pred(m1cate_5__T_));
- driversM__predDri20wMC pp_10_(.in(fire_both_), .mc(mc),
- .pred(m1cate_5__F_));
- driversM__predDri20wMC pp_11_(.in(fire_both_), .mc(mc),
- .pred(m1cate_6__T_));
- driversM__predDri20wMC pp_12_(.in(fire_both_), .mc(mc),
- .pred(m1cate_6__F_));
- orangeTSMC090nm__wire90 wire90_1(.a(net_18));
- orangeTSMC090nm__wire90 wire90_3(.a(net_49));
- orangeTSMC090nm__wire90 wire90_4(.a(net_62));
- orangeTSMC090nm__wire90 wire90_5(.a(net_67));
-endmodule /* predicateM__ohPredPred */
-
-module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_,
- flag_B__set_, flag_D__clr_, flag_D__set_, m1_Fl_, m1_rD_, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, ps_Fl_, sin, do_ins_, ps_do_, ps_skip_, sout, mc, p1p, p2p,
- rd);
- input flag_A__clr_;
- input flag_A__set_;
- input flag_B__clr_;
- input flag_B__set_;
- input flag_D__clr_;
- input flag_D__set_;
- input m1_Fl_;
- input m1_rD_;
- input m1cate_1__F_;
- input m1cate_1__T_;
- input m1cate_2__F_;
- input m1cate_2__T_;
- input m1cate_3__F_;
- input m1cate_3__T_;
- input m1cate_4__F_;
- input m1cate_4__T_;
- input m1cate_5__F_;
- input m1cate_5__T_;
- input m1cate_6__F_;
- input m1cate_6__T_;
- input ps_Fl_;
- input sin;
- output do_ins_;
- output ps_do_;
- output ps_skip_;
- output sout;
- inout mc;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire fire_both_, fire_do_, fire_skip_, net_11, net_19, net_41, net_46, net_63;
- wire net_82, net_92;
- wire [1:3] s;
-
- wiresL__bitAssignments bitAssig_0();
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (fire_do_, net_82);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (fire_skip_, net_63);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_2 (net_41, do_ins_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2_sy{sch}*/
- nand (strong0, strong1) #(100) nand2_sy_0 (net_63, net_92, net_11);
- // end Verilog_template
- redFive__nand2n_sy nand2n_s_0(.ina(net_63), .inb(net_82), .out(fire_both_));
- predicateM__nand3in20sr nand3in2_1(.inA(net_46), .inB(net_41), .inC(net_11),
- .resetLO(net_19), .out(net_82));
- redFive__nor2n_sy nor2n_sy_0(.ina(ps_skip_), .inb(ps_do_), .out(net_11));
- predicateM__ohPredDo ohPredDo_1(.fire_do_(fire_do_), .fire_skip_(fire_skip_),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
- .m1_Fl_(m1_Fl_), .m1_rD_(m1_rD_), .mc(mc), .ps_Fl_(ps_Fl_),
- .do_ins_(do_ins_), .ps_do_(ps_do_), .ps_skip_(ps_skip_), .s({s[3]}));
- predicateM__ohPredPred ohPredPr_1(.fire_both_(fire_both_),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_), .mc(mc),
- .any(net_92), .do(net_46), .resetLO(net_19), .s(s[1:2]));
- scanM__scanEx3h scanEx3h_0(.dIn(s[1:3]), .sin(sin), .mc(mc), .sout(sout),
- .p1p(p1p), .p2p(p2p), .rd(rd));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- orangeTSMC090nm__wire90 wire90_0(.a(net_11));
- orangeTSMC090nm__wire90 wire90_1(.a(net_41));
- orangeTSMC090nm__wire90 wire90_2(.a(net_46));
- orangeTSMC090nm__wire90 wire90_3(.a(net_19));
- orangeTSMC090nm__wire90 wire90_4(.a(net_82));
- orangeTSMC090nm__wire90 wire90_5(.a(net_63));
- orangeTSMC090nm__wire90 wire90_6(.a(net_92));
- orangeTSMC090nm__wire90 wire90_7(.a(fire_skip_));
- orangeTSMC090nm__wire90 wire90_9(.a(fire_both_));
- orangeTSMC090nm__wire90 wire90_11(.a(fire_do_));
-endmodule /* predicateM__ohPredAll */
-
-module centersJ__ctrAND2in100(inA, inB, out);
- input inA;
- input inB;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_158, net_161;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_9 (net_161, net_158);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (out, net_161);
- // end Verilog_template
- redFive__nor2n_sy nor2n_sy_0(.ina(inA), .inb(inB), .out(net_158));
- orangeTSMC090nm__wire90 wire90_6(.a(net_158));
- orangeTSMC090nm__wire90 wire90_7(.a(net_161));
-endmodule /* centersJ__ctrAND2in100 */
-
-module loopCountM__ilcLoad(do_ins_, sel_Ld_, sel_rD_, ilc_load_);
- input do_ins_;
- input sel_Ld_;
- input sel_rD_;
- output ilc_load_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_12;
-
- centersJ__ctrAND2in100 ctrAND2i_0(.inA(sel_rD_), .inB(net_12),
- .out(ilc_load_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_12, sel_Ld_, do_ins_);
- // end Verilog_template
- driversM__predDri40 predDri4_0(.in(ilc_load_), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_12));
-endmodule /* loopCountM__ilcLoad */
-
-module driversM__sucDri20or(inA, inB, succ);
- input inA;
- input inB;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_94;
-
- /* user-specified Verilog declarations */
- wor succ;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_94, succ);
- // end Verilog_template
- redFive__nms3 nms3b_0(.g(net_94), .g2(inB), .g3(inA), .d(succ));
- redFive__pms1 pms1_0(.g(inA), .d(succ));
- redFive__pms1 pms1_1(.g(inB), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_94));
-endmodule /* driversM__sucDri20or */
-
-module loopCountM__olcControlD(fire_Co_, fire_zz_, olc_zero_, olc_zoo_,
- flag_D__clr_, flag_D__set_, s);
- input fire_Co_;
- input fire_zz_;
- input olc_zero_;
- input olc_zoo_;
- output flag_D__clr_;
- output flag_D__set_;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_180, net_184, net_279, net_281, net_284, net_286, net_544, net_549;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_6 (net_180, olc_zoo_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_7 (net_184, olc_zero_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_18 (net_549, flag_D__set_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_19 (net_544, flag_D__clr_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[2], net_544);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_1 (s[1], net_549);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_286, net_180, fire_Co_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_1 (net_284, net_184, fire_zz_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_2 (net_279, olc_zoo_, fire_Co_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_3 (net_281, olc_zero_, fire_zz_);
- // end Verilog_template
- driversM__sucDri20or sucDri20_3(.inA(net_286), .inB(net_284),
- .succ(flag_D__clr_));
- driversM__sucDri20or sucDri20_4(.inA(net_279), .inB(net_281),
- .succ(flag_D__set_));
- orangeTSMC090nm__wire90 wire90_9(.a(net_281));
- orangeTSMC090nm__wire90 wire90_10(.a(net_279));
- orangeTSMC090nm__wire90 wire90_11(.a(net_286));
- orangeTSMC090nm__wire90 wire90_12(.a(net_284));
- orangeTSMC090nm__wire90 wire90_13(.a(net_180));
- orangeTSMC090nm__wire90 wire90_14(.a(net_184));
- orangeTSMC090nm__wire90 wire90_21(.a(net_549));
- orangeTSMC090nm__wire90 wire90_22(.a(net_544));
-endmodule /* loopCountM__olcControlD */
-
-module loopCountM__olcCount(do_ins_, olc_zero_, sel_Co_, fire_Co_, olc_dec_);
- input do_ins_;
- input olc_zero_;
- input sel_Co_;
- output fire_Co_;
- output olc_dec_;
-
- supply1 vdd;
- supply0 gnd;
- wire net_12;
-
- centersJ__ctrAND1in30 ctrAND1i_0(.in(net_12), .out(fire_Co_));
- centersJ__ctrAND2in100 ctrAND2i_0(.inA(olc_zero_), .inB(net_12),
- .out(olc_dec_));
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_0 (net_12, sel_Co_, do_ins_);
- // end Verilog_template
- driversM__predDri40 predDri4_0(.in(fire_Co_), .pred(do_ins_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_12));
-endmodule /* loopCountM__olcCount */
-
-module driversM__predDri10wMC(in, mc, pred);
- input in;
- input mc;
- output pred;
-
- supply1 vdd;
- supply0 gnd;
- wire net_145;
-
- orangeTSMC090nm__NMOSx NMOSx_0(.g(in), .d(pred), .s(gnd));
- orangeTSMC090nm__NMOSx NMOSx_1(.g(mc), .d(pred), .s(gnd));
- /* begin Verilog_template for redFive:invLT{sch}*/
- not (strong0, strong1) #(100) invLT_0 (net_145, pred);
- // end Verilog_template
- redFive__pms3 pms3_0(.g(in), .g2(net_145), .g3(mc), .d(pred));
- orangeTSMC090nm__wire90 wire90_0(.a(net_145));
-endmodule /* driversM__predDri10wMC */
-
-module driversM__sucDri10(in, succ);
- input in;
- output succ;
-
- supply1 vdd;
- supply0 gnd;
- wire net_109, net_94;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (net_94, succ);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_2 (net_109, in);
- // end Verilog_template
- redFive__nms2 nms2_0(.g(net_94), .g2(net_109), .d(succ));
- redFive__pms1 pms1_0(.g(net_109), .d(succ));
- orangeTSMC090nm__wire90 wire90_0(.a(net_94));
- orangeTSMC090nm__wire90 wire90_1(.a(net_109));
-endmodule /* driversM__sucDri10 */
-
-module loopCountM__olcLoad(do_ins_, doneLO_M_, mc, sel_Ld_, sel_rD_, fire_zz_,
- olc_load_);
- input do_ins_;
- input doneLO_M_;
- input mc;
- input sel_Ld_;
- input sel_rD_;
- output fire_zz_;
- output olc_load_;
-
- supply1 vdd;
- supply0 gnd;
- wire inv_34_out, net_1035, net_905, net_908, net_929, net_937, net_956;
- wire net_976;
- wire [2:2] do;
-
- centersJ__ctrAND3in100A ctrAND3i_2(.inA(do[2]), .inB(net_976), .inC(net_956),
- .out(olc_load_));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_28 (net_908, net_905);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_30 (net_976, sel_rD_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_32 (net_1035, net_937);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_34 (inv_34_out, net_905);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_7 (net_905, net_929);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_8 (net_937, net_908);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_5 (net_956, sel_Ld_, do_ins_);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2{sch}*/
- nand (strong0, strong1) #(100) nand2_7 (net_929, net_1035, do[2]);
- // end Verilog_template
- redFive__nand2n_sy nand2n_s_1(.ina(doneLO_M_), .inb(net_908),
- .out(fire_zz_));
- driversM__predDri10wMC predDri1_0(.in(net_956), .mc(mc), .pred(do[2]));
- driversM__predDri40 predDri4_0(.in(net_937), .pred(do_ins_));
- driversM__sucDri10 sucDri10_1(.in(olc_load_), .succ(do[2]));
- orangeTSMC090nm__wire90 wire90_17(.a(net_929));
- orangeTSMC090nm__wire90 wire90_25(.a(net_956));
- orangeTSMC090nm__wire90 wire90_39(.a(net_937));
- orangeTSMC090nm__wire90 wire90_42(.a(net_905));
- orangeTSMC090nm__wire90 wire90_48(.a(net_976));
- orangeTSMC090nm__wire90 wire90_50(.a(do[2]));
- orangeTSMC090nm__wire90 wire90_51(.a(net_1035));
- orangeTSMC090nm__wire90 wire90_52(.a(net_908));
-endmodule /* loopCountM__olcLoad */
-
-module loopCountM__loadORcount(do_ins_, doneLO_M_, mc, olc_zero_, olc_zoo_,
- sel_Co_, sel_Ld_, sel_rD_, flag_D__clr_, flag_D__set_, ilc_load_,
- olc_dec_, olc_load_, s);
- input do_ins_;
- input doneLO_M_;
- input mc;
- input olc_zero_;
- input olc_zoo_;
- input sel_Co_;
- input sel_Ld_;
- input sel_rD_;
- output flag_D__clr_;
- output flag_D__set_;
- output ilc_load_;
- output olc_dec_;
- output olc_load_;
- output [1:2] s;
-
- supply1 vdd;
- supply0 gnd;
- wire net_880, net_883;
-
- loopCountM__ilcLoad ilcLoad_0(.do_ins_(do_ins_), .sel_Ld_(sel_Ld_),
- .sel_rD_(sel_rD_), .ilc_load_(ilc_load_));
- loopCountM__olcControlD olcContr_1(.fire_Co_(net_883), .fire_zz_(net_880),
- .olc_zero_(olc_zero_), .olc_zoo_(olc_zoo_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .s(s[1:2]));
- loopCountM__olcCount olcCount_0(.do_ins_(do_ins_), .olc_zero_(olc_zero_),
- .sel_Co_(sel_Co_), .fire_Co_(net_883), .olc_dec_(olc_dec_));
- loopCountM__olcLoad olcLoad_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_),
- .mc(mc), .sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .fire_zz_(net_880),
- .olc_load_(olc_load_));
- orangeTSMC090nm__wire90 wire90_0(.a(net_880));
- orangeTSMC090nm__wire90 wire90_1(.a(net_883));
-endmodule /* loopCountM__loadORcount */
-
-module loopCountM__olcEven(count_T_, do, do_1, do_2, \inLO[2] , \inLO[4] ,
- \inLO[6] , load_T_, \bitt[2] , \bitt[4] , \bitt[6] );
- input count_T_;
- input [2:2] do;
- input [4:4] do_1;
- input [6:6] do_2;
- input \inLO[2] , \inLO[4] , \inLO[6] ;
- input load_T_;
- output \bitt[2] , \bitt[4] , \bitt[6] ;
-
- supply1 vdd;
- supply0 gnd;
- wire count_F_, load_F_;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_2 (count_F_, count_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_3 (load_F_, load_T_);
- // end Verilog_template
- loopCountM__ringB ringB_3(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_2[6:6]), .inLO({ \inLO[6] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[6] }));
- loopCountM__ringB ringB_4(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_1[4:4]), .inLO({ \inLO[4] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[4] }));
- loopCountM__ringB ringB_5(.count_F_(count_F_), .count_T_(count_T_),
- .do(do[2:2]), .inLO({ \inLO[2] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[2] }));
- orangeTSMC090nm__wire90 wire90_3(.a(count_F_));
- orangeTSMC090nm__wire90 wire90_4(.a(load_F_));
-endmodule /* loopCountM__olcEven */
-
-module loopCountM__olcOdd(count_T_, do, do_1, \inLO[1] , \inLO[3] , \inLO[5] ,
- load_T_, \bitt[1] , \bitt[3] , \bitt[5] );
- input count_T_;
- input [3:3] do;
- input [5:5] do_1;
- input \inLO[1] , \inLO[3] , \inLO[5] ;
- input load_T_;
- output \bitt[1] , \bitt[3] , \bitt[5] ;
-
- supply1 vdd;
- supply0 gnd;
- wire count_F_, load_F_;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_2 (load_F_, load_T_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(0) inv_3 (count_F_, count_T_);
- // end Verilog_template
- loopCountM__ringB ringB_3(.count_F_(count_F_), .count_T_(count_T_),
- .do(do_1[5:5]), .inLO({ \inLO[5] }), .load_F_(load_F_),
- .load_T_(load_T_), .bit({ \bitt[5] }));
- loopCountM__ringB ringB_4(.count_F_(count_F_), .count_T_(count_T_),
- .do(do[3:3]), .inLO({ \inLO[3] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[3] }));
- loopCountM__ringB ringB_5(.count_F_(count_F_), .count_T_(count_T_),
- .do({vdd}), .inLO({ \inLO[1] }), .load_F_(load_F_), .load_T_(load_T_),
- .bit({ \bitt[1] }));
- orangeTSMC090nm__wire90 wire90_2(.a(load_F_));
- orangeTSMC090nm__wire90 wire90_3(.a(count_F_));
-endmodule /* loopCountM__olcOdd */
-
-module loopCountM__olc(inLO, olc_dec_, olc_load_, bitt, olc_zero_, olc_zoo_);
- input [1:6] inLO;
- input olc_dec_;
- input olc_load_;
- output [1:6] bitt;
- output olc_zero_;
- output olc_zoo_;
-
- supply1 vdd;
- supply0 gnd;
- wire [6:2] do;
-
- loopCountM__calculate countLog_0(.bit({bitt[1]}), .bit_1({bitt[2]}),
- .bit_2({bitt[3]}), .bit_3({bitt[4]}), .bit_4({bitt[5]}),
- .bit_5({bitt[6]}), .do(do[2:2]), .do_1(do[3:3]), .do_2(do[4:4]),
- .do_3(do[5:5]), .do_4(do[6:6]), .zero(olc_zero_), .zoo(olc_zoo_));
- loopCountM__olcEven olcEven_1(.count_T_(olc_dec_), .do(do[2:2]),
- .do_1(do[4:4]), .do_2(do[6:6]), .\inLO[2] (inLO[2]), .\inLO[4] (inLO[4]),
- .\inLO[6] (inLO[6]), .load_T_(olc_load_), .\bitt[2] (bitt[2]), .\bitt[4]
- (bitt[4]), .\bitt[6] (bitt[6]));
- loopCountM__olcOdd olcOdd_2(.count_T_(olc_dec_), .do(do[3:3]),
- .do_1(do[5:5]), .\inLO[1] (inLO[1]), .\inLO[3] (inLO[3]), .\inLO[5]
- (inLO[5]), .load_T_(olc_load_), .\bitt[1] (bitt[1]), .\bitt[3] (bitt[3]),
- .\bitt[5] (bitt[5]));
- orangeTSMC090nm__wire90 wire90_1(.a(do[2]));
- orangeTSMC090nm__wire90 wire90_2(.a(do[3]));
- orangeTSMC090nm__wire90 wire90_3(.a(do[4]));
- orangeTSMC090nm__wire90 wire90_4(.a(do[5]));
- orangeTSMC090nm__wire90 wire90_5(.a(do[6]));
-endmodule /* loopCountM__olc */
-
-module loopCountM__olcWcont(do_ins_, doneLO_M_, inLO, sel_Co_, sel_Ld_,
- sel_rD_, sin, flag_D__clr_, flag_D__set_, ilc_load_, sout, mc, p1p, p2p,
- rd);
- input do_ins_;
- input doneLO_M_;
- input [1:6] inLO;
- input sel_Co_;
- input sel_Ld_;
- input sel_rD_;
- input sin;
- output flag_D__clr_;
- output flag_D__set_;
- output ilc_load_;
- output sout;
- inout mc;
- inout p1p;
- inout p2p;
- inout rd;
-
- supply1 vdd;
- supply0 gnd;
- wire net_46, net_81, olc_dec_, olc_load_, olc_zero_, olc_zoo_;
- wire [1:6] bitt;
- wire [1:2] s;
-
- loopCountM__loadORcount loadORco_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_),
- .mc(mc), .olc_zero_(olc_zero_), .olc_zoo_(olc_zoo_), .sel_Co_(sel_Co_),
- .sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .ilc_load_(ilc_load_), .olc_dec_(olc_dec_),
- .olc_load_(olc_load_), .s(s[1:2]));
- loopCountM__olc olc_0(.inLO(inLO[1:6]), .olc_dec_(olc_dec_),
- .olc_load_(olc_load_), .bitt(bitt[1:6]), .olc_zero_(olc_zero_),
- .olc_zoo_(olc_zoo_));
- scanM__scanEx2h scanEx2h_0(.dIn(s[1:2]), .sin(net_81), .mc(mc), .sout(sout),
- .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx3h scanEx3h_1(.dIn({bitt[1], bitt[3], bitt[5]}), .sin(sin),
- .mc(mc), .sout(net_46), .p1p(p1p), .p2p(p2p), .rd(rd));
- scanM__scanEx3h scanEx3h_2(.dIn({bitt[2], bitt[4], bitt[6]}), .sin(net_46),
- .mc(mc), .sout(net_81), .p1p(p1p), .p2p(p2p), .rd(rd));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- orangeTSMC090nm__wire90 wire90_1(.a(olc_zero_));
- orangeTSMC090nm__wire90 wire90_2(.a(olc_zoo_));
- orangeTSMC090nm__wire90 wire90_3(.a(olc_load_));
- orangeTSMC090nm__wire90 wire90_4(.a(olc_dec_));
- orangeTSMC090nm__wire90 wire90_5(.a(bitt[4]));
- orangeTSMC090nm__wire90 wire90_6(.a(bitt[5]));
- orangeTSMC090nm__wire90 wire90_7(.a(bitt[6]));
- orangeTSMC090nm__wire90 wire90_8(.a(bitt[1]));
- orangeTSMC090nm__wire90 wire90_9(.a(bitt[2]));
- orangeTSMC090nm__wire90 wire90_10(.a(bitt[3]));
-endmodule /* loopCountM__olcWcont */
-
-module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] ,
- \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8] , \m1[1] , \m1[2] ,
- \m1[3] , \m1[4] , \m1[5] , \m1[6] , \m1[7] , \m1[8] , \m1[9] , \m1[10] ,
- \m1[11] , \m1[12] , \m1[21] , \m1[22] , m1cate_1__F_, m1cate_1__T_,
- m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_, m1cate_4__F_,
- m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_, m1cate_6__T_,
- pred_D_, pred_T_, ps, sir, succ_sf_, do_ins_, fire_M_, flag_A__clr_,
- flag_A__set_, flag_D__clr_, flag_D__set_, ps_do_, ps_skip_, sor);
- input epi_torp_;
- input flag_C__T_;
- input [1:6] in;
- input \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] ,
- \inLO[8] ;
- input \m1[1] , \m1[2] , \m1[3] , \m1[4] , \m1[5] , \m1[6] , \m1[7] , \m1[8] ,
- \m1[9] , \m1[10] , \m1[11] , \m1[12] , \m1[21] , \m1[22] ;
- input m1cate_1__F_;
- input m1cate_1__T_;
- input m1cate_2__F_;
- input m1cate_2__T_;
- input m1cate_3__F_;
- input m1cate_3__T_;
- input m1cate_4__F_;
- input m1cate_4__T_;
- input m1cate_5__F_;
- input m1cate_5__T_;
- input m1cate_6__F_;
- input m1cate_6__T_;
- input pred_D_;
- input pred_T_;
- input [18:26] ps;
- input [1:9] sir;
- input succ_sf_;
- output do_ins_;
- output fire_M_;
- output flag_A__clr_;
- output flag_A__set_;
- output flag_D__clr_;
- output flag_D__set_;
- output ps_do_;
- output ps_skip_;
- output [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire doneLO_M_, flag_B__clr_, flag_B__set_, ilc_load_, net_244, net_249;
- wire net_279;
-
- wiresL__bitAssignments bitAssig_0();
- oneHotM__flags flags_0(.flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_B__clr_(flag_B__clr_),
- .flag_B__set_(flag_B__set_), .flag_C__T_(flag_C__T_), .m1({ \m1[1] ,
- \m1[2] , \m1[3] , \m1[4] , \m1[5] , \m1[6] , \m1[7] , \m1[8] ,
- \m1[9] , \m1[10] , \m1[11] , \m1[12] }), .sin(sir[1]), .sout(net_279),
- .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
- moveM__ilcMoveOut ilcMoveO_0(.do_ins_(do_ins_), .epi_torp_(epi_torp_),
- .ilc_load_(ilc_load_), .\inLO[1] ( \inLO[1] ), .\inLO[2] ( \inLO[2] ),
- .\inLO[3] ( \inLO[3] ), .\inLO[4] ( \inLO[4] ), .\inLO[5] ( \inLO[5] ),
- .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8] ), .pred_D_(pred_D_),
- .pred_T_(pred_T_), .sel_Di_(ps[18]), .sel_Mv_(ps[25]), .sel_Ti_(ps[19]),
- .sel_Tp_(ps[26]), .sin(net_249), .succ_sf_(succ_sf_),
- .doneLO_M_(doneLO_M_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_),
- .sout(sor[1]), .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
- loopCountM__muxForD muxForD_0(.in(in[1:6]), .sel(ps[20]), .outLO({ \inLO[1] ,
- \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8]
- }));
- predicateM__ohPredAll ohPredAl_0(.flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_B__clr_(flag_B__clr_),
- .flag_B__set_(flag_B__set_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .m1_Fl_( \m1[22] ), .m1_rD_( \m1[21] ),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_),
- .ps_Fl_(ps[22]), .sin(net_244), .do_ins_(do_ins_), .ps_do_(ps_do_),
- .ps_skip_(ps_skip_), .sout(net_249), .mc(sir[9]), .p1p(sir[3]),
- .p2p(sir[2]), .rd(sir[5]));
- loopCountM__olcWcont olcWcont_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_),
- .inLO({ \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] ,
- \inLO[6] }), .sel_Co_(ps[24]), .sel_Ld_(ps[23]), .sel_rD_(ps[21]),
- .sin(net_279), .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
- .ilc_load_(ilc_load_), .sout(net_244), .mc(sir[9]), .p1p(sir[3]),
- .p2p(sir[2]), .rd(sir[5]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- wiresL__tranCap tc_12_();
- wiresL__tranCap tc_13_();
- wiresL__tranCap tc_14_();
- wiresL__tranCap tc_15_();
- wiresL__tranCap tc_16_();
- orangeTSMC090nm__wire90 wire90_5(.a(flag_A__set_));
- orangeTSMC090nm__wire90 wire90_6(.a(flag_A__clr_));
- orangeTSMC090nm__wire90 wire90_7(.a(flag_B__set_));
- orangeTSMC090nm__wire90 wire90_8(.a(flag_B__clr_));
- orangeTSMC090nm__wire90 wire90_9(.a(flag_D__set_));
- orangeTSMC090nm__wire90 wire90_10(.a(flag_D__clr_));
- orangeTSMC090nm__wire90 wire90_24(.a(ilc_load_));
- orangeTSMC090nm__wire90 wire90_25(.a(doneLO_M_));
-endmodule /* stagesM__outDockCenter */
-
-module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_,
- m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_,
- m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_,
- m1cate_6__T_, pred_D_, pred_T_, sir, succ_sf_, do_ins_, fire_M_,
- flag_A__clr_, flag_A__set_, flag_D__clr_, flag_D__set_, \ps[1] , \ps[2] ,
- \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8] , \ps[9] , \ps[10] ,
- \ps[11] , \ps[12] , \ps[13] , \ps[14] , \ps[15] , \ps[16] , \ps[17] ,
- \ps[18] , \ps[19] , \ps[20] , \ps[27] , ps_do_, ps_skip_, sor);
- input epi_torp_;
- input flag_C__T_;
- input [1:6] in;
- input [1:27] m1;
- input m1cate_1__F_;
- input m1cate_1__T_;
- input m1cate_2__F_;
- input m1cate_2__T_;
- input m1cate_3__F_;
- input m1cate_3__T_;
- input m1cate_4__F_;
- input m1cate_4__T_;
- input m1cate_5__F_;
- input m1cate_5__T_;
- input m1cate_6__F_;
- input m1cate_6__T_;
- input pred_D_;
- input pred_T_;
- input [1:9] sir;
- input succ_sf_;
- output do_ins_;
- output fire_M_;
- output flag_A__clr_;
- output flag_A__set_;
- output flag_D__clr_;
- output flag_D__set_;
- output \ps[1] , \ps[2] , \ps[3] , \ps[4] , \ps[5] , \ps[6] , \ps[7] , \ps[8]
- , \ps[9] , \ps[10] , \ps[11] , \ps[12] , \ps[13] , \ps[14] , \ps[15] ,
- \ps[16] , \ps[17] , \ps[18] , \ps[19] , \ps[20] , \ps[27] ;
- output ps_do_;
- output ps_skip_;
- output [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire \inLO[1] ;
- wire \inLO[2] ;
- wire \inLO[3] ;
- wire \inLO[4] ;
- wire \inLO[5] ;
- wire \inLO[6] ;
- wire \inLO[8] ;
- wire [21:26] ps_1;
-
- registersM__dockPSreg dockPSre_0(.do_ins_(do_ins_), .m1(m1[1:27]), .outLO({
- \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] ,
- \inLO[8] }), .ps({ \ps[1] , \ps[2] , \ps[3] , \ps[4] , \ps[5] ,
- \ps[6] , \ps[7] , \ps[8] , \ps[9] , \ps[10] , \ps[11] , \ps[12] ,
- \ps[13] , \ps[14] , \ps[15] , \ps[16] , \ps[17] , \ps[18] , \ps[19]
- , \ps[20] , ps_1[21], ps_1[22], ps_1[23], ps_1[24], ps_1[25], ps_1[26],
- \ps[27] }));
- stagesM__outDockCenter outDockC_0(.epi_torp_(epi_torp_),
- .flag_C__T_(flag_C__T_), .in(in[1:6]), .\inLO[1] ( \inLO[1] ), .\inLO[2]
- ( \inLO[2] ), .\inLO[3] ( \inLO[3] ), .\inLO[4] ( \inLO[4] ), .\inLO[5] (
- \inLO[5] ), .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8] ), .\m1[1]
- (m1[1]), .\m1[2] (m1[2]), .\m1[3] (m1[3]), .\m1[4] (m1[4]), .\m1[5]
- (m1[5]), .\m1[6] (m1[6]), .\m1[7] (m1[7]), .\m1[8] (m1[8]), .\m1[9]
- (m1[9]), .\m1[10] (m1[10]), .\m1[11] (m1[11]), .\m1[12] (m1[12]),
- .\m1[21] (m1[21]), .\m1[22] (m1[22]), .m1cate_1__F_(m1cate_1__F_),
- .m1cate_1__T_(m1cate_1__T_), .m1cate_2__F_(m1cate_2__F_),
- .m1cate_2__T_(m1cate_2__T_), .m1cate_3__F_(m1cate_3__F_),
- .m1cate_3__T_(m1cate_3__T_), .m1cate_4__F_(m1cate_4__F_),
- .m1cate_4__T_(m1cate_4__T_), .m1cate_5__F_(m1cate_5__F_),
- .m1cate_5__T_(m1cate_5__T_), .m1cate_6__F_(m1cate_6__F_),
- .m1cate_6__T_(m1cate_6__T_), .pred_D_(pred_D_), .pred_T_(pred_T_), .ps({
- \ps[18] , \ps[19] , \ps[20] , ps_1[21], ps_1[22], ps_1[23], ps_1[24],
- ps_1[25], ps_1[26]}), .sir(sir[1:9]), .succ_sf_(succ_sf_),
- .do_ins_(do_ins_), .fire_M_(fire_M_), .flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .ps_do_(ps_do_), .ps_skip_(ps_skip_),
- .sor(sor[1:1]));
- orangeTSMC090nm__wire90 wire90_1(.a( \inLO[1] ));
- orangeTSMC090nm__wire90 wire90_2(.a( \inLO[2] ));
- orangeTSMC090nm__wire90 wire90_3(.a( \inLO[3] ));
- orangeTSMC090nm__wire90 wire90_4(.a( \inLO[4] ));
- orangeTSMC090nm__wire90 wire90_5(.a( \inLO[5] ));
- orangeTSMC090nm__wire90 wire90_6(.a( \inLO[6] ));
- orangeTSMC090nm__wire90 wire90_7(.a( \inLO[8] ));
-endmodule /* stagesM__outDockPredStage */
-
-module stageGroupsM__outM1PredLit(dp, dp_B_, epi_torp_, pred_D_, pred_R_,
- pred_T_, ring, signalBitFromInboundSwitchFabric, sir, dsA, dsA_TT_, dsD,
- dsD_1, flag_A__clr_, flag_A__set_, flag_D__clr_, flag_D__set_, m1,
- ps_do_, ps_skip_, sor, succ_D_, succ_T_, succ_m1_);
- input [1:37] dp;
- input dp_B_;
- input epi_torp_;
- input pred_D_;
- input pred_R_;
- input pred_T_;
- input [1:36] ring;
- input signalBitFromInboundSwitchFabric;
- input [1:9] sir;
- output [14:1] dsA;
- output dsA_TT_;
- output [1:6] dsD;
- output [37:7] dsD_1;
- output flag_A__clr_;
- output flag_A__set_;
- output flag_D__clr_;
- output flag_D__set_;
- output [1:36] m1;
- output ps_do_;
- output ps_skip_;
- output [1:1] sor;
- output succ_D_;
- output succ_T_;
- output succ_m1_;
-
- supply1 vdd;
- supply0 gnd;
- wire do_ins_, fire_M_, flag_C_, m1cate_1__F_, m1cate_1__T_, m1cate_2__F_;
- wire m1cate_2__T_, m1cate_3__F_, m1cate_3__T_, m1cate_4__F_, m1cate_4__T_;
- wire m1cate_5__F_, m1cate_5__T_, m1cate_6__F_, m1cate_6__T_, take_m1_;
- wire [8:8] net_47;
- wire \ps[1] ;
- wire \ps[2] ;
- wire \ps[3] ;
- wire \ps[4] ;
- wire \ps[5] ;
- wire \ps[6] ;
- wire \ps[7] ;
- wire \ps[8] ;
- wire \ps[9] ;
- wire \ps[10] ;
- wire \ps[11] ;
- wire \ps[12] ;
- wire \ps[13] ;
- wire \ps[14] ;
- wire \ps[15] ;
- wire \ps[16] ;
- wire \ps[17] ;
- wire \ps[18] ;
- wire \ps[19] ;
- wire \ps[20] ;
- wire \ps[27] ;
-
- stagesM__litDandP litDandP_0(.do_ins_(do_ins_), .dp(dp[1:37]), .dp_B_(dp_B_),
- .fire_M_(fire_M_), .\ps[1] ( \ps[1] ), .\ps[2] ( \ps[2] ), .\ps[3] (
- \ps[3] ), .\ps[4] ( \ps[4] ), .\ps[5] ( \ps[5] ), .\ps[6] ( \ps[6] ),
- .\ps[7] ( \ps[7] ), .\ps[8] ( \ps[8] ), .\ps[9] ( \ps[9] ), .\ps[10] (
- \ps[10] ), .\ps[11] ( \ps[11] ), .\ps[12] ( \ps[12] ), .\ps[13] ( \ps[13]
- ), .\ps[14] ( \ps[14] ), .\ps[15] ( \ps[15] ), .\ps[16] ( \ps[16] ),
- .\ps[17] ( \ps[17] ), .\ps[18] ( \ps[18] ), .\ps[19] ( \ps[19] ),
- .\ps[20] ( \ps[20] ), .\ps[27] ( \ps[27] ),
- .signalBitFromInboundSwitchFabric(signalBitFromInboundSwitchFabric),
- .dsA(dsA[14:1]), .dsA_TT_(dsA_TT_), .dsD({dsD[1], dsD[2], dsD[3], dsD[4],
- dsD[5], dsD[6], dsD_1[7], dsD_1[8], dsD_1[9], dsD_1[10], dsD_1[11],
- dsD_1[12], dsD_1[13], dsD_1[14], dsD_1[15], dsD_1[16], dsD_1[17],
- dsD_1[18], dsD_1[19], dsD_1[20], dsD_1[21], dsD_1[22], dsD_1[23],
- dsD_1[24], dsD_1[25], dsD_1[26], dsD_1[27], dsD_1[28], dsD_1[29],
- dsD_1[30], dsD_1[31], dsD_1[32], dsD_1[33], dsD_1[34], dsD_1[35],
- dsD_1[36], dsD_1[37]}), .flag_C_(flag_C_), .succ_D_(succ_D_),
- .succ_T_(succ_T_));
- stagesM__mOneDockStage mOneDock_0(.pred_R_(pred_R_), .ring(ring[1:36]),
- .sir(sir[1:9]), .m1(m1[1:36]), .m1cate_1__F_(m1cate_1__F_),
- .m1cate_1__T_(m1cate_1__T_), .m1cate_2__F_(m1cate_2__F_),
- .m1cate_2__T_(m1cate_2__T_), .m1cate_3__F_(m1cate_3__F_),
- .m1cate_3__T_(m1cate_3__T_), .m1cate_4__F_(m1cate_4__F_),
- .m1cate_4__T_(m1cate_4__T_), .m1cate_5__F_(m1cate_5__F_),
- .m1cate_5__T_(m1cate_5__T_), .m1cate_6__F_(m1cate_6__F_),
- .m1cate_6__T_(m1cate_6__T_), .sor({net_47[8]}), .succ_m1_(succ_m1_),
- .take_m1_(take_m1_));
- stagesM__outDockPredStage outDockP_0(.epi_torp_(epi_torp_),
- .flag_C__T_(flag_C_), .in(dsD[1:6]), .m1(m1[1:27]),
- .m1cate_1__F_(m1cate_1__F_), .m1cate_1__T_(m1cate_1__T_),
- .m1cate_2__F_(m1cate_2__F_), .m1cate_2__T_(m1cate_2__T_),
- .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_),
- .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_),
- .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_),
- .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_),
- .pred_D_(pred_D_), .pred_T_(pred_T_), .sir({net_47[8], sir[2], sir[3],
- sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}), .succ_sf_(succ_D_),
- .do_ins_(do_ins_), .fire_M_(fire_M_), .flag_A__clr_(flag_A__clr_),
- .flag_A__set_(flag_A__set_), .flag_D__clr_(flag_D__clr_),
- .flag_D__set_(flag_D__set_), .\ps[1] ( \ps[1] ), .\ps[2] ( \ps[2] ),
- .\ps[3] ( \ps[3] ), .\ps[4] ( \ps[4] ), .\ps[5] ( \ps[5] ), .\ps[6] (
- \ps[6] ), .\ps[7] ( \ps[7] ), .\ps[8] ( \ps[8] ), .\ps[9] ( \ps[9] ),
- .\ps[10] ( \ps[10] ), .\ps[11] ( \ps[11] ), .\ps[12] ( \ps[12] ),
- .\ps[13] ( \ps[13] ), .\ps[14] ( \ps[14] ), .\ps[15] ( \ps[15] ),
- .\ps[16] ( \ps[16] ), .\ps[17] ( \ps[17] ), .\ps[18] ( \ps[18] ),
- .\ps[19] ( \ps[19] ), .\ps[20] ( \ps[20] ), .\ps[27] ( \ps[27] ),
- .ps_do_(ps_do_), .ps_skip_(ps_skip_), .sor(sor[1:1]));
- orangeTSMC090nm__wire90 wire90_0(.a(flag_C_));
- orangeTSMC090nm__wire90 wire90_1(.a(fire_M_));
- orangeTSMC090nm__wire90 wire90_2(.a(do_ins_));
- orangeTSMC090nm__wire90 wire90_3(.a(m1cate_1__T_));
- orangeTSMC090nm__wire90 wire90_4(.a(m1cate_1__F_));
- orangeTSMC090nm__wire90 wire90_5(.a(m1cate_2__T_));
- orangeTSMC090nm__wire90 wire90_6(.a(m1cate_2__F_));
- orangeTSMC090nm__wire90 wire90_7(.a(m1cate_3__T_));
- orangeTSMC090nm__wire90 wire90_8(.a(m1cate_3__F_));
- orangeTSMC090nm__wire90 wire90_9(.a(m1cate_4__T_));
- orangeTSMC090nm__wire90 wire90_10(.a(m1cate_4__F_));
- orangeTSMC090nm__wire90 wire90_11(.a(m1cate_5__T_));
- orangeTSMC090nm__wire90 wire90_12(.a(m1cate_5__F_));
- orangeTSMC090nm__wire90 wire90_13(.a(m1cate_6__T_));
- orangeTSMC090nm__wire90 wire90_14(.a(m1cate_6__F_));
-endmodule /* stageGroupsM__outM1PredLit */
-
-module dockM__outputDock(do_epi_, dp, dp_B_, in, in_T_, pred_D_, pred_T_,
- signalBitFromInboundSwitchFabric, sir, dsA, dsA_TT_, dsD, fout, sor,
- succ_D_, succ_T_);
- input do_epi_;
- input [1:37] dp;
- input dp_B_;
- input [1:36] in;
- input in_T_;
- input pred_D_;
- input pred_T_;
- input signalBitFromInboundSwitchFabric;
- input [1:9] sir;
- output [14:1] dsA;
- output dsA_TT_;
- output [37:1] dsD;
- output fout;
- output [1:1] sor;
- output succ_D_;
- output succ_T_;
-
- supply1 vdd;
- supply0 gnd;
- wire flag_A__clr_, flag_A__set_, flag_D__clr_, flag_D__set_, net_15, net_84;
- wire net_88, ps_do_, ps_skip_, torp;
- wire [35:0] net_26;
- wire [35:0] net_57;
- wire [35:0] net_68;
- wire [8:8] net_75;
- wire [8:8] net_76;
-
- stageGroupsM__dockWagNine dockWagN_0(.in({net_26[35], net_26[34], net_26[33],
- net_26[32], net_26[31], net_26[30], net_26[29], net_26[28], net_26[27],
- net_26[26], net_26[25], net_26[24], net_26[23], net_26[22], net_26[21],
- net_26[20], net_26[19], net_26[18], net_26[17], net_26[16], net_26[15],
- net_26[14], net_26[13], net_26[12], net_26[11], net_26[10], net_26[9],
- net_26[8], net_26[7], net_26[6], net_26[5], net_26[4], net_26[3],
- net_26[2], net_26[1], net_26[0]}), .pred(net_15), .sir({net_75[8],
- sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8], sir[9]}),
- .out({net_57[35], net_57[34], net_57[33], net_57[32], net_57[31],
- net_57[30], net_57[29], net_57[28], net_57[27], net_57[26], net_57[25],
- net_57[24], net_57[23], net_57[22], net_57[21], net_57[20], net_57[19],
- net_57[18], net_57[17], net_57[16], net_57[15], net_57[14], net_57[13],
- net_57[12], net_57[11], net_57[10], net_57[9], net_57[8], net_57[7],
- net_57[6], net_57[5], net_57[4], net_57[3], net_57[2], net_57[1],
- net_57[0]}), .sor({net_76[8]}), .succ(net_84), .take({fout}));
- stageGroupsM__epiRQod epiRQod_1(.do_epi_(do_epi_), .do_od_(net_88),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .in(in[1:36]),
- .in_T_(in_T_), .m1({net_68[35], net_68[34], net_68[33], net_68[32],
- net_68[31], net_68[30], net_68[29], net_68[28], net_68[27], net_68[26],
- net_68[25], net_68[24], net_68[23], net_68[22], net_68[21], net_68[20],
- net_68[19], net_68[18], net_68[17], net_68[16], net_68[15], net_68[14],
- net_68[13], net_68[12], net_68[11], net_68[10], net_68[9], net_68[8],
- net_68[7], net_68[6], net_68[5], net_68[4], net_68[3], net_68[2],
- net_68[1], net_68[0]}), .ps_do_(ps_do_), .ps_skip_(ps_skip_),
- .sir(sir[1:9]), .epi_TORP_(torp), .rq({net_26[35], net_26[34],
- net_26[33], net_26[32], net_26[31], net_26[30], net_26[29], net_26[28],
- net_26[27], net_26[26], net_26[25], net_26[24], net_26[23], net_26[22],
- net_26[21], net_26[20], net_26[19], net_26[18], net_26[17], net_26[16],
- net_26[15], net_26[14], net_26[13], net_26[12], net_26[11], net_26[10],
- net_26[9], net_26[8], net_26[7], net_26[6], net_26[5], net_26[4],
- net_26[3], net_26[2], net_26[1], net_26[0]}), .rq_succ_(net_15),
- .sor({net_75[8]}));
- stageGroupsM__outM1PredLit outM1Pre_0(.dp(dp[1:37]), .dp_B_(dp_B_),
- .epi_torp_(torp), .pred_D_(pred_D_), .pred_R_(net_84), .pred_T_(pred_T_),
- .ring({net_57[35], net_57[34], net_57[33], net_57[32], net_57[31],
- net_57[30], net_57[29], net_57[28], net_57[27], net_57[26], net_57[25],
- net_57[24], net_57[23], net_57[22], net_57[21], net_57[20], net_57[19],
- net_57[18], net_57[17], net_57[16], net_57[15], net_57[14], net_57[13],
- net_57[12], net_57[11], net_57[10], net_57[9], net_57[8], net_57[7],
- net_57[6], net_57[5], net_57[4], net_57[3], net_57[2], net_57[1],
- net_57[0]}),
- .signalBitFromInboundSwitchFabric(signalBitFromInboundSwitchFabric),
- .sir({net_76[8], sir[2], sir[3], sir[4], sir[5], sir[6], sir[7], sir[8],
- sir[9]}), .dsA(dsA[14:1]), .dsA_TT_(dsA_TT_), .dsD({dsD[1], dsD[2],
- dsD[3], dsD[4], dsD[5], dsD[6]}), .dsD_1(dsD[37:7]),
- .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
- .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
- .m1({net_68[35], net_68[34], net_68[33], net_68[32], net_68[31],
- net_68[30], net_68[29], net_68[28], net_68[27], net_68[26], net_68[25],
- net_68[24], net_68[23], net_68[22], net_68[21], net_68[20], net_68[19],
- net_68[18], net_68[17], net_68[16], net_68[15], net_68[14], net_68[13],
- net_68[12], net_68[11], net_68[10], net_68[9], net_68[8], net_68[7],
- net_68[6], net_68[5], net_68[4], net_68[3], net_68[2], net_68[1],
- net_68[0]}), .ps_do_(ps_do_), .ps_skip_(ps_skip_), .sor(sor[1:1]),
- .succ_D_(succ_D_), .succ_T_(succ_T_), .succ_m1_(net_88));
- orangeTSMC090nm__wire90 wire90_1(.a(net_84));
- orangeTSMC090nm__wire90 wire90_2(.a(torp));
- orangeTSMC090nm__wire90 wire90_3(.a(net_88));
- orangeTSMC090nm__wire90 wire90_4(.a(net_15));
-endmodule /* dockM__outputDock */
-
-module centersJ__ctrAND3in100LT(inA, inB, inC, out);
- input inA;
- input inB;
- input inC;
- output out;
-
- supply1 vdd;
- supply0 gnd;
- wire net_104, net_130, net_138;
-
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_3 (out, net_104);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_4 (net_138, inC);
- // end Verilog_template
- /* begin Verilog_template for redFive:nand2LT_sy{sch}*/
- nand (strong0, strong1) #(100) nand2LT__0 (net_104, net_138, net_130);
- // end Verilog_template
- redFive__nor2n_sy nor2n_sy_0(.ina(inA), .inb(inB), .out(net_130));
- orangeTSMC090nm__wire90 wire90_0(.a(net_130));
- orangeTSMC090nm__wire90 wire90_4(.a(net_104));
- orangeTSMC090nm__wire90 wire90_5(.a(net_138));
-endmodule /* centersJ__ctrAND3in100LT */
-
-module gaspM__gaspTap(mc, pred, to_A_, to_B_, tok, fire, s, succ_A_, succ_B_,
- take);
- input mc;
- input pred;
- input to_A_;
- input to_B_;
- input tok;
- output fire;
- output [1:1] s;
- output succ_A_;
- output succ_B_;
- output take;
-
- supply1 vdd;
- supply0 gnd;
- wire net_163;
-
- centersJ__ctrAND3in100LT ctrAND3i_0(.inA(succ_A_), .inB(succ_B_),
- .inC(net_163), .out(fire));
- driversM__dataDriver60 dataDriv_0(.inA(tok), .inB(fire), .out(take));
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_0 (net_163, pred);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (s[1], net_163);
- // end Verilog_template
- driversM__predDri60wMC predDri6_1(.in(fire), .mc(mc), .pred(pred));
- driversM__sucANDdri60 sucANDdr_2(.inA(to_A_), .inB(fire), .succ(succ_A_));
- driversM__sucANDdri60 sucANDdr_3(.inA(to_B_), .inB(fire), .succ(succ_B_));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- orangeTSMC090nm__wire90 wire90_0(.a(net_163));
-endmodule /* gaspM__gaspTap */
-
-module scanM__scanFx2(dout, dout_1, sic, soc);
- output [1:1] dout;
- output [2:2] dout_1;
- inout [1:9] sic;
- inout [1:1] soc;
-
- supply1 vdd;
- supply0 gnd;
- wire net_30;
-
- scanM__scanCellF scanCell_3(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(sic[1]), .wr(sic[4]), .dout(dout[1:1]),
- .sout(net_30));
- scanM__scanCellF scanCell_4(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]),
- .rd(sic[5]), .sin(net_30), .wr(sic[4]), .dout(dout_1[2:2]),
- .sout(soc[1]));
- orangeTSMC090nm__wire90 wire90_0(.a(net_30));
-endmodule /* scanM__scanFx2 */
-
-module stagesM__tapStage(ain, ain_TT_, in, pred, aout, aout_TT_, out, succ_A_,
- succ_B_, sic, sir, soc, sor);
- input [14:1] ain;
- input ain_TT_;
- input [1:37] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output [1:37] out;
- output succ_A_;
- output succ_B_;
- inout [1:9] sic;
- inout [1:9] sir;
- inout [1:1] soc;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_0, net_3, net_54, to_A_, to_B_;
-
- registersM__addr1in60Cx15 addr1in6_0(.ain({ain[1], ain[2], ain[3], ain[4],
- ain[5], ain[6], ain[7], ain[8], ain[9], ain[10], ain[11], ain[12],
- ain[13], ain[14]}), .ain_TT_(ain_TT_), .fire(net_0), .aout({aout[1],
- aout[2], aout[3], aout[4], aout[5], aout[6], aout[7], aout[8], aout[9],
- aout[10], aout[11], aout[12], aout[13], aout[14]}),
- .aout_TT_(aout_TT_));
- registersM__data1in60Cx37 data1in6_0(.in(in[1:37]), .take(net_3),
- .out(out[1:37]));
- gaspM__gaspTap gaspTap_0(.mc(sir[9]), .pred(pred), .to_A_(to_A_),
- .to_B_(to_B_), .tok(ain_TT_), .fire(net_0), .s({net_54}),
- .succ_A_(succ_A_), .succ_B_(succ_B_), .take(net_3));
- scanM__scanEx1 scanEx1_0(.dIn({net_54}), .sir(sir[1:9]), .sor(sor[1:1]));
- scanM__scanFx2 scanFx2_0(.dout({to_A_}), .dout_1({to_B_}), .sic(sic[1:9]),
- .soc(soc[1:1]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
-endmodule /* stagesM__tapStage */
-
-module stageGroupsM__tapPropStop(ain, ain_TT_, cin, fin, in, pred, aout,
- aout_TT_, fout, out, succ_A_, succ_B_, sic, sid, sir, soc, sod, sor);
- input [14:1] ain;
- input ain_TT_;
- input cin;
- input fin;
- input [37:1] in;
- input pred;
- output [14:1] aout;
- output aout_TT_;
- output fout;
- output [37:1] out;
- output succ_A_;
- output succ_B_;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_85, net_91, properSt_1_fire;
- wire [8:8] net_100;
- wire [8:8] net_101;
- wire [8:8] net_105;
- wire [51:0] net_107;
-
- countersL__instructionCount instruct_0(.cin(cin), .count(net_91), .fin(fin),
- .fout(fout), .sid({net_105[8], sod[2], sod[3], sod[4], sod[5], sid[6],
- sid[7], sid[8], sid[9]}), .sod(sod[1:1]));
- stageGroupsM__properStopper properSt_1(.ain(ain[14:1]), .ain_TT_(ain_TT_),
- .in(in[37:1]), .pred(pred), .aout({net_107[37], net_107[38], net_107[39],
- net_107[40], net_107[41], net_107[42], net_107[43], net_107[44],
- net_107[45], net_107[46], net_107[47], net_107[48], net_107[49],
- net_107[50]}), .aout_TT_(net_107[51]), .extra(net_91),
- .fire(properSt_1_fire), .out({net_107[0], net_107[1], net_107[2],
- net_107[3], net_107[4], net_107[5], net_107[6], net_107[7], net_107[8],
- net_107[9], net_107[10], net_107[11], net_107[12], net_107[13],
- net_107[14], net_107[15], net_107[16], net_107[17], net_107[18],
- net_107[19], net_107[20], net_107[21], net_107[22], net_107[23],
- net_107[24], net_107[25], net_107[26], net_107[27], net_107[28],
- net_107[29], net_107[30], net_107[31], net_107[32], net_107[33],
- net_107[34], net_107[35], net_107[36]}), .succ(net_85), .sic(sic[1:9]),
- .sid(sid[1:9]), .sir(sir[1:9]), .soc({net_100[8], soc[2], soc[3], soc[4],
- soc[5]}), .sod({net_105[8], sod[2], sod[3], sod[4], sod[5]}),
- .sor({net_101[8], sor[2], sor[3], sor[4], sor[5]}));
- stagesM__tapStage tapStage_2(.ain({net_107[37], net_107[38], net_107[39],
- net_107[40], net_107[41], net_107[42], net_107[43], net_107[44],
- net_107[45], net_107[46], net_107[47], net_107[48], net_107[49],
- net_107[50]}), .ain_TT_(net_107[51]), .in({net_107[36], net_107[35],
- net_107[34], net_107[33], net_107[32], net_107[31], net_107[30],
- net_107[29], net_107[28], net_107[27], net_107[26], net_107[25],
- net_107[24], net_107[23], net_107[22], net_107[21], net_107[20],
- net_107[19], net_107[18], net_107[17], net_107[16], net_107[15],
- net_107[14], net_107[13], net_107[12], net_107[11], net_107[10],
- net_107[9], net_107[8], net_107[7], net_107[6], net_107[5], net_107[4],
- net_107[3], net_107[2], net_107[1], net_107[0]}), .pred(net_85),
- .aout(aout[14:1]), .aout_TT_(aout_TT_), .out({out[1], out[2], out[3],
- out[4], out[5], out[6], out[7], out[8], out[9], out[10], out[11],
- out[12], out[13], out[14], out[15], out[16], out[17], out[18], out[19],
- out[20], out[21], out[22], out[23], out[24], out[25], out[26], out[27],
- out[28], out[29], out[30], out[31], out[32], out[33], out[34], out[35],
- out[36], out[37]}), .succ_A_(succ_A_), .succ_B_(succ_B_),
- .sic({net_100[8], soc[2], soc[3], soc[4], soc[5], sic[6], sic[7], sic[8],
- sic[9]}), .sir({net_101[8], sor[2], sor[3], sor[4], sor[5], sir[6],
- sir[7], sir[8], sir[9]}), .soc(soc[1:1]), .sor(sor[1:1]));
- orangeTSMC090nm__wire90 wire90_2(.a(net_85));
-endmodule /* stageGroupsM__tapPropStop */
-
-module stageGroupsM__southFifo(cin, fin, aout, aout_TT_, fout, out, succ_tap_,
- sic, sid, sir, soc, sod, sor);
- input cin;
- input fin;
- output [14:1] aout;
- output aout_TT_;
- output fout;
- output [37:1] out;
- output succ_tap_;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
- inout [1:5] soc;
- inout [1:5] sod;
- inout [1:5] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire net_53, net_58, net_61;
- wire [8:8] net_64;
- wire [51:0] net_77;
- wire [51:0] net_79;
-
- stageGroupsM__tapPropStop tapPropS_1(.ain({net_79[37], net_79[38],
- net_79[39], net_79[40], net_79[41], net_79[42], net_79[43], net_79[44],
- net_79[45], net_79[46], net_79[47], net_79[48], net_79[49], net_79[50]}),
- .ain_TT_(net_79[51]), .cin(cin), .fin(fin), .in({net_79[0], net_79[1],
- net_79[2], net_79[3], net_79[4], net_79[5], net_79[6], net_79[7],
- net_79[8], net_79[9], net_79[10], net_79[11], net_79[12], net_79[13],
- net_79[14], net_79[15], net_79[16], net_79[17], net_79[18], net_79[19],
- net_79[20], net_79[21], net_79[22], net_79[23], net_79[24], net_79[25],
- net_79[26], net_79[27], net_79[28], net_79[29], net_79[30], net_79[31],
- net_79[32], net_79[33], net_79[34], net_79[35], net_79[36]}),
- .pred(net_61), .aout(aout[14:1]), .aout_TT_(aout_TT_), .fout(fout),
- .out(out[37:1]), .succ_A_(net_53), .succ_B_(succ_tap_), .sic(sic[1:9]),
- .sid(sid[1:9]), .sir({net_64[8], sir[2], sir[3], sir[4], sir[5], sir[6],
- sir[7], sir[8], sir[9]}), .soc(soc[1:5]), .sod(sod[1:5]),
- .sor(sor[1:5]));
- stageGroupsM__upDown8weak upDown8w_1(.ainD(aout[14:1]), .ainD_TT_(aout_TT_),
- .ainU({net_77[37], net_77[38], net_77[39], net_77[40], net_77[41],
- net_77[42], net_77[43], net_77[44], net_77[45], net_77[46], net_77[47],
- net_77[48], net_77[49], net_77[50]}), .ainU_TT_(net_77[51]),
- .inD(out[37:1]), .inU({net_77[0], net_77[1], net_77[2], net_77[3],
- net_77[4], net_77[5], net_77[6], net_77[7], net_77[8], net_77[9],
- net_77[10], net_77[11], net_77[12], net_77[13], net_77[14], net_77[15],
- net_77[16], net_77[17], net_77[18], net_77[19], net_77[20], net_77[21],
- net_77[22], net_77[23], net_77[24], net_77[25], net_77[26], net_77[27],
- net_77[28], net_77[29], net_77[30], net_77[31], net_77[32], net_77[33],
- net_77[34], net_77[35], net_77[36]}), .predD(net_53), .predU(net_58),
- .aoutD({net_77[37], net_77[38], net_77[39], net_77[40], net_77[41],
- net_77[42], net_77[43], net_77[44], net_77[45], net_77[46], net_77[47],
- net_77[48], net_77[49], net_77[50]}), .aoutD_TT_(net_77[51]),
- .aoutU({net_79[37], net_79[38], net_79[39], net_79[40], net_79[41],
- net_79[42], net_79[43], net_79[44], net_79[45], net_79[46], net_79[47],
- net_79[48], net_79[49], net_79[50]}), .aoutU_TT_(net_79[51]),
- .outD({net_77[0], net_77[1], net_77[2], net_77[3], net_77[4], net_77[5],
- net_77[6], net_77[7], net_77[8], net_77[9], net_77[10], net_77[11],
- net_77[12], net_77[13], net_77[14], net_77[15], net_77[16], net_77[17],
- net_77[18], net_77[19], net_77[20], net_77[21], net_77[22], net_77[23],
- net_77[24], net_77[25], net_77[26], net_77[27], net_77[28], net_77[29],
- net_77[30], net_77[31], net_77[32], net_77[33], net_77[34], net_77[35],
- net_77[36]}), .outU({net_79[0], net_79[1], net_79[2], net_79[3],
- net_79[4], net_79[5], net_79[6], net_79[7], net_79[8], net_79[9],
- net_79[10], net_79[11], net_79[12], net_79[13], net_79[14], net_79[15],
- net_79[16], net_79[17], net_79[18], net_79[19], net_79[20], net_79[21],
- net_79[22], net_79[23], net_79[24], net_79[25], net_79[26], net_79[27],
- net_79[28], net_79[29], net_79[30], net_79[31], net_79[32], net_79[33],
- net_79[34], net_79[35], net_79[36]}), .succD(net_58), .succU(net_61),
- .sir(sir[1:9]), .sor({net_64[8]}));
-endmodule /* stageGroupsM__southFifo */
-
-module stageGroupsM__tokenFIFO(pred, succ, sir, sor);
- input pred;
- output succ;
- inout [1:9] sir;
- inout [1:1] sor;
-
- supply1 vdd;
- supply0 gnd;
- wire aStage_3_fire, aStage_4_fire, aStage_5_fire, net_0, net_2;
- wire [1:3] s;
-
- gaspM__aStage aStage_3(.mc(sir[9]), .pred(pred), .fire(aStage_3_fire),
- .s({s[1]}), .succ(net_0));
- gaspM__aStage aStage_4(.mc(sir[9]), .pred(net_0), .fire(aStage_4_fire),
- .s({s[2]}), .succ(net_2));
- gaspM__aStage aStage_5(.mc(sir[9]), .pred(net_2), .fire(aStage_5_fire),
- .s({s[3]}), .succ(succ));
- scanM__scanEx3h scanEx3h_1(.dIn(s[1:3]), .sin(sir[1]), .mc(sir[9]),
- .sout(sor[1]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
- wiresL__tranCap tc_1_();
- wiresL__tranCap tc_2_();
- wiresL__tranCap tc_3_();
- wiresL__tranCap tc_4_();
- wiresL__tranCap tc_5_();
- wiresL__tranCap tc_6_();
- wiresL__tranCap tc_7_();
- wiresL__tranCap tc_8_();
- wiresL__tranCap tc_9_();
- wiresL__tranCap tc_10_();
- wiresL__tranCap tc_11_();
- wiresL__tranCap tc_12_();
- wiresL__tranCap tc_13_();
- wiresL__tranCap tc_14_();
- wiresL__tranCap tc_15_();
- wiresL__tranCap tc_16_();
- orangeTSMC090nm__wire90 wire90_0(.a(net_0));
- orangeTSMC090nm__wire90 wire90_1(.a(net_2));
-endmodule /* stageGroupsM__tokenFIFO */
-
-module marinaOutDock(fin, fout, sic, sid, sir);
- input fin;
- output fout;
- inout [1:9] sic;
- inout [1:9] sid;
- inout [1:9] sir;
-
- supply1 vdd;
- supply0 gnd;
- wire ain_T_, aout_T_, dockPred_D_, dockPred_T_, dockSucc_D_, dockSucc_T_;
- wire dsA_TT_, net_14, net_38, net_44;
- wire [14:1] ain;
- wire [14:1] aout;
- wire [37:1] din;
- wire [14:1] dsA;
- wire [37:1] dsD;
- wire \iout[1] ;
- wire \iout[2] ;
- wire \iout[3] ;
- wire \iout[4] ;
- wire \iout[5] ;
- wire \iout[6] ;
- wire \iout[7] ;
- wire \iout[8] ;
- wire \iout[9] ;
- wire \iout[10] ;
- wire \iout[11] ;
- wire \iout[12] ;
- wire \iout[13] ;
- wire \iout[14] ;
- wire \iout[15] ;
- wire \iout[16] ;
- wire \iout[17] ;
- wire \iout[18] ;
- wire \iout[20] ;
- wire \iout[21] ;
- wire \iout[22] ;
- wire \iout[23] ;
- wire \iout[24] ;
- wire \iout[25] ;
- wire \iout[26] ;
- wire \iout[27] ;
- wire \iout[28] ;
- wire \iout[29] ;
- wire \iout[30] ;
- wire \iout[31] ;
- wire \iout[32] ;
- wire \iout[33] ;
- wire \iout[34] ;
- wire \iout[35] ;
- wire \iout[36] ;
- wire \iout[37] ;
- wire [19:19] iout_1;
- wire [8:4] net_109;
- wire [8:4] net_116;
- wire [8:4] net_117;
- wire [8:8] net_119;
- wire [8:8] net_120;
-
- stageGroupsM__northFifo northFif_1(.ainU(dsA[14:1]), .ainU_TT_(dsA_TT_),
- .fin(net_38), .inU(dsD[37:1]), .predU(dockSucc_D_), .aoutD(ain[14:1]),
- .aoutD_TT_(ain_T_), .fout(fout), .outD(din[37:1]), .succD(dockPred_D_),
- .sic({net_116[8], net_116[7], net_116[6], net_116[5], net_116[4], sic[6],
- sic[7], sic[8], sic[9]}), .sid({net_117[8], net_117[7], net_117[6],
- net_117[5], net_117[4], sid[6], sid[7], sid[8], sid[9]}),
- .sir({net_109[8], net_109[7], net_109[6], net_109[5], net_109[4], sir[6],
- sir[7], sir[8], sir[9]}));
- dockM__outputDock outputDo_0(.do_epi_(net_14), .dp({din[1], din[2], din[3],
- din[4], din[5], din[6], din[7], din[8], din[9], din[10], din[11],
- din[12], din[13], din[14], din[15], din[16], din[17], din[18], din[19],
- din[20], din[21], din[22], din[23], din[24], din[25], din[26], din[27],
- din[28], din[29], din[30], din[31], din[32], din[33], din[34], din[35],
- din[36], din[37]}), .dp_B_(ain[6]), .in({ \iout[1] , \iout[2] ,
- \iout[3] , \iout[4] , \iout[5] , \iout[6] , \iout[7] , \iout[8] ,
- \iout[9] , \iout[10] , \iout[11] , \iout[12] , \iout[13] , \iout[14]
- , \iout[15] , \iout[16] , \iout[17] , \iout[18] , \iout[20] ,
- \iout[21] , \iout[22] , \iout[23] , \iout[24] , \iout[25] ,
- \iout[26] , \iout[27] , \iout[28] , \iout[29] , \iout[30] ,
- \iout[31] , \iout[32] , \iout[33] , \iout[34] , \iout[35] ,
- \iout[36] , \iout[37] }), .in_T_(aout_T_), .pred_D_(dockPred_D_),
- .pred_T_(dockPred_T_), .signalBitFromInboundSwitchFabric(ain[14]),
- .sir({net_119[8], net_109[7], net_109[6], net_109[5], net_109[4], sir[6],
- sir[7], sir[8], sir[9]}), .dsA(dsA[14:1]), .dsA_TT_(dsA_TT_),
- .dsD(dsD[37:1]), .fout(net_44), .sor({net_120[8]}),
- .succ_D_(dockSucc_D_), .succ_T_(dockSucc_T_));
- stageGroupsM__southFifo southFif_1(.cin(net_44), .fin(fin),
- .aout(aout[14:1]), .aout_TT_(aout_T_), .fout(net_38), .out({ \iout[37] ,
- \iout[36] , \iout[35] , \iout[34] , \iout[33] , \iout[32] ,
- \iout[31] , \iout[30] , \iout[29] , \iout[28] , \iout[27] ,
- \iout[26] , \iout[25] , \iout[24] , \iout[23] , \iout[22] ,
- \iout[21] , \iout[20] , iout_1[19], \iout[18] , \iout[17] , \iout[16]
- , \iout[15] , \iout[14] , \iout[13] , \iout[12] , \iout[11] ,
- \iout[10] , \iout[9] , \iout[8] , \iout[7] , \iout[6] , \iout[5] ,
- \iout[4] , \iout[3] , \iout[2] , \iout[1] }), .succ_tap_(net_14),
- .sic(sic[1:9]), .sid(sid[1:9]), .sir(sir[1:9]), .soc({net_116[8],
- net_116[7], net_116[6], net_116[5], net_116[4]}), .sod({net_117[8],
- net_117[7], net_117[6], net_117[5], net_117[4]}), .sor({net_119[8],
- net_109[7], net_109[6], net_109[5], net_109[4]}));
- stageGroupsM__tokenFIFO tokenFIF_1(.pred(dockSucc_T_), .succ(dockPred_T_),
- .sir({net_120[8], net_109[7], net_109[6], net_109[5], net_109[4], sir[6],
- sir[7], sir[8], sir[9]}), .sor({net_109[8]}));
-endmodule /* marinaOutDock */