new files from ivan
authorAdam Megacz <adam.megacz@sun.com>
Tue, 21 Apr 2009 06:22:15 +0000 (06:22 +0000)
committerAdam Megacz <adam.megacz@sun.com>
Tue, 21 Apr 2009 06:22:15 +0000 (06:22 +0000)
electric/loopCountM.jelib
testCode/marina.spi
testCode/marina.v

index 2a26ae9..59dddd3 100755 (executable)
@@ -1204,7 +1204,7 @@ EinA|zero|D5G2;|nor15@0|inA|I
 X
 
 # Cell ilcEven;6{sch}
-CilcEven;6{sch}||schematic|1216766649341|1240273053366|
+CilcEven;6{sch}||schematic|1216766649341|1240288914073|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||45|12|||XY|
 NOff-Page|conn@1||14.5|12|||XY|
@@ -1220,7 +1220,7 @@ NOff-Page|conn@23||-2.5|-29|||RRR|
 NOff-Page|conn@24||-69.5|0|||RR|
 NOff-Page|conn@25||-66|-16|||YR|
 IilcEven;1{ic}|ilcEven@0||51|30.5|||D5G4;
-IredFive:inv;1{ic}|inv@7||-40|-24|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@7||-40|-24|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFive:inv;1{ic}|inv@8||37|-23|X||D0G4;|ATTR_Delay(D5G1;NPX4;Y-4;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IlatchesK:mlat1in10;1{ic}|mlat1in1@1||-60|0|X||D5G4;
 IredFive:nor2n;1{ic}|nor2n@0||-60|-24|Y||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S15|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
@@ -1690,7 +1690,7 @@ EinA|zero|D5G2;|nor15@0|inA|I
 X
 
 # Cell ilcOdd;6{sch}
-CilcOdd;6{sch}||schematic|1216766649341|1240273024047|
+CilcOdd;6{sch}||schematic|1216766649341|1240288902097|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@1||15|12|||XY|
 NOff-Page|conn@2||-15|12|||XY|
@@ -1698,7 +1698,7 @@ NOff-Page|conn@3||24|0|||RR|
 NOff-Page|conn@4||-6|0|||RR|
 NOff-Page|conn@5||-36|0|||RR|
 NOff-Page|conn@6||48|-13.5|||XY|
-NOff-Page|conn@7||38|-30|||XY|
+NOff-Page|conn@7||38|-29|||XY|
 NOff-Page|conn@12||-76.5|-31|||Y|
 NWire_Con|conn@19||-15|-25||||
 NOff-Page|conn@20||-15|-31|||RRR|
@@ -1708,9 +1708,9 @@ NOff-Page|conn@24||-72|-20|||YR|
 NWire_Con|conn@25||-66|-12||||
 NGround|gnd@0||-48|-7||||
 IilcOdd;1{ic}|ilcOdd@0||39|37|||D5G4;
-IredFive:inv;1{ic}|inv@5||-45|-30|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFive:inv;1{ic}|inv@6||30|-30|X||D0G4;|ATTR_Delay(D5G1;NPX5;Y-3;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFive:inv;1{ic}|inv@7||-54|-18|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@5||-45|-30|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@6||30|-29|X||D0G4;|ATTR_Delay(D5G1;NPX5;Y-3;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@7||-54|-18|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IlatchesK:mlat2in10i;1{ic}|mlat2in1@1||-55|0|X||D5G4;
 IredFive:nor2n;1{ic}|nor2n@0||-66|-30|Y||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S15|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 Ngeneric:Invisible-Pin|pin@0||-31|45|||||ART_message(D5G6;)SilcOdd
@@ -1730,8 +1730,8 @@ NBus_Pin|pin@123||4.5|18|-1|-1||
 NBus_Pin|pin@124||34.5|18|-1|-1||
 NWire_Pin|pin@126||-33|-30||||
 NWire_Pin|pin@127||-33|-26||||
-NWire_Pin|pin@130||18|-30|||X|
-NWire_Pin|pin@131||18|-26|||X|
+NWire_Pin|pin@130||18|-29|||X|
+NWire_Pin|pin@131||18|-25|||X|
 NBus_Pin|pin@133||-12|18|-1|-1||
 NBus_Pin|pin@134||-12|24|-1|-1||
 NBus_Pin|pin@135||-12|-12|-1|-1||
@@ -1757,7 +1757,7 @@ IringB;1{ic}|ringB@3||-30|0|X||D5G4;
 IringB;1{ic}|ringB@4||0|0|X||D5G4;
 IringB;1{ic}|ringB@5||30|0|X||D5G4;
 IorangeTSMC090nm:wire90;1{ic}|wire90@4||-38.5|-30|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1587.9999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
-IorangeTSMC090nm:wire90;1{ic}|wire90@5||22.5|-30|X||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1458.0999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@5||22.5|-29|X||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1458.0999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@6||-47.5|-18|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D341.09999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@7||-57|-30|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1283.2999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 Abus|bit[1,3,5,7]|D5G2;|-0.5|IJ2700|conn@19||-15|-25|pin@186||-15|-20
@@ -1771,7 +1771,7 @@ Awire|ilc[decLO]|D5G2;||2700|pin@207||-66|-18|conn@25||-66|-12
 Awire|inLO[1]|D5G2;||900|pin@25||42|-2|pin@26||42|-6
 Awire|inLO[3]|D5G2;||900|pin@27||12|-2|pin@28||12|-6
 Awire|inLO[5]|D5G2;||900|pin@29||-18|-2|pin@30||-18|-6
-Awire|load[F]|D5G2;||2700|pin@130||18|-30|pin@131||18|-26
+Awire|load[F]|D5G2;||2700|pin@130||18|-29|pin@131||18|-25
 Abus|load[T,F]|D5G2;|-0.5|IJ900|pin@135||-12|-12|pin@136||-12|-18
 Abus|net@5||-0.5|IJ1800|pin@135||-12|-12|pin@68||5|-12
 Awire|net@93|||0|pin@29||-18|-2|ringB@3|inLO[1]|-23|-2
@@ -1791,9 +1791,9 @@ Abus|net@265||-0.5|IJ2700|ringB@4|count[T,F]|4.5|10|pin@123||4.5|18
 Abus|net@267||-0.5|IJ2700|ringB@5|count[T,F]|34.5|10|pin@124||34.5|18
 Awire|net@273|||0|wire90@4|a|-41|-30|inv@5|out|-42.5|-30
 Awire|net@274|||0|pin@126||-33|-30|wire90@4|b|-36|-30
-Awire|net@275|||1800|wire90@5|a|25|-30|inv@6|out|27.5|-30
-Awire|net@277|||1800|pin@130||18|-30|wire90@5|b|20|-30
-Awire|net@278|||0|conn@7|y|36|-30|inv@6|in|32.5|-30
+Awire|net@275|||1800|wire90@5|a|25|-29|inv@6|out|27.5|-29
+Awire|net@277|||1800|pin@130||18|-29|wire90@5|b|20|-29
+Awire|net@278|||0|conn@7|y|36|-29|inv@6|in|32.5|-29
 Abus|net@280||-0.5|IJ0|pin@67||35|-12|pin@68||5|-12
 Abus|net@281||-0.5|IJ0|pin@124||34.5|18|pin@123||4.5|18
 Abus|net@282||-0.5|IJ1800|pin@122||-25.5|18|pin@133||-12|18
@@ -3236,6 +3236,312 @@ Evdd_21||D5G2;|olcContr@3|vdd_11|P
 Evdd_22||D5G2;|olcContr@3|vdd_12|P
 X
 
+# Cell olcControl;3{sch}
+ColcControl;3{sch}||schematic|1230935566337|1240288198358|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@3||-23.5|65|||Y|
+NOff-Page|conn@5||-47.5|71|||XR|
+NOff-Page|conn@6||-42|71|||XYR|
+NOff-Page|conn@7||-102.5|65|||Y|
+NOff-Page|conn@8||20.5|64|||R|
+NOff-Page|conn@9||-21.5|70|||X|
+NOff-Page|conn@11||-60|66.5|||XR|
+NOff-Page|conn@12||-115|19|||XYRR|
+IcentersJ:ctrAND1in30;1{ic}|ctrAND1i@4||60|13|R||D5G4;
+IcentersJ:ctrAND2in100LT;1{ic}|ctrAND2i@3||-48|11|R||D5G4;
+IcentersJ:ctrAND2in100;1{ic}|ctrAND2i@5||72|13|R||D5G4;
+IcentersJ:ctrAND2in100LT;1{ic}|ctrAND2i@6||-60|45|R||D5G4;
+IcentersJ:ctrAND2in30;1{ic}|ctrAND2i@8||6|11|R||D5G4;
+IcentersJ:ctrAND3in30B;1{ic}|ctrAND3i@0||-108|3|R||D5G4;
+IredFive:inv;1{ic}|inv@6||54|45.5|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@7||12|45|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@14||47.5|0|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@18||44.5|-19.5|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@19||44.5|-28.5|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@20||-127|-24|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@21||-102|25|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@22||-72.5|36|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@25||-72|0|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@2||60.5|-28.5|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@3||60.5|-19.5|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@4||-110.5|-32|XRRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nand2;1{ic}|nand2@0||45|51|X||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nand2;1{ic}|nand2@1||21.5|51|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nand2;1{ic}|nand2@2||45|39|XY||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nand2;1{ic}|nand2@3||21.5|39|Y||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nor2_sy;1{ic}|nor2_sy@2||-8|1|XRR||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(T)I-1
+IolcControl;1{ic}|olcContr@0||53|64.5|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||1|79.5|||||ART_message(D5G5;)SolcControl
+Ngeneric:Invisible-Pin|pin@1||1|73.5|||||ART_message(D5G3;)Sies 20 April 2009
+NWire_Pin|pin@35||-30|24||||
+Ngeneric:Invisible-Pin|pin@73||63.5|42.5|||||ART_message(D3G2;)S[this stage sets,"flag[D] from a",newly-decremented,ilc value using,"the \"zoo\" signal."]
+NWire_Pin|pin@83||33|24.5||||
+NWire_Pin|pin@84||33|70.5||||
+NWire_Pin|pin@86||60|52|||X|
+NWire_Pin|pin@87||6|52||||
+NWire_Pin|pin@90||54|40|||X|
+NWire_Pin|pin@94||12|50||||
+NWire_Pin|pin@95||12|40||||
+NWire_Pin|pin@97||54|50|||X|
+NWire_Pin|pin@113||-48|24||||
+NWire_Pin|pin@121||-48|29.5||||
+Ngeneric:Invisible-Pin|pin@123||-45.5|29.5|||||ART_message(D3G2;)S[this stage fires,for load OLC.]
+Ngeneric:Invisible-Pin|pin@124||-11|50.5|||||ART_message(D3G2;)S[This stage sets,"flag[D] from","the olc[zero]",value.  Use after,"olc[load] or to",restore D after,move.]
+NWire_Pin|pin@144||-49|0||||
+NWire_Pin|pin@149||-47|0||||
+NWire_Pin|pin@150||0|22||||
+NWire_Pin|pin@151||0|18||||
+NWire_Pin|pin@155||54|22||||
+NWire_Pin|pin@156||54|19||||
+NWire_Pin|pin@159||42|24||||
+NWire_Pin|pin@160||42|0||||
+Ngeneric:Invisible-Pin|pin@176||-77.5|52|||X||ART_message(D3G2;)S[this stage fires,for load ILC.]
+NWire_Pin|pin@178||60|26||||
+NWire_Pin|pin@181||31|39||||
+NWire_Pin|pin@182||31|51||||
+NWire_Pin|pin@183||35|39||||
+NWire_Pin|pin@184||35|51||||
+Ngeneric:Invisible-Pin|pin@224||11.5|-16|||||ART_message(D3G2;)S[no use reporting,"do[Co] and do[2]","and do[reD]",because they can,never wait.]
+NWire_Pin|pin@225||37.5|-28.5||||
+NWire_Pin|pin@227||67.5|-19.5||||
+NWire_Pin|pin@228||67.5|-12.5||||
+NWire_Pin|pin@229||67.5|-28.5||||
+NWire_Pin|pin@230||67.5|-21.5||||
+NWire_Pin|pin@231||37.5|-19.5||||
+NWire_Pin|pin@232||37.5|-14.5||||
+NWire_Pin|pin@233||37.5|-24.5||||
+NWire_Pin|pin@234||71|0||||
+NWire_Pin|pin@235||73|1||||
+NWire_Pin|pin@236||72|24||||
+NWire_Pin|pin@238||60|0||||
+NWire_Pin|pin@244||-12|24|||X|
+NWire_Pin|pin@251||-110.5|-39||||
+Ngeneric:Invisible-Pin|pin@252||-123.5|16.5|||||ART_message(D3G2;)S[selects between,"1 = olc, 0 = ilc"]
+NWire_Pin|pin@254||-132|57||||
+NWire_Pin|pin@257||-132|-24||||
+NWire_Pin|pin@260||-110.5|-24||||
+NWire_Pin|pin@264||-102|35||||
+NWire_Pin|pin@266||-108|37||||
+NWire_Pin|pin@271||-60|57||||
+NWire_Pin|pin@273||-61|36||||
+NWire_Pin|pin@288||-78|36||||
+NWire_Pin|pin@289||-102|19||||
+NWire_Pin|pin@291||-108|17||||
+NWire_Pin|pin@292||-84|18||||
+NWire_Pin|pin@299||-84|-9||||
+NWire_Pin|pin@302||5|1||||
+NWire_Pin|pin@309||-30|0||||
+NWire_Pin|pin@310||-12|2||||
+NWire_Pin|pin@311||6|26||||
+NWire_Pin|pin@312||-63|-16||||
+NWire_Pin|pin@315||60|38||||
+Ngeneric:Invisible-Pin|pin@328||-114.5|45.5|||||ART_message(D3G2;)S[this stage gives,delay for counter,input data to settle.]
+NWire_Pin|pin@329||6|62||||
+NWire_Pin|pin@330||-108|62||||
+NWire_Pin|pin@332||-108|59||||
+NWire_Pin|pin@333||6|38||||
+NWire_Pin|pin@342||-84|0||||
+NWire_Pin|pin@343||-108|55||||
+NWire_Pin|pin@344||-108|51||||
+NWire_Pin|pin@346||7|-24||||
+NWire_Pin|pin@347||-78|-18||||
+NWire_Pin|pin@350||-63|-7||||
+NWire_Pin|pin@351||-59|-11||||
+NWire_Pin|pin@352||-59|-20||||
+NWire_Pin|pin@353||-59|-24||||
+NWire_Pin|pin@355||-105.5|-9||||
+NWire_Pin|pin@356||-107.5|-18||||
+NWire_Pin|pin@363||-30|-14||||
+NWire_Pin|pin@364||-52|-16||||
+NWire_Pin|pin@365||-52|-20||||
+NWire_Pin|pin@366||-49|-12||||
+IdriversL:predDri20wMC;1{ic}|predDri2@2||48|24|X||D5G4;
+IdriversL:predDri20wMC;1{ic}|predDri2@3||-6|24|X||D5G4;
+IdriversL:predDri20wMC;1{ic}|predDri2@5||-71|-18|XY||D5G4;
+IdriversL:predDri20wMC;1{ic}|predDri2@8||-71|-9|XY||D5G4;
+IdriversL:predDri20wMC;1{ic}|predDri2@9||-38|-14|||D5G4;
+IdriversL:predORdri20wMC;2{ic}|predORdr@1||-117.5|57|X||D5G4;
+IdriversL:sucANDdri20;1{ic}|sucANDdr@0||-87|36|||D5G4;
+IdriversL:sucANDdri20;1{ic}|sucANDdr@1||-93|18|Y||D5G4;
+IdriversL:sucDri20;1{ic}|sucDri20@0||-39|24|||D5G4;
+IdriversL:sucDri20or;1{ic}|sucDri20@3||33|61.5|YRRR||D5G4;
+IdriversL:sucDri20or;1{ic}|sucDri20@4||33|32|XYR||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@9||27.5|39|||D0G4;|ATTR_L(D5G1;PUD)D405.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@10||39|39|X||D0G4;|ATTR_L(D5G1;PUD)D472.9|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@11||39|51|X||D0G4;|ATTR_L(D5G1;PUD)D346.69999999999993|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@12||27.5|51|||D0G4;|ATTR_L(D5G1;PUD)D438.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@13||51|50|X||D0G4;|ATTR_L(D5G1;PUD)D143.2|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@14||15.5|50|||D0G4;|ATTR_L(D5G1;PUD)D144.29999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@17||-63.5|0|||D0G4;|ATTR_L(D5G1;PUD)D431.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@19||54.5|0|||D0G4;|ATTR_L(D5G1;PUD)D485.9000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@22||0|1|||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@23||52.5|-19.5|||D0G4;|ATTR_L(D5G1;PUD)D140.59999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@24||52.5|-28.5|||D0G4;|ATTR_L(D5G1;PUD)D140.6|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@25||-120|-24|||D0G4;|ATTR_L(D5G1;PUD)D140.59999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@26||-103|37|X||D0G4;|ATTR_L(D5G1;PUD)D127.4|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@27||-97|35|X||D0G4;|ATTR_L(D5G1;PUD)D127.4|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@28||-66|36|X||D0G4;|ATTR_L(D5G1;PUD)D127.4|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@31||-92|-18|||D0G4;|ATTR_L(D5G1;PUD)D140.59999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@32||-97|-9|||D0G4;|ATTR_L(D5G1;PUD)D140.59999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@36||-39.5|0|||D0G4;|ATTR_L(D5G1;PUD)D431.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@37||53.5|38|X||D0G4;|ATTR_L(D5G1;PUD)D472.9|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@39||0.5|62|||D0G4;|ATTR_L(D5G1;PUD)D144.29999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|do[2]|D5G2;||900|pin@35||-30|24|pin@309||-30|0
+Awire|do[Co]|D5G2;||900|pin@159||42|24|pin@160||42|0
+Awire|do[Ld]|D5G2;||900|pin@254||-132|57|pin@257||-132|-24
+Awire|do[reD]|D5G2;||900|pin@244||-12|24|pin@310||-12|2
+Awire|do[zz]|D5G2;||900|pin@292||-84|18|pin@342||-84|0
+Awire|fire[Co]|D5G2;||900|pin@315||60|38|pin@178||60|26
+Awire|fire[zz]|D5G2;||2700|pin@311||6|26|pin@333||6|38
+Awire|flag[D][clr]|D5G2;||900|pin@84||33|70.5|sucDri20@3|succ|33|64.5
+Awire|flag[D][clr]|D5G2;||2700|pin@225||37.5|-28.5|pin@233||37.5|-24.5
+Awire|flag[D][set]|D5G2;||2700|pin@83||33|24.5|sucDri20@4|succ|33|29
+Awire|flag[D][set]|D5G2;||2700|pin@231||37.5|-19.5|pin@232||37.5|-14.5
+Awire|mc|D5G2;||900|pin@150||0|22|pin@151||0|18
+Awire|mc|D5G2;||900|pin@155||54|22|pin@156||54|19
+Awire|mc|D5G2;||900|pin@343||-108|55|pin@344||-108|51
+Awire|mc|D5G2;||900|pin@364||-52|-16|pin@365||-52|-20
+Awire|net@25|||1800|pin@113||-48|24|sucDri20@0|in|-43|24
+Awire|net@164|||0|pin@86||60|52|nand2@0|inb|47.5|52
+Awire|net@165|||0|nand2@1|inb|19|52|pin@87||6|52
+Awire|net@180|||2700|inv@6|out|54|48|pin@97||54|50
+Awire|net@184|||2700|inv@7|out|12|47.5|pin@94||12|50
+Awire|net@185|||1800|pin@95||12|40|nand2@3|ina|19|40
+Awire|net@186|||1800|nand2@2|ina|47.5|40|pin@90||54|40
+Awire|net@279|||0|nand2@2|out|42.5|39|wire90@10|a|41.5|39
+Awire|net@281|||1800|nand2@3|out|24|39|wire90@9|a|25|39
+Awire|net@284|||0|wire90@12|a|25|51|nand2@1|out|24|51
+Awire|net@286|||1800|wire90@11|a|41.5|51|nand2@0|out|42.5|51
+Awire|net@287|||1800|wire90@13|a|53.5|50|pin@97||54|50
+Awire|net@288|||0|wire90@13|b|48.5|50|nand2@0|ina|47.5|50
+Awire|net@289|||1800|wire90@14|b|18|50|nand2@1|ina|19|50
+Awire|net@290|||0|wire90@14|a|13|50|pin@94||12|50
+Awire|net@334|||900|pin@113||-48|24|ctrAND2i@3|out|-48|17
+Awire|net@340|||2700|pin@144||-49|0|ctrAND2i@3|inB|-49|5
+Awire|net@348|||2700|pin@149||-47|0|ctrAND2i@3|inA|-47|5
+Awire|net@378|||1800|predDri2@2|mc|51|22|pin@155||54|22
+Awire|net@383|||0|predDri2@2|pred|45|24|pin@159||42|24
+Awire|net@386|||0|wire90@19|a|52|0|inv@14|out|50|0
+Awire|net@388|||0|inv@14|in|45|0|pin@160||42|0
+Awire|net@415|||1800|predDri2@2|in|51|26|pin@178||60|26
+Awire|net@422|||0|pin@181||31|39|wire90@9|b|30|39
+Awire|net@424|||0|pin@182||31|51|wire90@12|b|30|51
+Awire|net@425|||900|sucDri20@3|inA_1|31|58.5|pin@182||31|51
+Awire|net@426|||0|wire90@10|b|36.5|39|pin@183||35|39
+Awire|net@428|||0|wire90@11|b|36.5|51|pin@184||35|51
+Awire|net@429|||2700|pin@184||35|51|sucDri20@3|in|35|58.5
+Awire|net@532|||2700|sucDri20@4|in|35|35|pin@183||35|39
+Awire|net@533|||2700|sucDri20@4|inA_1|31|35|pin@181||31|39
+Awire|net@534|||0|invI@3|in|58|-19.5|wire90@23|b|55|-19.5
+Awire|net@535|||0|wire90@23|a|50|-19.5|inv@18|out|47|-19.5
+Awire|net@537|||1800|invI@3|out|63|-19.5|pin@227||67.5|-19.5
+Awire|net@538|||0|invI@2|in|58|-28.5|wire90@24|b|55|-28.5
+Awire|net@539|||0|wire90@24|a|50|-28.5|inv@19|out|47|-28.5
+Awire|net@540|||1800|invI@2|out|63|-28.5|pin@229||67.5|-28.5
+Awire|net@541|||0|inv@19|in|42|-28.5|pin@225||37.5|-28.5
+Awire|net@542|||0|inv@18|in|42|-19.5|pin@231||37.5|-19.5
+Awire|net@547|||1800|pin@238||60|0|pin@234||71|0
+Awire|net@548|||900|ctrAND2i@5|inB|71|7|pin@234||71|0
+Awire|net@552|||1800|wire90@19|b|57|0|pin@238||60|0
+Awire|net@553|||900|ctrAND1i@4|in|60|7|pin@238||60|0
+Awire|net@554|||2700|ctrAND1i@4|out|60|19|pin@178||60|26
+Awire|net@563|||0|predDri2@3|pred|-9|24|pin@244||-12|24
+Awire|net@571|||1800|predDri2@3|mc|-3|22|pin@150||0|22
+Awire|net@576|||0|wire90@25|a|-122.5|-24|inv@20|out|-124.5|-24
+Awire|net@580|||0|predORdr@1|pred|-120.5|57|pin@254||-132|57
+Awire|net@588|||0|inv@20|in|-129.5|-24|pin@257||-132|-24
+Awire|net@592|||0|pin@260||-110.5|-24|wire90@25|b|-117.5|-24
+Awire|net@595|||2700|invI@4|in|-110.5|-29.5|pin@260||-110.5|-24
+Awire|net@605|||2700|inv@21|out|-102|27.5|pin@264||-102|35
+Awire|net@612|||0|wire90@26|b|-105.5|37|pin@266||-108|37
+Awire|net@620|||2700|pin@271||-60|57|conn@11|a|-60|64.5
+Awire|net@625|||900|pin@266||-108|37|pin@291||-108|17
+Awire|net@627|||0|wire90@27|b|-99.5|35|pin@264||-102|35
+Awire|net@632|||1800|sucANDdr@0|succ|-82|36|pin@288||-78|36
+Awire|net@634|||0|pin@273||-61|36|wire90@28|a|-63.5|36
+Awire|net@635|||0|wire90@28|b|-68.5|36|inv@22|out|-70|36
+Awire|net@638|||1800|wire90@26|a|-100.5|37|sucANDdr@0|inB|-92|37
+Awire|net@652|||900|ctrAND2i@6|inB|-61|39|pin@273||-61|36
+Awire|net@653|||0|sucANDdr@0|inA|-92|35|wire90@27|a|-94.5|35
+Awire|net@656|||900|pin@271||-60|57|ctrAND2i@6|out|-60|51
+Awire|net@666|||0|inv@22|in|-75|36|pin@288||-78|36
+Awire|net@667|||1800|conn@12|y|-113|19|pin@289||-102|19
+Awire|net@668|||2700|pin@289||-102|19|inv@21|in|-102|22.5
+Awire|net@671|||900|pin@291||-108|17|ctrAND3i@0|out|-108|9
+Awire|net@672|||0|sucANDdr@1|inB|-98|17|pin@291||-108|17
+Awire|net@673|||1800|sucANDdr@1|succ|-88|18|pin@292||-84|18
+Awire|net@675|||0|sucANDdr@1|inA|-98|19|pin@289||-102|19
+Awire|net@686|||0|pin@299||-84|-9|wire90@32|b|-94.5|-9
+Awire|net@695|||1800|wire90@22|b|2.5|1|pin@302||5|1
+Awire|net@696|||2700|pin@302||5|1|ctrAND2i@8|inB|5|5
+Awire|net@710|||0|pin@35||-30|24|sucDri20@0|succ|-35|24
+Awire|net@712|||0|wire90@36|a|-42|0|pin@149||-47|0
+Awire|net@715|||1800|pin@309||-30|0|nor2_sy@2|inb|-10.5|0
+Awire|net@717|||0|nor2_sy@2|ina|-10.5|2|pin@310||-12|2
+Awire|net@719|||1800|predDri2@3|in|-3|26|pin@311||6|26
+Awire|net@724|||0|wire90@22|a|-2.5|1|nor2_sy@2|out|-5.5|1
+Awire|net@725|||900|pin@86||60|52|pin@315||60|38
+Awire|net@727|||1800|wire90@37|a|56|38|pin@315||60|38
+Awire|net@728|||0|wire90@37|b|51|38|nand2@2|inb|47.5|38
+Awire|net@750|||0|pin@312||-63|-16|predDri2@5|mc|-68|-16
+Awire|net@761|||2700|pin@87||6|52|pin@329||6|62
+Awire|net@765|||900|pin@330||-108|62|pin@332||-108|59
+Awire|net@766|||0|pin@332||-108|59|predORdr@1|in|-114.5|59
+Awire|net@767|||2700|pin@333||6|38|pin@87||6|52
+Awire|net@769|||0|nand2@3|inb|19|38|pin@333||6|38
+Awire|net@773|||1800|pin@330||-108|62|wire90@39|a|-2|62
+Awire|net@774|||0|pin@329||6|62|wire90@39|b|3|62
+Awire|net@781|||1800|predORdr@1|in_1|-114.5|57|pin@271||-60|57
+Awire|net@783|||0|wire90@17|a|-66|0|inv@25|out|-69.5|0
+Awire|net@789|||900|pin@342||-84|0|pin@299||-84|-9
+Awire|net@790|||0|inv@25|in|-74.5|0|pin@342||-84|0
+Awire|net@792|||1800|predORdr@1|mc|-114.5|55|pin@343||-108|55
+Awire|net@796|||1800|pin@260||-110.5|-24|pin@353||-59|-24
+Awire|net@797|||2700|ctrAND2i@8|out|6|17|pin@311||6|26
+Awire|net@802|||2700|pin@346||7|-24|ctrAND2i@8|inA|7|5
+Awire|net@803|||0|predDri2@5|pred|-74|-18|pin@347||-78|-18
+Awire|net@806|||0|predDri2@8|pred|-74|-9|pin@299||-84|-9
+Awire|net@809|||1800|predDri2@8|mc|-68|-7|pin@350||-63|-7
+Awire|net@810|||1800|predDri2@8|in|-68|-11|pin@351||-59|-11
+Awire|net@811|||1800|predDri2@5|in|-68|-20|pin@352||-59|-20
+Awire|net@812|||2700|pin@352||-59|-20|pin@351||-59|-11
+Awire|net@814|||900|pin@351||-59|-11|pin@353||-59|-24
+Awire|net@815|||1800|wire90@36|b|-37|0|pin@309||-30|0
+Awire|net@819|||2700|pin@347||-78|-18|pin@288||-78|36
+Awire|net@820|||0|pin@347||-78|-18|wire90@31|b|-89.5|-18
+Awire|net@821|||0|wire90@32|a|-99.5|-9|pin@355||-105.5|-9
+Awire|net@823|||0|wire90@31|a|-94.5|-18|pin@356||-107.5|-18
+Awire|net@827|||900|ctrAND3i@0|inA|-105.5|-3|pin@355||-105.5|-9
+Awire|net@828|||900|ctrAND3i@0|inB|-107.5|-3|pin@356||-107.5|-18
+Awire|net@833|||0|predDri2@9|in|-41|-12|pin@366||-49|-12
+Awire|net@836|||1800|pin@353||-59|-24|pin@346||7|-24
+Awire|net@841|||2700|pin@363||-30|-14|pin@309||-30|0
+Awire|net@842|||2700|pin@312||-63|-16|pin@350||-63|-7
+Awire|net@843|||0|pin@364||-52|-16|pin@312||-63|-16
+Awire|net@844|||1800|predDri2@9|pred|-35|-14|pin@363||-30|-14
+Awire|net@845|||0|predDri2@9|mc|-41|-16|pin@364||-52|-16
+Awire|net@847|||1800|wire90@17|b|-61|0|pin@144||-49|0
+Awire|net@849|||900|pin@144||-49|0|pin@366||-49|-12
+Awire|net@850|||900|ctrAND2i@6|inA|-59|39|pin@352||-59|-20
+Awire|not[Ld]|D5G2;||2700|pin@260||-110.5|-24|ctrAND3i@0|inC|-110.5|-3
+Awire|olc[dec]|D5G2;||900|pin@236||72|24|ctrAND2i@5|out|72|19
+Awire|olc[load]|D5G2;||2700|pin@113||-48|24|pin@121||-48|29.5
+Awire|olc[zero]|D5G2;||900|inv@7|in|12|42.5|pin@95||12|40
+Awire|olc[zero]|D5G2;||900|ctrAND2i@5|inA|73|7|pin@235||73|1
+Awire|olc[zoo]|D5G2;||900|inv@6|in|54|43|pin@90||54|40
+Awire|s[1]|D5G2;||900|invI@4|out|-110.5|-34.5|pin@251||-110.5|-39
+Awire|s[2]|D5G2;||2700|pin@227||67.5|-19.5|pin@228||67.5|-12.5
+Awire|s[3]|D5G2;||2700|pin@229||67.5|-28.5|pin@230||67.5|-21.5
+EDvoid||D4G2;|conn@12|a|I
+Edo[Ld,Co,reD]||D4G2;|conn@7|a|I
+Eflag[D][set,clr]||D6G2;|conn@8|y|O
+Eilc[load]||D6G2;|conn@11|y|O
+Emc||D4G2;|conn@6|a|I
+Eolc[load,dec]||D6G2;|conn@9|y|O
+Eolc[zero,zoo]||D4G2;|conn@3|a|I
+Es[1:3]||D6G2;|conn@5|y|O
+X
+
 # Cell olcControl;2{sch}
 ColcControl;2{sch}||schematic|1230935566337|1237210271565|I
 Ngeneric:Facet-Center|art@0||0|0||||AV
@@ -3949,6 +4255,742 @@ Efire[Co_1]@45086567|olc[dec]|D6G2;|conn@18|y|O
 Edo[Co_1]|olc[zero]|D4G2;|conn@17|a|I
 X
 
+# Cell olcControlA;1{ic}
+ColcControlA;1{ic}||artwork|1240288371789|1240289923322|E
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Nschematic:Bus_Pin|pin@0||-5|-1|-1|-1||
+Nschematic:Bus_Pin|pin@4||-5|1|-1|-1||
+Nschematic:Bus_Pin|pin@6||5|-1|-1|-1||
+Nschematic:Bus_Pin|pin@8||5|1|-1|-1||
+Nschematic:Bus_Pin|pin@10||0|3|-1|-1||
+Nschematic:Bus_Pin|pin@12||-3|3|-1|-1||
+Nschematic:Bus_Pin|pin@14||3|-3|-1|-1||
+NPin|pin@16||4|2|1|1||
+NPin|pin@17||-4|2|1|1||
+NPin|pin@18||-3|2|1|1||
+NPin|pin@19||-3|3|1|1||
+NPin|pin@20||-4|1|1|1||
+NPin|pin@21||-5|1|1|1||
+NPin|pin@24||0|2|1|1||
+NPin|pin@25||0|3|1|1||
+Ngeneric:Invisible-Pin|pin@26||0|0|||||ART_message(D5G2;)SolcA
+NPin|pin@27||4|1|1|1||
+NPin|pin@28||5|1|1|1||
+NPin|pin@29||-4|-2|1|1||
+NPin|pin@30||4|-2|1|1||
+NPin|pin@31||3|-2|1|1||
+NPin|pin@32||3|-3|1|1||
+NPin|pin@33||4|-1|1|1||
+NPin|pin@34||5|-1|1|1||
+NPin|pin@35||-4|-1|1|1||
+NPin|pin@36||-5|-1|1|1||
+Nschematic:Bus_Pin|pin@37||3|4|-1|-1||
+NPin|pin@39||3|2|1|1||
+NPin|pin@40||3|4|1|1||
+AThicker|net@8|||FS0|pin@20||-4|1|pin@21||-5|1
+AThicker|net@11|||FS0|pin@39||3|2|pin@24||0|2
+AThicker|net@12|||FS2700|pin@24||0|2|pin@25||0|3
+AThicker|net@14|||FS2700|pin@27||4|1|pin@16||4|2
+AThicker|net@15|||FS0|pin@24||0|2|pin@18||-3|2
+AThicker|net@16|||FS900|pin@20||-4|1|pin@35||-4|-1
+AThicker|net@17|||FS0|pin@18||-3|2|pin@17||-4|2
+AThicker|net@18|||FS2700|pin@33||4|-1|pin@27||4|1
+AThicker|net@19|||FS1800|pin@27||4|1|pin@28||5|1
+AThicker|net@20|||FS2700|pin@18||-3|2|pin@19||-3|3
+AThicker|net@21|||FS900|pin@17||-4|2|pin@20||-4|1
+AThicker|net@22|||FS1800|pin@31||3|-2|pin@30||4|-2
+AThicker|net@23|||FS900|pin@31||3|-2|pin@32||3|-3
+AThicker|net@24|||FS2700|pin@30||4|-2|pin@33||4|-1
+AThicker|net@25|||FS1800|pin@33||4|-1|pin@34||5|-1
+AThicker|net@26|||FS900|pin@35||-4|-1|pin@29||-4|-2
+AThicker|net@27|||FS0|pin@35||-4|-1|pin@36||-5|-1
+AThicker|net@28|||FS1800|pin@29||-4|-2|pin@31||3|-2
+AThicker|net@30|||FS0|pin@16||4|2|pin@39||3|2
+AThicker|net@31|||FS2700|pin@39||3|2|pin@40||3|4
+EDvoid||D5G2;|pin@0||I
+Edo[Ld]||D5G2;|pin@4||I
+Edo[zz]||D5G2;|pin@6||O
+Efire[zz]||D5G2;|pin@8||I
+Eilc[load]||D5G2;|pin@10||O
+Emc||D5G2;|pin@12||I
+Enot[Ld]||D5G2;|pin@14||O
+Enot[Ld_1]|s[1]|D5G2;|pin@37||O
+X
+
+# Cell olcControlA;1{sch}
+ColcControlA;1{sch}||schematic|1240279203422|1240289894367|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@3||-37|46|||Y|
+NOff-Page|conn@4||31|7|||XRR|
+NOff-Page|conn@5||5.5|51|||XY|
+NOff-Page|conn@6||42|52.5|||XR|
+NOff-Page|conn@7||-13|8|||XYRR|
+NOff-Page|conn@9||39|-42|||XYRRR|
+NOff-Page|conn@10||47|-35|||XRR|
+NOff-Page|conn@11||-22|-21.5|||XR|
+IcentersJ:ctrAND2in100LT;1{ic}|ctrAND2i@1||42|34|R||D5G4;
+IcentersJ:ctrAND3in30B;1{ic}|ctrAND3i@1||-6|-8|R||D5G4;
+IredFive:inv;1{ic}|inv@5||-25|-35|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@6||0|14|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@7||29.5|25|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@1||-15|-27|X||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IolcControlA;1{ic}|olcContr@0||39|68|||D5G4;
+NWire_Pin|pin@9||-4|51||||
+Ngeneric:Invisible-Pin|pin@23||-5|73.5|||||ART_message(D5G5;)SolcControlA
+Ngeneric:Invisible-Pin|pin@24||-5|67.5|||||ART_message(D5G3;)Sies 20 April 2009
+Ngeneric:Invisible-Pin|pin@35||24.5|41|||X||ART_message(D3G2;)S[this stage fires,for load ILC.]
+NWire_Pin|pin@36||41|25||||
+NWire_Pin|pin@37||24|25||||
+NWire_Pin|pin@38||0|8||||
+NWire_Pin|pin@39||-6|6||||
+NWire_Pin|pin@40||18|7||||
+NWire_Pin|pin@41||18|-20||||
+NWire_Pin|pin@42||39|-27||||
+Ngeneric:Invisible-Pin|pin@43||-12.5|34.5|||||ART_message(D3G2;)S[this stage gives,delay for counter,input data to settle.]
+NWire_Pin|pin@44||-6|51||||
+NWire_Pin|pin@45||-6|48||||
+NWire_Pin|pin@48||-6|44||||
+NWire_Pin|pin@49||-6|40||||
+NWire_Pin|pin@50||24|-29||||
+NWire_Pin|pin@51||39|-18||||
+NWire_Pin|pin@52||43|-22||||
+NWire_Pin|pin@53||43|-31||||
+NWire_Pin|pin@54||43|-35||||
+NWire_Pin|pin@55||-3.5|-20||||
+NWire_Pin|pin@56||-5.5|-29||||
+Ngeneric:Invisible-Pin|pin@57||-21.5|5.5|||||ART_message(D3G2;)S[selects between,"1 = olc, 0 = ilc"]
+NWire_Pin|pin@59||-30|46||||
+NWire_Pin|pin@60||-30|-35||||
+NWire_Pin|pin@61||-8.5|-35||||
+NWire_Pin|pin@62||0|24||||
+NWire_Pin|pin@63||-6|26||||
+NWire_Pin|pin@64||42|46||||
+NWire_Pin|pin@65||-8.5|-27||||
+NWire_Pin|pin@66||-22|-27||||
+IdriversL:predDri20wMC;1{ic}|predDri2@1||31|-29|XY||D5G4;
+IdriversL:predDri20wMC;1{ic}|predDri2@2||31|-20|XY||D5G4;
+IdriversL:predORdri20wMC;2{ic}|predORdr@1||-15.5|46|X||D5G4;
+IdriversL:sucANDdri20;1{ic}|sucANDdr@2||15|25|||D5G4;
+IdriversL:sucANDdri20;1{ic}|sucANDdr@3||9|7|Y||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@9||-18|-35|||D0G4;|ATTR_L(D5G1;PUD)D140.59999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@10||-1|26|X||D0G4;|ATTR_L(D5G1;PUD)D127.4|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@11||5|24|X||D0G4;|ATTR_L(D5G1;PUD)D127.4|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@12||36|25|X||D0G4;|ATTR_L(D5G1;PUD)D127.4|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@13||10|-29|||D0G4;|ATTR_L(D5G1;PUD)D140.59999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@14||5|-20|||D0G4;|ATTR_L(D5G1;PUD)D140.59999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|do[ilc]|D5G2;||2700|pin@50||24|-29|pin@37||24|25
+Awire|mc|D5G2;||900|pin@48||-6|44|pin@49||-6|40
+Awire|net@57|||0|conn@5|y|3.5|51|pin@9||-4|51
+Awire|net@58|||0|wire90@9|a|-20.5|-35|inv@5|out|-22.5|-35
+Awire|net@59|||0|predORdr@1|pred|-18.5|46|pin@59||-30|46
+Awire|net@60|||0|wire90@11|b|2.5|24|pin@62||0|24
+Awire|net@61|||1800|sucANDdr@2|succ|20|25|pin@37||24|25
+Awire|net@62|||0|pin@36||41|25|wire90@12|a|38.5|25
+Awire|net@63|||0|wire90@12|b|33.5|25|inv@7|out|32|25
+Awire|net@64|||1800|wire90@10|a|1.5|26|sucANDdr@2|inB|10|26
+Awire|net@65|||900|ctrAND2i@1|inB|41|28|pin@36||41|25
+Awire|net@66|||0|sucANDdr@2|inA|10|24|wire90@11|a|7.5|24
+Awire|net@67|||900|pin@64||42|46|ctrAND2i@1|out|42|40
+Awire|net@68|||0|inv@7|in|27|25|pin@37||24|25
+Awire|net@69|||1800|conn@7|y|-11|8|pin@38||0|8
+Awire|net@70|||0|inv@5|in|-27.5|-35|pin@60||-30|-35
+Awire|net@71|||2700|pin@38||0|8|inv@6|in|0|11.5
+Awire|net@72|||900|pin@39||-6|6|ctrAND3i@1|out|-6|-2
+Awire|net@73|||0|sucANDdr@3|inB|4|6|pin@39||-6|6
+Awire|net@74|||1800|sucANDdr@3|succ|14|7|pin@40||18|7
+Awire|net@75|||0|sucANDdr@3|inA|4|8|pin@38||0|8
+Awire|net@76|||0|pin@41||18|-20|wire90@14|b|7.5|-20
+Awire|net@77|||0|pin@42||39|-27|predDri2@1|mc|34|-27
+Awire|net@78|||900|pin@44||-6|51|pin@45||-6|48
+Awire|net@79|||0|pin@45||-6|48|predORdr@1|in|-12.5|48
+Awire|net@80|||1800|predORdr@1|in_1|-12.5|46|pin@64||42|46
+Awire|net@81|||0|pin@61||-8.5|-35|wire90@9|b|-15.5|-35
+Awire|net@85|||1800|predORdr@1|mc|-12.5|44|pin@48||-6|44
+Awire|net@86|||1800|pin@61||-8.5|-35|pin@54||43|-35
+Awire|net@87|||0|predDri2@1|pred|28|-29|pin@50||24|-29
+Awire|net@88|||0|predDri2@2|pred|28|-20|pin@41||18|-20
+Awire|net@89|||1800|predDri2@2|mc|34|-18|pin@51||39|-18
+Awire|net@90|||1800|predDri2@2|in|34|-22|pin@52||43|-22
+Awire|net@91|||1800|predDri2@1|in|34|-31|pin@53||43|-31
+Awire|net@92|||2700|pin@65||-8.5|-27|ctrAND3i@1|inC|-8.5|-14
+Awire|net@93|||2700|pin@53||43|-31|pin@52||43|-22
+Awire|net@94|||900|pin@52||43|-22|pin@54||43|-35
+Awire|net@96|||0|pin@50||24|-29|wire90@13|b|12.5|-29
+Awire|net@97|||0|wire90@14|a|2.5|-20|pin@55||-3.5|-20
+Awire|net@98|||0|wire90@13|a|7.5|-29|pin@56||-5.5|-29
+Awire|net@99|||900|ctrAND3i@1|inA|-3.5|-14|pin@55||-3.5|-20
+Awire|net@100|||900|ctrAND3i@1|inB|-5.5|-14|pin@56||-5.5|-29
+Awire|net@101|||2700|pin@42||39|-27|pin@51||39|-18
+Awire|net@105|||900|ctrAND2i@1|inA|43|28|pin@53||43|-31
+Awire|net@106|||2700|inv@6|out|0|16.5|pin@62||0|24
+Awire|net@107|||0|wire90@10|b|-3.5|26|pin@63||-6|26
+Awire|net@108|||2700|pin@64||42|46|conn@6|a|42|50.5
+Awire|net@109|||900|pin@63||-6|26|pin@39||-6|6
+Awire|net@110|||0|pin@9||-4|51|pin@44||-6|51
+Awire|net@111|||1800|conn@3|y|-35|46|pin@59||-30|46
+Awire|net@112|||900|pin@59||-30|46|pin@60||-30|-35
+Awire|net@113|||2700|conn@9|y|39|-40|pin@42||39|-27
+Awire|net@115|||1800|pin@40||18|7|conn@4|a|29|7
+Awire|net@116|||900|pin@40||18|7|pin@41||18|-20
+Awire|net@117|||1800|pin@54||43|-35|conn@10|a|45|-35
+Awire|net@118|||2700|pin@61||-8.5|-35|pin@65||-8.5|-27
+Awire|net@119|||1800|invI@1|in|-12.5|-27|pin@65||-8.5|-27
+Awire|net@120|||900|conn@11|a|-22|-23.5|pin@66||-22|-27
+Awire|net@121|||1800|pin@66||-22|-27|invI@1|out|-17.5|-27
+EDvoid||D4G2;|conn@7|a|I
+Edo[Ld]||D4G2;|conn@3|a|I
+Eilc[load_1]|do[zz]|D6G2;|conn@4|y|O
+Edo[Ld_1]|fire[zz]|D4G2;|conn@5|a|I
+Eilc[load_1]@406197795|ilc[load]|D6G2;|conn@6|y|O
+Emc||D4G2;|conn@9|a|I
+Eilc[load_2]|not[Ld]|D6G2;|conn@10|y|O
+Enot[Ld_1]|s[1]|D6G2;|conn@11|y|O
+X
+
+# Cell olcControlB;1{ic}
+ColcControlB;1{ic}||artwork|1240288115267|1240289795726|E
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Nschematic:Bus_Pin|pin@0||-5|1|-1|-1||
+Nschematic:Bus_Pin|pin@2||3|3|-1|-1||
+Nschematic:Bus_Pin|pin@4||-3|-3|-1|-1||
+Nschematic:Bus_Pin|pin@6||-3|3|-1|-1||
+NPin|pin@8||-4|-2|1|1||
+NPin|pin@9||4|-2|1|1||
+NPin|pin@10||4|2|1|1||
+NPin|pin@11||-4|2|1|1||
+NPin|pin@12||-3|2|1|1||
+NPin|pin@13||-3|3|1|1||
+NPin|pin@14||-4|1|1|1||
+NPin|pin@15||-5|1|1|1||
+NPin|pin@16||-3|-2|1|1||
+NPin|pin@17||-3|-3|1|1||
+NPin|pin@18||3|2|1|1||
+NPin|pin@19||3|3|1|1||
+Ngeneric:Invisible-Pin|pin@20||0|0|||||ART_message(D5G2;)SolcB
+Nschematic:Bus_Pin|pin@21||5|0|-1|-1||
+NPin|pin@23||4|0|1|1||
+NPin|pin@24||5|0|1|1||
+Nschematic:Bus_Pin|pin@25||-5|-1|-1|-1||
+NPin|pin@27||-4|-1|1|1||
+NPin|pin@28||-5|-1|1|1||
+AThicker|net@4|||FS2700|pin@12||-3|2|pin@13||-3|3
+AThicker|net@5|||FS900|pin@11||-4|2|pin@14||-4|1
+AThicker|net@6|||FS0|pin@14||-4|1|pin@15||-5|1
+AThicker|net@7|||FS1800|pin@8||-4|-2|pin@16||-3|-2
+AThicker|net@8|||FS900|pin@16||-3|-2|pin@17||-3|-3
+AThicker|net@9|||FS0|pin@10||4|2|pin@18||3|2
+AThicker|net@10|||FS2700|pin@18||3|2|pin@19||3|3
+AThicker|net@11|||FS1800|pin@16||-3|-2|pin@9||4|-2
+AThicker|net@12|||FS2700|pin@23||4|0|pin@10||4|2
+AThicker|net@13|||FS0|pin@18||3|2|pin@12||-3|2
+AThicker|net@14|||FS900|pin@14||-4|1|pin@27||-4|-1
+AThicker|net@15|||FS0|pin@12||-3|2|pin@11||-4|2
+AThicker|net@17|||FS2700|pin@9||4|-2|pin@23||4|0
+AThicker|net@18|||FS1800|pin@23||4|0|pin@24||5|0
+AThicker|net@20|||FS900|pin@27||-4|-1|pin@8||-4|-2
+AThicker|net@21|||FS0|pin@27||-4|-1|pin@28||-5|-1
+Emc_1|do[reD]|D5G2;|pin@25||I
+Edo[zz]||D5G2;|pin@0||I
+Efire[zz]||D5G2;|pin@2||O
+Emc||D5G2;|pin@21||I
+Enot[Ld]||D5G2;|pin@4||I
+Eolc[load]||D5G2;|pin@6||O
+X
+
+# Cell olcControlB;1{sch}
+ColcControlB;1{sch}||schematic|1240279626137|1240289776383|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||28|23.5|||XR|
+NOff-Page|conn@1||-26|24.5|||XR|
+NOff-Page|conn@2||-51|-7|||Y|
+NOff-Page|conn@3||-42|-31|||Y|
+NOff-Page|conn@4||34.5|13.5|||XYR|
+NOff-Page|conn@5||4|17|||XYRR|
+IcentersJ:ctrAND2in100LT;1{ic}|ctrAND2i@2||-26|1|R||D5G4;
+IcentersJ:ctrAND2in30;1{ic}|ctrAND2i@3||28|4|R||D5G4;
+IredFive:inv;1{ic}|inv@3||-42|-7|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nor2_sy;1{ic}|nor2_sy@1||14|-6|XRR||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(T)I-1
+IolcControlB;1{ic}|olcContr@0||31|37|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||0.5|42|||||ART_message(D5G5;)SolcControlB
+Ngeneric:Invisible-Pin|pin@1||0.5|36|||||ART_message(D5G3;)Sies 20 April 2009
+NWire_Pin|pin@36||-26|17||||
+Ngeneric:Invisible-Pin|pin@38||-23.5|19.5|||||ART_message(D3G2;)S[this stage fires,for load OLC.]
+NWire_Pin|pin@40||-25|-7||||
+NWire_Pin|pin@41||22|15||||
+NWire_Pin|pin@42||22|11||||
+NWire_Pin|pin@43||10|17|||X|
+NWire_Pin|pin@44||27|-6||||
+NWire_Pin|pin@45||-8|-7||||
+NWire_Pin|pin@46||10|-5||||
+NWire_Pin|pin@47||28|19||||
+NWire_Pin|pin@50||29|-31||||
+NWire_Pin|pin@51||-8|17||||
+NWire_Pin|pin@53||-8|-21||||
+NWire_Pin|pin@54||-27|-23||||
+NWire_Pin|pin@55||-27|-27||||
+NWire_Pin|pin@56||-27|-19||||
+NWire_Pin|pin@57||-27|-7||||
+IdriversL:predDri20wMC;1{ic}|predDri2@3||16|17|X||D5G4;
+IdriversL:predDri20wMC;1{ic}|predDri2@4||-16|-21|||D5G4;
+IdriversL:sucDri20;1{ic}|sucDri20@1||-17|17|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@6||22|-6|||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@7||-17.5|-7|||D0G4;|ATTR_L(D5G1;PUD)D431.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@8||-33.5|-7|||D0G4;|ATTR_L(D5G1;PUD)D431.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|do[2]|D5G2;||900|pin@51||-8|17|pin@45||-8|-7
+Awire|mc|D5G2;||900|pin@41||22|15|pin@42||22|11
+Awire|mc|D5G2;||900|pin@54||-27|-23|pin@55||-27|-27
+Awire|net@53|||1800|pin@36||-26|17|sucDri20@1|in|-21|17
+Awire|net@54|||900|pin@36||-26|17|ctrAND2i@2|out|-26|7
+Awire|net@56|||2700|pin@40||-25|-7|ctrAND2i@2|inA|-25|-5
+Awire|net@57|||0|predDri2@3|pred|13|17|pin@43||10|17
+Awire|net@58|||1800|predDri2@3|mc|19|15|pin@41||22|15
+Awire|net@59|||1800|wire90@6|b|24.5|-6|pin@44||27|-6
+Awire|net@60|||2700|pin@44||27|-6|ctrAND2i@3|inB|27|-2
+Awire|net@61|||0|pin@51||-8|17|sucDri20@1|succ|-13|17
+Awire|net@62|||0|wire90@7|a|-20|-7|pin@40||-25|-7
+Awire|net@63|||1800|pin@45||-8|-7|nor2_sy@1|inb|11.5|-7
+Awire|net@64|||0|nor2_sy@1|ina|11.5|-5|pin@46||10|-5
+Awire|net@65|||1800|predDri2@3|in|19|19|pin@47||28|19
+Awire|net@66|||0|wire90@6|a|19.5|-6|nor2_sy@1|out|16.5|-6
+Awire|net@67|||2700|ctrAND2i@3|out|28|10|pin@47||28|19
+Awire|net@68|||2700|pin@50||29|-31|ctrAND2i@3|inA|29|-2
+Awire|net@69|||1800|wire90@7|b|-15|-7|pin@45||-8|-7
+Awire|net@70|||0|predDri2@4|in|-19|-19|pin@56||-27|-19
+Awire|net@72|||2700|pin@53||-8|-21|pin@45||-8|-7
+Awire|net@74|||1800|predDri2@4|pred|-13|-21|pin@53||-8|-21
+Awire|net@75|||0|predDri2@4|mc|-19|-23|pin@54||-27|-23
+Awire|net@80|||900|conn@1|a|-26|22.5|pin@36||-26|17
+Awire|net@81|||0|wire90@8|a|-36|-7|inv@3|out|-39.5|-7
+Awire|net@82|||900|pin@57||-27|-7|pin@56||-27|-19
+Awire|net@83|||900|ctrAND2i@2|inB|-27|-5|pin@57||-27|-7
+Awire|net@84|||1800|wire90@8|b|-31|-7|pin@57||-27|-7
+Awire|net@87|||1800|conn@2|y|-49|-7|inv@3|in|-44.5|-7
+Awire|net@90|||900|conn@0|a|28|21.5|pin@47||28|19
+Awire|net@92|||0|pin@50||29|-31|conn@3|y|-40|-31
+Awire|net@93|||1800|conn@5|y|6|17|pin@43||10|17
+Awire|net@94|||900|pin@43||10|17|pin@46||10|-5
+Emc_1|do[reD]|D4G2;|conn@5|a|I
+ErD|do[zz]|D4G2;|conn@2|a|I
+Efire[zz]||D6G2;|conn@0|y|O
+Emc||D4G2;|conn@4|a|I
+Edo[zz_1]|not[Ld]|D4G2;|conn@3|a|I
+Eolc[load]||D6G2;|conn@1|y|O
+X
+
+# Cell olcControlC;1{ic}
+ColcControlC;1{ic}||artwork|1240287917947|1240288704951|E
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Nschematic:Bus_Pin|pin@0||-5|1|-1|-1||
+Nschematic:Bus_Pin|pin@2||-3|3|-1|-1||
+Nschematic:Bus_Pin|pin@4||5|0|-1|-1||
+Nschematic:Bus_Pin|pin@6||3|3|-1|-1||
+Nschematic:Bus_Pin|pin@8||3|-3|-1|-1||
+NPin|pin@10||-4|-2|1|1||
+NPin|pin@11||4|-2|1|1||
+NPin|pin@12||4|2|1|1||
+NPin|pin@13||-4|2|1|1||
+NPin|pin@14||-3|2|1|1||
+NPin|pin@15||-3|3|1|1||
+NPin|pin@16||-4|1|1|1||
+NPin|pin@17||-5|1|1|1||
+NPin|pin@18||3|-2|1|1||
+NPin|pin@19||3|-3|1|1||
+NPin|pin@20||3|2|1|1||
+NPin|pin@21||3|3|1|1||
+Ngeneric:Invisible-Pin|pin@22||0|0|||||ART_message(D5G2;)SolcC
+NPin|pin@23||4|0|1|1||
+NPin|pin@24||5|0|1|1||
+AThicker|net@5|||FS1800|pin@18||3|-2|pin@11||4|-2
+AThicker|net@6|||FS2700|pin@23||4|0|pin@12||4|2
+AThicker|net@7|||FS0|pin@20||3|2|pin@14||-3|2
+AThicker|net@8|||FS900|pin@16||-4|1|pin@10||-4|-2
+AThicker|net@9|||FS0|pin@14||-3|2|pin@13||-4|2
+AThicker|net@10|||FS2700|pin@14||-3|2|pin@15||-3|3
+AThicker|net@11|||FS900|pin@13||-4|2|pin@16||-4|1
+AThicker|net@12|||FS0|pin@16||-4|1|pin@17||-5|1
+AThicker|net@13|||FS1800|pin@10||-4|-2|pin@18||3|-2
+AThicker|net@14|||FS900|pin@18||3|-2|pin@19||3|-3
+AThicker|net@15|||FS0|pin@12||4|2|pin@20||3|2
+AThicker|net@16|||FS2700|pin@20||3|2|pin@21||3|3
+AThicker|net@17|||FS2700|pin@11||4|-2|pin@23||4|0
+AThicker|net@18|||FS1800|pin@23||4|0|pin@24||5|0
+Edo[Co]||D5G2;|pin@0||I
+Efire[Co]||D5G2;|pin@2||O
+Emc||D5G2;|pin@4||I
+Eolc[dec]||D5G2;|pin@6||O
+Eolc[zero]||D5G2;|pin@8||I
+X
+
+# Cell olcControlC;1{lay}
+ColcControlC;1{lay}||cmos90|1232819186778|1240290211520|I|ATTR_NCC(D5G3;NTX-6;Y140;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1239553775974
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-1-Metal-2-Con|contact@0||-61.5|-100||||
+NX-Metal-1-Metal-2-Con|contact@1||-84|-100||||
+NX-Metal-1-Metal-2-Con|contact@2||37|-44||||
+NX-Metal-1-Metal-2-Con|contact@3||-101|-44||||
+NX-Metal-1-Metal-2-Con|contact@4||11|-44||||
+NX-Metal-1-Metal-2-Con|contact@6||-44.5|-112||||
+NX-Metal-1-Metal-2-Con|contact@7||-86|-6||||
+NX-Metal-1-Metal-2-Con|contact@8||22|-6||||
+NX-Metal-1-Metal-2-Con|contact@9||81|-6||||
+NX-Metal-1-Metal-2-Con|contact@10||25|-112||||
+IcentersJ:ctrAND1in30;1{lay}|ctrAND1i@0||-14|-72|||D5G4;
+IcentersJ:ctrAND1in30;1{lay}|ctrAND1i@2||88|-72|||D5G4;
+IcentersJ:ctrAND2in100;2{lay}|ctrAND2i@0||-33|72|X||D5G4;
+IdriversJ:driveConnecter;3{lay}|driveCon@0||-94|35|Y||D5G4;
+Igates1inM:inv10D;1{lay}|inv10D@0||64|72|XY||D5G4;
+Igates2inM:nor05sym;2{lay}|nor05sym@0||-56|-72|||D5G4;
+NMetal-2-Pin|pin@68||-109.5|6.7||||
+NMetal-1-Pin|pin@71||65.5|8||||
+NMetal-1-Pin|pin@74||113|15||||
+NMetal-1-Pin|pin@76||96|15||||
+NMetal-2-Pin|pin@79||-75|-100||||
+NMetal-2-Pin|pin@89||-74|-44||||
+NMetal-2-Pin|pin@91||-26|-112||||
+NMetal-1-Pin|pin@97||79|97||||
+NMetal-1-Pin|pin@102||-86|-68||||
+NMetal-1-Pin|pin@105||-56|-57||||
+NMetal-1-Pin|pin@106||58|8||||
+NMetal-1-Pin|pin@107||53|65||||
+NMetal-2-Pin|pin@112||0|-6||||
+NMetal-1-Pin|pin@113||-44.5|-91||||
+NMetal-1-Pin|pin@114||25|-107||||
+NMetal-1-Pin|pin@116||20|-107||||
+IdriversL:predDri20wMC;3{lay}|predDri2@1||37|-72|Y||D5G4;
+IdriversL:predDri20wMC;3{lay}|predDri2@2||-101|-72|XY||D5G4;
+IdriversL:predDri20wMC;3{lay}|predDri2@3||96|72|||D5G4;
+IwiresL:select15;1{lay}|select15@0||55|72|||D5G4;
+IwiresL:wellContacts13;1{lay}|wellCont@0||-73|-72|||D5G4;
+Ametal-1|net@250|||S900|ctrAND2i@0|out|-110|88|driveCon@0|out|-110|35
+Ametal-2|net@251||1.2|S0|driveCon@0|take|-102|6.7|pin@68||-109.5|6.7
+Ametal-1|net@263|||S2700|ctrAND1i@2|in[1]|65.5|-57|pin@71||65.5|8
+Ametal-1|net@267|||S0|pin@71||65.5|8|pin@106||58|8
+Ametal-1|net@268|||S2700|ctrAND1i@2|out|113|-72|pin@74||113|15
+Ametal-1|net@271|||S0|pin@74||113|15|pin@76||96|15
+Ametal-1|net@272|||S2700|pin@76||96|15|predDri2@3|in|96|50
+Ametal-2|net@282|||S1800|contact@1||-84|-100|pin@79||-75|-100
+Ametal-1|net@283||0.4|S900|predDri2@2|pred|-84|-88|contact@1||-84|-100
+Ametal-2|net@284|||S1800|pin@89||-74|-44|contact@4||11|-44
+Ametal-1|net@285|||S2700|predDri2@1|in|37|-50|contact@2||37|-44
+Ametal-1|net@287|||S2700|predDri2@2|in|-101|-50|contact@3||-101|-44
+Ametal-2|net@288|||S1800|contact@4||11|-44|contact@2||37|-44
+Ametal-1|net@289|||S2700|ctrAND1i@0|out|11|-72|contact@4||11|-44
+Ametal-2|net@296|||S0|ctrAND1i@2|gnd_1|58.5|-72|predDri2@1|gnd_1|58.5|-72
+Ametal-2|net@297|||S0|ctrAND1i@2|vdd_3|58.5|-122|predDri2@1|vdd_2|58.5|-122
+Ametal-2|net@298|||S0|ctrAND1i@2|vdd_2|58.5|-22|predDri2@1|vdd_3|58.5|-22
+Ametal-2|net@299|||S0|predDri2@1|gnd|15.5|-72|ctrAND1i@0|gnd_2|15.5|-72
+Ametal-2|net@300|||S0|predDri2@1|vdd|15.5|-122|ctrAND1i@0|vdd_5|15.5|-122
+Ametal-2|net@301|||S0|predDri2@1|vdd_1|15.5|-22|ctrAND1i@0|vdd_4|15.5|-22
+Ametal-1|net@307|||S2700|predDri2@2|mc|-86|-65|contact@7||-86|-6
+Ametal-1|net@309|||S2700|predDri2@1|mc|22|-65|contact@8||22|-6
+Ametal-2|net@310|||S1800|contact@8||22|-6|contact@9||81|-6
+Ametal-1|net@311|||S900|predDri2@3|mc|81|65|contact@9||81|-6
+Ametal-2|net@312|||S1800|pin@79||-75|-100|contact@0||-61.5|-100
+Ametal-2|net@324|||S1800|contact@3||-101|-44|pin@89||-74|-44
+Ametal-2|net@326|||S0|pin@91||-26|-112|contact@6||-44.5|-112
+Ametal-2|net@334||6.2|S0|inv10D@0|gnd_1|55.5|72|ctrAND2i@0|gnd|54|72
+Ametal-2|net@335||6.2|S0|inv10D@0|vdd_2|55.5|22|ctrAND2i@0|vdd_1|54|22
+Ametal-2|net@336||6.2|S0|inv10D@0|vdd_3|55.5|122|ctrAND2i@0|vdd|54|122
+Ametal-2|net@337|||S1800|inv10D@0|gnd|72.5|72|predDri2@3|gnd|74.5|72
+Ametal-2|net@338|||S1800|inv10D@0|vdd_1|72.5|122|predDri2@3|vdd|74.5|122
+Ametal-2|net@339|||S1800|inv10D@0|vdd|72.5|22|predDri2@3|vdd_1|74.5|22
+Ametal-1|net@340|||S2700|predDri2@3|pred|79|88|pin@97||79|97
+Ametal-1|net@341|||S0|pin@97||79|97|inv10D@0|in|64|97
+Ametal-1|net@350|||S900|predDri2@2|mc|-86|-65|pin@102||-86|-68
+Ametal-2|net@353|||S0|pin@112||0|-6|contact@7||-86|-6
+Ametal-2|net@354|||S0|wellCont@0|gnd_1|-68.5|-72|nor05sym@0|gnd|-68.5|-72
+Ametal-2|net@355|||S0|wellCont@0|vdd_2|-68.5|-122|nor05sym@0|vdd_1|-68.5|-122
+Ametal-2|net@356|||S0|wellCont@0|vdd_3|-68.5|-22|nor05sym@0|vdd|-68.5|-22
+Ametal-2|net@357|||S0|wellCont@0|gnd|-77.5|-72|predDri2@2|gnd|-79.5|-72
+Ametal-2|net@358|||S0|wellCont@0|vdd|-77.5|-122|predDri2@2|vdd|-79.5|-122
+Ametal-2|net@359|||S0|wellCont@0|vdd_1|-77.5|-22|predDri2@2|vdd_1|-79.5|-22
+Ametal-2|net@360||6.2|S0|nor05sym@0|vdd_3|-43.5|-122|ctrAND1i@0|vdd_3|-43.5|-122
+Ametal-2|net@361||6.2|S1800|ctrAND1i@0|gnd_1|-43.5|-72|nor05sym@0|gnd_1|-43.5|-72
+Ametal-2|net@362||6.2|S1800|ctrAND1i@0|vdd_2|-43.5|-22|nor05sym@0|vdd_2|-43.5|-22
+Ametal-1|net@364|||S2700|contact@0||-61.5|-100|nor05sym@0|inA|-61.5|-91
+Ametal-1|net@366|||S0|ctrAND1i@0|in[1]|-36.5|-57|pin@105||-56|-57
+Ametal-1|net@367|||S2700|pin@105||-56|-57|nor05sym@0|out_1|-56|-34.4
+Ametal-1|net@369|||S2700|pin@106||58|8|inv10D@0|out|58|65
+Ametal-1|net@371|||S0|inv10D@0|out|58|65|pin@107||53|65
+Ametal-1|net@372|||S2700|pin@107||53|65|ctrAND2i@0|inB|53|81
+Ametal-2|net@383|||S0|contact@8||22|-6|pin@112||0|-6
+Ametal-1|net@384|||S2700|contact@6||-44.5|-112|pin@113||-44.5|-91
+Ametal-1|net@385|||S0|pin@113||-44.5|-91|nor05sym@0|inB|-50.5|-91
+Ametal-2|net@391|||S1800|pin@91||-26|-112|contact@10||25|-112
+Ametal-1|net@392|||S2700|contact@10||25|-112|pin@114||25|-107
+Ametal-1|net@394|||S0|pin@114||25|-107|pin@116||20|-107
+Ametal-1|net@395|||S2700|pin@116||20|-107|predDri2@1|pred|20|-88
+Edo[2]||D5G4;|pin@79||I
+Edo[Co]||D5G4;|predDri2@3|pred|O
+Edo[reD]||D5G4;|pin@91||O
+Efire[Co]||D5G4;|predDri2@3|in|I
+Efire[zz]||D5G4;|pin@89||O
+Egnd||D5G4;|ctrAND2i@0|gnd_1|G
+Egnd_2||D5G4;|predDri2@3|gnd_1|G
+Egnd_3||D5G4;|predDri2@2|gnd_1|G
+Egnd_4||D5G4;|ctrAND1i@2|gnd_2|G
+Emc||D5G4;|pin@112||I
+Emc_1||D5G4;|predDri2@3|mc_1|I
+Eolc[dec]||D5G4;|pin@68||O
+Eolc[zero]||D5G4;|ctrAND2i@0|inA|I
+Evdd||D5G4;|ctrAND2i@0|vdd_2|P
+Evdd_3||D5G4;|ctrAND2i@0|vdd_3|P
+Evdd_4||D5G4;|predDri2@3|vdd_2|P
+Evdd_5||D5G4;|predDri2@3|vdd_3|P
+Evdd_6||D5G4;|predDri2@2|vdd_2|P
+Evdd_7||D5G4;|predDri2@2|vdd_3|P
+Evdd_8||D5G4;|ctrAND1i@2|vdd_4|P
+Evdd_9||D5G4;|ctrAND1i@2|vdd_5|P
+X
+
+# Cell olcControlC;1{sch}
+ColcControlC;1{sch}||schematic|1230935566337|1240287927365|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@6||-1.5|28.5|||XYR|
+NOff-Page|conn@7||-14.5|-1.5|||Y|
+NOff-Page|conn@9||8|25|||XR|
+NOff-Page|conn@17||30.5|-16.5|||XY|
+NOff-Page|conn@18||20|17.5|||XR|
+IcentersJ:ctrAND1in30;1{ic}|ctrAND1i@3||8|-3.5|R||D5G4;
+IcentersJ:ctrAND2in100;1{ic}|ctrAND2i@0||20|-3.5|R||D5G4;
+IredFive:inv;1{ic}|inv@14||-4.5|-16.5|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IolcControlC;1{ic}|olcContr@0||36.5|60|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||3|50.5|||||ART_message(D5G5;)SolcControlC
+Ngeneric:Invisible-Pin|pin@73||11|33|||||ART_message(D3G2;)S[this stage fires,for count OLC.]
+NWire_Pin|pin@155||2|11.5||||
+NWire_Pin|pin@156||2|8.5||||
+NWire_Pin|pin@159||-10|13.5||||
+NWire_Pin|pin@160||-10|-16.5||||
+NWire_Pin|pin@161||8|-16.5||||
+NWire_Pin|pin@178||8|15.5||||
+NWire_Pin|pin@241||-10|-1.5||||
+NWire_Pin|pin@242||19|-16.5||||
+NWire_Pin|pin@246||21|-16.5||||
+Ngeneric:Invisible-Pin|pin@248||3|44.5|||||ART_message(D5G3;)Sies 20 April 2009
+IdriversL:predDri20wMC;1{ic}|predDri2@2||-4|13.5|X||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@19||3.5|-16.5|||D0G4;|ATTR_L(D5G1;PUD)D142.59999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|mc|D5G2;||900|pin@155||2|11.5|pin@156||2|8.5
+Awire|net@378|||1800|predDri2@2|mc|-1|11.5|pin@155||2|11.5
+Awire|net@383|||0|predDri2@2|pred|-7|13.5|pin@159||-10|13.5
+Awire|net@385|||1800|wire90@19|b|6|-16.5|pin@161||8|-16.5
+Awire|net@386|||0|wire90@19|a|1|-16.5|inv@14|out|-2|-16.5
+Awire|net@388|||0|inv@14|in|-7|-16.5|pin@160||-10|-16.5
+Awire|net@401|||900|ctrAND1i@3|in|8|-9.5|pin@161||8|-16.5
+Awire|net@415|||1800|predDri2@2|in|-1|15.5|pin@178||8|15.5
+Awire|net@523|||900|pin@178||8|15.5|ctrAND1i@3|out|8|2.5
+Awire|net@551|||900|pin@241||-10|-1.5|pin@160||-10|-16.5
+Awire|net@570|||900|pin@159||-10|13.5|pin@241||-10|-1.5
+Awire|net@571|||1800|conn@7|y|-12.5|-1.5|pin@241||-10|-1.5
+Awire|net@573|||900|ctrAND2i@0|inB|19|-9.5|pin@242||19|-16.5
+Awire|net@578|||0|pin@242||19|-16.5|pin@161||8|-16.5
+Awire|net@581|||0|conn@17|y|28.5|-16.5|pin@246||21|-16.5
+Awire|net@584|||2700|pin@246||21|-16.5|ctrAND2i@0|inA|21|-9.5
+Awire|net@590|||2700|pin@178||8|15.5|conn@9|a|8|23
+Awire|net@592|||900|conn@18|a|20|15.5|ctrAND2i@0|out|20|2.5
+Edo[Co]||D4G2;|conn@7|a|I
+Efire[Co]||D6G2;|conn@9|y|O
+Emc||D4G2;|conn@6|a|I
+Eolc[dec]||D6G2;|conn@18|y|O
+Eolc[zero]||D4G2;|conn@17|a|I
+X
+
+# Cell olcControlD;1{ic}
+ColcControlD;1{ic}||artwork|1240288689648|1240289079801|E
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Nschematic:Bus_Pin|pin@0||3|-3|-1|-1||
+Nschematic:Bus_Pin|pin@2||-3|-3|-1|-1||
+Nschematic:Bus_Pin|pin@4||-3|3|-1|-1|R|
+Ngeneric:Invisible-Pin|pin@5||-3|2|1|1|R|
+Nschematic:Bus_Pin|pin@6||0|-4|-1|-1|R|
+Ngeneric:Invisible-Pin|pin@7||0|-2|1|1|R|
+Nschematic:Bus_Pin|pin@8||3|4|-1|-1|R|
+Ngeneric:Invisible-Pin|pin@9||3|2|1|1|R|
+NPin|pin@10||-4|-2|1|1||
+NPin|pin@11||4|-2|1|1||
+NPin|pin@12||4|2|1|1||
+NPin|pin@13||-4|2|1|1||
+NPin|pin@18||3|-2|1|1||
+NPin|pin@19||3|-3|1|1||
+Ngeneric:Invisible-Pin|pin@22||0|0|||||ART_message(D5G2;)SolcD
+NPin|pin@25||-3|-2|1|1||
+NPin|pin@26||-3|-3|1|1||
+Aschematic:bus|net@2||-0.5|IJ2700|pin@5||-3|2|pin@4||-3|3
+Aschematic:bus|net@3||-0.5|IJ900|pin@7||0|-2|pin@6||0|-4
+Aschematic:bus|net@4||-0.5|IJ2700|pin@9||3|2|pin@8||3|4
+AThicker|net@8|||FS1800|pin@25||-3|-2|pin@18||3|-2
+AThicker|net@9|||FS900|pin@18||3|-2|pin@19||3|-3
+AThicker|net@14|||FS1800|pin@18||3|-2|pin@11||4|-2
+AThicker|net@20|||FS1800|pin@10||-4|-2|pin@25||-3|-2
+AThicker|net@21|||FS900|pin@25||-3|-2|pin@26||-3|-3
+AThicker|net@22|||FS900|pin@13||-4|2|pin@10||-4|-2
+AThicker|net@23|||FS2700|pin@11||4|-2|pin@12||4|2
+AThicker|net@24|||FS1800|pin@13||-4|2|pin@12||4|2
+Efire[Co]||D5G2;|pin@0||I
+Efire[zz]||D5G2;|pin@2||I
+Eflag[D][set,clr]||D5G2;|pin@4||O
+Eolc[zero,zoo]||D5G2;|pin@6||I
+Es[2,3]||D5G2;|pin@8||O
+X
+
+# Cell olcControlD;2{lay}
+ColcControlD;2{lay}||cmos90|1232819186778|1240290116497||ATTR_NCC(D5G3;NTX-6;Y140;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1239703888825
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-1-Metal-2-Con|contact@3||-70|-62||||
+NX-Metal-1-Metal-2-Con|contact@4||25|-62||||
+NX-Metal-1-Metal-2-Con|contact@5||-11.5|-6||||
+NX-Metal-1-Metal-2-Con|contact@6||-62|-6||||
+NX-Metal-1-Metal-2-Con|contact@7||-16.5|44|||Y|
+NX-Metal-1-Metal-2-Con|contact@8||-68|44|||Y|
+NX-Metal-1-Metal-2-Con|contact@10||-16.5|-44|||Y|
+NX-Metal-1-Metal-2-Con|contact@11||-68|-44|||Y|
+NX-Metal-1-Metal-2-Con|contact@21||56|88||||
+NX-Metal-1-Metal-2-Con|contact@22||16.5|88||||
+NX-Metal-1-Metal-2-Con|contact@23||39|-56||||
+NX-Metal-1-Metal-2-Con|contact@24||56|-56||||
+NX-Metal-1-Metal-2-Con|contact@25||70.5|82||||
+NX-Metal-1-Metal-2-Con|contact@26||70.5|-50||||
+Igates1inM:inv05;1{lay}|inv05@1||-42.5|72|||D5G4;
+Igates1inM:inv05;1{lay}|inv05@4||-42.5|-72|Y||D5G4;
+Igates1inM:inv510;3{lay}|inv510@4||62|72|||D5G4;
+Igates1inM:inv510;3{lay}|inv510@5||62|-72|||D5G4;
+Igates2inM:nand5A;1{lay}|nand5A@0||-63|72|XY||D5G4;
+Igates2inM:nand5A;1{lay}|nand5A@1||-21.5|72|Y||D5G4;
+Igates2inM:nand5A;1{lay}|nand5A@2||-63|-72|X||D5G4;
+Igates2inM:nand5A;1{lay}|nand5A@3||-21.5|-72|||D5G4;
+NMetal-1-Pin|pin@0||-38|76.5|||Y|
+NMetal-1-Pin|pin@1||-35|76.5|||Y|
+NMetal-1-Pin|pin@3||-35|88|||Y|
+NMetal-1-Pin|pin@5||-27.5|88|||Y|
+NMetal-1-Pin|pin@6||-40.5|97|||Y|
+NMetal-1-Pin|pin@7||-38|-76||||
+NMetal-1-Pin|pin@8||-34|-76||||
+NMetal-1-Pin|pin@9||-34|-92||||
+NMetal-1-Pin|pin@11||-27.5|-92||||
+NMetal-1-Pin|pin@12||-40.5|-97||||
+NMetal-1-Pin|pin@15||9|83.9||||
+NMetal-1-Pin|pin@22||-11.5|-48||||
+NMetal-1-Pin|pin@28||9|-48||||
+NMetal-1-Pin|pin@29||-14.5|83.9||||
+NMetal-2-Pin|pin@49||-46.5|44|||Y|
+NMetal-1-Pin|pin@59||16.5|106||||
+NMetal-2-Pin|pin@60||34.5|88||||
+NMetal-1-Pin|pin@63||39|-38||||
+NMetal-2-Pin|pin@64||34.5|-56||||
+NMetal-1-Pin|pin@65||25|48||||
+NMetal-1-Pin|pin@66||42|48||||
+NMetal-1-Pin|pin@67||42|2||||
+NMetal-2-Pin|pin@70||-46.5|-44|||Y|
+NMetal-1-Pin|pin@75||-22.5|2||||
+NMetal-2-Pin|pin@77||56|82||||
+NMetal-2-Pin|pin@79||60|-50||||
+IdriversL:sucDri20or;1{lay}|sucDri20@0||24|-72|||D5G4;
+IdriversL:sucDri20or;1{lay}|sucDri20@1||24|72|||D5G4;
+IwiresL:wellContacts13;1{lay}|wellCont@0||-5.5|72|||D5G4;
+IwiresL:wellContacts13;1{lay}|wellCont@1||-5.5|-72|||D5G4;
+Ametal-1|net@8|||S2700|inv05@1|out[1]|-38|65|pin@0||-38|76.5
+Ametal-1|net@9|||S1800|pin@0||-38|76.5|pin@1||-35|76.5
+Ametal-1|net@10|||S2700|pin@1||-35|76.5|pin@3||-35|88
+Ametal-2|net@11|||S1800|inv05@1|gnd|-51.5|72|nand5A@0|gnd|-51.5|72
+Ametal-2|net@12|||S1800|inv05@1|vdd_1|-51.5|22|nand5A@0|vdd|-51.5|22
+Ametal-2|net@13|||S1800|inv05@1|vdd|-51.5|122|nand5A@0|vdd_1|-51.5|122
+Ametal-2|net@14|||S1800|inv05@1|gnd_1|-33.5|72|nand5A@1|gnd|-33|72
+Ametal-2|net@15|||S1800|inv05@1|vdd_3|-33.5|22|nand5A@1|vdd|-33|22
+Ametal-2|net@16|||S1800|inv05@1|vdd_2|-33.5|122|nand5A@1|vdd_1|-33|122
+Ametal-1|net@20|||S2700|pin@5||-27.5|88|nand5A@1|ina|-27.5|97
+Ametal-1|net@21|||S2700|inv05@1|in[1]|-40.5|87|pin@6||-40.5|97
+Ametal-1|net@22|||S0|pin@6||-40.5|97|nand5A@0|ina|-57|97
+Ametal-1|net@23|||S900|pin@8||-34|-76|pin@9||-34|-92
+Ametal-2|net@24|||S1800|inv05@4|gnd|-51.5|-72|nand5A@2|gnd|-51.5|-72
+Ametal-2|net@25|||S1800|inv05@4|vdd_1|-51.5|-22|nand5A@2|vdd|-51.5|-22
+Ametal-2|net@26|||S1800|inv05@4|vdd|-51.5|-122|nand5A@2|vdd_1|-51.5|-122
+Ametal-2|net@27|||S1800|inv05@4|gnd_1|-33.5|-72|nand5A@3|gnd|-33|-72
+Ametal-2|net@28|||S1800|inv05@4|vdd_3|-33.5|-22|nand5A@3|vdd|-33|-22
+Ametal-2|net@29|||S1800|inv05@4|vdd_2|-33.5|-122|nand5A@3|vdd_1|-33|-122
+Ametal-1|net@32|||S900|pin@11||-27.5|-92|nand5A@3|ina|-27.5|-97
+Ametal-1|net@33|||S900|inv05@4|in[1]|-40.5|-87|pin@12||-40.5|-97
+Ametal-1|net@34|||S0|pin@12||-40.5|-97|nand5A@2|ina|-57|-97
+Ametal-1|net@35|||S900|inv05@4|out[1]|-38|-65|pin@7||-38|-76
+Ametal-1|net@36|||S1800|pin@7||-38|-76|pin@8||-34|-76
+Ametal-1|net@39|||S1800|pin@3||-35|88|pin@5||-27.5|88
+Ametal-1|net@40|||S1800|pin@9||-34|-92|pin@11||-27.5|-92
+Ametal-1|net@42|||S2700|pin@15||9|83.9|sucDri20@1|inA|9|85
+Ametal-1|net@58|||S2700|nand5A@2|out|-70|-80.1|contact@3||-70|-62
+Ametal-1|net@62|||S2700|sucDri20@0|inB|25|-82|contact@4||25|-62
+Ametal-2|net@63|||S1800|contact@3||-70|-62|contact@4||25|-62
+Ametal-1|net@69|||S2700|pin@22||-11.5|-48|contact@5||-11.5|-6
+Ametal-2|net@71|||S1800|contact@6||-62|-6|contact@5||-11.5|-6
+Ametal-2|net@94|||S0|wellCont@0|gnd_1|-1|72|sucDri20@1|gnd|-1|72
+Ametal-2|net@95|||S0|wellCont@0|vdd_2|-1|22|sucDri20@1|vdd_1|-1|22
+Ametal-2|net@96|||S0|wellCont@0|vdd_3|-1|122|sucDri20@1|vdd|-1|122
+Ametal-2|net@102|||S1800|wellCont@1|gnd_1|-1|-72|sucDri20@0|gnd|-1|-72
+Ametal-2|net@103|||S1800|wellCont@1|vdd_2|-1|-122|sucDri20@0|vdd_1|-1|-122
+Ametal-2|net@104|||S1800|wellCont@1|vdd_3|-1|-22|sucDri20@0|vdd|-1|-22
+Ametal-1|net@107|||S900|pin@28||9|-48|sucDri20@0|inA|9|-59
+Ametal-1|net@108|||S1800|pin@22||-11.5|-48|pin@28||9|-48
+Ametal-1|net@111|||S2700|nand5A@1|inb|-16.5|43|contact@7||-16.5|44
+Ametal-2|net@112|||S1800|pin@49||-46.5|44|contact@7||-16.5|44
+Ametal-1|net@113|||S2700|nand5A@0|inb|-68|43|contact@8||-68|44
+Ametal-1|net@120|||S900|nand5A@3|inb|-16.5|-43|contact@10||-16.5|-44
+Ametal-2|net@121|||S1800|pin@70||-46.5|-44|contact@10||-16.5|-44
+Ametal-1|net@122|||S900|nand5A@2|inb|-68|-43|contact@11||-68|-44
+Ametal-1|net@134|||S0|pin@15||9|83.9|pin@29||-14.5|83.9
+Ametal-1|net@135|||S900|pin@29||-14.5|83.9|nand5A@1|out|-14.5|80.1
+Ametal-2|net@195|||S1800|contact@8||-68|44|pin@49||-46.5|44
+Ametal-2|net@210|||S1800|inv510@5|gnd|49|-72|sucDri20@0|gnd_1|49|-72
+Ametal-2|net@211|||S1800|inv510@5|vdd|49|-22|sucDri20@0|vdd_2|49|-22
+Ametal-2|net@212|||S1800|inv510@5|vdd_1|49|-122|sucDri20@0|vdd_3|49|-122
+Ametal-2|net@217|||S1800|pin@60||34.5|88|contact@21||56|88
+Ametal-1|net@218||0.4|S2700|inv510@4|in[1]|56|79|contact@21||56|88
+Ametal-1|net@223|||S2700|contact@22||16.5|88|pin@59||16.5|106
+Ametal-1|net@224|||S1800|pin@59||16.5|106|sucDri20@1|succ|19.5|106
+Ametal-2|net@225|||S1800|contact@22||16.5|88|pin@60||34.5|88
+Ametal-1|net@229|||S2700|contact@23||39|-56|pin@63||39|-38
+Ametal-1|net@230|||S0|pin@63||39|-38|sucDri20@0|succ|19.5|-38
+Ametal-2|net@231|||S1800|pin@64||34.5|-56|contact@23||39|-56
+Ametal-2|net@233|||S0|contact@24||56|-56|pin@64||34.5|-56
+Ametal-1|net@234||0.4|S2700|inv510@5|in[1]|56|-65|contact@24||56|-56
+Ametal-2|net@235|||S0|inv510@4|gnd|49|72|sucDri20@1|gnd_1|49|72
+Ametal-2|net@236|||S0|inv510@4|vdd|49|122|sucDri20@1|vdd_2|49|122
+Ametal-2|net@237|||S0|inv510@4|vdd_1|49|22|sucDri20@1|vdd_3|49|22
+Ametal-1|net@246|||S900|sucDri20@1|inB|25|62|pin@65||25|48
+Ametal-1|net@247|||S1800|pin@65||25|48|pin@66||42|48
+Ametal-1|net@248|||S900|pin@66||42|48|pin@67||42|2
+Ametal-2|net@257|||S1800|contact@11||-68|-44|pin@70||-46.5|-44
+Ametal-2|net@264|||S0|nand5A@1|gnd_1|-10|72|wellCont@0|gnd|-10|72
+Ametal-2|net@265|||S0|nand5A@1|vdd_2|-10|22|wellCont@0|vdd|-10|22
+Ametal-2|net@266|||S0|nand5A@1|vdd_3|-10|122|wellCont@0|vdd_1|-10|122
+Ametal-2|net@267|||S0|wellCont@1|gnd|-10|-72|nand5A@3|gnd_1|-10|-72
+Ametal-2|net@268|||S0|wellCont@1|vdd|-10|-122|nand5A@3|vdd_3|-10|-122
+Ametal-2|net@269|||S0|wellCont@1|vdd_1|-10|-22|nand5A@3|vdd_2|-10|-22
+Ametal-1|net@272|||S900|pin@75||-22.5|2|nand5A@3|out_2|-22.5|-61.6
+Ametal-1|net@273|||S0|pin@67||42|2|pin@75||-22.5|2
+Ametal-1|net@275|||S900|nand5A@0|out_2|-62|61.6|contact@6||-62|-6
+Ametal-1|net@276|||S2700|inv510@4|out10|70.5|79|contact@25||70.5|82
+Ametal-2|net@277|||S0|contact@25||70.5|82|pin@77||56|82
+Ametal-1|net@278|||S2700|inv510@5|out10|70.5|-65|contact@26||70.5|-50
+Ametal-2|net@279|||S0|contact@26||70.5|-50|pin@79||60|-50
+Efire[Co]||D5G4;|pin@49||I
+Ego[zero]|fire[zz]|D5G4;|pin@70||I
+Eflag[D][clr]||D5G4;|pin@60||O
+Eflag[D][set]||D5G4;|pin@64||O
+Egnd||D5G4;|nand5A@0|gnd_1|G
+Egnd_1||D5G4;|nand5A@2|gnd_1|G
+Egnd_4||D5G4;|inv510@4|gnd_1|G
+Egnd_5||D5G4;|inv510@5|gnd_1|G
+Eolc[zero]||D5G4;|pin@12||I
+Eolc[zoo]||D5G4;|pin@6||I
+Es[2]||D5G4;|pin@79||O
+Es[3]||D5G4;|pin@77||O
+Evdd||D5G4;|nand5A@0|vdd_2|P
+Evdd_2||D5G4;|nand5A@2|vdd_2|P
+Evdd_3||D5G4;|nand5A@2|vdd_3|P
+Evdd_4||D5G4;|inv510@4|vdd_2|P
+Evdd_5||D5G4;|inv510@4|vdd_3|P
+Evdd_8||D5G4;|inv510@5|vdd_2|P
+Evdd_9||D5G4;|inv510@5|vdd_3|P
+Evdd_11||D5G4;|nand5A@0|vdd_3|P
+X
+
 # Cell olcControlD;1{lay}
 ColcControlD;1{lay}||cmos90|1232819186778|1239703868553||ATTR_NCC(D5G3;NTX-6;Y140;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1239703888825
 Ngeneric:Facet-Center|art@0||0|0||||AV
@@ -4108,6 +5150,112 @@ Evdd_9||D5G2;|inv510@5|vdd_3|P
 Evdd_11||D5G2;|nand5A@0|vdd_3|P
 X
 
+# Cell olcControlD;2{sch}
+ColcControlD;2{sch}||schematic|1230935566337|1240288695220|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@3||-4.5|44|||Y|
+NOff-Page|conn@8||57|17||||
+NOff-Page|conn@14||55.5|24|||XR|
+NOff-Page|conn@16||2.5|38|||Y|
+NOff-Page|conn@17||67.5|38|||XY|
+IredFive:inv;1{ic}|inv@6||54|45.5|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@7||12|45|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@18||27|15|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@19||27|6|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@0||43|6|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@1||43|15|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nand2;1{ic}|nand2@0||45|51|X||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nand2;1{ic}|nand2@1||21.5|51|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nand2;1{ic}|nand2@2||45|39|XY||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nand2;1{ic}|nand2@3||21.5|39|Y||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IolcControlD;1{ic}|olcContr@0||53|82|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||1|79.5|||||ART_message(D5G5;)SolcControlD
+Ngeneric:Invisible-Pin|pin@73||63|44.5|||||ART_message(D3G2;)S[this side fires,for count OLC.]
+NWire_Pin|pin@83||33|24.5||||
+NWire_Pin|pin@84||33|70.5||||
+NWire_Pin|pin@85||60|38|||X|
+NWire_Pin|pin@86||60|52|||X|
+NWire_Pin|pin@87||6|52||||
+NWire_Pin|pin@89||6|38||||
+NWire_Pin|pin@90||54|40|||X|
+NWire_Pin|pin@94||12|50||||
+NWire_Pin|pin@95||12|40||||
+NWire_Pin|pin@97||54|50|||X|
+Ngeneric:Invisible-Pin|pin@124||-5|31|||||ART_message(D3G2;)S[this side sets,the flags from,"\"zero\" after load."]
+NWire_Pin|pin@181||31|39||||
+NWire_Pin|pin@182||31|51||||
+NWire_Pin|pin@183||35|39||||
+NWire_Pin|pin@184||35|51||||
+NWire_Pin|pin@224||50|13||||
+NWire_Pin|pin@225||20|15||||
+NWire_Pin|pin@226||20|20||||
+NWire_Pin|pin@227||20|10||||
+NWire_Pin|pin@228||20|6||||
+NWire_Pin|pin@229||50|15||||
+NWire_Pin|pin@230||50|22||||
+NWire_Pin|pin@231||50|6||||
+Ngeneric:Invisible-Pin|pin@232||1|73.5|||||ART_message(D5G3;)Sies 20 April 2009
+IdriversL:sucDri20or;1{ic}|sucDri20@3||33|61.5|YRRR||D5G4;
+IdriversL:sucDri20or;1{ic}|sucDri20@4||33|32|XYR||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@9||27.5|39|||D0G4;|ATTR_L(D5G1;PUD)D406.2|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@10||39|39|X||D0G4;|ATTR_L(D5G1;PUD)D488.9|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@11||39|51|X||D0G4;|ATTR_L(D5G1;PUD)D348.7|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@12||27.5|51|||D0G4;|ATTR_L(D5G1;PUD)D411.6|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@13||51|50|X||D0G4;|ATTR_L(D5G1;PUD)D147.29999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@14||15.5|50|||D0G4;|ATTR_L(D5G1;PUD)D143.2|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@21||35|15|||D0G4;|ATTR_L(D5G1;PUD)D142.60000000000002|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@22||35|6|||D0G4;|ATTR_L(D5G1;PUD)D142.60000000000002|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Awire|flag[D][clr]|D5G2;||900|pin@84||33|70.5|sucDri20@3|succ|33|64.5
+Awire|flag[D][clr]|D5G2;||2700|pin@228||20|6|pin@227||20|10
+Awire|flag[D][set]|D5G2;||2700|pin@83||33|24.5|sucDri20@4|succ|33|29
+Awire|flag[D][set]|D5G2;||2700|pin@225||20|15|pin@226||20|20
+Awire|net@162|||1800|nand2@2|inb|47.5|38|pin@85||60|38
+Awire|net@164|||0|pin@86||60|52|nand2@0|inb|47.5|52
+Awire|net@165|||0|nand2@1|inb|19|52|pin@87||6|52
+Awire|net@168|||1800|pin@89||6|38|nand2@3|inb|19|38
+Awire|net@180|||2700|inv@6|out|54|48|pin@97||54|50
+Awire|net@184|||2700|inv@7|out|12|47.5|pin@94||12|50
+Awire|net@185|||1800|pin@95||12|40|nand2@3|ina|19|40
+Awire|net@186|||1800|nand2@2|ina|47.5|40|pin@90||54|40
+Awire|net@279|||0|nand2@2|out|42.5|39|wire90@10|a|41.5|39
+Awire|net@281|||1800|nand2@3|out|24|39|wire90@9|a|25|39
+Awire|net@284|||0|wire90@12|a|25|51|nand2@1|out|24|51
+Awire|net@286|||1800|wire90@11|a|41.5|51|nand2@0|out|42.5|51
+Awire|net@287|||1800|wire90@13|a|53.5|50|pin@97||54|50
+Awire|net@288|||0|wire90@13|b|48.5|50|nand2@0|ina|47.5|50
+Awire|net@289|||1800|wire90@14|b|18|50|nand2@1|ina|19|50
+Awire|net@290|||0|wire90@14|a|13|50|pin@94||12|50
+Awire|net@356|||900|pin@87||6|52|pin@89||6|38
+Awire|net@360|||2700|pin@85||60|38|pin@86||60|52
+Awire|net@422|||0|pin@181||31|39|wire90@9|b|30|39
+Awire|net@424|||0|pin@182||31|51|wire90@12|b|30|51
+Awire|net@425|||900|sucDri20@3|inA_1|31|58.5|pin@182||31|51
+Awire|net@426|||0|wire90@10|b|36.5|39|pin@183||35|39
+Awire|net@428|||0|wire90@11|b|36.5|51|pin@184||35|51
+Awire|net@429|||2700|pin@184||35|51|sucDri20@3|in|35|58.5
+Awire|net@539|||2700|sucDri20@4|in|35|35|pin@183||35|39
+Awire|net@540|||2700|sucDri20@4|inA_1|31|35|pin@181||31|39
+Awire|net@543|||1800|invI@1|out|45.5|15|pin@229||50|15
+Awire|net@544|||0|invI@0|in|40.5|6|wire90@22|b|37.5|6
+Awire|net@545|||0|wire90@22|a|32.5|6|inv@19|out|29.5|6
+Awire|net@546|||1800|invI@0|out|45.5|6|pin@231||50|6
+Awire|net@547|||0|inv@19|in|24.5|6|pin@228||20|6
+Awire|net@548|||0|inv@18|in|24.5|15|pin@225||20|15
+Awire|net@549|||0|invI@1|in|40.5|15|wire90@21|b|37.5|15
+Awire|net@550|||0|wire90@21|a|32.5|15|inv@18|out|29.5|15
+Awire|net@580|||1800|conn@16|y|4.5|38|pin@89||6|38
+Awire|net@581|||0|conn@17|y|65.5|38|pin@85||60|38
+Awire|olc[zero]|D5G2;||900|inv@7|in|12|42.5|pin@95||12|40
+Awire|olc[zoo]|D5G2;||900|inv@6|in|54|43|pin@90||54|40
+Awire|s[2]|D5G2;||2700|pin@229||50|15|pin@230||50|22
+Awire|s[3]|D5G2;||2700|pin@231||50|6|pin@224||50|13
+Efire[Co]||D4G2;|conn@17|a|I
+Ego[zero]|fire[zz]|D4G2;|conn@16|a|I
+Eflag[D][set,clr]||D6G2;|conn@8|y|O
+Eolc[zero,zoo]||D4G2;|conn@3|a|I
+Es[2,3]||D6G2;|conn@14|y|O
+X
+
 # Cell olcControlD;1{sch}
 ColcControlD;1{sch}||schematic|1230935566337|1236908967051|I
 Ngeneric:Facet-Center|art@0||0|0||||AV
@@ -4595,6 +5743,93 @@ Evdd_12||D5G2;|inv10D@3|vdd_2|P
 Evdd_13||D5G2;|inv10D@3|vdd_3|P
 X
 
+# Cell olcControlParts;1{sch}
+ColcControlParts;1{sch}||schematic|1240288568458|1240289972590|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||24|11.5|||YRRR|
+NOff-Page|conn@1||-6.5|22.5|||XR|
+NOff-Page|conn@2||21|28|||R|
+NOff-Page|conn@4||-27|9|||XYR|
+NOff-Page|conn@5||6|14|||XR|
+NOff-Page|conn@6||39|11.5|||XR|
+NOff-Page|conn@7||-25.5|21.5|||Y|
+NOff-Page|conn@8||-24|8.5|||XR|
+NOff-Page|conn@9||-36|-1|||XYRR|
+IolcControlA;1{ic}|olcContr@0||-24|0|||D5G4;
+IolcControlB;1{ic}|olcContr@1||9|0|||D5G4;
+IolcControlC;1{ic}|olcContr@2||36|0|||D5G4;
+IolcControlD;1{ic}|olcContr@3||24|19.5|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||1|46.5|||||ART_message(D5G5;)SolcControlParts
+Ngeneric:Invisible-Pin|pin@1||1|40.5|||||ART_message(D5G3;)Sies 20 April 2009
+NWire_Pin|pin@3||12|6||||
+NWire_Pin|pin@4||21|6||||
+NWire_Pin|pin@5||-12|1||||
+NWire_Pin|pin@7||-12|6||||
+NWire_Pin|pin@8||16.5|0||||
+NWire_Pin|pin@9||16.5|-4||||
+NWire_Pin|pin@10||44|0||||
+NWire_Pin|pin@11||44|-2.5||||
+NWire_Pin|pin@12||39|-7.5||||
+NWire_Pin|pin@13||27|6||||
+NWire_Pin|pin@15||33|6||||
+NWire_Pin|pin@16||-6|-1||||
+NWire_Pin|pin@17||-6|1||||
+NWire_Pin|pin@18||-32|1||||
+NWire_Pin|pin@19||-32|5.5||||
+NWire_Pin|pin@20||-21|-7.5||||
+NWire_Pin|pin@21||6|-7.5||||
+NWire_Pin|pin@22||27|1||||
+NWire_Pin|pin@23||27|4.5||||
+NWire_Pin|pin@24||0.5|-1||||
+NWire_Pin|pin@26||0.5|-3.5||||
+NBus_Pin|pin@27||27|27.5|-1|-1||
+NWire_Pin|pin@28||-21|7||||
+Awire|do[Co]|D5G2;||2700|pin@22||27|1|pin@23||27|4.5
+Awire|do[Ld]|D5G2;||2700|pin@18||-32|1|pin@19||-32|5.5
+Awire|do[reD]|D5G2;||900|pin@24||0.5|-1|pin@26||0.5|-3.5
+Awire|do[zz]|D5G2;||2700|pin@16||-6|-1|pin@17||-6|1
+Awire|fire[zz]|D5G2;||2700|olcContr@1|fire[zz]|12|3|pin@3||12|6
+Awire|mc|D5G2;||900|pin@8||16.5|0|pin@9||16.5|-4
+Awire|mc|D5G2;||900|pin@10||44|0|pin@11||44|-2.5
+Abus|net@0||-0.5|IJ900|olcContr@3|olc[zero,zoo]|24|15.5|conn@0|y|24|13.5
+Abus|net@2||-0.5|IJ900|conn@2|a|21|26|olcContr@3|flag[D][set,clr]|21|22.5
+Awire|net@5|||1800|pin@3||12|6|pin@4||21|6
+Awire|net@6|||2700|pin@4||21|6|olcContr@3|fire[zz]|21|16.5
+Awire|net@7|||1800|olcContr@0|fire[zz]|-19|1|pin@5||-12|1
+Awire|net@10|||1800|pin@7||-12|6|pin@3||12|6
+Awire|net@11|||2700|pin@5||-12|1|pin@7||-12|6
+Awire|net@12|||900|conn@4|y|-27|7|olcContr@0|mc|-27|3
+Awire|net@13|||1800|olcContr@1|mc|14|0|pin@8||16.5|0
+Awire|net@15|||1800|olcContr@2|mc|41|0|pin@10||44|0
+Awire|net@20|||2700|pin@13||27|6|olcContr@3|fire[Co]|27|16.5
+Awire|net@21|||1800|pin@13||27|6|pin@15||33|6
+Awire|net@22|||900|pin@15||33|6|olcContr@2|fire[Co]|33|3
+Awire|net@23|||1800|olcContr@0|do[zz]|-19|-1|pin@16||-6|-1
+Awire|net@25|||1800|pin@17||-6|1|olcContr@1|do[zz]|4|1
+Awire|net@26|||900|conn@5|a|6|12|olcContr@1|olc[load]|6|3
+Awire|net@27|||900|conn@6|a|39|9.5|olcContr@2|olc[dec]|39|3
+Awire|net@28|||0|olcContr@0|do[Ld]|-29|1|pin@18||-32|1
+Awire|net@30|||900|conn@8|a|-24|6.5|olcContr@0|ilc[load]|-24|3
+Awire|net@32|||1800|pin@20||-21|-7.5|pin@21||6|-7.5
+Awire|net@33|||2700|pin@21||6|-7.5|olcContr@1|not[Ld]|6|-3
+Awire|net@34|||0|olcContr@2|do[Co]|31|1|pin@22||27|1
+Awire|net@36|||1800|conn@9|y|-34|-1|olcContr@0|Dvoid|-29|-1
+Awire|net@37|||0|olcContr@1|mc_1|4|-1|pin@24||0.5|-1
+Awire|not[Ld]|D5G2;||900|olcContr@0|not[Ld]|-21|-3|pin@20||-21|-7.5
+Awire|olc[zero]|D5G2;||900|olcContr@2|olc[zero]|39|-3|pin@12||39|-7.5
+Awire|s[1]|D5G2;||2700|olcContr@0|not[Ld_1]|-21|4|pin@28||-21|7
+Abus|s[2,3]|D5G2;|-0.5|IJ2700|olcContr@3|s[2,3]|27|23.5|pin@27||27|27.5
+EDvoid||D4G2;|conn@9|a|I
+Edo[Ld,Co,reD]||D4G2;|conn@7|a|I
+Eflag[D][set,clr]||D6G2;|conn@2|y|O
+Eilc[load]||D6G2;|conn@8|y|O
+Emc||D4G2;|conn@4|a|I
+Eolc[dec]||D6G2;|conn@6|y|O
+Eolc[load]||D6G2;|conn@5|y|O
+Eolc[zero,zoo]||D4G2;|conn@0|a|I
+Es[2,3]|s[1:3]|D6G2;|conn@1|y|O
+X
+
 # Cell olcEven;1{ic}
 ColcEven;1{ic}||artwork|1216797193489|1230943951936|EI
 Ngeneric:Facet-Center|art@0||0|0||||AV
@@ -5857,7 +7092,7 @@ Evdd_7||D5G2;|mlat1in5@6|vdd_3|P
 X
 
 # Cell ringB;1{sch}
-CringB;1{sch}||schematic|1216757841833|1221300240954|I
+CringB;1{sch}||schematic|1216757841833|1240290589391|I
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-29|-12|||RR|
 NOff-Page|conn@1||21|-20|||XYRRR|
@@ -5867,7 +7102,7 @@ NOff-Page|conn@6||4|18|||XYRR|
 IredFive:inv;1{ic}|inv@0||-13|-12|X||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFive:inv;1{ic}|inv@1||-15.5|6|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFive:inv;1{ic}|inv@2||0|6|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFive:inv;1{ic}|inv@3||42|1|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@3||42|1|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IlatchesK:mlat1in5i;1{ic}|mlat1in5@0||15|6|Y||D5G4;
 IlatchesK:mlat1in5i;1{ic}|mlat1in5@1||15|18|Y||D5G4;
 IlatchesK:mlat2in10i;1{ic}|mlat2in1@0||8|-12|X||D5G4;
index cba5dd4..9dd7c8c 100644 (file)
@@ -1,7 +1,7 @@
 *** SPICE deck for cell marinaOut{sch} from library aMarinaM
 *** Created on Mon Nov 17, 2008 08:47:24
 *** Last revised on Mon Mar 30, 2009 06:59:15
-*** Written on Mon Apr 20, 2009 18:24:51 by Electric VLSI Design System, 
+*** Written on Mon Apr 20, 2009 23:21:39 by Electric VLSI Design System, 
 *version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -7367,15 +7367,6 @@ Xwire90@4 wire90@4_a do[5] wire90-554_3-layer_1-width_3
 Xwire90@5 wire90@5_a do[6] wire90-463_3-layer_1-width_3
 .ENDS olc
 
-*** CELL: centersJ:ctrAND1in100{sch}
-.SUBCKT ctrAND1in100 in out
-Xinv@11 net@125 net@120 inv-X_30
-XinvI@3 in net@101 inv-X_10
-XinvI@4 net@82 out inv-X_100
-Xwire90@1 net@101 net@125 wire90-414-layer_1-width_3
-Xwire90@2 net@120 net@82 wire90-927-layer_1-width_3
-.ENDS ctrAND1in100
-
 *** CELL: centersJ:ctrAND2in100{sch}
 .SUBCKT ctrAND2in100 inA inB out
 Xinv@9 net@163 net@161 inv-X_30
@@ -7385,6 +7376,17 @@ Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3
 Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3
 .ENDS ctrAND2in100
 
+*** CELL: centersJ:ctrAND3in30B{sch}
+.SUBCKT ctrAND3in30B inA inB inC out
+Xinv@4 inC net@30 inv-X_5
+Xinv@5 net@9 out inv-X_30
+Xnand2LT_@0 net@15 net@19 net@27 nand2LT_sy-X_10
+Xnor2n_sy@0 inA inB net@6 nor2n_sy-X_5
+Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
+Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
+Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
+.ENDS ctrAND3in30B
+
 *** CELL: orangeTSMC090nm:NMOSx{sch}
 .SUBCKT NMOSx-X_3_999 d g s
 MNMOSf@0 d g s gnd nch W='11.997*(1+ABN/sqrt(11.997*2))' L='2' 
@@ -7408,38 +7410,6 @@ Xwire90@0 net@142 net@94 wire90-124_7-layer_1-width_3
 .ENDS sucDri20or
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-802-R_34_667m a b
-Ccap@0 gnd net@14 2.941f
-Ccap@1 gnd net@8 2.941f
-Ccap@2 gnd net@11 2.941f
-Rres@0 net@14 a 4.634
-Rres@1 net@11 net@14 9.268
-Rres@2 b net@8 4.634
-Rres@3 net@8 net@11 9.268
-.ENDS wire-C_0_011f-802-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-802-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-802-R_34_667m
-.ENDS wire90-802-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-911_4-R_34_667m a b
-Ccap@0 gnd net@14 3.342f
-Ccap@1 gnd net@8 3.342f
-Ccap@2 gnd net@11 3.342f
-Rres@0 net@14 a 5.266
-Rres@1 net@11 net@14 10.532
-Rres@2 b net@8 5.266
-Rres@3 net@8 net@11 10.532
-.ENDS wire-C_0_011f-911_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-911_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-911_4-R_34_667m
-.ENDS wire90-911_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
 .SUBCKT wire-C_0_011f-405-R_34_667m a b
 Ccap@0 gnd net@14 1.485f
 Ccap@1 gnd net@8 1.485f
@@ -7568,38 +7538,6 @@ Xwire@0 a b wire-C_0_011f-485_9-R_34_667m
 .ENDS wire90-485_9-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-208_9-R_34_667m a b
-Ccap@0 gnd net@14 0.766f
-Ccap@1 gnd net@8 0.766f
-Ccap@2 gnd net@11 0.766f
-Rres@0 net@14 a 1.207
-Rres@1 net@11 net@14 2.414
-Rres@2 b net@8 1.207
-Rres@3 net@8 net@11 2.414
-.ENDS wire-C_0_011f-208_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-208_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-208_9-R_34_667m
-.ENDS wire90-208_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-127_4-R_34_667m a b
-Ccap@0 gnd net@14 0.467f
-Ccap@1 gnd net@8 0.467f
-Ccap@2 gnd net@11 0.467f
-Rres@0 net@14 a 0.736
-Rres@1 net@11 net@14 1.472
-Rres@2 b net@8 0.736
-Rres@3 net@8 net@11 1.472
-.ENDS wire-C_0_011f-127_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-127_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-127_4-R_34_667m
-.ENDS wire90-127_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
 .SUBCKT wire-C_0_011f-215_9-R_34_667m a b
 Ccap@0 gnd net@14 0.792f
 Ccap@1 gnd net@8 0.792f
@@ -7631,54 +7569,79 @@ Rres@3 net@8 net@11 1.625
 Xwire@0 a b wire-C_0_011f-140_6-R_34_667m
 .ENDS wire90-140_6-layer_1-width_3
 
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-127_4-R_34_667m a b
+Ccap@0 gnd net@14 0.467f
+Ccap@1 gnd net@8 0.467f
+Ccap@2 gnd net@11 0.467f
+Rres@0 net@14 a 0.736
+Rres@1 net@11 net@14 1.472
+Rres@2 b net@8 0.736
+Rres@3 net@8 net@11 1.472
+.ENDS wire-C_0_011f-127_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-127_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-127_4-R_34_667m
+.ENDS wire90-127_4-layer_1-width_3
+
 *** CELL: loopCountM:olcControl{sch}
 .SUBCKT olcControl Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] 
 +ilc[load] mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3]
-XctrAND1i@0 net@527 net@165 ctrAND1in30
-XctrAND1i@3 net@519 ilc[load] ctrAND1in100
-XctrAND1i@4 net@547 net@162 ctrAND1in30
-XctrAND2i@3 do[2] net@339 olc[load] ctrAND2in100LT
+XctrAND1i@4 net@547 fire[Co] ctrAND1in30
+XctrAND2i@3 net@348 net@340 olc[load] ctrAND2in100LT
 XctrAND2i@5 olc[zero] net@547 olc[dec] ctrAND2in100
+XctrAND2i@6 not[Ld] net@634 ilc[load] ctrAND2in100LT
+XctrAND2i@8 not[Ld] net@695 fire[zz] ctrAND2in30
+XctrAND3i@0 net@821 net@823 not[Ld] net@612 ctrAND3in30B
 Xinv@6 olc[zoo] net@180 inv-X_5
 Xinv@7 olc[zero] net@184 inv-X_5
 Xinv@14 do[Co] net@386 inv-X_10
-Xinv@16 Dvoid net@451 inv-X_5
 Xinv@18 flag[D][set] net@535 inv-X_5
 Xinv@19 flag[D][clr] net@539 inv-X_5
-Xinv@20 do[Ld] net@576 inv-X_5
+Xinv@20 do[Ld] net@576 inv-X_10
+Xinv@21 Dvoid net@605 inv-X_5
+Xinv@22 net@632 net@635 inv-X_5
+Xinv@25 do[zz] net@783 inv-X_5
 XinvI@2 net@538 s[3] inv-X_10
 XinvI@3 net@534 s[2] inv-X_10
-XinvI@4 net@575 s[1] inv-X_10
-Xnand2@0 net@288 net@162 net@286 nand2-X_5
-Xnand2@1 net@289 net@165 net@284 nand2-X_5
-Xnand2@2 olc[zoo] net@162 net@279 nand2-X_5
-Xnand2@3 olc[zero] net@165 net@281 nand2-X_5
-Xnand2@4 Dvoid do[Ld] net@471 nand2-X_5
-Xnand2@5 net@455 do[Ld] net@438 nand2-X_5
-Xnor2_sy@1 do[reD] do[2] net@556 nor2_sy-X_5
-XpredDri2@0 net@358 mc do[2] predDri20wMC
-XpredDri2@2 net@162 mc do[Co] predDri20wMC
-XpredDri2@3 net@165 mc do[reD] predDri20wMC
-XpredORdr@0 ilc[load] olc[load] mc do[Ld] predORdri20wMC
-XsucDri20@0 olc[load] net@278 sucDri20
+XinvI@4 not[Ld] s[1] inv-X_10
+Xnand2@0 net@288 fire[Co] net@286 nand2-X_5
+Xnand2@1 net@289 fire[zz] net@284 nand2-X_5
+Xnand2@2 olc[zoo] net@728 net@279 nand2-X_5
+Xnand2@3 olc[zero] fire[zz] net@281 nand2-X_5
+Xnor2_sy@2 do[reD] do[2] net@724 nor2_sy-X_5
+XpredDri2@2 fire[Co] mc do[Co] predDri20wMC
+XpredDri2@3 fire[zz] mc do[reD] predDri20wMC
+XpredDri2@5 not[Ld] mc net@632 predDri20wMC
+XpredDri2@8 not[Ld] mc do[zz] predDri20wMC
+XpredDri2@9 net@340 mc do[2] predDri20wMC
+XpredORdr@1 net@765 ilc[load] mc do[Ld] predORdri20wMC
+XsucANDdr@0 net@653 net@638 net@632 sucANDdri20
+XsucANDdr@1 Dvoid net@612 do[zz] sucANDdri20
+XsucDri20@0 olc[load] do[2] sucDri20
 XsucDri20@3 net@428 net@424 flag[D][clr] sucDri20or
 XsucDri20@4 net@426 net@422 flag[D][set] sucDri20or
-Xwire90@6 net@358 net@165 wire90-802-layer_1-width_3
-Xwire90@8 net@278 do[2] wire90-911_4-layer_1-width_3
 Xwire90@9 net@281 net@422 wire90-405-layer_1-width_3
 Xwire90@10 net@279 net@426 wire90-472_9-layer_1-width_3
 Xwire90@11 net@286 net@428 wire90-346_7-layer_1-width_3
 Xwire90@12 net@284 net@424 wire90-438_9-layer_1-width_3
 Xwire90@13 net@180 net@288 wire90-143_2-layer_1-width_3
 Xwire90@14 net@184 net@289 wire90-144_3-layer_1-width_3
-Xwire90@17 net@471 net@339 wire90-431_3-layer_1-width_3
+Xwire90@17 net@783 net@340 wire90-431_3-layer_1-width_3
 Xwire90@19 net@386 net@547 wire90-485_9-layer_1-width_3
-Xwire90@20 net@438 net@519 wire90-208_9-layer_1-width_3
-Xwire90@21 net@455 net@451 wire90-127_4-layer_1-width_3
-Xwire90@22 net@556 net@527 wire90-215_9-layer_1-width_3
+Xwire90@22 net@724 net@695 wire90-215_9-layer_1-width_3
 Xwire90@23 net@535 net@534 wire90-140_6-layer_1-width_3
 Xwire90@24 net@539 net@538 wire90-140_6-layer_1-width_3
-Xwire90@25 net@576 net@575 wire90-140_6-layer_1-width_3
+Xwire90@25 net@576 not[Ld] wire90-140_6-layer_1-width_3
+Xwire90@26 net@638 net@612 wire90-127_4-layer_1-width_3
+Xwire90@27 net@653 net@605 wire90-127_4-layer_1-width_3
+Xwire90@28 net@634 net@635 wire90-127_4-layer_1-width_3
+Xwire90@31 net@823 net@632 wire90-140_6-layer_1-width_3
+Xwire90@32 net@821 do[zz] wire90-140_6-layer_1-width_3
+Xwire90@36 net@348 do[2] wire90-431_3-layer_1-width_3
+Xwire90@37 fire[Co] net@728 wire90-472_9-layer_1-width_3
+Xwire90@39 net@765 fire[zz] wire90-144_3-layer_1-width_3
 .ENDS olcControl
 
 *** CELL: orangeTSMC090nm:wire{sch}
index 06b48c3..f4e6258 100644 (file)
@@ -1,7 +1,7 @@
 /* Verilog for cell 'marinaOut{sch}' from library 'aMarinaM' */
 /* Created on Mon Nov 17, 2008 08:47:24 */
 /* Last revised on Mon Mar 30, 2009 06:59:15 */
-/* Written on Mon Apr 20, 2009 17:38:34 by Electric VLSI Design System, version 8.08k */
+/* Written on Mon Apr 20, 2009 23:21:36 by Electric VLSI Design System, version 8.08k */
 
 module orangeTSMC090nm__wire(a);
   input a;
@@ -4505,7 +4505,7 @@ module loopCountM__ringB(count_F_, count_T_, do, inLO, load_F_, load_T_, bit);
   not (strong0, strong1) #(100) inv_2 (net_65, net_67);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_3 (xx_F_, xx_T_);
+  not (strong0, strong1) #(0) inv_3 (xx_F_, xx_T_);
   // end Verilog_template
   latchesK__mlat1in5i mlat1in5_0(.c_F_(xx_T_), .c_T_(xx_F_), .in(net_65), 
       .out(net_9));
@@ -4541,7 +4541,7 @@ module loopCountM__ilcEven(do, do_1, do_2, ilc_decLO_, \inLO[2] , \inLO[4] ,
   wire count_F_, count_T_, load_F_;
 
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_7 (count_F_, count_T_);
+  not (strong0, strong1) #(0) inv_7 (count_F_, count_T_);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
   not (strong0, strong1) #(0) inv_8 (load_F_, load_T_);
@@ -4579,13 +4579,13 @@ module loopCountM__ilcOdd(do, do_1, do_2, ilc_decLO_, \inLO[1] , \inLO[3] ,
   wire check_T_, count_F_, count_T_, load_F_;
 
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_5 (count_F_, count_T_);
+  not (strong0, strong1) #(0) inv_5 (count_F_, count_T_);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
   not (strong0, strong1) #(0) inv_6 (load_F_, load_T_);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_7 (check_T_, ilc_decLO_);
+  not (strong0, strong1) #(0) inv_7 (check_T_, ilc_decLO_);
   // end Verilog_template
   latchesK__mlat2in10i mlat2in1_1(.clA_F_(load_F_), .clA_T_(load_T_), 
       .clB_F_(ilc_decLO_), .clB_T_(check_T_), .inA(gnd), .inB(do_2[7]), .out({ 
@@ -5542,46 +5542,50 @@ module loopCountM__olc(inLO, olc_dec_, olc_load_, bitt, olc_zero_, olc_zoo_);
   orangeTSMC090nm__wire90 wire90_5(.a(do[6]));
 endmodule   /* loopCountM__olc */
 
-module centersJ__ctrAND1in100(in, out);
-  input in;
+module centersJ__ctrAND2in100(inA, inB, out);
+  input inA;
+  input inB;
   output out;
 
   supply1 vdd;
   supply0 gnd;
-  wire net_101, net_82;
+  wire net_158, net_161;
 
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_11 (net_82, net_101);
-  // end Verilog_template
-  /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) invI_3 (net_101, in);
+  not (strong0, strong1) #(100) inv_9 (net_161, net_158);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) invI_4 (out, net_82);
+  not (strong0, strong1) #(100) invI_1 (out, net_161);
   // end Verilog_template
-  orangeTSMC090nm__wire90 wire90_1(.a(net_101));
-  orangeTSMC090nm__wire90 wire90_2(.a(net_82));
-endmodule   /* centersJ__ctrAND1in100 */
+  redFive__nor2n_sy nor2n_sy_0(.ina(inA), .inb(inB), .out(net_158));
+  orangeTSMC090nm__wire90 wire90_6(.a(net_158));
+  orangeTSMC090nm__wire90 wire90_7(.a(net_161));
+endmodule   /* centersJ__ctrAND2in100 */
 
-module centersJ__ctrAND2in100(inA, inB, out);
+module centersJ__ctrAND3in30B(inA, inB, inC, out);
   input inA;
   input inB;
+  input inC;
   output out;
 
   supply1 vdd;
   supply0 gnd;
-  wire net_158, net_161;
+  wire net_19, net_6, net_9;
 
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_9 (net_161, net_158);
+  not (strong0, strong1) #(100) inv_4 (net_19, inC);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) invI_1 (out, net_161);
+  not (strong0, strong1) #(100) inv_5 (out, net_9);
   // end Verilog_template
-  redFive__nor2n_sy nor2n_sy_0(.ina(inA), .inb(inB), .out(net_158));
-  orangeTSMC090nm__wire90 wire90_6(.a(net_158));
-  orangeTSMC090nm__wire90 wire90_7(.a(net_161));
-endmodule   /* centersJ__ctrAND2in100 */
+  /* begin Verilog_template for redFive:nand2LT_sy{sch}*/
+  nand (strong0, strong1) #(100) nand2LT__0 (net_9, net_6, net_19);
+  // end Verilog_template
+  redFive__nor2n_sy nor2n_sy_0(.ina(inA), .inb(inB), .out(net_6));
+  orangeTSMC090nm__wire90 wire90_0(.a(net_6));
+  orangeTSMC090nm__wire90 wire90_1(.a(net_9));
+  orangeTSMC090nm__wire90 wire90_2(.a(net_19));
+endmodule   /* centersJ__ctrAND3in30B */
 
 module driversL__sucDri20or(inA, inB, succ);
   input inA;
@@ -5620,17 +5624,22 @@ module loopCountM__olcControl(Dvoid, do_Co_, do_Ld_, do_reD_, mc, olc_zero_,
 
   supply1 vdd;
   supply0 gnd;
-  wire net_162, net_165, net_180, net_184, net_279, net_281, net_284, net_286;
-  wire net_339, net_386, net_438, net_451, net_527, net_534, net_538, net_575;
+  wire do_zz_, fire_Co_, fire_zz_, net_180, net_184, net_279, net_281, net_284;
+  wire net_286, net_340, net_386, net_534, net_538, net_605, net_612, net_632;
+  wire net_634, net_695, not_Ld_;
   wire [2:2] do;
 
-  centersJ__ctrAND1in30 ctrAND1i_0(.in(net_527), .out(net_165));
-  centersJ__ctrAND1in100 ctrAND1i_3(.in(net_438), .out(ilc_load_));
-  centersJ__ctrAND1in30 ctrAND1i_4(.in(net_386), .out(net_162));
-  centersJ__ctrAND2in100LT ctrAND2i_3(.inA(do[2]), .inB(net_339), 
+  centersJ__ctrAND1in30 ctrAND1i_4(.in(net_386), .out(fire_Co_));
+  centersJ__ctrAND2in100LT ctrAND2i_3(.inA(do[2]), .inB(net_340), 
       .out(olc_load_));
   centersJ__ctrAND2in100 ctrAND2i_5(.inA(olc_zero_), .inB(net_386), 
       .out(olc_dec_));
+  centersJ__ctrAND2in100LT ctrAND2i_6(.inA(not_Ld_), .inB(net_634), 
+      .out(ilc_load_));
+  centersJ__ctrAND2in30 ctrAND2i_8(.inA(not_Ld_), .inB(net_695), 
+      .out(fire_zz_));
+  centersJ__ctrAND3in30B ctrAND3i_0(.inA(do_zz_), .inB(net_632), .inC(not_Ld_), 
+      .out(net_612));
   /* begin Verilog_template for redFive:inv{sch}*/
   not (strong0, strong1) #(100) inv_6 (net_180, olc_zoo_);
   // end Verilog_template
@@ -5641,73 +5650,82 @@ module loopCountM__olcControl(Dvoid, do_Co_, do_Ld_, do_reD_, mc, olc_zero_,
   not (strong0, strong1) #(100) inv_14 (net_386, do_Co_);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_16 (net_451, Dvoid);
-  // end Verilog_template
-  /* begin Verilog_template for redFive:inv{sch}*/
   not (strong0, strong1) #(100) inv_18 (net_534, flag_D__set_);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
   not (strong0, strong1) #(100) inv_19 (net_538, flag_D__clr_);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_20 (net_575, do_Ld_);
+  not (strong0, strong1) #(100) inv_20 (not_Ld_, do_Ld_);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) invI_2 (s[3], net_538);
+  not (strong0, strong1) #(100) inv_21 (net_605, Dvoid);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) invI_3 (s[2], net_534);
+  not (strong0, strong1) #(100) inv_22 (net_634, net_632);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) invI_4 (s[1], net_575);
+  not (strong0, strong1) #(100) inv_25 (net_340, do_zz_);
   // end Verilog_template
-  /* begin Verilog_template for redFive:nand2{sch}*/
-  nand (strong0, strong1) #(100) nand2_0 (net_286, net_180, net_162);
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) invI_2 (s[3], net_538);
   // end Verilog_template
-  /* begin Verilog_template for redFive:nand2{sch}*/
-  nand (strong0, strong1) #(100) nand2_1 (net_284, net_184, net_165);
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) invI_3 (s[2], net_534);
+  // end Verilog_template
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) invI_4 (s[1], not_Ld_);
   // end Verilog_template
   /* begin Verilog_template for redFive:nand2{sch}*/
-  nand (strong0, strong1) #(100) nand2_2 (net_279, olc_zoo_, net_162);
+  nand (strong0, strong1) #(100) nand2_0 (net_286, net_180, fire_Co_);
   // end Verilog_template
   /* begin Verilog_template for redFive:nand2{sch}*/
-  nand (strong0, strong1) #(100) nand2_3 (net_281, olc_zero_, net_165);
+  nand (strong0, strong1) #(100) nand2_1 (net_284, net_184, fire_zz_);
   // end Verilog_template
   /* begin Verilog_template for redFive:nand2{sch}*/
-  nand (strong0, strong1) #(100) nand2_4 (net_339, Dvoid, do_Ld_);
+  nand (strong0, strong1) #(100) nand2_2 (net_279, olc_zoo_, fire_Co_);
   // end Verilog_template
   /* begin Verilog_template for redFive:nand2{sch}*/
-  nand (strong0, strong1) #(100) nand2_5 (net_438, net_451, do_Ld_);
+  nand (strong0, strong1) #(100) nand2_3 (net_281, olc_zero_, fire_zz_);
   // end Verilog_template
   /* begin Verilog_template for redFive:nor2_sy{sch}*/
-  nor (strong0, strong1) #(100) nor2_sy_1 (net_527, do_reD_, do[2]);
-  // end Verilog_template
-  driversL__predDri20wMC predDri2_0(.in(net_165), .mc(mc), .pred(do[2]));
-  driversL__predDri20wMC predDri2_2(.in(net_162), .mc(mc), .pred(do_Co_));
-  driversL__predDri20wMC predDri2_3(.in(net_165), .mc(mc), .pred(do_reD_));
-  driversL__predORdri20wMC predORdr_0(.inA(ilc_load_), .inB(olc_load_), 
-      .mc(mc), .pred(do_Ld_));
+  nor (strong0, strong1) #(100) nor2_sy_2 (net_695, do_reD_, do[2]);
+  // end Verilog_template
+  driversL__predDri20wMC predDri2_2(.in(fire_Co_), .mc(mc), .pred(do_Co_));
+  driversL__predDri20wMC predDri2_3(.in(fire_zz_), .mc(mc), .pred(do_reD_));
+  driversL__predDri20wMC predDri2_5(.in(not_Ld_), .mc(mc), .pred(net_632));
+  driversL__predDri20wMC predDri2_8(.in(not_Ld_), .mc(mc), .pred(do_zz_));
+  driversL__predDri20wMC predDri2_9(.in(net_340), .mc(mc), .pred(do[2]));
+  driversL__predORdri20wMC predORdr_1(.inA(fire_zz_), .inB(ilc_load_), .mc(mc), 
+      .pred(do_Ld_));
+  driversL__sucANDdri20 sucANDdr_0(.inA(net_605), .inB(net_612), 
+      .succ(net_632));
+  driversL__sucANDdri20 sucANDdr_1(.inA(Dvoid), .inB(net_612), .succ(do_zz_));
   driversL__sucDri20 sucDri20_0(.in(olc_load_), .succ(do[2]));
   driversL__sucDri20or sucDri20_3(.inA(net_286), .inB(net_284), 
       .succ(flag_D__clr_));
   driversL__sucDri20or sucDri20_4(.inA(net_279), .inB(net_281), 
       .succ(flag_D__set_));
-  orangeTSMC090nm__wire90 wire90_6(.a(net_165));
-  orangeTSMC090nm__wire90 wire90_8(.a(do[2]));
   orangeTSMC090nm__wire90 wire90_9(.a(net_281));
   orangeTSMC090nm__wire90 wire90_10(.a(net_279));
   orangeTSMC090nm__wire90 wire90_11(.a(net_286));
   orangeTSMC090nm__wire90 wire90_12(.a(net_284));
   orangeTSMC090nm__wire90 wire90_13(.a(net_180));
   orangeTSMC090nm__wire90 wire90_14(.a(net_184));
-  orangeTSMC090nm__wire90 wire90_17(.a(net_339));
+  orangeTSMC090nm__wire90 wire90_17(.a(net_340));
   orangeTSMC090nm__wire90 wire90_19(.a(net_386));
-  orangeTSMC090nm__wire90 wire90_20(.a(net_438));
-  orangeTSMC090nm__wire90 wire90_21(.a(net_451));
-  orangeTSMC090nm__wire90 wire90_22(.a(net_527));
+  orangeTSMC090nm__wire90 wire90_22(.a(net_695));
   orangeTSMC090nm__wire90 wire90_23(.a(net_534));
   orangeTSMC090nm__wire90 wire90_24(.a(net_538));
-  orangeTSMC090nm__wire90 wire90_25(.a(net_575));
+  orangeTSMC090nm__wire90 wire90_25(.a(not_Ld_));
+  orangeTSMC090nm__wire90 wire90_26(.a(net_612));
+  orangeTSMC090nm__wire90 wire90_27(.a(net_605));
+  orangeTSMC090nm__wire90 wire90_28(.a(net_634));
+  orangeTSMC090nm__wire90 wire90_31(.a(net_632));
+  orangeTSMC090nm__wire90 wire90_32(.a(do_zz_));
+  orangeTSMC090nm__wire90 wire90_36(.a(do[2]));
+  orangeTSMC090nm__wire90 wire90_37(.a(fire_Co_));
+  orangeTSMC090nm__wire90 wire90_39(.a(fire_zz_));
 endmodule   /* loopCountM__olcControl */
 
 module loopCountM__olcWcont(Dvoid, do_Co_, do_Ld_, do_reD_, inLO, sin,