have break signal flush input/output fifos

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index d21a446..05b66ee 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -57,7 +57,8 @@ module main
                     data_to_host_write_enable,
                     data_to_host_full,
                     data_to_fleet_empty,
-                    break_o);
+                    break_o,
+                    break);
 
    always @(posedge clk) break_last <= break_o;
    assign break = break_o && !break_last;

diff --git a/src/edu/berkeley/fleet/fpga/sasc_fifo4.v b/src/edu/berkeley/fleet/fpga/sasc_fifo4.v
index 6729f18..59aec78 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/sasc_fifo4.v
+++ b/src/edu/berkeley/fleet/fpga/sasc_fifo4.v
@@ -70,7 +70,6 @@ output  [7:0] dout;
 input          re;
 output         full, empty;
 
-
 ////////////////////////////////////////////////////////////////////
 //
 // Local Wires

diff --git a/src/edu/berkeley/fleet/fpga/sasc_top.v b/src/edu/berkeley/fleet/fpga/sasc_top.v
index 257597b..2f5a1ae 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/sasc_top.v
+++ b/src/edu/berkeley/fleet/fpga/sasc_top.v
@@ -90,7 +90,7 @@ module sasc_top(      clk, rst,
 
                        // Internal Interface
                        din_i, dout_o, re_i, we_i, full_o, empty_o,
-                        break_o);
+                        break_o, flush_i);
 
 input          clk;
 input          rst;
@@ -99,6 +99,7 @@ output                txd_o;
 input          cts_i;
 output         rts_o; 
 output          break_o;
+input           flush_i;
 reg break_r;
 input          sio_ce;
 input          sio_ce_x4;
@@ -149,7 +150,7 @@ reg         [5:0]   rxd_dly; //New input delay used to ensure no baud clocks
 //
 
 sasc_fifo4 tx_fifo(    .clk(           clk             ),
-                       .rst(           rst             ),
+                       .rst(           rst && !flush_i ),
                        .clr(           1'b0            ),
                        .din(           din_i           ),
                        .we(            we_i            ),
@@ -160,7 +161,7 @@ sasc_fifo4 tx_fifo( .clk(           clk             ),
                        );
 
 sasc_fifo4 rx_fifo(    .clk(           clk             ),
-                       .rst(           rst             ),
+                       .rst(           rst && !flush_i ),
                        .clr(           1'b0            ),
                        .din(           rxr[9:2]        ),
                        .we(            rx_we           ),