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testSignExtendedLiteral() passes
authorrkao <rkao>
Mon, 24 Nov 2008 21:09:36 +0000 (21:09 +0000)
committerrkao <rkao>
Mon, 24 Nov 2008 21:09:36 +0000 (21:09 +0000)
electric/dockPartOD.jelib patch | blob | history
electric/registersL.jelib patch | blob | history
testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java patch | blob | history
testCode/marina.spi patch | blob | history

diff --git a/electric/dockPartOD.jelib b/electric/dockPartOD.jelib
index 3ff196b..b2df796 100755 (executable)
--- a/electric/dockPartOD.jelib
+++ b/electric/dockPartOD.jelib
@@ -1,5 +1,5 @@
 # header information:
-HdockPartOD|8.08j
+HdockPartOD|8.08k
 
 # Views:
 Vicon|ic
@@ -352,7 +352,7 @@ Esel[long]||D4G2;|conn@7|a|I
 X
 
 # Cell dataAddrRegAll;1{ic}
-CdataAddrRegAll;1{ic}||artwork|1217252608495|1227284210332|E
+CdataAddrRegAll;1{ic}||artwork|1217252608495|1227553422777|E
 Ngeneric:Facet-Center|art@0||0|0||||AV
 Nschematic:Bus_Pin|pin@0||-5|-5|-1|-1||
 Ngeneric:Invisible-Pin|pin@1||-4|-5|1|1||
@@ -401,7 +401,7 @@ AThicker|net@69|||FS1800|pin@61||-4|-4|pin@62||4|-4
 Efire[M,L]||D5G2;|pin@8||I
 Eflag[C]||D5G2;|pin@57||O
 EinA[T,1:37]|inA[1:37,T],ain[1:14]|D5G2;|pin@0||I
-Elit[1:19]|lit[19,20],od[1:18]|D5G2;|pin@10||I
+Elit[1:19]|od[1:18],lit[19,20]|D5G2;|pin@10||I
 EoutS[T,1:37]|outS[1:37,T],aout[1:14]|D5G2;|pin@4||O
 EsigA||D5G2;|pin@58||I
 EsigS||D5G2;|pin@59||I
@@ -687,7 +687,7 @@ Evdd_36||D5G2;|thePathR@0|vdd_10|P
 X
 
 # Cell dataAddrRegAll;1{sch}
-CdataAddrRegAll;1{sch}||schematic|1216109820230|1227284210332|
+CdataAddrRegAll;1{sch}||schematic|1216109820230|1227553422777|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||37|0||||
 NOff-Page|conn@2||-32.5|12|||XRR|
@@ -775,7 +775,7 @@ Awire|sign|D5G2;||2700|pin@32||-8|-7|pin@33||-8|-4
 Efire[M,L]||D4G2;|conn@5|a|I
 Eflag[C]||D6G2;|conn@10|y|O
 EinA[T,1:37]|inA[1:37,T],ain[1:14]|D4G2;|conn@2|a|I
-Elit[1:19]|lit[19,20],od[1:18]|D4G2;|conn@3|a|I
+Elit[1:19]|od[1:18],lit[19,20]|D4G2;|conn@3|a|I
 EoutS[T,1:37]|outS[1:37,T],aout[1:14]|D6G2;|conn@0|y|O
 EsigA||D4G2;|conn@12|a|I
 EsigS||D4G2;|conn@11|a|I
diff --git a/electric/registersL.jelib b/electric/registersL.jelib
index 096d747..f5353a0 100755 (executable)
--- a/electric/registersL.jelib
+++ b/electric/registersL.jelib
@@ -8405,7 +8405,7 @@ Evdd_3||D5G2;|dataMux4@0|vdd_1|P
 X
 
 # Cell dataMuxAll;1{sch}
-CdataMuxAll;1{sch}||schematic|1216087490865|1227290795965|I
+CdataMuxAll;1{sch}||schematic|1216087490865|1227556738639|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@2||-18|-6||||
 NOff-Page|conn@3||31|6||||
@@ -8413,12 +8413,14 @@ NOff-Page|conn@6||28|0||||
 NOff-Page|conn@8||31|30||||
 IdataMux4;1{ic}|dataMux4@0||22|12|||D5G4;
 IdataMuxAll;1{ic}|dataMuxA@0||22|43.5|||D5G4;
-IredFour:inv;1{ic}|inv@0||16|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S80|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFour:inv;1{ic}|inv@2||1.5|-8|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFour:inv;1{ic}|inv@0||18|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S80|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFour:inv;1{ic}|inv@2||2.5|-8|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFour:inv;1{ic}|inv@5||-19|1|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFour:inv;1{ic}|inv@6||6|24|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S100|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFour:inv;1{ic}|inv@7||24|24|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S80|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFour:nand2_sy;1{ic}|nand2_sy@0||1|0|Y||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFour:inv;1{ic}|inv@8||12.5|-8|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFour:inv;1{ic}|inv@9||11.5|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S40|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFour:nand2_sy;1{ic}|nand2_sy@0||-2|0|Y||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 Ngeneric:Invisible-Pin|pin@0||-11.5|49.5|||||ART_message(D5G6;)SdataMuxAll
 Ngeneric:Invisible-Pin|pin@1||-11.5|35.5|||||ART_message(D5G3;)Sies 20 November 2008
 Ngeneric:Invisible-Pin|pin@2||-11.5|44.5|||||ART_message(D5G3;)Sthe overlap part of the shadow register
@@ -8428,8 +8430,8 @@ NBus_Pin|pin@11||31|10|-1|-1||
 NBus_Pin|pin@12||31|15.5|-1|-1||
 NBus_Pin|pin@13||18.5|12|-1|-1||
 NBus_Pin|pin@14||18.5|6|-1|-1||
-NWire_Pin|pin@18||8|-8||||
-NWire_Pin|pin@19||8|-12.5||||
+NWire_Pin|pin@18||23|-8||||
+NWire_Pin|pin@19||23|-12.5||||
 NWire_Pin|pin@34||-5|-1||||
 Ngeneric:Invisible-Pin|pin@36||-44|24|||||ART_message(D3G2;)S["lit[20] = TRUE selects",the latched input,for shift literal.]
 NWire_Pin|pin@38||-5|-8||||
@@ -8446,7 +8448,7 @@ NWire_Pin|pin@67||-26|1||||
 NWire_Pin|pin@68||-26|6||||
 Ngeneric:Invisible-Pin|pin@69||-11.5|40.5|||||ART_message(D5G3;)Splus power drivers for selection
 IorangeTSMC090nm:wire90;1{ic}|wire90@8||-10.5|1|||D0G4;|ATTR_L(D5G1;PUD)D953.8999999999996|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
-IorangeTSMC090nm:wire90;1{ic}|wire90@9||8.5|0|||D0G4;|ATTR_L(D5G1;PUD)D668.1999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@9||4.5|0|||D0G4;|ATTR_L(D5G1;PUD)D668.1999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@10||31.5|24|||D0G4;|ATTR_L(D5G1;PUD)D4189.700000000002|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@11||13.5|24|||D0G4;|ATTR_L(D5G1;PUD)D6941.500000000004|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
 Awire|lit[15]|D5G2;||900|pin@34||-5|-1|pin@38||-5|-8
@@ -8456,13 +8458,11 @@ Awire|net@2|||0|dataMux4@0|inB|23|8|pin@5||22|8
 Awire|net@3|||900|pin@5||22|8|pin@6||22|0
 Abus|net@12||-0.5|IJ1800|dataMux4@0|out[1:4]|27|10|pin@11||31|10
 Abus|net@14||-0.5|IJ0|dataMux4@0|lit[16:19]|21|12|pin@13||18.5|12
-Awire|net@26|||1800|inv@2|out|4|-8|pin@18||8|-8
 Awire|net@61|||1800|inv@5|out|-16.5|1|wire90@8|a|-13|1
-Awire|net@64|||1800|wire90@9|b|11|0|inv@0|in|13.5|0
-Awire|net@67|||0|inv@2|in|-1|-8|pin@38||-5|-8
-Awire|net@75|||0|wire90@9|a|6|0|nand2_sy@0|out|3.5|0
-Awire|net@80|||1800|pin@34||-5|-1|nand2_sy@0|inb|-1.5|-1
-Awire|net@104|||1800|inv@0|out|18.5|0|pin@6||22|0
+Awire|net@67|||0|inv@2|in|0|-8|pin@38||-5|-8
+Awire|net@75|||0|wire90@9|a|2|0|nand2_sy@0|out|0.5|0
+Awire|net@80|||1800|pin@34||-5|-1|nand2_sy@0|inb|-4.5|-1
+Awire|net@104|||1800|inv@0|out|20.5|0|pin@6||22|0
 Awire|net@105|||0|conn@6|a|26|0|pin@6||22|0
 Abus|net@109||-0.5|IJ0|pin@14||18.5|6|pin@59||14|6
 Awire|net@110|||1800|pin@60||18|24|inv@7|in|21.5|24
@@ -8470,12 +8470,16 @@ Awire|net@111|||1800|inv@6|out|8.5|24|wire90@11|a|11|24
 Awire|net@112|||0|pin@60||18|24|wire90@11|b|16|24
 Awire|net@113|||1800|inv@7|out|26.5|24|wire90@10|a|29|24
 Awire|net@114|||0|pin@62||36|24|wire90@10|b|34|24
-Awire|net@115|||0|nand2_sy@0|ina|-1.5|1|pin@64||-6|1
+Awire|net@115|||0|nand2_sy@0|ina|-4.5|1|pin@64||-6|1
 Awire|net@116|||0|pin@64||-6|1|wire90@8|b|-8|1
 Awire|net@117|||2700|pin@64||-6|1|pin@65||-6|24
 Awire|net@118|||1800|pin@65||-6|24|inv@6|in|3.5|24
 Awire|net@119|||0|inv@5|in|-21.5|1|pin@67||-26|1
-Awire|out[15]|D5G2;||900|pin@18||8|-8|pin@19||8|-12.5
+Awire|net@120|||1800|inv@2|out|5|-8|inv@8|in|10|-8
+Awire|net@121|||1800|inv@8|out|15|-8|pin@18||23|-8
+Awire|net@122|||1800|inv@9|out|14|0|inv@0|in|15.5|0
+Awire|net@123|||0|inv@9|in|9|0|wire90@9|b|7|0
+Awire|out[15]|D5G2;||900|pin@18||23|-8|pin@19||23|-12.5
 Abus|out[16:19]|D5G2;|-0.5|IJ2700|pin@11||31|10|pin@12||31|15.5
 Awire|s[F]|D5G2;||900|pin@62||36|24|pin@63||36|19.5
 Abus|s[T,F]|D5G2;|-0.5|IJ2700|dataMux4@0|s[T,F]|25|13|pin@66||25|18
@@ -10763,7 +10767,7 @@ Evdd_16||D5G2;|strap1hV@19|vdd_5|P
 X
 
 # Cell theDregister;1{ic}
-CtheDregister;1{ic}||artwork|1225675331036|1227290795965|EI
+CtheDregister;1{ic}||artwork|1225675331036|1227561810793|EI
 Ngeneric:Facet-Center|art@0||0|0||||AV
 Nschematic:Bus_Pin|pin@3||-2|3|-1|-1||
 Nschematic:Bus_Pin|pin@4||-3|-1|-1|-1||
@@ -10798,6 +10802,7 @@ NPin|pin@43||-3|-8|1|1||
 NPin|pin@44||-3|-12|1|1||
 NPin|pin@45||-2|-7|1|1||
 NPin|pin@46||-2|-8|1|1||
+Nschematic:Bus_Pin|pin@47||-3|-3|-1|-1||
 AThicker|net@0|||FS900|pin@20||-2|-2|pin@10||-2|-3
 AThicker|net@1|||FS2700|pin@11||-3|-2|pin@12||-3|2
 AThicker|net@2|||FS2700|pin@13||1|2|pin@14||1|3
@@ -10827,6 +10832,7 @@ Efire[A,B]|fire[M,L]|D5G2;|pin@3||I
 Eflag[C]||D5G2;|pin@37||O
 EinA[1:37]|inA[T,1:37]|D5G2;|pin@4||I
 EinB[1:19]|lit[1:19]|D5G2;|pin@5||I
+Eod[17]||D5G2;|pin@47||U
 EoutS[1:37]|outS[T,1:37]|D5G2;|pin@6||O
 Es[T,F]||D5G2;|pin@7||I
 EsigA||D5G2;|pin@38||I
@@ -11915,7 +11921,7 @@ Evdd_28||D5G2;|data2in1@3|vdd_6|P
 X
 
 # Cell theDregister;3{sch}
-CtheDregister;3{sch}||schematic|1225653382016|1227315536817|I
+CtheDregister;3{sch}||schematic|1225653382016|1227561695354|I
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-52.5|-4|||Y|
 NOff-Page|conn@2||-60|-12|||Y|
@@ -11926,6 +11932,7 @@ NOff-Page|conn@16||12|33.5|||YR|
 NOff-Page|conn@17||-1.5|-20||||
 NOff-Page|conn@18||-23|-22|||Y|
 NOff-Page|conn@19||-23|-18|||Y|
+NOff-Page|conn@20||-60|-26||||
 IdRegDrive;1{ic}|dRegDriv@1||-41.5|0|||D5G4;
 IdRegSignal;1{ic}|dRegSign@0||-12|-20|||D5G4;
 IdataMux18;1{ic}|dataMux1@0||9|24|||D5G4;
@@ -11986,7 +11993,6 @@ Abus|inA[20:37]|D5G2;|-0.5|IJ2700|pin@25||27|-6|pin@26||27|-1
 Abus|inA[T,19]|D5G2;|-0.5|IJ2700|pin@64||-55.5|-1|pin@65||-55.5|3
 Abus|inB[20:37]|D5G2;|-0.5|IJ2700|pin@28||27|1|pin@43||27|22
 Abus|lit[1:18]|D5G2;|-0.5|IJ900|pin@31||-21|6|pin@32||-21|1
-Awire|lit[17]|D5G2;||900|pin@91||-48|-6|pin@100||-48|-26
 Awire|lit[19]|D5G2;||2700|pin@95||-48|1|pin@96||-48|4.5
 Awire|net@3|||900|pin@5||34|12|lat[20:37]|hcl[B]|34|3
 Awire|net@6|||2700|pin@7||34|-12|lat[20:37]|hcl[A]|34|-3
@@ -12025,6 +12031,8 @@ Awire|net@163|||900|pin@103||-18|-21|pin@108||-18|-22
 Awire|net@164|||2700|pin@101||-18|-19|pin@109||-18|-18
 Awire|net@168|||0|pin@108||-18|-22|conn@18|y|-21|-22
 Awire|net@169|||0|pin@109||-18|-18|conn@19|y|-21|-18
+Awire|net@170|||1800|conn@20|y|-58|-26|pin@100||-48|-26
+Awire|net@171|||900|pin@91||-48|-6|pin@100||-48|-26
 Abus|outS[1:18]|D5G2;|-0.5|IJ900|pin@33||-6|0|pin@34||-6|-5
 Abus|outS[20:37]|D5G2;|-0.5|IJ900|pin@36||42|0|pin@37||42|-6
 Abus|outS[T,19]|D5G2;|-0.5|IJ2700|pin@68||-33|0|pin@69||-33|3
@@ -12032,6 +12040,7 @@ Efire[A,B]|fire[M,L]|D4G2;|conn@0|a|I
 Eflag[C]||D6G2;|conn@17|y|O
 EinA[T,1:37]||D4G2;|conn@2|a|I
 EinB[T,1:19]|lit[1:19]|D4G2;|conn@12|a|I
+Eod[17]||D5G2;X-4;|conn@20|a|U
 EoutS[T,1:37]||D6G2;|conn@9|y|O
 Es[T,F]||D4G2;|conn@16|a|I
 EsigA||D4G2;|conn@19|a|I
diff --git a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
index 74b91f7..007e3e5 100644 (file)
--- a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
+++ b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
@@ -1339,7 +1339,7 @@ public class MarinaTest {
             fatal(dataItems.size()!=1, "expected exactly one data item, got " + dataItems.size());
 
             BitVector bv = dataItems.get(0);
-            prln("got back " + bv);
+            prln("got back " + MarinaUtils.extractData(bv).getState());
 
             boolean mismatch = false;
             String err = "";
diff --git a/testCode/marina.spi b/testCode/marina.spi
index c806be0..aa4d239 100644 (file)
--- a/testCode/marina.spi
+++ b/testCode/marina.spi
@@ -1,7 +1,7 @@
 *** SPICE deck for cell marina{sch} from library marinaL
 *** Created on Mon Nov 17, 2008 08:47:24
 *** Last revised on Sun Nov 23, 2008 13:52:46
-*** Written on Sun Nov 23, 2008 13:52:59 by Electric VLSI Design System, 
+*** Written on Mon Nov 24, 2008 13:27:07 by Electric VLSI Design System, 
 *version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -138,6 +138,24 @@ XNMOS@0 out in gnd NMOSx-X_100
 XPMOS@0 out in vdd PMOSx-X_100
 .ENDS inv-X_100
 
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_40 d g s
+MNMOSf@0 d g s gnd nch W='120*(1+ABN/sqrt(120*2))' L='2' 
++DELVTO='AVT0N/sqrt(120*2)'
+.ENDS NMOSx-X_40
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_40 d g s
+MPMOSf@0 d g s vdd pch W='240*(1+ABP/sqrt(240*2))' L='2'  
++DELVTO='AVT0P/sqrt(240*2)'
+.ENDS PMOSx-X_40
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_40 in out
+XNMOS@0 out in gnd NMOSx-X_40
+XPMOS@0 out in vdd PMOSx-X_40
+.ENDS inv-X_40
+
 *** CELL: orangeTSMC090nm:PMOSx{sch}
 .SUBCKT PMOSx-X_20 d g s
 MPMOSf@0 d g s vdd pch W='120*(1+ABP/sqrt(120*2))' L='2'  
@@ -238,14 +256,16 @@ Xwire@0 a b wire-C_0_011f-6941_5-R_34_667m
 +out[16] out[17] out[18] out[19] s[F] s[T] sign
 XdataMux4@0 lit[16] lit[17] lit[18] lit[19] out[16] out[17] out[18] out[19] 
 +s[F] s[T] sign dataMux4
-Xinv@0 net@64 sign inv-X_80
-Xinv@2 lit[15] out[15] inv-X_10
+Xinv@0 net@122 sign inv-X_80
+Xinv@2 lit[15] net@120 inv-X_10
 Xinv@5 lit[20] net@61 inv-X_30
 Xinv@6 net@115 net@111 inv-X_100
 Xinv@7 s[T] net@113 inv-X_80
+Xinv@8 net@120 out[15] inv-X_10
+Xinv@9 net@123 net@122 inv-X_40
 Xnand2_sy@0 net@115 lit[15] net@75 nand2_sy-X_20
 Xwire90@8 net@61 net@115 wire90-953_9-layer_1-width_3
-Xwire90@9 net@75 net@64 wire90-668_2-layer_1-width_3
+Xwire90@9 net@75 net@123 wire90-668_2-layer_1-width_3
 Xwire90@10 net@113 s[F] wire90-4189_7-layer_1-width_3
 Xwire90@11 net@111 s[T] wire90-6941_5-layer_1-width_3
 .ENDS dataMuxAll
@@ -430,12 +450,6 @@ Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3
 Xwire90@2 net@19 net@17 wire90-555_8-layer_1-width_3
 .ENDS latch2in60C
 
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_40 d g s
-MNMOSf@0 d g s gnd nch W='120*(1+ABN/sqrt(120*2))' L='2' 
-+DELVTO='AVT0N/sqrt(120*2)'
-.ENDS NMOSx-X_40
-
 *** CELL: redFour:nms2{sch}
 .SUBCKT nms2-X_20 d g g2
 XNMOS@0 d g2 net@0 NMOSx-X_40
@@ -642,15 +656,15 @@ Xwire90@0 net@39 net@42 wire90-277_3-layer_1-width_3
 +inA[30] inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] 
 +inA[5] inA[6] inA[7] inA[8] inA[9] inA[T] lit[10] lit[11] lit[12] lit[13] 
 +lit[14] lit[15] lit[16] lit[17] lit[18] lit[19] lit[1] lit[2] lit[3] lit[4] 
-+lit[5] lit[6] lit[7] lit[8] lit[9] outS[10] outS[11] outS[12] outS[13] 
++lit[5] lit[6] lit[7] lit[8] lit[9] od[17] outS[10] outS[11] outS[12] outS[13] 
 +outS[14] outS[15] outS[16] outS[17] outS[18] outS[19] outS[1] outS[20] 
 +outS[21] outS[22] outS[23] outS[24] outS[25] outS[26] outS[27] outS[28] 
 +outS[29] outS[2] outS[30] outS[31] outS[32] outS[33] outS[34] outS[35] 
 +outS[36] outS[37] outS[3] outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] 
 +outS[T] s[F] s[T] sigA sigS sign
-XdRegDriv@1 lit[17] dcl[L] dcl[M] fire[L] fire[M] lit[19] inA[19] inA[T] 
+XdRegDriv@1 od[17] dcl[L] dcl[M] fire[L] fire[M] lit[19] inA[19] inA[T] 
 +outS[19] outS[T] dRegDrive
-XdRegSign@0 lit[17] net@6 fire[M] flag[C] sigA sigS dRegSignal
+XdRegSign@0 od[17] net@6 fire[M] flag[C] sigA sigS dRegSignal
 XdataMux1@0 outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] outS[16] 
 +outS[17] outS[18] outS[1] outS[2] outS[3] outS[4] outS[5] outS[6] outS[7] 
 +outS[8] outS[9] inB[29] inB[30] inB[31] inB[32] inB[33] inB[34] inB[35] 
@@ -794,11 +808,12 @@ XtheDregi@0 fire[L] fire[M] flag[C] inA[10] inA[11] inA[12] inA[13] inA[14]
 +inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] inA[5] 
 +inA[6] inA[7] inA[8] inA[9] inA[T] od[10] od[11] od[12] od[13] od[14] bk[15] 
 +bk[16] bk[17] bk[18] bk[19] od[1] od[2] od[3] od[4] od[5] od[6] od[7] od[8] 
-+od[9] outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] outS[16] outS[17] 
-+outS[18] outS[19] outS[1] outS[20] outS[21] outS[22] outS[23] outS[24] 
-+outS[25] outS[26] outS[27] outS[28] outS[29] outS[2] outS[30] outS[31] 
-+outS[32] outS[33] outS[34] outS[35] outS[36] outS[37] outS[3] outS[4] outS[5] 
-+outS[6] outS[7] outS[8] outS[9] outS[T] s[F] s[T] sigA sigS sign theDregister
++od[9] od[17] outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] outS[16] 
++outS[17] outS[18] outS[19] outS[1] outS[20] outS[21] outS[22] outS[23] 
++outS[24] outS[25] outS[26] outS[27] outS[28] outS[29] outS[2] outS[30] 
++outS[31] outS[32] outS[33] outS[34] outS[35] outS[36] outS[37] outS[3] 
++outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] outS[T] s[F] s[T] sigA sigS 
++sign theDregister
 XthePathR@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
 +ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] aout[10] aout[11] aout[12] aout[13] 
 +aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] 
@@ -1615,12 +1630,6 @@ XPMOS@1 out ina vdd PMOSx-X_10
 Xnms2_sy@0 out ina inb nms2_sy-X_10
 .ENDS nand2_sy-X_10
 
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_40 d g s
-MPMOSf@0 d g s vdd pch W='240*(1+ABP/sqrt(240*2))' L='2'  
-+DELVTO='AVT0P/sqrt(240*2)'
-.ENDS PMOSx-X_40
-
 *** CELL: redFour:pms2{sch}
 .SUBCKT pms2-X_20 d g g2
 XPMOS@0 net@2 g vdd PMOSx-X_40
@@ -8936,12 +8945,6 @@ Xwire90@83 net@954 net@964 wire90-353_6-layer_1-width_3
 Xwire90@84 net@955 net@959 wire90-309_5-layer_1-width_3
 .ENDS array
 
-*** CELL: redFour:inv{sch}
-.SUBCKT inv-X_40 in out
-XNMOS@0 out in gnd NMOSx-X_40
-XPMOS@0 out in vdd PMOSx-X_40
-.ENDS inv-X_40
-
 *** CELL: orangeTSMC090nm:wire{sch}
 .SUBCKT wire-C_0_011f-262_8-R_34_667m a b
 Ccap@0 gnd net@14 0.964f
@@ -9550,9 +9553,9 @@ XdataAddr@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
 +inD[15] inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] 
 +inD[23] inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] 
 +inD[31] inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] 
-+inD[6] inD[7] inD[8] inD[9] od[15] od[1] od[2] od[12] od[13] od[14] od[15] 
-+od[16] od[17] od[18] od[19] od[20] od[3] od[4] od[5] od[6] od[7] od[8] od[9] 
-+od[10] od[11] outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] outS[16] 
++inD[6] inD[7] inD[8] inD[9] od[15] od[19] od[20] od[10] od[11] od[12] od[13] 
++od[14] od[15] od[16] od[17] od[18] od[1] od[2] od[3] od[4] od[5] od[6] od[7] 
++od[8] od[9] outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] outS[16] 
 +outS[17] outS[18] outS[19] outS[1] outS[20] outS[21] outS[22] outS[23] 
 +outS[24] outS[25] outS[26] outS[27] outS[28] outS[29] outS[2] outS[30] 
 +outS[31] outS[32] outS[33] outS[34] outS[35] outS[36] outS[37] outS[3] 
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