new files from Ivan, 04-May

diff --git a/electric/predicateM.jelib b/electric/predicateM.jelib
index 5c85a0b..620a1fe 100755 (executable)
--- a/electric/predicateM.jelib
+++ b/electric/predicateM.jelib
@@ -1,5 +1,5 @@
 # header information:
-HpredicateM|8.08k
+HpredicateM|8.09a
 
 # Views:
 Vicon|ic
@@ -529,7 +529,7 @@ EresetLO||D4G2;|conn@4|a|I
 X
 
 # Cell ohPredAll;1{ic}
-CohPredAll;1{ic}||artwork|1231971642098|1241321017421|E
+CohPredAll;1{ic}||artwork|1231971642098|1241472740268|E
 Ngeneric:Facet-Center|art@0||0|0||||AV
 Nschematic:Bus_Pin|pin@0||2|-7|-1|-1||
 Nschematic:Bus_Pin|pin@2||-4|-3|-1|-1||
@@ -560,12 +560,12 @@ NPin|pin@43||-2|7|1|1||
 Ngeneric:Invisible-Pin|pin@44||0|8|||||ART_message(D5G1.5;)S3
 NPin|pin@47||2|-6|1|1||
 NPin|pin@48||2|-7|1|1||
-Nschematic:Bus_Pin|pin@49||-1|3|-1|-1||
-Nschematic:Bus_Pin|pin@52||3|-3|-1|-1||
-Nschematic:Bus_Pin|pin@53||5|-3||||
+Nschematic:Bus_Pin|pin@49||-4|0|-1|-1||
+NPin|pin@50||-3|0|1|1||
+NPin|pin@51||-4|0|1|1||
 Aschematic:bus|net@1||-0.5|IJ0|pin@3||-3|-3|pin@2||-4|-3
 Aschematic:bus|net@5||-0.5|IJ1800|pin@11||3|3|pin@10||4|3
-AThicker|net@7|||FS2700|pin@14||-3|-6|pin@15||-3|6
+AThicker|net@7|||FS2700|pin@50||-3|0|pin@15||-3|6
 AThicker|net@13|||FS1800|pin@15||-3|6|pin@20||0|6
 AThicker|net@14|||FS2700|pin@20||0|6|pin@21||0|7
 Aschematic:bus|net@15||-0.5|IJ0|pin@23||-3|3|pin@22||-4|3
@@ -583,13 +583,14 @@ AThicker|net@36|||FS1800|pin@14||-3|-6|pin@47||2|-6
 AThicker|net@37|||FS2700|pin@17||3|-6|pin@16||3|6
 AThicker|net@38|||FS1800|pin@47||2|-6|pin@17||3|-6
 AThicker|net@39|||FS900|pin@47||2|-6|pin@48||2|-7
-Aschematic:bus|net@41|||IJ1800|pin@52||3|-3|pin@53||5|-3
+AThicker|net@40|||FS2700|pin@14||-3|-6|pin@50||-3|0
+AThicker|net@41|||FS0|pin@50||-3|0|pin@51||-4|0
 Edo[Lo,Co,Tp,Mv,Lt]|do[ins]|D5G2;|pin@0||O
-Eflag[A,B][set,clr]|flag[A,B,D][set,clr]|D5G2;X-5;Y-1.5;|pin@2||I
+Eflag[A,B][set,clr]|flag[A,B,D][set,clr]|D5G2;|pin@2||I
 Esel[Fl,Lo,Co,Tp,Mv,Lt,Cd]|m1[Fl,rD]|D5G2;|pin@25||I
 Em1cate[1:6][T,F]||D5G2;|pin@22||I
 Ep2p,p1p,rd|p2p,p1p,rd,mc|D5G2;|pin@32||B
-Eps[Fl]||D5G2;|pin@53||I
+Eps[Fl]||D5G2;|pin@49||I
 Esucc[skip,do]|ps[skip,do]|D5G2;|pin@10||O
 Esin||D5G2;|pin@34||I
 Esout||D5G2;|pin@36||O

diff --git a/electric/programsM.jelib b/electric/programsM.jelib
index 46bd88f..bd1815b 100755 (executable)
--- a/electric/programsM.jelib
+++ b/electric/programsM.jelib
@@ -369,7 +369,7 @@ Eshift||D5G2;|pin@4||I
 X
 
 # Cell programA;1{sch}
-CprogramA;1{sch}||schematic|1219331355301|1240953953277|
+CprogramA;1{sch}||schematic|1219331355301|1241459534985|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 IwiresL:bitAssignments;1{ic}|bitAssig@0||22|11.5||V|D5G4;
 NOff-Page|conn@0||-24|18|||X|
@@ -411,11 +411,11 @@ NBus_Pin|pin@538||-20|36|-1|-1||
 NBus_Pin|pin@539||-20|30|-1|-1||
 IprogramA;1{ic}|programA@0||25|36|||D5G4;
 IprogramPartsM:flClrAB;1{ic}|skClrAB@1||0|6|||D5G4;
-IskipAlways;1{ic}|skipAlwa@1||-36|6|||D5G4;
-IskipAlways;1{ic}|skipAlwa@2||-36|-42|||D5G4;
 IskipNever;1{ic}|skipNeve@8||-36|-6|||D5G4;
 IskipNever;1{ic}|skipNeve@13||-36|-30|||D5G4;
-IskipWhenD;1{ic}|skipWhen@9||-36|-54|||D5G4;
+IskipNever;1{ic}|skipNeve@14||-36|6|||D5G4;
+IskipNever;1{ic}|skipNeve@15||-36|-42|||D5G4;
+IskipNever;1{ic}|skipNeve@16||-36|-54|||D5G4;
 IskipWhenD;1{ic}|skipWhen@11||-36|-18|||D5G4;
 IprogramPartsM:srDrive;1{ic}|srDrive@7||-30|24|X||D5G4;
 IprogramPartsM:srFirst;1{ic}|srFirst@1||-49|6|||D5G4;
@@ -453,9 +453,9 @@ Awire|net@727|||2700|pin@399||-28|18|srDrive@7|mc|-28|21
 Awire|net@728|||0|conn@1|y|-21|24|srDrive@7|shift|-26|24
 Awire|net@729|||0|conn@0|y|-26|18|pin@399||-28|18
 Abus|net@905||-0.5|IJ1800|pin@365||-42|36|lat[1:36]|out[1]|-32|36
-Abus|net@906||-0.5|IJ900|skipAlwa@1|intD[31:36]|-36|8|skipNeve@8|intD[31:36]|-36|-4
-Abus|net@925||-0.5|IJ1800|srFirst@1|out[T,F]|-45|6|skipAlwa@1|s[T,F]|-40|6
-Abus|net@928||-0.5|IJ1800|skipAlwa@1|s[T,F]|-40|6|insSetFl@7|s[T,F]|-24|6
+Abus|net@906||-0.5|IJ900|skipNeve@14|intD[31:36]|-36|8|skipNeve@8|intD[31:36]|-36|-4
+Abus|net@925||-0.5|IJ1800|srFirst@1|out[T,F]|-45|6|skipNeve@14|s[T,F]|-40|6
+Abus|net@928||-0.5|IJ1800|skipNeve@14|s[T,F]|-40|6|insSetFl@7|s[T,F]|-24|6
 Abus|net@929||-0.5|IJ1800|insSetFl@7|s[T,F]|-24|6|skClrAB@1|s[T,F]|-6|6
 Abus|net@932||-0.5|IJ1800|srThru@4|out[T,F]|-45|-6|skipNeve@8|s[T,F]|-40|-6
 Abus|net@933||-0.5|IJ1800|insLoadO@5|s[T,F]|-24|-6|number3@2|s[T,F]|-6|-6
@@ -463,21 +463,21 @@ Abus|net@934||-0.5|IJ0|insLoadO@5|s[T,F]|-24|-6|skipNeve@8|s[T,F]|-40|-6
 Abus|net@935||-0.5|IJ2700|insLoadO@5|outD[19:30]|-18|-4|insSetFl@7|outD[19:30]|-18|8
 Abus|net@936||-0.5|IJ2700|number3@2|intD[1:18]|0|-4|skClrAB@1|intD[1:18]|0|8
 Abus|net@942||-0.5|IJ1800|skipNeve@13|s[T,F]|-40|-30|insMove@5|s[T,F]|-24|-30
-Abus|net@944||-0.5|IJ1800|skipAlwa@2|s[T,F]|-40|-42|insSetFl@13|s[T,F]|-24|-42
+Abus|net@944||-0.5|IJ1800|skipNeve@15|s[T,F]|-40|-42|insSetFl@13|s[T,F]|-24|-42
 Abus|net@946||-0.5|IJ1800|skipWhen@11|s[T,F]|-40|-18|insLoadI@2|s[T,F]|-24|-18
-Abus|net@947||-0.5|IJ1800|srThru@7|out[T,F]|-45|-54|skipWhen@9|s[T,F]|-40|-54
-Abus|net@948||-0.5|IJ1800|skipWhen@9|s[T,F]|-40|-54|insDecre@3|in[T,F]|-24|-54
+Abus|net@947||-0.5|IJ1800|srThru@7|out[T,F]|-45|-54|skipNeve@16|s[T,F]|-40|-54
+Abus|net@948||-0.5|IJ1800|skipNeve@16|s[T,F]|-40|-54|insDecre@3|in[T,F]|-24|-54
 Abus|net@958||-0.5|IJ1800|insDecre@3|in[T,F]|-24|-54|numberXX@1|s[T,F]|-6|-54
 Abus|net@960||-0.5|IJ1800|lat[1:36]|in[1]|-28|36|pin@538||-20|36
 Abus|net@962||-0.5|IJ1800|insMove@5|s[T,F]|-24|-30|mvBitsCa@3|s[T,F]|-6|-30
 Abus|net@963||-0.5|IJ1800|insSetFl@13|s[T,F]|-24|-42|flBgets-@3|s[T,F]|-6|-42
 Abus|net@964||-0.5|IJ1800|insLoadI@2|s[T,F]|-24|-18|number3@3|s[T,F]|-6|-18
 Abus|net@965||-0.5|IJ0|skipNeve@13|s[T,F]|-40|-30|srThru@5|out[T,F]|-45|-30
-Abus|net@966||-0.5|IJ0|skipAlwa@2|s[T,F]|-40|-42|srThru@6|out[T,F]|-45|-42
+Abus|net@966||-0.5|IJ0|skipNeve@15|s[T,F]|-40|-42|srThru@6|out[T,F]|-45|-42
 Abus|net@967||-0.5|IJ1800|srLoop@1|out[T,F]|-45|-18|skipWhen@11|s[T,F]|-40|-18
 Abus|net@968||-0.5|IJ900|skipNeve@8|intD[31:36]|-36|-4|skipWhen@11|intD[31:36]|-36|-16
-Abus|net@969||-0.5|IJ2700|skipAlwa@2|intD[31:36]|-36|-40|skipNeve@13|intD[31:36]|-36|-28
-Abus|net@970||-0.5|IJ2700|skipWhen@9|intD[31:36]|-36|-52|skipAlwa@2|intD[31:36]|-36|-40
+Abus|net@969||-0.5|IJ2700|skipNeve@15|intD[31:36]|-36|-40|skipNeve@13|intD[31:36]|-36|-28
+Abus|net@970||-0.5|IJ2700|skipNeve@16|intD[31:36]|-36|-52|skipNeve@15|intD[31:36]|-36|-40
 Abus|net@971||-0.5|IJ2700|skipNeve@13|intD[31:36]|-36|-28|skipWhen@11|intD[31:36]|-36|-16
 Abus|net@972||-0.5|IJ900|insLoadO@5|outD[19:30]|-18|-4|insLoadI@2|outD[19:30]|-18|-16
 Abus|net@973||-0.5|IJ900|insLoadI@2|outD[19:30]|-18|-16|insMove@5|outD[19:30]|-18|-28
@@ -490,7 +490,7 @@ Abus|net@979||-0.5|IJ2700|number3@3|intD[1:18]|0|-16|number3@2|intD[1:18]|0|-4
 Abus|val[1:18]|D5G2;|-0.5|IJ2700|skClrAB@1|intD[1:18]|0|8|pin@534||0|12
 Abus|val[1:36]|D5G2;|-0.5|IJ900|pin@538||-20|36|pin@539||-20|30
 Abus|val[19:30]|D5G2;|-0.5|IJ2700|insSetFl@7|outD[19:30]|-18|8|pin@533||-18|12
-Abus|val[31:36]|D5G2;|-0.5|IJ2700|skipAlwa@1|intD[31:36]|-36|8|pin@518||-36|12
+Abus|val[31:36]|D5G2;|-0.5|IJ2700|skipNeve@14|intD[31:36]|-36|8|pin@518||-36|12
 Edata[1:36]||D6G2;|conn@3|y|O
 Emc||D4G2;|conn@0|a|I
 Eshift||D4G2;|conn@1|a|I

diff --git a/electric/stagesM.jelib b/electric/stagesM.jelib
index 945fbb7..c8b24b4 100755 (executable)
--- a/electric/stagesM.jelib
+++ b/electric/stagesM.jelib
@@ -1,5 +1,5 @@
 # header information:
-HstagesM|8.08k
+HstagesM|8.09a
 
 # Views:
 Vicon|ic
@@ -5902,7 +5902,7 @@ Etake[1]|take[od]|D6G2;|conn@3|y|O
 X
 
 # Cell outDockCenter;1{ic}
-CoutDockCenter;1{ic}||artwork|1237129228588|1241320861699|EI
+CoutDockCenter;1{ic}||artwork|1237129228588|1241472893214|EI
 Ngeneric:Facet-Center|art@0||0|0||||AV
 Nschematic:Bus_Pin|pin@2||6|-8|-1|-1|R|
 Ngeneric:Invisible-Pin|pin@3||6|-6|1|1|R|
@@ -6000,7 +6000,7 @@ Esucc[sf]||D5G2;|pin@67||I
 X
 
 # Cell outDockCenter;6{lay}
-CoutDockCenter;6{lay}||cmos90|1236868105838|1241216356279|
+CoutDockCenter;6{lay}||cmos90|1236868105838|1241473584807|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NX-Metal-3-Metal-4-Con|contact@5||-530|-337||||
 NX-Metal-2-Metal-3-Con|contact@6||-530|-328||||
@@ -6416,6 +6416,7 @@ Esel[Di]|ps[18]|D5G5;|ilcMoveO@2|sel[Di]|I
 Esel[Ti]|ps[19]|D5G7;|ilcMoveO@2|sel[Ti]|I
 Ebit[20]|ps[20]|D5G7;|muxForD@0|sel|I
 Esel[rD]|ps[21]|D5G5;|olcWcont@3|sel[rD]|I
+Eps[Fl]|ps[22]|D5G5;|ohPredAl@2|ps[Fl]|I
 Esel[Ld]|ps[23]|D5G5;|olcWcont@3|sel[Ld]|I
 Esel[Co]|ps[24]|D5G7;|olcWcont@3|sel[Co]|I
 Esel[Mv]|ps[25]|D5G7;|ilcMoveO@2|sel[Mv]|I
@@ -6483,7 +6484,7 @@ Evdd_65|vdd_37|D5G7;|cover7hN@0|vdd_63|P
 X
 
 # Cell outDockCenter;3{sch}
-CoutDockCenter;3{sch}||schematic|1233272314089|1241322693027|
+CoutDockCenter;3{sch}||schematic|1233272314089|1241472893214|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 IwiresL:bitAssignments;1{ic}|bitAssig@0||-62|29|||D5G4;
 NOff-Page|conn@0||23|-20.5|||RRR|
@@ -6570,8 +6571,8 @@ NWire_Pin|pin@189||-81|-1||||
 NBus_Pin|pin@193||-6|-30|-1|-1||
 NBus_Pin|pin@196||-114|-15|-1|-1||
 NBus_Pin|pin@198||-26|-17|-1|-1||
-NBus_Pin|pin@199||-15.5|-9|-1|-1||
-NBus_Pin|pin@200||-15.5|-14|-1|-1||
+NWire_Pin|pin@199||-41.5|-6||||
+NWire_Pin|pin@200||-41.5|-9.5||||
 IwiresL:tranCap;1{ic}|tc[1:16]|D5G3;X2;Y2;|-93|27|||D5G4;
 IorangeTSMC090nm:wire90;1{ic}|wire90@5||-52|23|||D0G4;|ATTR_L(D5G1;PUD)S3750|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@6||-52|17|||D0G4;|ATTR_L(D5G1;PUD)S3560|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
@@ -6650,9 +6651,9 @@ Awire|net@296|||0|pin@185||-22|-27|pin@188||-81|-27
 Awire|net@297|||2700|pin@188||-81|-27|pin@189||-81|-1
 Awire|net@298|||1800|pin@189||-81|-1|olcWcont@0|do[ins]|-77|-1
 Abus|net@303||-0.5|IJ900|conn@37||-6|-36|conn@13|y|-6|-39
-Abus|net@305|||IJ0|pin@199||-15.5|-9|ohPredAl@0|ps[Fl]|-19|-9
+Awire|net@304|||0|ohPredAl@0|ps[Fl]|-28|-6|pin@199||-41.5|-6
 Abus|sel[Di,Ti,LL,rD,Fl,Ld,Co,Mv,Tp]|D5G2;|-0.5|IJ2700|conn@37||-6|-36|pin@193||-6|-30
-Abus|sel[Fl]|D5G2;|-0.5|IJ900|pin@199||-15.5|-9|pin@200||-15.5|-14
+Awire|sel[Fl]|D5G2;||900|pin@199||-41.5|-6|pin@200||-41.5|-9.5
 Awire|sel[LL]|D5G2;||900|muxForD@0|sel|12.5|-27|pin@167||12.5|-31
 Abus|sel[Ld,Co,rD]|D5G2;|-0.5|IJ900|pin@97||-84|-3|pin@125||-84|-6
 Abus|sel[Mv,Tp,Di,Ti]|D5G2;|-0.5|IJ2700|pin@168||13|-17.5|ilcMoveO@0|bit[Di,Ti]|13|-13
@@ -6787,7 +6788,7 @@ Esucc[sf]||D5G2;|pin@66||I
 X
 
 # Cell outDockPredStage;7{lay}
-CoutDockPredStage;7{lay}||cmos90|1237130886640|1241212843263||DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241212897245
+CoutDockPredStage;7{lay}||cmos90|1237130886640|1241474090092||DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241212897245
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NX-Metal-2-Metal-3-Con|contact@21||1248|-28||||
 NX-Metal-2-Metal-3-Con|contact@22||1536|-16||||
@@ -6891,6 +6892,9 @@ NX-Metal-2-Metal-3-Con|contact@158||-1488|-416||||
 NX-Metal-2-Metal-3-Con|contact@162||-1200|34||||
 NX-Metal-2-Metal-3-Con|contact@163||-1056|-348||||
 NX-Metal-1-Metal-2-Con|contact@164||334.5|-348||||
+NX-Metal-2-Metal-3-Con|contact@165||-774|-416||||
+NX-Metal-2-Metal-3-Con|contact@166||-774|128||||
+NX-Metal-1-Metal-2-Con|contact@167||-485.5|128||||
 IregistersM:dockPSreg;5{lay}|dockPSre@4||0|-432|||D5G4;
 IfanPinsM:m3new18;1{lay}|m3new18@0||924|633.5|||D5G4;
 IfanPinsM:m3new36;1{lay}|m3new36@0||-6|-490|||D5G4;
@@ -6906,6 +6910,7 @@ NMetal-3-Pin|pin@180||-234|81||||
 NMetal-3-Pin|pin@183||-1488|633.5||||
 NMetal-1-Pin|pin@187||-923|28||||
 NMetal-1-Pin|pin@188||-937|28||||
+NMetal-1-Pin|pin@193||-485.5|119||||
 Ametal-2|net@91|||S1800|pin@131||1261|-16|contact@22||1536|-16
 Ametal-2|net@170|||S1800|contact@42||-624|-354|contact@43||-365|-354
 Ametal-2|net@200|||S1800|contact@44||-768|-360|contact@45||-459|-360
@@ -7120,6 +7125,11 @@ Ametal-1|net@1145||0.4|S2700|pin@188||-937|28|contact@156||-937|34
 Ametal-3|net@1147|||S2700|contact@152||-1056|-416|contact@163||-1056|-348
 Ametal-1|net@1149|||S900|outDockC@5|sel[Co]|334.5|-313|contact@164||334.5|-348
 Ametal-2|net@1151|||S1800|contact@163||-1056|-348|contact@164||334.5|-348
+Ametal-2|net@1153|||S0|dockPSre@4|ps[22]|-756|-416|contact@165||-774|-416
+Ametal-3|net@1154|||S2700|contact@165||-774|-416|contact@166||-774|128
+Ametal-2|net@1157|||S1800|contact@166||-774|128|contact@167||-485.5|128
+Ametal-1|net@1158|||S900|contact@167||-485.5|128|pin@193||-485.5|119
+Ametal-1|net@1159|||S1800|pin@193||-485.5|119|outDockC@5|ps[Fl]|-473.5|119
 Edo[ins]||D5G7;|pin@180||O
 Eepi[torp]||D5G7;|outDockC@5|epi[torp]|I
 Efire[M]||D5G7;|outDockC@5|fire[M]|I
@@ -7302,10 +7312,10 @@ Evdd_64||D5G7;|outDockC@5|vdd_52|P
 X
 
 # Cell outDockPredStage;2{sch}
-CoutDockPredStage;2{sch}||schematic|1237130083475|1241322317904|
+CoutDockPredStage;2{sch}||schematic|1237130083475|1241473926126|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@1||13|-18||||
-NOff-Page|conn@2||69|-18.5||||
+NOff-Page|conn@2||41.5|-18||||
 NOff-Page|conn@4||22.5|0||||
 NOff-Page|conn@6||11|12.5|||R|
 NOff-Page|conn@7||-11|14.5|||XRRR|
@@ -7318,7 +7328,6 @@ NOff-Page|conn@16||-7|12|||YR|
 NOff-Page|conn@17||-23.5|-2|||XY|
 NOff-Page|conn@18||20|5|||X|
 NOff-Page|conn@19||26.5|-10||||
-NWire_Con|conn@21||60|-18.5||||
 IregistersM:dockPSreg;1{ic}|dockPSre@0||25|-18|||D5G4;
 IoutDockCenter;1{ic}|outDockC@0||0|0|||D5G4;
 IoutDockPredStage;1{ic}|outDockP@0||41|17|||D5G4;
@@ -7326,7 +7335,7 @@ Ngeneric:Invisible-Pin|pin@0||2|36.5|||||ART_message(D5G6;)SoutDockPredStage
 Ngeneric:Invisible-Pin|pin@1||1|27.5|||||ART_message(D5G3;)Sies 25 April 2009
 Ngeneric:Invisible-Pin|pin@2||0|31.5|||||ART_message(D5G4;)S"the \"guts\" plus psRegister"
 NBus_Pin|pin@7||-6|-18|-1|-1||
-NBus_Pin|pin@9||6|-15.5|-1|-1||
+NBus_Pin|pin@9||6|-12.5|-1|-1||
 NBus_Pin|pin@28||-11|-23|-1|-1||
 NWire_Pin|pin@34||-24|-12||||
 NWire_Pin|pin@35||-24|-15||||
@@ -7347,8 +7356,6 @@ NBus_Pin|pin@50||34|-18|-1|-1||
 NBus_Pin|pin@51||34|-23|-1|-1||
 NWire_Pin|pin@52||11|-10||||
 NWire_Pin|pin@53||23|-10||||
-NBus_Pin|pin@55||55.5|-13.5|-1|-1||
-NBus_Pin|pin@56||55.5|-18.5|-1|-1||
 IorangeTSMC090nm:wire90;1{ic}|wire90@1||-30.5|-12|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D5146.200000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@2||-30.5|-18|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D5054.200000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@3||-30.5|-24|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D4771.5|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
@@ -7392,11 +7399,8 @@ Awire|net@102|||0|wire90@8|a|14|-10|pin@52||11|-10
 Awire|net@103|||1800|wire90@8|b|19|-10|pin@53||23|-10
 Awire|net@105|||2700|dockPSre@0|fire[1]|23|-15|pin@53||23|-10
 Awire|net@106|||0|conn@19|a|24.5|-10|pin@53||23|-10
-Abus|net@110|||IJ0|conn@21||60|-18.5|pin@56||55.5|-18.5
-Abus|net@111|||IJ1800|conn@21||60|-18.5|conn@2|a|67|-18.5
-Abus|psx[1:20,27]|D5G2;|-0.5|IJ900|pin@55||55.5|-13.5|pin@56||55.5|-18.5
-Abus|psx[1:27]|D5G2;|-0.5|IJ900|pin@50||34|-18|pin@51||34|-23
-Abus|psx[18:26]|D5G2;|-0.5|IJ900|outDockC@0|bit[Di,Ti,Do]|6|-8|pin@9||6|-15.5
+Abus|ps[1:27]|D5G2;|-0.5|IJ900|pin@50||34|-18|pin@51||34|-23
+Abus|ps[18:26]|D5G2;|-0.5|IJ900|outDockC@0|bit[Di,Ti,Do]|6|-8|pin@9||6|-12.5
 Efire[M_1]|do[ins]|D6G2;|conn@19|y|O
 Eepi[torp]||D4G2;|conn@10|a|I
 Efire[M]||D6G2;|conn@6|y|O

diff --git a/testCode/marina.spi b/testCode/marina.spi
index c2b50a2..54c4309 100644 (file)
--- a/testCode/marina.spi
+++ b/testCode/marina.spi
@@ -1,7 +1,7 @@
 *** SPICE deck for cell marinaOutDock{sch} from library aMarinaM
 *** Created on Mon Nov 17, 2008 08:47:24
 *** Last revised on Sat May 02, 2009 06:16:53
-*** Written on Mon May 04, 2009 13:31:09 by Electric VLSI Design System, 
+*** Written on Mon May 04, 2009 15:10:52 by Electric VLSI Design System, 
 *version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -8414,18 +8414,17 @@ XdockPSre@0 do[ins] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
 +m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] 
 +m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] inLO[1] inLO[2] inLO[3] 
 +inLO[4] inLO[5] inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] 
-+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] psx[21] psx[22] psx[23] psx[24] 
-+psx[25] psx[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] 
-+dockPSreg
++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] 
++ps[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] dockPSreg
 XoutDockC@0 net@101 epi[torp] fire[M] flag[A][clr] flag[A][set] flag[C][T] 
 +flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] 
 +inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] m1[11] m1[12] m1[1] m1[21] 
 +m1[22] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] 
 +m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] 
 +m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D] 
-+pred[T] ps[18] ps[19] ps[20] psx[21] psx[22] psx[23] psx[24] psx[25] psx[26] 
-+ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] 
-+sir[9] sor[1] succ[sf] outDockCenter
++pred[T] ps[18] ps[19] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[do] 
++ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] 
++sor[1] succ[sf] outDockCenter
 Xwire90@1 wire90@1_a inLO[1] wire90-5146_2-layer_1-width_3
 Xwire90@2 wire90@2_a inLO[2] wire90-5054_2-layer_1-width_3
 Xwire90@3 wire90@3_a inLO[3] wire90-4771_5-layer_1-width_3

diff --git a/testCode/marina.v b/testCode/marina.v
index 31e484e..75bdbbd 100644 (file)
--- a/testCode/marina.v
+++ b/testCode/marina.v
@@ -1,7 +1,7 @@
 /* Verilog for cell 'marinaOutDock{sch}' from library 'aMarinaM' */
 /* Created on Mon Nov 17, 2008 08:47:24 */
 /* Last revised on Sat May 02, 2009 06:16:53 */
-/* Written on Mon May 04, 2009 13:31:06 by Electric VLSI Design System, version 8.08k */
+/* Written on Mon May 04, 2009 15:10:48 by Electric VLSI Design System, version 8.08k */
 
 module orangeTSMC090nm__wire(a);
   input a;
@@ -6019,14 +6019,14 @@ module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_,
   wire \inLO[5] ;
   wire \inLO[6] ;
   wire \inLO[8] ;
-  wire [21:26] psx;
+  wire [21:26] ps_1;
 
   registersM__dockPSreg dockPSre_0(.do_ins_(do_ins_), .m1(m1[1:27]), .outLO({ 
       \inLO[1] ,  \inLO[2] ,  \inLO[3] ,  \inLO[4] ,  \inLO[5] ,  \inLO[6] ,  
       \inLO[8] }), .ps({ \ps[1] ,  \ps[2] ,  \ps[3] ,  \ps[4] ,  \ps[5] ,  
       \ps[6] ,  \ps[7] ,  \ps[8] ,  \ps[9] ,  \ps[10] ,  \ps[11] ,  \ps[12] ,  
       \ps[13] ,  \ps[14] ,  \ps[15] ,  \ps[16] ,  \ps[17] ,  \ps[18] ,  \ps[19] 
-      ,  \ps[20] , psx[21], psx[22], psx[23], psx[24], psx[25], psx[26],  
+      ,  \ps[20] , ps_1[21], ps_1[22], ps_1[23], ps_1[24], ps_1[25], ps_1[26],  
       \ps[27] }));
   stagesM__outDockCenter outDockC_0(.epi_torp_(epi_torp_), 
       .flag_C__T_(flag_C__T_), .in(in[1:6]), .\inLO[1] ( \inLO[1] ), .\inLO[2] 
@@ -6042,8 +6042,8 @@ module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_,
       .m1cate_4__T_(m1cate_4__T_), .m1cate_5__F_(m1cate_5__F_), 
       .m1cate_5__T_(m1cate_5__T_), .m1cate_6__F_(m1cate_6__F_), 
       .m1cate_6__T_(m1cate_6__T_), .pred_D_(pred_D_), .pred_T_(pred_T_), .ps({ 
-      \ps[18] ,  \ps[19] ,  \ps[20] , psx[21], psx[22], psx[23], psx[24], 
-      psx[25], psx[26]}), .sir(sir[1:9]), .succ_sf_(succ_sf_), 
+      \ps[18] ,  \ps[19] ,  \ps[20] , ps_1[21], ps_1[22], ps_1[23], ps_1[24], 
+      ps_1[25], ps_1[26]}), .sir(sir[1:9]), .succ_sf_(succ_sf_), 
       .do_ins_(do_ins_), .fire_M_(fire_M_), .flag_A__clr_(flag_A__clr_), 
       .flag_A__set_(flag_A__set_), .flag_D__clr_(flag_D__clr_), 
       .flag_D__set_(flag_D__set_), .ps_do_(ps_do_), .ps_skip_(ps_skip_),