\maketitle
\begin{abstract}
+Changes:
+
+\color{red}
+\begin{tabular}{rl}
+7-Mar
+& Moved address bits to the LSB-side of a 37-bit instruction \\
+& Added {\it micro-instruction} and {\it composite instruction} terms \\
+& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
+& Created the {\tt Hold} field \\
+& Changed how ReLooping works \\
+& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
+\end{tabular}
+\color{black}
\end{abstract}
\vfill
\setlength{\bitwidth}{3.5mm}
{\tt \footnotesize
\begin{bytefield}{37}
- \bitheader[b]{0,25,26,36}\\
- \bitbox{11}{dispatch path}
+ \bitheader[b]{0,10,11,36}\\
\bitbox{26}{instruction}
+\color{red}
+ \bitbox{11}{dispatch path}
+\color{black}
\end{bytefield}}
{\bf Note:} the instruction encodings below are simply ``something to
budget. The final instruction encodings will probably be
different.
-All instructions other than {\tt interrupt}, {\tt massacre}, {\tt clog},
-and {\tt unclog} have the following format:
+All instruction words have the following format:
\setlength{\bitwidth}{3.5mm}
{\tt \footnotesize
\begin{bytefield}{37}
- \bitheader[b]{0,21,22,23,24,25,26,36}\\
-\color{light}
- \bitbox{11}{dispatch path}
+ \bitheader[b]{0,10,11,36}\\
+\color{black}
+\color{red}
+ \bitbox{2}{Hold}
\color{black}
- \bitbox{1}{IM}
- \bitbox{1}{DL}
\bitbox{2}{P}
\color{light}
\bitbox[tbr]{22}{}
+\color{red}
+ \bitbox{11}{dispatch path}
+\color{black}
\color{black}
\end{bytefield}}
-The abbreviation {\tt IM} stands for {\it Interruptible/Massacreable}.
-An {\tt interrupt} or {\tt massacre} instruction will not execute
-until an instruction with the {\tt IM} bit is present at the head of
-the instruction fifo.
+\color{red}
+Each instruction word is called a {\it micro instruction}.
+Collections of one or more micro instruction are known as {\it
+ composite instructions}. The {\tt Hold} field indicates how micro
+instructions are gathered together into composite instructions:
+
+\begin{itemize}
+\item {\tt 00:} {\tt solo} -- this word is not part of a composite instruction
+\item {\tt 01:} {\tt soloT} -- like {\tt solo}, but {\tt torpedo}-able
+\item {\tt 10:} {\tt body} -- this word is part of a composite instruction, but not the last
+\item {\tt 11:} {\tt tail} -- this is the last micro instruction in a composite instruction
+\end{itemize}
-The abbreviation {\tt DL} stands for {\it Decrement Loop}; if this bit
-is set, the loop counter decrements. Once an instruction has
-finished executing (including repeating, if applicable), the
-instruction will reloop if the loop count ({\tt LC}) value was
-greater than zero {\it prior to decrementing}.
+Solo instructions never reloop (described later); they are
+``one-shot'' instructions. Multiple solo instructions may be in the
+instruction fifo simultaneously. A {\tt solo} instruction is immune
+to {\tt torpedo}s (described later); a {\tt soloT} instruction is
+not\footnote{the {\tt soloT} instruction is meant to be used for
+ ``standing repeating'' instructions}.
+
+Composite instructions reloop until the loop counter is zero. When a
+composite instruction is in the instruction fifo, no other
+instructions may enter the fifo. A {\tt body} instruction is immune
+to {\tt torpedo}s; a {\tt tail} instruction is not. \color{black}
The abbreviation {\tt P} stands for {\it predicate}; this is a two-bit
code that indicates if the instruction should be executed or ignored.
{\tt takeLoopCounter} & N & Y \\
{\tt takeRepeatCounter} & N & Y \\
\hline
-{\tt clog} & N & N \\
-{\tt unclog} & n/a & n/a \\
-{\tt interrupt} & n/a & n/a \\
-{\tt massacre} & n/a & n/a \\\hline
+\color{red}
+{\tt torpedo} \color{black} & n/a & n/a \\
+
+%{\tt clog} & N & N \\
+%{\tt unclog} & n/a & n/a \\
+%{\tt interrupt} & n/a & n/a \\
+%{\tt massacre} & n/a & n/a \\
+\hline
\end{tabular}
\end{center}
\end{minipage}
{\bf RePeating}\\
An instruction will repeat if it is classified as a repeating
-instruction and the repeat counter is nonzero. Instructions
-non-repeating instructions have no effect on the repeat
+instruction and the repeat counter is nonzero.
+Non-repeating instructions have no effect on the repeat
counter (except for {\tt repeat}, of course).
{\bf ReLooping}\\
-An instruction reloops if {\bf all} of the following are true:
-\begin{enumerate}
-\item The repeat counter has reached zero.
-\item The instruction is a ``relooping instruction'' as shown below.
-\item The loop counter is greater than zero. This check takes into
- account the result of a {\tt literal} instruction, but does not
- take into account the effect of the {\tt DL} bit.
-\end{enumerate}
-{\it Important:} if an instruction is {\it not} going to reloop
-(according to the rules above), it must execute even if the tail of
-the instruction fifo is occupied (full).
+\color{red}
+Solo instructions (both {\tt solo} and {\tt soloT})
+completely ignore the loop counter; it has no effect on them.
+
+If a {\tt body} or {\tt tail} instruction reaches the on deck stage
+and the loop counter ({\tt LC}) is zero, the instruction dies
+immediately without executing or relooping.
+
+If a {\tt body} or {\tt tail} instruction reaches the on deck stage
+and the loop counter ({\tt LC}) is nonzero, a (duplicate) copy of that
+instruction is immediately enqueued at the head of the instruction
+fifo; the original instruction then waits at {\tt OD} until either its
+execution conditions are met or it is {\tt torpedo}ed.
+\color{black}
\pagebreak
\begin{bytefield}{26}
\bitheader[b]{12-16,19,21}\\
\color{light}
- \bitbox{1}{IM}
- \bitbox{1}{DL}
+ \bitbox{2}{Hold}
\bitbox{2}{P}
\color{black}
\bitbox{3}{001}
\pagebreak
\subsection{{\tt data}, {\tt datahi}, {\tt datalo}}
-These instructions load part or all of the data latch ({\tt DL}).
+These instructions load part or all of the data latch ({\tt D}).
{\tt datahi: Literal[18:1]\to D[37:20]} (and {\tt Literal[18]\to S})
\begin{bytefield}{26}
\bitheader[b]{0,18,19,21}\\
\color{light}
- \bitbox{1}{IM}
- \bitbox{1}{DL}
+ \bitbox{2}{Hold}
\bitbox{2}{P}
\color{black}
\bitbox{1}{0}
\begin{bytefield}{26}
\bitheader[b]{0,18,19,21}\\
\color{light}
- \bitbox{1}{IM}
- \bitbox{1}{DL}
+ \bitbox{2}{Hold}
\bitbox{2}{P}
\color{black}
\bitbox{1}{0}
\begin{bytefield}{26}
\bitheader[b]{0,18,19,21}\\
\color{light}
- \bitbox{1}{IM}
- \bitbox{1}{DL}
+ \bitbox{2}{Hold}
\bitbox{2}{P}
\color{black}
\bitbox{1}{1}
\begin{bytefield}{26}
\bitheader[b]{0,7,8,15,16-19,21}\\
\color{light}
- \bitbox{1}{IM}
- \bitbox{1}{DL}
+ \bitbox{2}{Hold}
\bitbox{2}{P}
\color{black}
\bitbox{3}{000}
\begin{bytefield}{26}
\bitheader[b]{16-19,21}\\
\color{light}
- \bitbox{1}{IM}
- \bitbox{1}{DL}
+ \bitbox{2}{Hold}
\bitbox{2}{P}
\color{black}
\bitbox{3}{000}
\subsection{{\tt loop}}
-This instruction loads the loop counter with either a literal or the
+This instruction loads the loop counter {\tt LC} with either {\tt max(0,LC-1)}, a literal or the
contents of the {\tt data} register.
\setlength{\bitwidth}{5mm}
\begin{bytefield}{26}
\bitheader[b]{16-19,21,24}\\
\color{light}
- \bitbox{1}{IM}
-\color{black}
- \bitbox{1}{0}
+ \bitbox{2}{Hold}
\color{light}
\bitbox[tbr]{2}{P}
\color{black}
\end{bytefield}}\\
\begin{bytefield}{26}
+\color{red}
+ \bitbox[r]{19}{\raggedleft {\tt max(0,LC-1)}:\hspace{0.2cm}\ }
+ \bitbox{2}{\tt 00}
+%\color{light}
+ \bitbox[tbr]{5}{}
+%\color{black}
+\color{black}
+\end{bytefield}
+
+\begin{bytefield}{26}
\bitbox[r]{19}{\raggedleft from data latch:\hspace{0.2cm}\ }
- \bitbox{1}{\tt 0}
+ \bitbox{2}{\tt 01}
\color{light}
- \bitbox[tbr]{6}{}
+ \bitbox[tbr]{5}{}
\color{black}
\end{bytefield}
\bitbox{6}{\tt Literal}
\end{bytefield}
-Note that the bit normally marked {\tt DL} (``decrement loop
- counter'') {\bf must} be set to {\tt
- 0} in this case.
-
\pagebreak
\subsection{{\tt takeLoopCounter}}
\begin{bytefield}{26}
\bitheader[b]{16-19,21}\\
\color{light}
- \bitbox{1}{IM}
- \bitbox{1}{DL}
+ \bitbox{2}{Hold}
\bitbox{2}{P}
\color{black}
\bitbox{3}{000}
\begin{bytefield}{26}
\bitheader[b]{16-19,21}\\
\color{light}
- \bitbox{1}{IM}
- \bitbox{1}{DL}
+ \bitbox{2}{Hold}
\bitbox{2}{P}
\color{black}
\bitbox{3}{???}
latch and leaves all other bits of the data latch unchanged.
\pagebreak
-\subsection{{\tt interrupt}}
+\color{red}
+\subsection{{\tt torpedo}}
\setlength{\bitwidth}{5mm}
{\tt
\bitbox{2}{00}
\color{light}
\bitbox[tbr]{16}{}
-%\color{black}
-% \bitbox{6}{Count}
-\end{bytefield}}
-
-When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
-there for the {\tt OD} stage to be full with an instruction that has
-the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
-{\it will not execute}, but {\it may reloop} if the conditions for
-relooping are met.
-\footnote{The ability to interrupt an instruction yet have it reloop is very
-useful for processing chunks of data with a fixed size header and/or
-footer and a variable length body.}
-
-
-\subsection{{\tt massacre}}
-
-\setlength{\bitwidth}{5mm}
-{\tt
-\begin{bytefield}{26}
- \bitheader[b]{16-19,21}\\
-\color{light}
- \bitbox{4}{}
-\color{black}
- \bitbox{3}{000}
- \bitbox{1}{1}
- \bitbox{2}{01}
-\color{light}
- \bitbox[tbr]{16}{}
-\color{black}
-\end{bytefield}}
-
-When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
-for the {\tt OD} stage to be full with an instruction that has the
-{\tt IM} bit set. When this occurs, all instructions in the
-instruction fifo (including {\tt OD}) are retired.
-
-\subsection{{\tt clog}}
-
-\setlength{\bitwidth}{5mm}
-{\tt
-\begin{bytefield}{26}
- \bitheader[b]{16-19,21}\\
-\color{light}
- \bitbox{4}{}
-\color{black}
- \bitbox{3}{000}
- \bitbox{1}{1}
- \bitbox{2}{10}
-\color{light}
- \bitbox[tbr]{16}{}
-\color{black}
\end{bytefield}}
-When a {\tt clog} instruction reaches {\tt OD}, it remains there and
-no more instructions will be executed until an {\tt unclog} is
-performed.
-
-\subsection{{\tt unclog}}
-
-\setlength{\bitwidth}{5mm}
-{\tt
-\begin{bytefield}{26}
- \bitheader[b]{16-19,21}\\
-\color{light}
- \bitbox{4}{}
-\color{black}
- \bitbox{3}{000}
- \bitbox{1}{1}
- \bitbox[lrtb]{2}{11}
-\color{light}
- \bitbox[tbr]{16}{}
+When a {\tt torpedo} instruction reaches {\tt IH}, it will wait there
+until an instruction is on deck (at {\tt OD}) and that instruction's
+{\tt Hold} field is {\tt tail} or {\tt soloT}. The {\tt torpedo} will then
+annihilate the on-deck instruction {\it and set the loop counter to zero}.
\color{black}
-\end{bytefield}}
-When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
-until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
-instructions retire.
-Note that issuing an {\tt unclog} instruction to a dock which is not
-clogged and whose instruction fifo contains no {\tt clog} instructions
-will cause the dock to deadlock.
+%\pagebreak
+%\subsection{{\tt interrupt}}
+%
+%\setlength{\bitwidth}{5mm}
+%{\tt
+%\begin{bytefield}{26}
+% \bitheader[b]{0,5,16-19,21}\\
+%\color{light}
+% \bitbox{4}{}
+%\color{black}
+% \bitbox{3}{000}
+% \bitbox{1}{1}
+% \bitbox{2}{00}
+%\color{light}
+% \bitbox[tbr]{16}{}
+%\end{bytefield}}
+%
+%When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
+%there for the {\tt OD} stage to be full with an instruction that has
+%the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
+%{\it will not execute}, but {\it may reloop} if the conditions for
+%relooping are met.
+%\footnote{The ability to interrupt an instruction yet have it reloop is very
+%useful for processing chunks of data with a fixed size header and/or
+%footer and a variable length body.}
+%
+%
+%\subsection{{\tt massacre}}
+%
+%\setlength{\bitwidth}{5mm}
+%{\tt
+%\begin{bytefield}{26}
+% \bitheader[b]{16-19,21}\\
+%\color{light}
+% \bitbox{4}{}
+%\color{black}
+% \bitbox{3}{000}
+% \bitbox{1}{1}
+% \bitbox{2}{01}
+%\color{light}
+% \bitbox[tbr]{16}{}
+%\color{black}
+%\end{bytefield}}
+%
+%When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
+%for the {\tt OD} stage to be full with an instruction that has the
+%{\tt IM} bit set. When this occurs, all instructions in the
+%instruction fifo (including {\tt OD}) are retired.
+%
+%\subsection{{\tt clog}}
+%
+%\setlength{\bitwidth}{5mm}
+%{\tt
+%\begin{bytefield}{26}
+% \bitheader[b]{16-19,21}\\
+%\color{light}
+% \bitbox{4}{}
+%\color{black}
+% \bitbox{3}{000}
+% \bitbox{1}{1}
+% \bitbox{2}{10}
+%\color{light}
+% \bitbox[tbr]{16}{}
+%\color{black}
+%\end{bytefield}}
+%
+%When a {\tt clog} instruction reaches {\tt OD}, it remains there and
+%no more instructions will be executed until an {\tt unclog} is
+%performed.
+%
+%\subsection{{\tt unclog}}
+%
+%\setlength{\bitwidth}{5mm}
+%{\tt
+%\begin{bytefield}{26}
+% \bitheader[b]{16-19,21}\\
+%\color{light}
+% \bitbox{4}{}
+%\color{black}
+% \bitbox{3}{000}
+% \bitbox{1}{1}
+% \bitbox[lrtb]{2}{11}
+%\color{light}
+% \bitbox[tbr]{16}{}
+%\color{black}
+%\end{bytefield}}
+%
+%When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
+%until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
+%instructions retire.
+%
+%Note that issuing an {\tt unclog} instruction to a dock which is not
+%clogged and whose instruction fifo contains no {\tt clog} instructions
+%will cause the dock to deadlock.
projects / fleet.git / commitdiff