make getAck()/getReq() private, add isFull()

diff --git a/src/edu/berkeley/fleet/fpga/FunnelModule.java b/src/edu/berkeley/fleet/fpga/FunnelModule.java
index 7003a54..b138a9e 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/FunnelModule.java
+++ b/src/edu/berkeley/fleet/fpga/FunnelModule.java
@@ -22,7 +22,7 @@ public class FunnelModule extends Module {
         Module.SourcePort  in2p = createInputPort("in2", fpga.WIDTH_PACKET);
 
         // FIXME: biased towards in2p side
-        new Event(new Object[] { in1p, outp, "!"+in2p.getReq() },
+        new Event(new Object[] { in1p, outp, "!"+in2p.isFull() },
                   new Action[] { in1p, outp,
                                  new AssignAction(outp, in1p) });
         new Event(new Object[] { in2p, outp },

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index 9ffafdd..848f80c 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -241,8 +241,9 @@ public class Verilog {
                     portorder.add(name);
             }
             public String getVerilogName() { return name; }
-            public String getAck() { return name+"_a"; }
-            public String getReq() { return name+"_r"; }
+            String getAck() { return name+"_a"; }
+            String getReq() { return name+"_r"; }
+            public String isFull() { return "("+name+"_r"+" && !"+name+"_a)"; }
             public abstract String getInterface();
             public abstract String getSimpleInterface();
             public abstract String getDeclaration();