== FPGA ==============================================================
- wire [`DATAWIDTH:0] sum;
+ wire [`WORDWIDTH:0] sum;
wire cin;
- wire [(`DATAWIDTH-1):0] in2_inverted;
+ wire [(`WORDWIDTH-1):0] in2_inverted;
- wire [(`DATAWIDTH-1):0] res;
+ wire [(`WORDWIDTH-1):0] res;
wire isplus;
wire eq;
wire cout;
assign cin = isplus ? 0 : 1;
assign in2_inverted = isplus ? in2_d : ~in2_d;
assign sum = {in1_d,cin} + {in2_inverted,cin};
- assign res = sum[`DATAWIDTH:1];
- assign greater = !res[`DATAWIDTH-1];
- assign both_negative = in1_d[`DATAWIDTH-1] && in2_d[`DATAWIDTH-1];
+ assign res = sum[`WORDWIDTH:1];
+ assign greater = !res[`WORDWIDTH-1];
+ assign both_negative = in1_d[`WORDWIDTH-1] && in2_d[`WORDWIDTH-1];
assign eq = in1_d == in2_d;
- assign cout = sum[`DATAWIDTH];
+ assign cout = sum[`WORDWIDTH];
- assign out_d_[`DATAWIDTH] =
+ assign out_d_[`WORDWIDTH] =
(inOp_d==0) ? 1'b0 :
(inOp_d==1) ? 1'b0 :
(inOp_d==2) ? cout :
(inOp_d==9) ? ~greater :
0;
- assign out_d_[(`DATAWIDTH-1):0] =
+ assign out_d_[(`WORDWIDTH-1):0] =
(inOp_d==0) ? (in1_d) :
(inOp_d==1) ? (in2_d) :
(inOp_d==2) ? (res) :
(inOp_d==3) ? (res) :
(inOp_d==4) ? (greater ? in1_d : in2_d) :
(inOp_d==5) ? (greater ? in2_d : in1_d) :
- (inOp_d==6) ? {{ (`DATAWIDTH-1) {1'b0 }}, eq } :
+ (inOp_d==6) ? {{ (`WORDWIDTH-1) {1'b0 }}, eq } :
(inOp_d==9) ? (both_negative ? in1_d : (greater ? in1_d : in2_d)) :
0;
== FPGA ==============================================================
- reg [(`DATAWIDTH-1):0] temp;
- reg [(`DATAWIDTH):0] out_d;
+ reg [(`WORDWIDTH-1):0] temp;
+ reg [(`WORDWIDTH):0] out_d;
reg [1:0] state;
initial state = 0;
assign out_d_ = out_d;
- wire [(`DATAWIDTH-1):0] majority;
- wire [(`DATAWIDTH-1):0] xors;
+ wire [(`WORDWIDTH-1):0] majority;
+ wire [(`WORDWIDTH-1):0] xors;
genvar i;
generate
- for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
+ for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
assign majority[i] = (temp[i] & out_d[i]) | (in_d[i] & out_d[i]) | (temp[i] & in_d[i]);
assign xors[i] = temp[i] ^ out_d[i] ^ in_d[i];
end
end else if (state == 1) begin
temp <= in_d;
end else if (state == 2) begin
- out_d <= { majority[`DATAWIDTH-1:0], 1'b0 };
+ out_d <= { majority[`WORDWIDTH-1:0], 1'b0 };
temp <= xors;
`fill_out
end
== FPGA ==============================================================
- reg [`DATAWIDTH-1:0] temp;
- initial temp = {`DATAWIDTH{1'b1}};
+ reg [`WORDWIDTH-1:0] temp;
+ initial temp = {`WORDWIDTH{1'b1}};
reg full;
initial full = 0;
wire op_count; assign op_count = inOp_d==12;
end else if (`inOp_full) begin
if (!full) begin
if (op_count && `in1_full && `in2_full) begin
- temp <= in1_d[`DATAWIDTH-1:0] - in2_d[`DATAWIDTH-1:0];
+ temp <= in1_d[`WORDWIDTH-1:0] - in2_d[`WORDWIDTH-1:0];
`drain_in1
full <= 1;
end else if (op_c1 && `in1_full) begin
- temp <= in1_d[`DATAWIDTH-1:0]-1;
+ temp <= in1_d[`WORDWIDTH-1:0]-1;
`drain_in1
full <= 1;
end else if (op_c2 && `in2_full) begin
- temp <= in2_d[`DATAWIDTH-1:0]-1;
+ temp <= in2_d[`WORDWIDTH-1:0]-1;
`drain_in2
full <= 1;
end
- end else if (temp[`DATAWIDTH-1]) begin
+ end else if (temp[`WORDWIDTH-1]) begin
full <= 0;
`drain_inOp
if (op_count) begin
reg dram_isread;
reg dram_write_data_push;
reg dram_read_data_pop;
- reg [`DATAWIDTH:0] out_d;
+ reg [`WORDWIDTH:0] out_d;
wire [31:0] dram_addr__;
assign dram_addr_r_ = dram_addr_r;
assign dram_write_data_push_ = dram_write_data_push;
assign dram_read_data_pop_ = dram_read_data_pop;
assign dram_write_data_ = inDataWrite_d;
-// assign dram_write_data_ = inDataWrite_d[(`DATAWIDTH-1):0];
+// assign dram_write_data_ = inDataWrite_d[(`WORDWIDTH-1):0];
assign out_d_ = out_d;
always @(posedge clk) begin
== FPGA ==============================================================
- reg [`DATAWIDTH-1:0] out_d;
+ reg [`WORDWIDTH-1:0] out_d;
assign out_d_ = out_d;
always @(posedge clk) begin
genvar i;
generate
- for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
+ for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}];
end
endgenerate
== FPGA ==============================================================
- wire [(`DATAWIDTH-1):0] out1;
- wire [(`DATAWIDTH-1):0] out2;
+ wire [(`WORDWIDTH-1):0] out1;
+ wire [(`WORDWIDTH-1):0] out2;
reg [(`CODEBAG_SIZE_BITS-1):0] counter;
reg [(`BRAM_ADDR_WIDTH-1):0] cursor;
initial dispatching_cbd = 0;
wire [(`BRAM_ADDR_WIDTH-1):0] addr1;
- assign addr1 = write_flag ? inAddrWrite_d[(`DATAWIDTH-1):0] : inAddrRead_d[(`DATAWIDTH-1):0];
+ assign addr1 = write_flag ? inAddrWrite_d[(`WORDWIDTH-1):0] : inAddrRead_d[(`WORDWIDTH-1):0];
bram14 mybram(clk, rst, write_flag, addr1, cursor, inDataWrite_d, out1, out2);
assign out_d_ = { out_w , (dispatching_cbd ? out2 : out1) };
// assumes we never want a zero-length codebag
if (`inCBD_full && `out_empty) begin
if (!dispatching_cbd) begin
- cursor <= inCBD_d[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)];
+ cursor <= inCBD_d[(`WORDWIDTH-1):(`CODEBAG_SIZE_BITS)];
counter <= 0;
dispatching_cbd <= 1;
end
== FPGA ==============================================================
- reg [(`DATAWIDTH):0] out_d;
+ reg [(`WORDWIDTH):0] out_d;
assign out_d_ = out_d;
reg full;
shamt <= 0;
full <= 1;
end else if (!shamt_eq) begin
- out_d <= { out_d[0], out_d[0], out_d[`DATAWIDTH-1:1] };
+ out_d <= { out_d[0], out_d[0], out_d[`WORDWIDTH-1:1] };
shamt <= shamt+1;
end else begin
`drain_in
=> clean up fabricelement methods
=> get rid of addcrap
=> automatic width-setting on ports
-=> nuke DATAWIDTH?
- => serdes and fastclock/slowclock?
*/
public class Fpga extends FleetTwoFleet {
pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v")));
pw.println("`define BRAM_ADDR_WIDTH 14");
- pw.println("`define BRAM_DATA_WIDTH `DATAWIDTH");
+ pw.println("`define BRAM_DATA_WIDTH `WORDWIDTH");
pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))");
pw.println("`define BRAM_NAME bram14");
pw.println("`include \"bram.inc\"");
boolean debug = "debug".equals(filename);
- pw.println("`define DATAWIDTH "+WIDTH_WORD);
+ pw.println("`define WORDWIDTH "+WIDTH_WORD);
pw.println("`define CODEBAG_SIZE_BITS "+CBD_SIZE.valmaskwidth);
pw.println();
projects / fleet.git / commitdiff