`define input(r, a, a_, w, d) input r; output a_; reg a; assign a_=a; input w d; initial a=0;
`define output(r, r_, a, w, d) output r_; input a; reg r; assign r_=r; output w d; initial r=0;
-`define onread(req, ack) if (!req && ack) ack=0; else if (req && !ack) begin ack=1;
-`define onwrite(req, ack) if (!req && !ack) req = 1; else if (req && ack) begin req = 0;
-//`define onread2(req, ack) if (!req && ack) ack<=0; else if (req && !ack) begin ack<=1;
+`define onread(req, ack) if (!req && ack) ack <= 0; else if (req && !ack) begin ack <=1;
+`define onwrite(req, ack) if (!req && !ack) req <= 1; else if (req && ack) begin req <= 0;
+//`define onread2(req, ack) if (!req && ack) ack<=0; else if (req && !ack) begin ack<=1;
//`define onwrite2(req, ack) if (req && ack) begin req <= 0;
`define onread2(req, ack) if (req && !ack) begin ack = 1;