remove synthesis attributes that xst doesnt understand

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_ctrl.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_ctrl.v
index 1160208..7141237 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_ctrl.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_ctrl.v
@@ -261,7 +261,7 @@ module ddr2_ctrl #
   reg [11:0]                               refi_cnt_r;
   reg                                      refi_cnt_ok_r;
   reg                                      rst_r
-                                           /* synthesis syn_preserve = 1 */;
+                                           /* */;
   reg                                      rst_r1
                                            /* synthesis syn_maxfan = 10 */;
   reg [7:0]                                rfc_cnt_r;

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_calib.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_calib.v
index 76a0751..349dd7a 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_calib.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_calib.v
@@ -1232,8 +1232,8 @@ module ddr2_phy_calib #
          .D   (cal2_rd_data_sel[rd_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /* synthesis syn_preserve = 1 */
-           /* synthesis syn_replicate = 0 */;
+         ) /* */
+           /*  */;
     end
   endgenerate
 
@@ -1505,8 +1505,8 @@ module ddr2_phy_calib #
          .D   (calib_rden_srl_a[cal_rden_ff_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /* synthesis syn_preserve = 1 */
-           /* synthesis syn_replicate = 0 */;
+         ) /*  */
+           /*  */;
     end
   endgenerate
 
@@ -1528,7 +1528,7 @@ module ddr2_phy_calib #
          .D   (calib_rden_srl_out),
          .R   (1'b0),
          .S   (1'b0)
-     ) /* synthesis syn_preserve = 1 */;
+     ) /*  */;
 
   // convert to CLKDIV domain. Two version are generated because we need
   // to be able to tell exactly which fast (clk) clock cycle the read
@@ -1560,8 +1560,8 @@ module ddr2_phy_calib #
          .D   (rden_dly[rden_ff_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /* synthesis syn_preserve = 1 */
-           /* synthesis syn_replicate = 0 */;
+         ) /*  */
+           /*  */;
     end
   endgenerate
 
@@ -1590,7 +1590,7 @@ module ddr2_phy_calib #
          .D   (rden_srl_out[rden_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /* synthesis syn_preserve = 1 */;
+         ) /*  */;
     end
   endgenerate
 
@@ -2004,8 +2004,8 @@ module ddr2_phy_calib #
          .D   (gate_dly[gate_ff_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /* synthesis syn_preserve = 1 */
-           /* synthesis syn_replicate = 0 */;
+         ) /*  */
+           /*  */;
     end
   endgenerate
 
@@ -2044,7 +2044,7 @@ module ddr2_phy_calib #
          .D   (gate_srl_out[gate_i]),
          .R   (1'b0),
          .S   (1'b0)
-           ) /* synthesis syn_preserve = 1 */;
+           ) /*  */;
       end else begin: gen_gate_base_dly_le3
         assign gate_srl_out_r[gate_i] = gate_srl_out[gate_i];
       end
@@ -2057,8 +2057,8 @@ module ddr2_phy_calib #
          .D   (gate_srl_out_r[gate_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /* synthesis syn_preserve = 1 */
-           /* synthesis syn_replicate = 0 */;
+         ) /*  */
+           /*  */;
     end
   endgenerate
 

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_ctl_io.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_ctl_io.v
index 625a5dc..d0e5de1 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_ctl_io.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_ctl_io.v
@@ -179,7 +179,7 @@ module ddr2_phy_ctl_io #
      .CLR (1'b0),
      .D   (ras_n_mux),
      .PRE (rst0)
-     ) /* synthesis syn_useioff = 1 */;
+     ) /*  */;
 
   // CAS: = 1 at reset
   (* IOB = "TRUE" *) FDCPE u_ff_cas_n
@@ -190,7 +190,7 @@ module ddr2_phy_ctl_io #
      .CLR (1'b0),
      .D   (cas_n_mux),
      .PRE (rst0)
-     ) /* synthesis syn_useioff = 1 */;
+     ) /*  */;
 
   // WE: = 1 at reset
   (* IOB = "TRUE" *) FDCPE u_ff_we_n
@@ -201,7 +201,7 @@ module ddr2_phy_ctl_io #
      .CLR (1'b0),
      .D   (we_n_mux),
      .PRE (rst0)
-     ) /* synthesis syn_useioff = 1 */;
+     ) /*  */;
 
   // CKE: = 0 at reset
   genvar cke_i;
@@ -215,7 +215,7 @@ module ddr2_phy_ctl_io #
          .CLR (rst0),
          .D   (phy_init_cke[cke_i]),
          .PRE (1'b0)
-         ) /* synthesis syn_useioff = 1 */;
+         ) /*  */;
     end
   endgenerate
 
@@ -238,7 +238,7 @@ module ddr2_phy_ctl_io #
             .CLR (1'b0),
             .D   (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
             .PRE (rst0)
-            ) /* synthesis syn_useioff = 1 */;
+            ) /*  */;
       end else begin // if (TWO_T_TIME_EN)
          (* IOB = "TRUE" *) FDCPE u_ff_cs_n
            (
@@ -248,7 +248,7 @@ module ddr2_phy_ctl_io #
             .CLR (1'b0),
             .D   (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
             .PRE (rst0)
-            ) /* synthesis syn_useioff = 1 */;
+            ) /*  */;
       end // else: !if(TWO_T_TIME_EN)
     end
   endgenerate
@@ -265,7 +265,7 @@ module ddr2_phy_ctl_io #
          .CLR (1'b0),
          .D   (addr_mux[addr_i]),
          .PRE (1'b0)
-         ) /* synthesis syn_useioff = 1 */;
+         ) /*  */;
     end
   endgenerate
 
@@ -281,7 +281,7 @@ module ddr2_phy_ctl_io #
          .CLR (1'b0),
          .D   (ba_mux[ba_i]),
          .PRE (1'b0)
-         ) /* synthesis syn_useioff = 1 */;
+         ) /*  */;
     end
   endgenerate
 
@@ -298,7 +298,7 @@ module ddr2_phy_ctl_io #
            .CLR (rst0),
           .D   (odt[(odt_i*CS_NUM)/ODT_WIDTH]),
            .PRE (1'b0)
-           ) /* synthesis syn_useioff = 1 */;
+           ) /*  */;
       end
     end
   endgenerate

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dq_iob.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dq_iob.v
index 854079a..7a8ff90 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dq_iob.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dq_iob.v
@@ -360,8 +360,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_0m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/* */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -372,8 +372,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_0m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/* */
+          /*  */;
       // Stage 3 falling -> rising edge translation
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -385,8 +385,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/* */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -397,8 +397,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/* */
+          /*  */;
 
       //*********************************************************
       // Slice #2 (posedge CLK): Used for:
@@ -415,8 +415,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_0m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/* */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -428,8 +428,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_0m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
     end else if ((DQ_MS == 0) && (DQ_COL == 0)) begin: gen_stg2_0s
 
@@ -462,8 +462,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_0s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -474,8 +474,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_0s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -487,8 +487,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -499,8 +499,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
        AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -512,8 +512,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_0s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "CFF",
        AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -524,8 +524,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_0s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
     end else if ((DQ_MS == 1) && (DQ_COL == 1))  begin: gen_stg2_1m
 
@@ -558,8 +558,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_1m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -570,8 +570,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_1m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -583,8 +583,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -595,8 +595,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -608,8 +608,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_1m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -620,8 +620,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_1m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
     end else if ((DQ_MS == 0) && (DQ_COL == 1)) begin: gen_stg2_1s
 
@@ -654,8 +654,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_1s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -666,8 +666,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_1s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -679,8 +679,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -691,8 +691,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -704,8 +704,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_1s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -716,8 +716,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_1s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
     end else if ((DQ_MS == 1) && (DQ_COL == 2)) begin: gen_stg2_2m
 
@@ -750,8 +750,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_2m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -762,8 +762,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_2m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -775,8 +775,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -787,8 +787,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -800,8 +800,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_2m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -812,8 +812,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_2m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
     end else if ((DQ_MS == 0) && (DQ_COL == 2)) begin: gen_stg2_2s
 
@@ -846,8 +846,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_2s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -858,8 +858,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_2s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_fall
@@ -870,8 +870,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -882,8 +882,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -895,8 +895,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_2s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -907,8 +907,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_2s),
          .R   (1'b0),
          .S   (1'b0)
-         )/* synthesis syn_preserve = 1 */
-          /* synthesis syn_replicate = 0 */;
+         )/*  */
+          /*  */;
 
     end
   endgenerate

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dqs_iob.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dqs_iob.v
index a626f72..14e29b4 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dqs_iob.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dqs_iob.v
@@ -93,7 +93,7 @@ module ddr2_phy_dqs_iob #
   wire                     dqs_oe_n_delay;
   wire                     dqs_oe_n_r;
   wire                     dqs_rst_n_delay;
-  reg                      dqs_rst_n_r /* synthesis syn_preserve = 1*/;
+  reg                      dqs_rst_n_r /* */;
   wire                     dqs_out;
   wire                     en_dqs_sync /* synthesis syn_keep = 1 */;
 
@@ -229,7 +229,7 @@ module ddr2_phy_dqs_iob #
      .Q   (dqs_oe_n_r),
      .C   (clk180),
      .PRE (rst0)
-     ) /* synthesis syn_useioff = 1 */;
+     ) /* */;
 
   //***************************************************************************
 

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_init.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_init.v
index 4282b63..32f7b03 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_init.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_init.v
@@ -770,8 +770,8 @@ module ddr2_phy_init #
      .D   (phy_init_done_r1),
      .R   (1'b0),
      .S   (1'b0)
-     ) /* synthesis syn_preserve=1 */
-       /* synthesis syn_replicate = 0 */;
+     ) /* */
+       /*  */;
 
   //synthesis translate_off
   always @(posedge calib_done[0])

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_usr_rd.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_usr_rd.v
index 8f20e0d..5972da8 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_usr_rd.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_usr_rd.v
@@ -97,7 +97,7 @@ module ddr2_usr_rd #
   reg [(DQS_WIDTH*DQ_PER_DQS)-1:0]  rd_data_in_rise_r;
   wire                              rden;
   reg [DQS_WIDTH-1:0]               rden_sel_r
-                                    /* synthesis syn_preserve=1 */;
+                                    /* */;
   wire [DQS_WIDTH-1:0]              rden_sel_mux;
   wire [(DQS_WIDTH*DQ_PER_DQS)-1:0] rise_data;
 
@@ -142,7 +142,7 @@ module ddr2_usr_rd #
          .D   (ctrl_rden_sel[rd_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /* synthesis syn_preserve=1 */;
+         ) /* */;
     end
   endgenerate