-*** SPICE deck for cell marina{sch} from library aMarinaM
+*** SPICE deck for cell marinaOut{sch} from library aMarinaM
*** Created on Mon Nov 17, 2008 08:47:24
-*** Last revised on Sun Mar 15, 2009 16:05:57
-*** Written on Tue Mar 17, 2009 13:21:05 by Electric VLSI Design System,
+*** Last revised on Fri Mar 20, 2009 07:12:49
+*** Written on Fri Mar 20, 2009 16:35:52 by Electric VLSI Design System,
*version 8.08k
*** Layout tech: cmos90, foundry TSMC
*** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
* Model cards are described in this file:
.include '../testCode/header.hsp'
-*** CELL: wiresL:bitAssignments{sch}
-.SUBCKT bitAssignments
-.ENDS bitAssignments
-
*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_30 d g s
-MNMOSf@0 d g s gnd nch W='90*(1+ABN/sqrt(90*2))' L='2'
-+DELVTO='AVT0N/sqrt(90*2)'
-.ENDS NMOSx-X_30
+.SUBCKT NMOSx-X_40 d g s
+MNMOSf@0 d g s gnd nch W='120*(1+ABN/sqrt(120*2))' L='2'
++DELVTO='AVT0N/sqrt(120*2)'
+.ENDS NMOSx-X_40
*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_30 d g s
-MPMOSf@0 d g s vdd pch W='180*(1+ABP/sqrt(180*2))' L='2'
-+DELVTO='AVT0P/sqrt(180*2)'
-.ENDS PMOSx-X_30
+.SUBCKT PMOSx-X_40 d g s
+MPMOSf@0 d g s vdd pch W='240*(1+ABP/sqrt(240*2))' L='2'
++DELVTO='AVT0P/sqrt(240*2)'
+.ENDS PMOSx-X_40
*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_30 in out
-XNMOS@0 out in gnd NMOSx-X_30
-XPMOS@0 out in vdd PMOSx-X_30
-.ENDS inv-X_30
+.SUBCKT inv-X_40 in out
+XNMOS@0 out in gnd NMOSx-X_40
+XPMOS@0 out in vdd PMOSx-X_40
+.ENDS inv-X_40
*** CELL: orangeTSMC090nm:PMOSx{sch}
.SUBCKT PMOSx-X_10 d g s
.ENDS PMOSx-X_10
*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_10 d g s
-MNMOSf@0 d g s gnd nch W='30*(1+ABN/sqrt(30*2))' L='2'
-+DELVTO='AVT0N/sqrt(30*2)'
-.ENDS NMOSx-X_10
+.SUBCKT NMOSx-X_20 d g s
+MNMOSf@0 d g s gnd nch W='60*(1+ABN/sqrt(60*2))' L='2'
++DELVTO='AVT0N/sqrt(60*2)'
+.ENDS NMOSx-X_20
*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_5 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_10
-XNMOS@1 net@0 g gnd NMOSx-X_10
-.ENDS nms2-X_5
+.SUBCKT nms2-X_10 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_20
+XNMOS@1 net@0 g gnd NMOSx-X_20
+.ENDS nms2-X_10
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_10 d g g2
-Xnms2@0 d g g2 nms2-X_5
-Xnms2@1 d g2 g nms2-X_5
-.ENDS nms2_sy-X_10
+*** CELL: redFive:nand2{sch}
+.SUBCKT nand2-X_10 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_10
+XPMOS@1 out inb vdd PMOSx-X_10
+Xnms2@0 out ina inb nms2-X_10
+.ENDS nand2-X_10
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_10 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_10
-XPMOS@1 out ina vdd PMOSx-X_10
-Xnms2_sy@0 out ina inb nms2_sy-X_10
-.ENDS nand2_sy-X_10
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-506_4-R_34_667m a b
+Ccap@0 gnd net@14 1.857f
+Ccap@1 gnd net@8 1.857f
+Ccap@2 gnd net@11 1.857f
+Rres@0 net@14 a 2.926
+Rres@1 net@11 net@14 5.852
+Rres@2 b net@8 2.926
+Rres@3 net@8 net@11 5.852
+.ENDS wire-C_0_011f-506_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-506_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-506_4-R_34_667m
+.ENDS wire90-506_4-layer_1-width_3
+
+*** CELL: countersL:cntShift{sch}
+.SUBCKT cntShift ctgLO myp1p myp2p sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
++sid[7] sid[8] sid[9] sin
+Xinv@3 net@98 myp1p inv-X_40
+Xinv@4 net@100 myp2p inv-X_40
+Xnand2@4 ctgLO sid[2] net@99 nand2-X_10
+Xnand2@5 ctgLO sid[3] net@97 nand2-X_10
+Xwire90@9 net@98 net@97 wire90-506_4-layer_1-width_3
+Xwire90@10 net@100 net@99 wire90-506_4-layer_1-width_3
+.ENDS cntShift
*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_2_5 d g s
-MNMOSf@0 d g s gnd nch W='7.5*(1+ABN/sqrt(7.5*2))' L='2'
-+DELVTO='AVT0N/sqrt(7.5*2)'
-.ENDS NMOSx-X_2_5
+.SUBCKT NMOSx-X_10 d g s
+MNMOSf@0 d g s gnd nch W='30*(1+ABN/sqrt(30*2))' L='2'
++DELVTO='AVT0N/sqrt(30*2)'
+.ENDS NMOSx-X_10
+
+*** CELL: redFive:inv{sch}
+.SUBCKT inv-X_10 in out
+XNMOS@0 out in gnd NMOSx-X_10
+XPMOS@0 out in vdd PMOSx-X_10
+.ENDS inv-X_10
*** CELL: orangeTSMC090nm:PMOSx{sch}
.SUBCKT PMOSx-X_5 d g s
+DELVTO='AVT0P/sqrt(30*2)'
.ENDS PMOSx-X_5
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_2_5 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_5
-XPMOS@1 d g2 net@2 PMOSx-X_5
-.ENDS pms2-X_2_5
+*** CELL: redFive:nms2{sch}
+.SUBCKT nms2-X_5 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_10
+XNMOS@1 net@0 g gnd NMOSx-X_10
+.ENDS nms2-X_5
-*** CELL: redFive:pms2_sy{sch}
-.SUBCKT pms2_sy-X_5 d g g2
-Xpms2@0 d g g2 pms2-X_2_5
-Xpms2@1 d g2 g pms2-X_2_5
-.ENDS pms2_sy-X_5
+*** CELL: redFive:nand2{sch}
+.SUBCKT nand2-X_5 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_5
+XPMOS@1 out inb vdd PMOSx-X_5
+Xnms2@0 out ina inb nms2-X_5
+.ENDS nand2-X_5
-*** CELL: redFive:nor2HT_sy{sch}
-.SUBCKT nor2HT_sy-X_5 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_2_5
-XNMOS@1 out ina gnd NMOSx-X_2_5
-Xpms2_sy@0 out ina inb pms2_sy-X_5
-.ENDS nor2HT_sy-X_5
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_20 d g s
+MPMOSf@0 d g s vdd pch W='120*(1+ABP/sqrt(120*2))' L='2'
++DELVTO='AVT0P/sqrt(120*2)'
+.ENDS PMOSx-X_20
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-414-R_34_667m a b
-Ccap@0 gnd net@14 1.518f
-Ccap@1 gnd net@8 1.518f
-Ccap@2 gnd net@11 1.518f
-Rres@0 net@14 a 2.392
-Rres@1 net@11 net@14 4.784
-Rres@2 b net@8 2.392
-Rres@3 net@8 net@11 4.784
-.ENDS wire-C_0_011f-414-R_34_667m
+*** CELL: redFive:nms2_sy{sch}
+.SUBCKT nms2_sy-X_20 d g g2
+Xnms2@0 d g g2 nms2-X_10
+Xnms2@1 d g2 g nms2-X_10
+.ENDS nms2_sy-X_20
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-414-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-414-R_34_667m
-.ENDS wire90-414-layer_1-width_3
+*** CELL: redFive:nand2_sy{sch}
+.SUBCKT nand2_sy-X_20 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_20
+XPMOS@1 out ina vdd PMOSx-X_20
+Xnms2_sy@0 out ina inb nms2_sy-X_20
+.ENDS nand2_sy-X_20
-*** CELL: centersJ:ctrAND3in30A{sch}
-.SUBCKT ctrAND3in30A inA inB inC out outM
-Xinv@1 outM out inv-X_30
-Xnand2_sy@0 net@15 inC outM nand2_sy-X_10
-Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5
-Xwire90@0 net@6 net@15 wire90-414-layer_1-width_3
-.ENDS ctrAND3in30A
+*** CELL: countersL:cntFreq{sch}
+.SUBCKT cntFreq count ctgLO fin fout myFin
+Xinv@0 ctgLO net@17 inv-X_10
+Xinv@1 count ctgLO inv-X_40
+Xnand2@0 net@18 myFin net@72 nand2-X_5
+Xnand2@1 ctgLO fin net@33 nand2-X_5
+Xnand2_sy@0 net@34 net@39 fout nand2_sy-X_20
+Xwire90@2 net@17 net@18 wire90-506_4-layer_1-width_3
+Xwire90@4 net@34 net@33 wire90-506_4-layer_1-width_3
+Xwire90@5 net@39 net@72 wire90-506_4-layer_1-width_3
+.ENDS cntFreq
*** CELL: orangeTSMC090nm:NMOSx{sch}
.SUBCKT NMOSx-X_5 d g s
XPMOS@0 out in vdd PMOSx-X_5
.ENDS inv-X_5
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_10 in out
-XNMOS@0 out in gnd NMOSx-X_10
-XPMOS@0 out in vdd PMOSx-X_10
-.ENDS inv-X_10
-
-*** CELL: redFive:nor2_sy{sch}
-.SUBCKT nor2_sy-X_5 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_5
-XNMOS@1 out ina gnd NMOSx-X_5
-Xpms2_sy@0 out ina inb pms2_sy-X_5
-.ENDS nor2_sy-X_5
-
-*** CELL: redFive:nor2n_sy{sch}
-.SUBCKT nor2n_sy-X_5 ina inb out
-Xnor2@0 ina inb out nor2_sy-X_5
-.ENDS nor2n_sy-X_5
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_20 d g s
-MNMOSf@0 d g s gnd nch W='60*(1+ABN/sqrt(60*2))' L='2'
-+DELVTO='AVT0N/sqrt(60*2)'
-.ENDS NMOSx-X_20
-
*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_4 d g s
-MNMOSf@0 d g s gnd nch W='12*(1+ABN/sqrt(12*2))' L='2'
-+DELVTO='AVT0N/sqrt(12*2)'
-.ENDS NMOSx-X_4
+.SUBCKT NMOSx-X_1_733 d g s
+MNMOSf@0 d g s gnd nch W='5.199*(1+ABN/sqrt(5.199*2))' L='2'
++DELVTO='AVT0N/sqrt(5.199*2)'
+.ENDS NMOSx-X_1_733
*** CELL: orangeTSMC090nm:PMOSx{sch}
.SUBCKT PMOSx-X_4 d g s
+DELVTO='AVT0P/sqrt(24*2)'
.ENDS PMOSx-X_4
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_4 in out
-XNMOS@0 out in gnd NMOSx-X_4
-XPMOS@0 out in vdd PMOSx-X_4
-.ENDS inv-X_4
-
*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_3_999 d g s
-MPMOSf@0 d g s vdd pch W='23.994*(1+ABP/sqrt(23.994*2))' L='2'
-+DELVTO='AVT0P/sqrt(23.994*2)'
-.ENDS PMOSx-X_3_999
-
-*** CELL: redFive:pms3{sch}
-.SUBCKT pms3-X_1_333 d g g2 g3
-XPMOS@0 d g3 net@2 PMOSx-X_3_999
-XPMOS@1 net@2 g2 net@5 PMOSx-X_3_999
-XPMOS@2 net@5 g vdd PMOSx-X_3_999
-.ENDS pms3-X_1_333
+.SUBCKT PMOSx-X_1 d g s
+MPMOSf@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2'
++DELVTO='AVT0P/sqrt(6*2)'
+.ENDS PMOSx-X_1
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-106_7-R_34_667m a b
-Ccap@0 gnd net@14 0.391f
-Ccap@1 gnd net@8 0.391f
-Ccap@2 gnd net@11 0.391f
-Rres@0 net@14 a 0.616
-Rres@1 net@11 net@14 1.233
-Rres@2 b net@8 0.616
-Rres@3 net@8 net@11 1.233
-.ENDS wire-C_0_011f-106_7-R_34_667m
+*** CELL: latchPartsK:latchKeep{sch}
+.SUBCKT latchKeep out[B] out[s]
+XNMOSx@0 out[B] out[s] gnd NMOSx-X_1_733
+XNMOSx@1 out[s] out[B] gnd NMOSx-X_1_733
+XPMOSx@0 out[B] out[s] vdd PMOSx-X_4
+XPMOSx@1 out[s] out[B] vdd PMOSx-X_1
+.ENDS latchKeep
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-106_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-106_7-R_34_667m
-.ENDS wire90-106_7-layer_1-width_3
-
-*** CELL: driversL:predDri20wMC{sch}
-.SUBCKT predDri20wMC in mc pred
-XNMOSx@0 pred in gnd NMOSx-X_20
-XNMOSx@1 pred mc gnd NMOSx-X_4
-Xinv@0 pred net@145 inv-X_4
-Xpms3@0 pred net@177 in mc pms3-X_1_333
-Xwire90@0 net@177 net@145 wire90-106_7-layer_1-width_3
-.ENDS predDri20wMC
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_20 d g s
-MPMOSf@0 d g s vdd pch W='120*(1+ABP/sqrt(120*2))' L='2'
-+DELVTO='AVT0P/sqrt(120*2)'
-.ENDS PMOSx-X_20
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_6_667 d g s
-MPMOSf@0 d g s vdd pch W='40.002*(1+ABP/sqrt(40.002*2))' L='2'
-+DELVTO='AVT0P/sqrt(40.002*2)'
-.ENDS PMOSx-X_6_667
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_20_001 d g s
-MNMOSf@0 d g s gnd nch W='60.003*(1+ABN/sqrt(60.003*2))' L='2'
-+DELVTO='AVT0N/sqrt(60.003*2)'
-.ENDS NMOSx-X_20_001
-
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_6_667 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_20_001
-XNMOS@1 net@7 g gnd NMOSx-X_20_001
-XNMOS@2 net@6 g2 net@7 NMOSx-X_20_001
-.ENDS nms3-X_6_667
-
-*** CELL: redFive:nand3{sch}
-.SUBCKT nand3-X_6_667 ina inb inc out
-XPMOS@0 out inc vdd PMOSx-X_6_667
-XPMOS@1 out inb vdd PMOSx-X_6_667
-XPMOS@2 out ina vdd PMOSx-X_6_667
-Xnms3@0 out ina inb inc nms3-X_6_667
-.ENDS nand3-X_6_667
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_2 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_4
-XNMOS@1 net@0 g gnd NMOSx-X_4
-.ENDS nms2-X_2
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-309-R_34_667m a b
-Ccap@0 gnd net@14 1.133f
-Ccap@1 gnd net@8 1.133f
-Ccap@2 gnd net@11 1.133f
-Rres@0 net@14 a 1.785
-Rres@1 net@11 net@14 3.571
-Rres@2 b net@8 1.785
-Rres@3 net@8 net@11 3.571
-.ENDS wire-C_0_011f-309-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-309-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-309-R_34_667m
-.ENDS wire90-309-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-114_9-R_34_667m a b
-Ccap@0 gnd net@14 0.421f
-Ccap@1 gnd net@8 0.421f
-Ccap@2 gnd net@11 0.421f
-Rres@0 net@14 a 0.664
-Rres@1 net@11 net@14 1.328
-Rres@2 b net@8 0.664
-Rres@3 net@8 net@11 1.328
-.ENDS wire-C_0_011f-114_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-114_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-114_9-R_34_667m
-.ENDS wire90-114_9-layer_1-width_3
-
-*** CELL: driversL:suc3ANDdri20{sch}
-.SUBCKT suc3ANDdri20 inA inB inC succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_20
-Xinv@0 succ net@71 inv-X_4
-Xnand3@0 inA inB inC net@67 nand3-X_6_667
-Xnms2@0 succ net@75 net@51 nms2-X_2
-Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3
-Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3
-.ENDS suc3ANDdri20
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_5 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_5
-XPMOS@1 out inb vdd PMOSx-X_5
-Xnms2@0 out ina inb nms2-X_5
-.ENDS nand2-X_5
-
-*** CELL: driversL:sucANDdri20{sch}
-.SUBCKT sucANDdri20 inA inB succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_20
-Xinv@0 succ net@71 inv-X_4
-Xnand2@0 inA inB net@67 nand2-X_5
-Xnms2@0 succ net@75 net@51 nms2-X_2
-Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3
-Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3
-.ENDS sucANDdri20
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-372_8-R_34_667m a b
-Ccap@0 gnd net@14 1.367f
-Ccap@1 gnd net@8 1.367f
-Ccap@2 gnd net@11 1.367f
-Rres@0 net@14 a 2.154
-Rres@1 net@11 net@14 4.308
-Rres@2 b net@8 2.154
-Rres@3 net@8 net@11 4.308
-.ENDS wire-C_0_011f-372_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-372_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-372_8-R_34_667m
-.ENDS wire90-372_8-layer_1-width_3
-
-*** CELL: gaspM:gaspEpi{sch}
-.SUBCKT gaspEpi epi[OTHER] epi[TAIL] epi[TORP] fire mc pred s[1] tailBit
-+tokenLO
-XctrAND3i@3 net@1068 epi[TORP] net@1082 fire net@1119 ctrAND3in30A
-Xinv@5 pred net@987 inv-X_5
-XinvI@0 net@987 s[1] inv-X_10
-XinvI@1 tokenLO net@1146 inv-X_5
-XinvI@3 tailBit net@1147 inv-X_5
-Xnor2n_sy@0 epi[TAIL] epi[OTHER] net@1079 nor2n_sy-X_5
-XpredDri2@0 fire mc pred predDri20wMC
-Xsuc3ANDd@0 tokenLO net@1148 fire epi[OTHER] suc3ANDdri20
-Xsuc3ANDd@1 tokenLO tailBit fire epi[TAIL] suc3ANDdri20
-XsucANDdr@1 net@1139 fire epi[TORP] sucANDdri20
-Xwire90@0 net@987 net@1068 wire90-372_8-layer_1-width_3
-Xwire90@3 net@1079 net@1082 wire90-372_8-layer_1-width_3
-Xwire90@4 net@1139 net@1146 wire90-372_8-layer_1-width_3
-Xwire90@6 net@1148 net@1147 wire90-372_8-layer_1-width_3
-.ENDS gaspEpi
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_1_733 d g s
-MNMOSf@0 d g s gnd nch W='5.199*(1+ABN/sqrt(5.199*2))' L='2'
-+DELVTO='AVT0N/sqrt(5.199*2)'
-.ENDS NMOSx-X_1_733
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_1 d g s
-MPMOSf@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2'
-+DELVTO='AVT0P/sqrt(6*2)'
-.ENDS PMOSx-X_1
-
-*** CELL: latchPartsK:latchKeep{sch}
-.SUBCKT latchKeep out[B] out[s]
-XNMOSx@0 out[B] out[s] gnd NMOSx-X_1_733
-XNMOSx@1 out[s] out[B] gnd NMOSx-X_1_733
-XPMOSx@0 out[B] out[s] vdd PMOSx-X_4
-XPMOSx@1 out[s] out[B] vdd PMOSx-X_1
-.ENDS latchKeep
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_3 d g s
+MNMOSf@0 d g s gnd nch W='9*(1+ABN/sqrt(9*2))' L='2' DELVTO='AVT0N/sqrt(9*2)'
+.ENDS NMOSx-X_3
*** CELL: orangeTSMC090nm:NMOSx{sch}
.SUBCKT NMOSx-X_6 d g s
+DELVTO='AVT0N/sqrt(18*2)'
.ENDS NMOSx-X_6
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_3 d g s
-MNMOSf@0 d g s gnd nch W='9*(1+ABN/sqrt(9*2))' L='2' DELVTO='AVT0N/sqrt(9*2)'
-.ENDS NMOSx-X_3
-
*** CELL: redFive:invLT{sch}
.SUBCKT invLT-X_5 in out
XNMOS@0 out in gnd NMOSx-X_10
.ENDS invLT-X_5
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-123_7-R_34_667m a b
-Ccap@0 gnd net@14 0.454f
-Ccap@1 gnd net@8 0.454f
-Ccap@2 gnd net@11 0.454f
-Rres@0 net@14 a 0.715
-Rres@1 net@11 net@14 1.429
-Rres@2 b net@8 0.715
-Rres@3 net@8 net@11 1.429
-.ENDS wire-C_0_011f-123_7-R_34_667m
+.SUBCKT wire-C_0_011f-124_4-R_34_667m a b
+Ccap@0 gnd net@14 0.456f
+Ccap@1 gnd net@8 0.456f
+Ccap@2 gnd net@11 0.456f
+Rres@0 net@14 a 0.719
+Rres@1 net@11 net@14 1.438
+Rres@2 b net@8 0.719
+Rres@3 net@8 net@11 1.438
+.ENDS wire-C_0_011f-124_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-123_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-123_7-R_34_667m
-.ENDS wire90-123_7-layer_1-width_3
+.SUBCKT wire90-124_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-124_4-R_34_667m
+.ENDS wire90-124_4-layer_1-width_3
-*** CELL: latchPartsK:latchPointT{sch}
-.SUBCKT latchPointT hcl in[1] x[F] x[T]
-XPMOSx@0 in[1] hcl x[T] NMOSx-X_6
-XPMOSx@1 net@8 hcl x[F] NMOSx-X_3
+*** CELL: latchPartsK:latchPointF{sch}
+.SUBCKT latchPointF hcl in[1] x[F] x[T]
+XPMOSx@0 in[1] hcl x[T] NMOSx-X_3
+XPMOSx@1 net@8 hcl x[F] NMOSx-X_6
Xinv@0 in[1] net@105 invLT-X_5
-Xwire90@0 net@105 net@8 wire90-123_7-layer_1-width_3
-.ENDS latchPointT
+Xwire90@0 net@105 net@8 wire90-124_4-layer_1-width_3
+.ENDS latchPointF
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-180_9-R_34_667m a b
-Ccap@0 gnd net@14 0.663f
-Ccap@1 gnd net@8 0.663f
-Ccap@2 gnd net@11 0.663f
-Rres@0 net@14 a 1.045
-Rres@1 net@11 net@14 2.09
-Rres@2 b net@8 1.045
-Rres@3 net@8 net@11 2.09
-.ENDS wire-C_0_011f-180_9-R_34_667m
+.SUBCKT wire-C_0_011f-145_9-R_34_667m a b
+Ccap@0 gnd net@14 0.535f
+Ccap@1 gnd net@8 0.535f
+Ccap@2 gnd net@11 0.535f
+Rres@0 net@14 a 0.843
+Rres@1 net@11 net@14 1.686
+Rres@2 b net@8 0.843
+Rres@3 net@8 net@11 1.686
+.ENDS wire-C_0_011f-145_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-180_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-180_9-R_34_667m
-.ENDS wire90-180_9-layer_1-width_3
-
-*** CELL: latchesK:raw1inLatchT{sch}
-.SUBCKT raw1inLatchT hcl[A] inA[1] out[T]
-XlatchFlo@0 out[T] net@29 latchKeep
-XlatchPoi@0 hcl[A] inA[1] net@7 out[T] latchPointT
-Xwire90@0 net@7 net@29 wire90-180_9-layer_1-width_3
-.ENDS raw1inLatchT
+.SUBCKT wire90-145_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-145_9-R_34_667m
+.ENDS wire90-145_9-layer_1-width_3
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_20 in out
-XNMOS@0 out in gnd NMOSx-X_20
-XPMOS@0 out in vdd PMOSx-X_20
-.ENDS inv-X_20
+*** CELL: latchesK:raw2inLatchF{sch}
+.SUBCKT raw2inLatchF hcl[A] hcl[B] inA[1] inB[1] out[F]
+XlatchKee@0 out[F] net@63 latchKeep
+XlatchPoi@0 hcl[A] inA[1] out[F] net@45 latchPointF
+XlatchPoi@1 hcl[B] inB[1] out[F] net@45 latchPointF
+Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3
+.ENDS raw2inLatchF
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-250_9-R_34_667m a b
-Ccap@0 gnd net@14 0.92f
-Ccap@1 gnd net@8 0.92f
-Ccap@2 gnd net@11 0.92f
-Rres@0 net@14 a 1.45
-Rres@1 net@11 net@14 2.899
-Rres@2 b net@8 1.45
-Rres@3 net@8 net@11 2.899
-.ENDS wire-C_0_011f-250_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-250_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-250_9-R_34_667m
-.ENDS wire90-250_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-214_6-R_34_667m a b
-Ccap@0 gnd net@14 0.787f
-Ccap@1 gnd net@8 0.787f
-Ccap@2 gnd net@11 0.787f
-Rres@0 net@14 a 1.24
-Rres@1 net@11 net@14 2.48
-Rres@2 b net@8 1.24
-Rres@3 net@8 net@11 2.48
-.ENDS wire-C_0_011f-214_6-R_34_667m
+.SUBCKT wire-C_0_011f-242_1-R_34_667m a b
+Ccap@0 gnd net@14 0.888f
+Ccap@1 gnd net@8 0.888f
+Ccap@2 gnd net@11 0.888f
+Rres@0 net@14 a 1.399
+Rres@1 net@11 net@14 2.798
+Rres@2 b net@8 1.399
+Rres@3 net@8 net@11 2.798
+.ENDS wire-C_0_011f-242_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-214_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-214_6-R_34_667m
-.ENDS wire90-214_6-layer_1-width_3
-
-*** CELL: latchesK:latch1in20B{sch}
-.SUBCKT latch1in20B hcl in[1] out[1]
-Xhi2inLat@0 hcl in[1] net@19 raw1inLatchT
-Xinv@0 net@23 out[1] inv-X_20
-XinvLT@0 net@18 net@25 inv-X_5
-Xwire90@0 net@19 net@18 wire90-250_9-layer_1-width_3
-Xwire90@1 net@25 net@23 wire90-214_6-layer_1-width_3
-.ENDS latch1in20B
+.SUBCKT wire90-242_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-242_1-R_34_667m
+.ENDS wire90-242_1-layer_1-width_3
-*** CELL: registersM:ins1in20Bx18{sch}
-.SUBCKT ins1in20Bx18 hcl in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2]
-+out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-Xlx[1] hcl in[1] out[1] latch1in20B
-Xlx[2] hcl in[2] out[2] latch1in20B
-Xlx[3] hcl in[3] out[3] latch1in20B
-Xlx[4] hcl in[4] out[4] latch1in20B
-Xlx[5] hcl in[5] out[5] latch1in20B
-Xlx[6] hcl in[6] out[6] latch1in20B
-Xlx[7] hcl in[7] out[7] latch1in20B
-Xlx[8] hcl in[8] out[8] latch1in20B
-Xlx[9] hcl in[9] out[9] latch1in20B
-Xlx[10] hcl in[10] out[10] latch1in20B
-Xlx[11] hcl in[11] out[11] latch1in20B
-Xlx[12] hcl in[12] out[12] latch1in20B
-Xlx[13] hcl in[13] out[13] latch1in20B
-Xlx[14] hcl in[14] out[14] latch1in20B
-Xlx[15] hcl in[15] out[15] latch1in20B
-Xlx[16] hcl in[16] out[16] latch1in20B
-Xlx[17] hcl in[17] out[17] latch1in20B
-Xlx[18] hcl in[18] out[18] latch1in20B
-.ENDS ins1in20Bx18
+*** CELL: latchesK:latch2in10A{sch}
+.SUBCKT latch2in10A hcl[A] hcl[B] inA[1] inB[1] out[1]
+Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF
+XinvLT@1 net@16 out[1] inv-X_10
+Xwire90@1 dataBar net@16 wire90-242_1-layer_1-width_3
+.ENDS latch2in10A
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2550-R_34_667m a b
-Ccap@0 gnd net@14 9.35f
-Ccap@1 gnd net@8 9.35f
-Ccap@2 gnd net@11 9.35f
-Rres@0 net@14 a 14.733
-Rres@1 net@11 net@14 29.467
-Rres@2 b net@8 14.733
-Rres@3 net@8 net@11 29.467
-.ENDS wire-C_0_011f-2550-R_34_667m
+*** CELL: redFive:pms2{sch}
+.SUBCKT pms2-X_2_5 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_5
+XPMOS@1 d g2 net@2 PMOSx-X_5
+.ENDS pms2-X_2_5
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2550-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2550-R_34_667m
-.ENDS wire90-2550-layer_1-width_3
+*** CELL: redFive:pms2_sy{sch}
+.SUBCKT pms2_sy-X_5 d g g2
+Xpms2@0 d g g2 pms2-X_2_5
+Xpms2@1 d g2 g pms2-X_2_5
+.ENDS pms2_sy-X_5
-*** CELL: registersM:ins1in20Bx36{sch}
-.SUBCKT ins1in20Bx36 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9]
-Xins1in20@0 net@13 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] ins1in20Bx18
-Xins1in20@1 net@11 in[28] in[29] in[30] in[31] in[32] in[33] in[34] in[35]
-+in[36] in[19] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] out[28]
-+out[29] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[19]
-+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] ins1in20Bx18
-Xwire90@0 hcl[1] net@13 wire90-2550-layer_1-width_3
-Xwire90@1 hcl[1] net@11 wire90-2550-layer_1-width_3
-.ENDS ins1in20Bx36
+*** CELL: redFive:nor2_sy{sch}
+.SUBCKT nor2_sy-X_5 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_5
+XNMOS@1 out ina gnd NMOSx-X_5
+Xpms2_sy@0 out ina inb pms2_sy-X_5
+.ENDS nor2_sy-X_5
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_60 d g s
-MNMOSf@0 d g s gnd nch W='180*(1+ABN/sqrt(180*2))' L='2'
-+DELVTO='AVT0N/sqrt(180*2)'
-.ENDS NMOSx-X_60
+*** CELL: redFive:nor2n_sy{sch}
+.SUBCKT nor2n_sy-X_5 ina inb out
+Xnor2@0 ina inb out nor2_sy-X_5
+.ENDS nor2n_sy-X_5
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_60 d g s
-MPMOSf@0 d g s vdd pch W='360*(1+ABP/sqrt(360*2))' L='2'
-+DELVTO='AVT0P/sqrt(360*2)'
-.ENDS PMOSx-X_60
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-214_2-R_34_667m a b
+Ccap@0 gnd net@14 0.785f
+Ccap@1 gnd net@8 0.785f
+Ccap@2 gnd net@11 0.785f
+Rres@0 net@14 a 1.238
+Rres@1 net@11 net@14 2.475
+Rres@2 b net@8 1.238
+Rres@3 net@8 net@11 2.475
+.ENDS wire-C_0_011f-214_2-R_34_667m
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_60 in out
-XNMOS@0 out in gnd NMOSx-X_60
-XPMOS@0 out in vdd PMOSx-X_60
-.ENDS inv-X_60
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-214_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-214_2-R_34_667m
+.ENDS wire90-214_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-544_2-R_34_667m a b
-Ccap@0 gnd net@14 1.995f
-Ccap@1 gnd net@8 1.995f
-Ccap@2 gnd net@11 1.995f
-Rres@0 net@14 a 3.144
-Rres@1 net@11 net@14 6.289
-Rres@2 b net@8 3.144
-Rres@3 net@8 net@11 6.289
-.ENDS wire-C_0_011f-544_2-R_34_667m
+.SUBCKT wire-C_0_011f-413_4-R_34_667m a b
+Ccap@0 gnd net@14 1.516f
+Ccap@1 gnd net@8 1.516f
+Ccap@2 gnd net@11 1.516f
+Rres@0 net@14 a 2.389
+Rres@1 net@11 net@14 4.777
+Rres@2 b net@8 2.389
+Rres@3 net@8 net@11 4.777
+.ENDS wire-C_0_011f-413_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-544_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-544_2-R_34_667m
-.ENDS wire90-544_2-layer_1-width_3
-
-*** CELL: driversJ:latchDriver60{sch}
-.SUBCKT latchDriver60 in out
-Xinv@1 in net@16 inv-X_20
-XinvI@0 net@8 out inv-X_60
-Xwire90@0 net@16 net@8 wire90-544_2-layer_1-width_3
-.ENDS latchDriver60
+.SUBCKT wire90-413_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-413_4-R_34_667m
+.ENDS wire90-413_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-124_4-R_34_667m a b
-Ccap@0 gnd net@14 0.456f
-Ccap@1 gnd net@8 0.456f
-Ccap@2 gnd net@11 0.456f
-Rres@0 net@14 a 0.719
-Rres@1 net@11 net@14 1.438
-Rres@2 b net@8 0.719
-Rres@3 net@8 net@11 1.438
-.ENDS wire-C_0_011f-124_4-R_34_667m
+.SUBCKT wire-C_0_011f-231_2-R_34_667m a b
+Ccap@0 gnd net@14 0.848f
+Ccap@1 gnd net@8 0.848f
+Ccap@2 gnd net@11 0.848f
+Rres@0 net@14 a 1.336
+Rres@1 net@11 net@14 2.672
+Rres@2 b net@8 1.336
+Rres@3 net@8 net@11 2.672
+.ENDS wire-C_0_011f-231_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-124_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-124_4-R_34_667m
-.ENDS wire90-124_4-layer_1-width_3
+.SUBCKT wire90-231_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-231_2-R_34_667m
+.ENDS wire90-231_2-layer_1-width_3
-*** CELL: latchPartsK:latchPointF{sch}
-.SUBCKT latchPointF hcl in[1] x[F] x[T]
-XPMOSx@0 in[1] hcl x[T] NMOSx-X_3
-XPMOSx@1 net@8 hcl x[F] NMOSx-X_6
-Xinv@0 in[1] net@105 invLT-X_5
-Xwire90@0 net@105 net@8 wire90-124_4-layer_1-width_3
-.ENDS latchPointF
+*** CELL: countersL:cntScnOne{sch}
+.SUBCKT cntScnOne cin ctgLO out p1p p2p sin
+Xinv@0 out net@14 inv-X_5
+Xlatch2in@0 cB p1p net@3 net@3 out latch2in10A
+Xlatch2in@1 cA p2p net@15 sin net@6 latch2in10A
+Xnor2n_sy@0 ctgLO cB net@20 nor2n_sy-X_5
+Xnor2n_sy@2 ctgLO cin net@25 nor2n_sy-X_5
+Xwire90@0 net@15 net@14 wire90-214_2-layer_1-width_3
+Xwire90@1 net@6 net@3 wire90-506_4-layer_1-width_3
+Xwire90@2 net@20 cA wire90-413_4-layer_1-width_3
+Xwire90@3 net@25 cB wire90-231_2-layer_1-width_3
+.ENDS cntScnOne
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-146_1-R_34_667m a b
-Ccap@0 gnd net@14 0.536f
-Ccap@1 gnd net@8 0.536f
-Ccap@2 gnd net@11 0.536f
-Rres@0 net@14 a 0.844
-Rres@1 net@11 net@14 1.688
-Rres@2 b net@8 0.844
-Rres@3 net@8 net@11 1.688
-.ENDS wire-C_0_011f-146_1-R_34_667m
+.SUBCKT wire-C_0_011f-668_5-R_34_667m a b
+Ccap@0 gnd net@14 2.451f
+Ccap@1 gnd net@8 2.451f
+Ccap@2 gnd net@11 2.451f
+Rres@0 net@14 a 3.862
+Rres@1 net@11 net@14 7.725
+Rres@2 b net@8 3.862
+Rres@3 net@8 net@11 7.725
+.ENDS wire-C_0_011f-668_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-146_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-146_1-R_34_667m
-.ENDS wire90-146_1-layer_1-width_3
-
-*** CELL: latchesK:raw1inLatchF{sch}
-.SUBCKT raw1inLatchF hcl in[1] out[F]
-XlatchFlo@0 out[F] net@58 latchKeep
-XlatchPoi@0 hcl in[1] out[F] net@45 latchPointF
-Xwire90@0 net@45 net@58 wire90-146_1-layer_1-width_3
-.ENDS raw1inLatchF
-
-*** CELL: redFive:invLT{sch}
-.SUBCKT invLT-X_10 in out
-XNMOS@0 out in gnd NMOSx-X_20
-XPMOS@0 out in vdd PMOSx-X_10
-.ENDS invLT-X_10
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-282-R_34_667m a b
-Ccap@0 gnd net@14 1.034f
-Ccap@1 gnd net@8 1.034f
-Ccap@2 gnd net@11 1.034f
-Rres@0 net@14 a 1.629
-Rres@1 net@11 net@14 3.259
-Rres@2 b net@8 1.629
-Rres@3 net@8 net@11 3.259
-.ENDS wire-C_0_011f-282-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-282-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-282-R_34_667m
-.ENDS wire90-282-layer_1-width_3
-
-*** CELL: latchesK:latch1in10A{sch}
-.SUBCKT latch1in10A hcl in[1] out[1]
-Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF
-XinvLT@0 net@18 out[1] invLT-X_10
-Xwire90@0 net@19 net@18 wire90-282-layer_1-width_3
-.ENDS latch1in10A
+.SUBCKT wire90-668_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-668_5-R_34_667m
+.ENDS wire90-668_5-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-145_9-R_34_667m a b
-Ccap@0 gnd net@14 0.535f
-Ccap@1 gnd net@8 0.535f
-Ccap@2 gnd net@11 0.535f
-Rres@0 net@14 a 0.843
-Rres@1 net@11 net@14 1.686
-Rres@2 b net@8 0.843
-Rres@3 net@8 net@11 1.686
-.ENDS wire-C_0_011f-145_9-R_34_667m
+.SUBCKT wire-C_0_011f-680_5-R_34_667m a b
+Ccap@0 gnd net@14 2.495f
+Ccap@1 gnd net@8 2.495f
+Ccap@2 gnd net@11 2.495f
+Rres@0 net@14 a 3.932
+Rres@1 net@11 net@14 7.864
+Rres@2 b net@8 3.932
+Rres@3 net@8 net@11 7.864
+.ENDS wire-C_0_011f-680_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-145_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-145_9-R_34_667m
-.ENDS wire90-145_9-layer_1-width_3
+.SUBCKT wire90-680_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-680_5-R_34_667m
+.ENDS wire90-680_5-layer_1-width_3
-*** CELL: latchesK:raw2inLatchF{sch}
-.SUBCKT raw2inLatchF hcl[A] hcl[B] inA[1] inB[1] out[F]
-XlatchKee@0 out[F] net@63 latchKeep
-XlatchPoi@0 hcl[A] inA[1] out[F] net@45 latchPointF
-XlatchPoi@1 hcl[B] inB[1] out[F] net@45 latchPointF
-Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3
-.ENDS raw2inLatchF
+*** CELL: countersL:cntScnFour{sch}
+.SUBCKT cntScnFour cin ctgLO out p1p p2p sin
+XcntScnOn@0 net@88 ctgLO net@40 p1p p2p net@88 cntScnOne
+XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne
+XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne
+XcntScnOn@3 net@94 ctgLO out p1p p2p net@94 cntScnOne
+Xwire90@4 net@40 net@94 wire90-668_5-layer_1-width_3
+Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3
+Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3
+.ENDS cntScnFour
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-311_7-R_34_667m a b
-Ccap@0 gnd net@14 1.143f
-Ccap@1 gnd net@8 1.143f
-Ccap@2 gnd net@11 1.143f
-Rres@0 net@14 a 1.801
-Rres@1 net@11 net@14 3.602
-Rres@2 b net@8 1.801
-Rres@3 net@8 net@11 3.602
-.ENDS wire-C_0_011f-311_7-R_34_667m
+*** CELL: countersL:cntScnThree{sch}
+.SUBCKT cntScnThree cin ctgLO out p1p p2p sin
+XcntScnOn@0 net@88 ctgLO out p1p p2p net@88 cntScnOne
+XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne
+XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne
+Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3
+Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3
+.ENDS cntScnThree
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-311_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-311_7-R_34_667m
-.ENDS wire90-311_7-layer_1-width_3
+*** CELL: countersL:cntScnTwelve{sch}
+.SUBCKT cntScnTwelve cin ctgLO out p1p p2p sin
+XcntScnFo@0 net@60 ctgLO out p1p p2p net@60 cntScnFour
+XcntScnFo@1 cin ctgLO net@43 p1p p2p sin cntScnFour
+XcntScnFo@2 net@61 ctgLO net@46 p1p p2p net@61 cntScnFour
+Xwire90@5 net@43 net@61 wire90-668_5-layer_1-width_3
+Xwire90@6 net@46 net@60 wire90-668_5-layer_1-width_3
+.ENDS cntScnTwelve
-*** CELL: latchesK:latch2in10Alo{sch}
-.SUBCKT latch2in10Alo hcl[A] hcl[B] inA[1] inB[1] out[1]
-Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF
-XinvLT@0 net@15 out[1] invLT-X_10
-Xwire90@0 dataBar net@15 wire90-311_7-layer_1-width_3
-.ENDS latch2in10Alo
+*** CELL: countersL:instructionCount{sch}
+.SUBCKT instructionCount cin count fin fout sid[1] sid[2] sid[3] sid[4]
++sid[5] sid[6] sid[7] sid[8] sid[9] sod[1]
+XcntContr@0 ctgLO myp1p myp2p sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
++sid[7] sid[8] sid[9] sod[1] cntShift
+XcntFreq@0 count ctgLO fin fout net@77 cntFreq
+XcntScnFo@1 cin ctgLO net@1 myp1p myp2p sid[1] cntScnFour
+XcntScnTh@0 net@77 ctgLO net@78 myp1p myp2p net@77 cntScnThree
+XcntScnTw@3 net@2 ctgLO net@124 myp1p myp2p net@2 cntScnTwelve
+XcntScnTw@5 net@136 ctgLO net@144 myp1p myp2p net@136 cntScnTwelve
+Xwire90@0 net@1 net@2 wire90-506_4-layer_1-width_3
+Xwire90@1 net@124 net@77 wire90-506_4-layer_1-width_3
+Xwire90@2 net@78 net@136 wire90-506_4-layer_1-width_3
+Xwire90@3 net@144 sod[1] wire90-506_4-layer_1-width_3
+.ENDS instructionCount
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-218_4-R_34_667m a b
-Ccap@0 gnd net@14 0.801f
-Ccap@1 gnd net@8 0.801f
-Ccap@2 gnd net@11 0.801f
-Rres@0 net@14 a 1.262
-Rres@1 net@11 net@14 2.524
-Rres@2 b net@8 1.262
-Rres@3 net@8 net@11 2.524
-.ENDS wire-C_0_011f-218_4-R_34_667m
+.SUBCKT wire-C_0_011f-146_1-R_34_667m a b
+Ccap@0 gnd net@14 0.536f
+Ccap@1 gnd net@8 0.536f
+Ccap@2 gnd net@11 0.536f
+Rres@0 net@14 a 0.844
+Rres@1 net@11 net@14 1.688
+Rres@2 b net@8 0.844
+Rres@3 net@8 net@11 1.688
+.ENDS wire-C_0_011f-146_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-218_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-218_4-R_34_667m
-.ENDS wire90-218_4-layer_1-width_3
-
-*** CELL: scanJ:scanCellE{sch}
-.SUBCKT scanJ__scanCellE dIn[1] p1p p2p rd sin sout
-Xlatch1in@0 p2p sin net@2 latch1in10A
-Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo
-Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3
-.ENDS scanJ__scanCellE
-
-*** CELL: scanJ:scanEx1vertA{sch}
-.SUBCKT scanEx1vertA dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sor[1]
-XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanJ__scanCellE
-.ENDS scanEx1vertA
+.SUBCKT wire90-146_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-146_1-R_34_667m
+.ENDS wire90-146_1-layer_1-width_3
-*** CELL: stagesM:epiDockStage{sch}
-.SUBCKT epiDockStage do[epi] epi[10] epi[11] epi[12] epi[13] epi[14] epi[15]
-+epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] epi[21] epi[22] epi[23]
-+epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30] epi[31]
-+epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6] epi[7]
-+epi[8] epi[9] epi[OTHER] epi[TAIL] epi[TORP] in[10] in[11] in[12] in[13]
-+in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
-+in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
-+in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] sir[1]
-+sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] take[epi]
-XanEpiSta@1 epi[OTHER] epi[TAIL] epi[TORP] net@5 sir[9] do[epi] net@47 in[28]
-+in[T] gaspEpi
-Xins1in20@0 take[epi] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] epi[10] epi[11] epi[12] epi[13] epi[14]
-+epi[15] epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] epi[21] epi[22]
-+epi[23] epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30]
-+epi[31] epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6]
-+epi[7] epi[8] epi[9] ins1in20Bx36
-XlatchDri@0 net@0 take[epi] latchDriver60
-XscanEx1v@1 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1vertA
-Xwire90@0 net@0 net@5 wire90-372_8-layer_1-width_3
-.ENDS epiDockStage
+*** CELL: latchesK:raw1inLatchF{sch}
+.SUBCKT raw1inLatchF hcl in[1] out[F]
+XlatchFlo@0 out[F] net@58 latchKeep
+XlatchPoi@0 hcl in[1] out[F] net@45 latchPointF
+Xwire90@0 net@45 net@58 wire90-146_1-layer_1-width_3
+.ENDS raw1inLatchF
-*** CELL: redFive:nand2LT_sy{sch}
-.SUBCKT nand2LT_sy-X_10 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_5
-XPMOS@1 out inb vdd PMOSx-X_5
-Xnms2_sy@0 out ina inb nms2_sy-X_10
-.ENDS nand2LT_sy-X_10
+*** CELL: redFive:inv{sch}
+.SUBCKT inv-X_20 in out
+XNMOS@0 out in gnd NMOSx-X_20
+XPMOS@0 out in vdd PMOSx-X_20
+.ENDS inv-X_20
*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_12 d g s
-MNMOSf@0 d g s gnd nch W='36*(1+ABN/sqrt(36*2))' L='2'
-+DELVTO='AVT0N/sqrt(36*2)'
-.ENDS NMOSx-X_12
+.SUBCKT NMOSx-X_60 d g s
+MNMOSf@0 d g s gnd nch W='180*(1+ABN/sqrt(180*2))' L='2'
++DELVTO='AVT0N/sqrt(180*2)'
+.ENDS NMOSx-X_60
*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_9_999 d g s
-MPMOSf@0 d g s vdd pch W='59.994*(1+ABP/sqrt(59.994*2))' L='2'
-+DELVTO='AVT0P/sqrt(59.994*2)'
-.ENDS PMOSx-X_9_999
-
-*** CELL: redFive:pms3{sch}
-.SUBCKT pms3-X_3_333 d g g2 g3
-XPMOS@0 d g3 net@2 PMOSx-X_9_999
-XPMOS@1 net@2 g2 net@5 PMOSx-X_9_999
-XPMOS@2 net@5 g vdd PMOSx-X_9_999
-.ENDS pms3-X_3_333
-
-*** CELL: gates3inM:nor3in6.6sym{sch}
-.SUBCKT nor3in6_6sym inA inB inC out
-XNMOSx@0 out inC gnd NMOSx-X_12
-XNMOSx@7 out inB gnd NMOSx-X_12
-XNMOSx@8 out inA gnd NMOSx-X_12
-Xpms3@0 out inA inB inC pms3-X_3_333
-Xpms3@1 out inC inB inA pms3-X_3_333
-.ENDS nor3in6_6sym
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-956_7-R_34_667m a b
-Ccap@0 gnd net@14 3.508f
-Ccap@1 gnd net@8 3.508f
-Ccap@2 gnd net@11 3.508f
-Rres@0 net@14 a 5.528
-Rres@1 net@11 net@14 11.055
-Rres@2 b net@8 5.528
-Rres@3 net@8 net@11 11.055
-.ENDS wire-C_0_011f-956_7-R_34_667m
+.SUBCKT PMOSx-X_60 d g s
+MPMOSf@0 d g s vdd pch W='360*(1+ABP/sqrt(360*2))' L='2'
++DELVTO='AVT0P/sqrt(360*2)'
+.ENDS PMOSx-X_60
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-956_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-956_7-R_34_667m
-.ENDS wire90-956_7-layer_1-width_3
+*** CELL: redFive:inv{sch}
+.SUBCKT inv-X_60 in out
+XNMOS@0 out in gnd NMOSx-X_60
+XPMOS@0 out in vdd PMOSx-X_60
+.ENDS inv-X_60
*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-294_8-R_34_667m a b
Xwire@0 a b wire-C_0_011f-294_8-R_34_667m
.ENDS wire90-294_8-layer_1-width_3
-*** CELL: oneHotM:onDeck{sch}
-.SUBCKT onDeck bits[ABORT] bits[HEAD] fire[od] flag[A][clr] flag[A][set]
-+flag[D][clr] flag[D][set] mc od[ABORT] od[HEAD] od[OTHER] pred s[1] s[2]
-Xinv@8 pred net@358 inv-X_5
-Xinv@9 bits[HEAD] net@441 inv-X_5
-Xinv@10 bits[ABORT] net@463 inv-X_5
-XinvI@1 net@368 fire[od] inv-X_30
-XinvI@2 net@317 s[2] inv-X_10
-XinvI@3 net@314 s[1] inv-X_10
-Xnand2LT_@0 net@371 net@374 net@367 nand2LT_sy-X_10
-Xnor2_sy@4 flag[A][set] flag[A][clr] net@305 nor2_sy-X_5
-Xnor2_sy@5 flag[D][set] flag[D][clr] net@297 nor2_sy-X_5
-Xnor3in3_@2 net@317 net@436 net@314 net@322 nor3in6_6sym
-Xnor3in3_@5 od[ABORT] od[OTHER] od[HEAD] net@476 nor3in6_6sym
-XpredDri2@2 fire[od] mc pred predDri20wMC
-Xsuc3ANDd@1 net@438 net@485 fire[od] od[OTHER] suc3ANDdri20
-XsucANDdr@0 bits[HEAD] net@444 od[HEAD] sucANDdri20
-XsucANDdr@4 bits[ABORT] fire[od] od[ABORT] sucANDdri20
-Xwire90@10 fire[od] net@444 wire90-956_7-layer_1-width_3
-Xwire90@11 net@322 net@374 wire90-294_8-layer_1-width_3
-Xwire90@13 net@297 net@317 wire90-294_8-layer_1-width_3
-Xwire90@15 net@305 net@436 wire90-294_8-layer_1-width_3
-Xwire90@16 net@358 net@314 wire90-294_8-layer_1-width_3
-Xwire90@18 net@371 net@476 wire90-294_8-layer_1-width_3
-Xwire90@19 net@368 net@367 wire90-294_8-layer_1-width_3
-Xwire90@20 net@441 net@438 wire90-294_8-layer_1-width_3
-Xwire90@21 net@463 net@485 wire90-294_8-layer_1-width_3
-.ENDS onDeck
-
-*** CELL: scanM:scanCellE{sch}
-.SUBCKT scanM__scanCellE dIn[1] p1p p2p rd sin sout
-Xlatch1in@0 p2p sin net@2 latch1in10A
-Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo
-Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3
-.ENDS scanM__scanCellE
-
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-297_6-R_34_667m a b
-Ccap@0 gnd net@14 1.091f
-Ccap@1 gnd net@8 1.091f
-Ccap@2 gnd net@11 1.091f
-Rres@0 net@14 a 1.719
-Rres@1 net@11 net@14 3.439
-Rres@2 b net@8 1.719
-Rres@3 net@8 net@11 3.439
-.ENDS wire-C_0_011f-297_6-R_34_667m
+.SUBCKT wire-C_0_011f-546_2-R_34_667m a b
+Ccap@0 gnd net@14 2.003f
+Ccap@1 gnd net@8 2.003f
+Ccap@2 gnd net@11 2.003f
+Rres@0 net@14 a 3.156
+Rres@1 net@11 net@14 6.312
+Rres@2 b net@8 3.156
+Rres@3 net@8 net@11 6.312
+.ENDS wire-C_0_011f-546_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-297_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-297_6-R_34_667m
-.ENDS wire90-297_6-layer_1-width_3
+.SUBCKT wire90-546_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-546_2-R_34_667m
+.ENDS wire90-546_2-layer_1-width_3
-*** CELL: scanM:scanEx2{sch}
-.SUBCKT scanEx2 dIn[1] dIn[2] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sor[1]
-XscanCell@3 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanM__scanCellE
-XscanCell@4 dIn[2] sir[3] sir[2] sir[5] net@27 sor[1] scanM__scanCellE
-Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
-.ENDS scanEx2
+*** CELL: latchesK:latch1in60C{sch}
+.SUBCKT latch1in60C hcl inS[1] outS[1]
+Xhi2inLat@0 hcl inS[1] net@14 raw1inLatchF
+XinvLT@0 net@15 net@18 invLT-X_5
+XinvLT@1 net@16 net@19 inv-X_20
+XinvLT@2 net@17 outS[1] inv-X_60
+Xwire90@0 net@14 net@15 wire90-294_8-layer_1-width_3
+Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3
+Xwire90@2 net@19 net@17 wire90-546_2-layer_1-width_3
+.ENDS latch1in60C
+
+*** CELL: registersM:addr1in60Cx7{sch}
+.SUBCKT addr1in60Cx7 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1]
++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire
+Xlat[1] fire ain[1] aout[1] latch1in60C
+Xlat[2] fire ain[2] aout[2] latch1in60C
+Xlat[3] fire ain[3] aout[3] latch1in60C
+Xlat[4] fire ain[4] aout[4] latch1in60C
+Xlat[5] fire ain[5] aout[5] latch1in60C
+Xlat[6] fire ain[6] aout[6] latch1in60C
+Xlat[7] fire ain[7] aout[7] latch1in60C
+.ENDS addr1in60Cx7
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-791_7-R_34_667m a b
-Ccap@0 gnd net@14 2.903f
-Ccap@1 gnd net@8 2.903f
-Ccap@2 gnd net@11 2.903f
-Rres@0 net@14 a 4.574
-Rres@1 net@11 net@14 9.149
-Rres@2 b net@8 4.574
-Rres@3 net@8 net@11 9.149
-.ENDS wire-C_0_011f-791_7-R_34_667m
+.SUBCKT wire-C_0_011f-2330-R_34_667m a b
+Ccap@0 gnd net@14 8.543f
+Ccap@1 gnd net@8 8.543f
+Ccap@2 gnd net@11 8.543f
+Rres@0 net@14 a 13.462
+Rres@1 net@11 net@14 26.924
+Rres@2 b net@8 13.462
+Rres@3 net@8 net@11 26.924
+.ENDS wire-C_0_011f-2330-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-791_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-791_7-R_34_667m
-.ENDS wire90-791_7-layer_1-width_3
+.SUBCKT wire90-2330-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2330-R_34_667m
+.ENDS wire90-2330-layer_1-width_3
-*** CELL: stagesM:onDeckDockStage{sch}
-.SUBCKT onDeckDockStage do[od] flag[A][clr] flag[A][set] flag[D][clr]
-+flag[D][set] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18]
-+m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28]
-+m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4]
-+m1[5] m1[6] m1[7] m1[8] m1[9] od[10] od[11] od[12] od[13] od[14] od[15]
-+od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25]
-+od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35]
-+od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] od[ABORT] od[HEAD] od[OTHER]
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1]
-+take[od]
-Xins1in20@0 take[od] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
-+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
-+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] od[10] od[11] od[12] od[13] od[14] od[15]
-+od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25]
-+od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35]
-+od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] ins1in20Bx36
-XlatchDri@0 fire[1] take[od] latchDriver60
-XonDeck@0 m1[29] m1[30] net@11 flag[A][clr] flag[A][set] flag[D][clr]
-+flag[D][set] sir[9] od[ABORT] od[HEAD] od[OTHER] do[od] net@62[1] net@62[0]
-+onDeck
-XscanEx2v@2 net@62[1] net@62[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sor[1] scanEx2
-Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3
-.ENDS onDeckDockStage
+*** CELL: registersM:addr1in60Cx15{sch}
+.SUBCKT addr1in60Cx15 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
++aout[7] aout[8] aout[9] aout[TT] fire
+Xaddr1in6@0 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8]
++aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@17 addr1in60Cx7
+Xaddr1in6@1 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
++aout[3] aout[4] aout[5] aout[6] aout[7] net@19 addr1in60Cx7
+Xlatch1in@0 fire ain[TT] aout[TT] latch1in60C
+Xwire90@0 net@19 fire wire90-2330-layer_1-width_3
+Xwire90@1 fire net@17 wire90-2330-layer_1-width_3
+.ENDS addr1in60Cx15
+
+*** CELL: registersM:data1in60Cx18{sch}
+.SUBCKT data1in60Cx18 dcl in[10] in[11] in[12] in[13] in[14] in[15] in[16]
++in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2]
++out[3] out[4] out[5] out[6] out[7] out[8] out[9]
+Xlat[1] dcl in[1] out[1] latch1in60C
+Xlat[2] dcl in[2] out[2] latch1in60C
+Xlat[3] dcl in[3] out[3] latch1in60C
+Xlat[4] dcl in[4] out[4] latch1in60C
+Xlat[5] dcl in[5] out[5] latch1in60C
+Xlat[6] dcl in[6] out[6] latch1in60C
+Xlat[7] dcl in[7] out[7] latch1in60C
+Xlat[8] dcl in[8] out[8] latch1in60C
+Xlat[9] dcl in[9] out[9] latch1in60C
+Xlat[10] dcl in[10] out[10] latch1in60C
+Xlat[11] dcl in[11] out[11] latch1in60C
+Xlat[12] dcl in[12] out[12] latch1in60C
+Xlat[13] dcl in[13] out[13] latch1in60C
+Xlat[14] dcl in[14] out[14] latch1in60C
+Xlat[15] dcl in[15] out[15] latch1in60C
+Xlat[16] dcl in[16] out[16] latch1in60C
+Xlat[17] dcl in[17] out[17] latch1in60C
+Xlat[18] dcl in[18] out[18] latch1in60C
+.ENDS data1in60Cx18
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-242_1-R_34_667m a b
-Ccap@0 gnd net@14 0.888f
-Ccap@1 gnd net@8 0.888f
-Ccap@2 gnd net@11 0.888f
-Rres@0 net@14 a 1.399
-Rres@1 net@11 net@14 2.798
-Rres@2 b net@8 1.399
-Rres@3 net@8 net@11 2.798
-.ENDS wire-C_0_011f-242_1-R_34_667m
+.SUBCKT wire-C_0_011f-2550-R_34_667m a b
+Ccap@0 gnd net@14 9.35f
+Ccap@1 gnd net@8 9.35f
+Ccap@2 gnd net@11 9.35f
+Rres@0 net@14 a 14.733
+Rres@1 net@11 net@14 29.467
+Rres@2 b net@8 14.733
+Rres@3 net@8 net@11 29.467
+.ENDS wire-C_0_011f-2550-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-242_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-242_1-R_34_667m
-.ENDS wire90-242_1-layer_1-width_3
+.SUBCKT wire90-2550-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2550-R_34_667m
+.ENDS wire90-2550-layer_1-width_3
-*** CELL: latchesK:latch2in20A{sch}
-.SUBCKT latch2in20A hcl[A] hcl[B] inA[1] inB[1] out[1]
-Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@36 raw2inLatchF
-XinvLT@1 net@16 out[1] inv-X_20
-Xwire90@1 net@36 net@16 wire90-242_1-layer_1-width_3
-.ENDS latch2in20A
+*** CELL: registersM:data1in60Cx37{sch}
+.SUBCKT data1in60Cx37 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37]
++in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4]
++out[5] out[6] out[7] out[8] out[9] take
+Xdata1in6@1 net@19 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
++out[4] out[5] out[6] out[7] out[8] out[9] data1in60Cx18
+Xdata1in6@2 net@17 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
++in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29]
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20]
++out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] data1in60Cx18
+Xlatch1in@0 take in[19] out[19] latch1in60C
+Xwire90@2 take net@17 wire90-2550-layer_1-width_3
+Xwire90@3 net@19 take wire90-2550-layer_1-width_3
+.ENDS data1in60Cx37
-*** CELL: registersM:ins2in20Ax18{sch}
-.SUBCKT ins2in20Ax18 hcl[A] hcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
-+inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6]
-+inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16]
-+inB[17] inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
-+inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
-+out[18] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-Xlx[1] hcl[A] hcl[B] inA[1] inB[1] out[1] latch2in20A
-Xlx[2] hcl[A] hcl[B] inA[2] inB[2] out[2] latch2in20A
-Xlx[3] hcl[A] hcl[B] inA[3] inB[3] out[3] latch2in20A
-Xlx[4] hcl[A] hcl[B] inA[4] inB[4] out[4] latch2in20A
-Xlx[5] hcl[A] hcl[B] inA[5] inB[5] out[5] latch2in20A
-Xlx[6] hcl[A] hcl[B] inA[6] inB[6] out[6] latch2in20A
-Xlx[7] hcl[A] hcl[B] inA[7] inB[7] out[7] latch2in20A
-Xlx[8] hcl[A] hcl[B] inA[8] inB[8] out[8] latch2in20A
-Xlx[9] hcl[A] hcl[B] inA[9] inB[9] out[9] latch2in20A
-Xlx[10] hcl[A] hcl[B] inA[10] inB[10] out[10] latch2in20A
-Xlx[11] hcl[A] hcl[B] inA[11] inB[11] out[11] latch2in20A
-Xlx[12] hcl[A] hcl[B] inA[12] inB[12] out[12] latch2in20A
-Xlx[13] hcl[A] hcl[B] inA[13] inB[13] out[13] latch2in20A
-Xlx[14] hcl[A] hcl[B] inA[14] inB[14] out[14] latch2in20A
-Xlx[15] hcl[A] hcl[B] inA[15] inB[15] out[15] latch2in20A
-Xlx[16] hcl[A] hcl[B] inA[16] inB[16] out[16] latch2in20A
-Xlx[17] hcl[A] hcl[B] inA[17] inB[17] out[17] latch2in20A
-Xlx[18] hcl[A] hcl[B] inA[18] inB[18] out[18] latch2in20A
-.ENDS ins2in20Ax18
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_25 d g s
+MPMOSf@0 d g s vdd pch W='150*(1+ABP/sqrt(150*2))' L='2'
++DELVTO='AVT0P/sqrt(150*2)'
+.ENDS PMOSx-X_25
-*** CELL: registersM:ins2in20Ax36{sch}
-.SUBCKT ins2in20Ax36 hcl[A] hcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
-+inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22]
-+inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30]
-+inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6]
-+inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16]
-+inB[17] inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24]
-+inB[25] inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32]
-+inB[33] inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
-+inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
-+out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25]
-+out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33]
-+out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-Xins2in20@2 net@178 net@162 inA[28] inA[29] inA[30] inA[31] inA[32] inA[33]
-+inA[34] inA[35] inA[36] inA[19] inA[20] inA[21] inA[22] inA[23] inA[24]
-+inA[25] inA[26] inA[27] inB[28] inB[29] inB[30] inB[31] inB[32] inB[33]
-+inB[34] inB[35] inB[36] inB[19] inB[20] inB[21] inB[22] inB[23] inB[24]
-+inB[25] inB[26] inB[27] out[28] out[29] out[30] out[31] out[32] out[33]
-+out[34] out[35] out[36] out[19] out[20] out[21] out[22] out[23] out[24]
-+out[25] out[26] out[27] ins2in20Ax18
-Xins2in20@3 net@157 net@177 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
-+inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax18
-Xwire90@0 net@178 hcl[A] wire90-2550-layer_1-width_3
-Xwire90@1 hcl[A] net@157 wire90-2550-layer_1-width_3
-Xwire90@2 net@162 hcl[B] wire90-2550-layer_1-width_3
-Xwire90@3 hcl[B] net@177 wire90-2550-layer_1-width_3
-.ENDS ins2in20Ax36
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_50 d g s
+MNMOSf@0 d g s gnd nch W='150*(1+ABN/sqrt(150*2))' L='2'
++DELVTO='AVT0N/sqrt(150*2)'
+.ENDS NMOSx-X_50
+
+*** CELL: redFive:nms2{sch}
+.SUBCKT nms2-X_25 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_50
+XNMOS@1 net@0 g gnd NMOSx-X_50
+.ENDS nms2-X_25
+
+*** CELL: redFive:nand2{sch}
+.SUBCKT nand2-X_25 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_25
+XPMOS@1 out inb vdd PMOSx-X_25
+Xnms2@0 out ina inb nms2-X_25
+.ENDS nand2-X_25
+
+*** CELL: arbiterM:half2inArb{sch}
+.SUBCKT half2inArb cross grant[B] inA req[B]
+XNMOSx@0 vdd req[B] grant[B] PMOSx-X_10
+XPMOSx@0 cross inA grant[B] NMOSx-X_10
+Xnor2n@0 inA req[B] cross nand2-X_25
+.ENDS half2inArb
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-927-R_34_667m a b
-Ccap@0 gnd net@14 3.399f
-Ccap@1 gnd net@8 3.399f
-Ccap@2 gnd net@11 3.399f
-Rres@0 net@14 a 5.356
-Rres@1 net@11 net@14 10.712
-Rres@2 b net@8 5.356
-Rres@3 net@8 net@11 10.712
-.ENDS wire-C_0_011f-927-R_34_667m
+.SUBCKT wire-C_0_011f-830_7-R_34_667m a b
+Ccap@0 gnd net@14 3.046f
+Ccap@1 gnd net@8 3.046f
+Ccap@2 gnd net@11 3.046f
+Rres@0 net@14 a 4.8
+Rres@1 net@11 net@14 9.599
+Rres@2 b net@8 4.8
+Rres@3 net@8 net@11 9.599
+.ENDS wire-C_0_011f-830_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-927-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-927-R_34_667m
-.ENDS wire90-927-layer_1-width_3
+.SUBCKT wire90-830_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-830_7-R_34_667m
+.ENDS wire90-830_7-layer_1-width_3
-*** CELL: centersJ:ctrAND1in30{sch}
-.SUBCKT ctrAND1in30 in out
-Xinv@11 net@125 net@120 inv-X_10
-XinvI@1 net@82 out inv-X_30
-XinvI@2 in net@101 inv-X_5
-Xwire90@1 net@101 net@125 wire90-414-layer_1-width_3
-Xwire90@2 net@120 net@82 wire90-927-layer_1-width_3
-.ENDS ctrAND1in30
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-834_6-R_34_667m a b
+Ccap@0 gnd net@14 3.06f
+Ccap@1 gnd net@8 3.06f
+Ccap@2 gnd net@11 3.06f
+Rres@0 net@14 a 4.822
+Rres@1 net@11 net@14 9.644
+Rres@2 b net@8 4.822
+Rres@3 net@8 net@11 9.644
+.ENDS wire-C_0_011f-834_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-834_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-834_6-R_34_667m
+.ENDS wire90-834_6-layer_1-width_3
+
+*** CELL: arbiterM:arbiter2{sch}
+.SUBCKT arbiter2 grant[A] grant[B] req[A] req[B]
+XhalfArb@2 net@12 grant[A] net@5 req[A] half2inArb
+XhalfArb@3 net@13 grant[B] net@8 req[B] half2inArb
+Xwire90@0 net@12 net@8 wire90-830_7-layer_1-width_3
+Xwire90@1 net@5 net@13 wire90-834_6-layer_1-width_3
+.ENDS arbiter2
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_100 d g s
+MNMOSf@0 d g s gnd nch W='300*(1+ABN/sqrt(300*2))' L='2'
++DELVTO='AVT0N/sqrt(300*2)'
+.ENDS NMOSx-X_100
*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_6 d g s
-MPMOSf@0 d g s vdd pch W='36*(1+ABP/sqrt(36*2))' L='2'
-+DELVTO='AVT0P/sqrt(36*2)'
-.ENDS PMOSx-X_6
+.SUBCKT PMOSx-X_100 d g s
+MPMOSf@0 d g s vdd pch W='600*(1+ABP/sqrt(600*2))' L='2'
++DELVTO='AVT0P/sqrt(600*2)'
+.ENDS PMOSx-X_100
*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_6 in out
-XNMOS@0 out in gnd NMOSx-X_6
-XPMOS@0 out in vdd PMOSx-X_6
-.ENDS inv-X_6
-
-*** CELL: redFive:pms1{sch}
-.SUBCKT pms1-X_20 d g
-XPMOS@0 d g vdd PMOSx-X_20
-.ENDS pms1-X_20
+.SUBCKT inv-X_100 in out
+XNMOS@0 out in gnd NMOSx-X_100
+XPMOS@0 out in vdd PMOSx-X_100
+.ENDS inv-X_100
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-124_7-R_34_667m a b
-Ccap@0 gnd net@14 0.457f
-Ccap@1 gnd net@8 0.457f
-Ccap@2 gnd net@11 0.457f
-Rres@0 net@14 a 0.72
-Rres@1 net@11 net@14 1.441
-Rres@2 b net@8 0.72
-Rres@3 net@8 net@11 1.441
-.ENDS wire-C_0_011f-124_7-R_34_667m
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_15 d g s
+MPMOSf@0 d g s vdd pch W='90*(1+ABP/sqrt(90*2))' L='2'
++DELVTO='AVT0P/sqrt(90*2)'
+.ENDS PMOSx-X_15
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-124_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-124_7-R_34_667m
-.ENDS wire90-124_7-layer_1-width_3
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_30 d g s
+MNMOSf@0 d g s gnd nch W='90*(1+ABN/sqrt(90*2))' L='2'
++DELVTO='AVT0N/sqrt(90*2)'
+.ENDS NMOSx-X_30
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-503_4-R_34_667m a b
-Ccap@0 gnd net@14 1.846f
-Ccap@1 gnd net@8 1.846f
-Ccap@2 gnd net@11 1.846f
-Rres@0 net@14 a 2.909
-Rres@1 net@11 net@14 5.817
-Rres@2 b net@8 2.909
-Rres@3 net@8 net@11 5.817
-.ENDS wire-C_0_011f-503_4-R_34_667m
+*** CELL: redFive:nms2{sch}
+.SUBCKT nms2-X_15 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_30
+XNMOS@1 net@0 g gnd NMOSx-X_30
+.ENDS nms2-X_15
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-503_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-503_4-R_34_667m
-.ENDS wire90-503_4-layer_1-width_3
+*** CELL: redFive:nms2_sy{sch}
+.SUBCKT nms2_sy-X_30 d g g2
+Xnms2@0 d g g2 nms2-X_15
+Xnms2@1 d g2 g nms2-X_15
+.ENDS nms2_sy-X_30
-*** CELL: driversL:sucDri20{sch}
-.SUBCKT sucDri20 in succ
-Xinv@1 succ net@94 inv-X_4
-Xinv@2 in net@110 inv-X_6
-Xnms2@0 succ net@117 net@109 nms2-X_2
-Xpms1@0 succ net@109 pms1-X_20
-Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3
-Xwire90@1 net@110 net@109 wire90-503_4-layer_1-width_3
-.ENDS sucDri20
+*** CELL: redFive:nand2LT_sy{sch}
+.SUBCKT nand2LT_sy-X_30 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_15
+XPMOS@1 out inb vdd PMOSx-X_15
+Xnms2_sy@0 out ina inb nms2_sy-X_30
+.ENDS nand2LT_sy-X_30
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-301_8-R_34_667m a b
-Ccap@0 gnd net@14 1.107f
-Ccap@1 gnd net@8 1.107f
-Ccap@2 gnd net@11 1.107f
-Rres@0 net@14 a 1.744
-Rres@1 net@11 net@14 3.487
-Rres@2 b net@8 1.744
-Rres@3 net@8 net@11 3.487
-.ENDS wire-C_0_011f-301_8-R_34_667m
+.SUBCKT wire-C_0_011f-399_2-R_34_667m a b
+Ccap@0 gnd net@14 1.464f
+Ccap@1 gnd net@8 1.464f
+Ccap@2 gnd net@11 1.464f
+Rres@0 net@14 a 2.306
+Rres@1 net@11 net@14 4.613
+Rres@2 b net@8 2.306
+Rres@3 net@8 net@11 4.613
+.ENDS wire-C_0_011f-399_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-301_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-301_8-R_34_667m
-.ENDS wire90-301_8-layer_1-width_3
+.SUBCKT wire90-399_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-399_2-R_34_667m
+.ENDS wire90-399_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-732_5-R_34_667m a b
-Ccap@0 gnd net@14 2.686f
-Ccap@1 gnd net@8 2.686f
-Ccap@2 gnd net@11 2.686f
-Rres@0 net@14 a 4.232
-Rres@1 net@11 net@14 8.464
-Rres@2 b net@8 4.232
-Rres@3 net@8 net@11 8.464
-.ENDS wire-C_0_011f-732_5-R_34_667m
+.SUBCKT wire-C_0_011f-1013_8-R_34_667m a b
+Ccap@0 gnd net@14 3.717f
+Ccap@1 gnd net@8 3.717f
+Ccap@2 gnd net@11 3.717f
+Rres@0 net@14 a 5.858
+Rres@1 net@11 net@14 11.715
+Rres@2 b net@8 5.858
+Rres@3 net@8 net@11 11.715
+.ENDS wire-C_0_011f-1013_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-732_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-732_5-R_34_667m
-.ENDS wire90-732_5-layer_1-width_3
+.SUBCKT wire90-1013_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1013_8-R_34_667m
+.ENDS wire90-1013_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-142_6-R_34_667m a b
-Ccap@0 gnd net@14 0.523f
-Ccap@1 gnd net@8 0.523f
-Ccap@2 gnd net@11 0.523f
-Rres@0 net@14 a 0.824
-Rres@1 net@11 net@14 1.648
-Rres@2 b net@8 0.824
-Rres@3 net@8 net@11 1.648
-.ENDS wire-C_0_011f-142_6-R_34_667m
+.SUBCKT wire-C_0_011f-468_3-R_34_667m a b
+Ccap@0 gnd net@14 1.717f
+Ccap@1 gnd net@8 1.717f
+Ccap@2 gnd net@11 1.717f
+Rres@0 net@14 a 2.706
+Rres@1 net@11 net@14 5.411
+Rres@2 b net@8 2.706
+Rres@3 net@8 net@11 5.411
+.ENDS wire-C_0_011f-468_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-142_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-142_6-R_34_667m
-.ENDS wire90-142_6-layer_1-width_3
+.SUBCKT wire90-468_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-468_3-R_34_667m
+.ENDS wire90-468_3-layer_1-width_3
-*** CELL: oneHotM:reQueueB{sch}
-.SUBCKT reQueueB circulate epi[TAIL] mc od[HEAD] s[1] s[2]
-XctrAND1i@0 net@1 net@7 ctrAND1in30
-Xinv@2 od[HEAD] net@127 inv-X_5
-Xinv@3 epi[TAIL] net@125 inv-X_5
-XinvI@3 net@128 s[1] inv-X_10
-XinvI@4 net@126 s[2] inv-X_10
-Xnand2@0 od[HEAD] epi[TAIL] net@0 nand2-X_5
-XpredDri2@1 net@7 mc epi[TAIL] predDri20wMC
-XpredDri2@2 net@7 mc od[HEAD] predDri20wMC
-XsucDri20@0 net@9 circulate sucDri20
-Xwire90@0 net@0 net@1 wire90-301_8-layer_1-width_3
-Xwire90@1 net@7 net@9 wire90-732_5-layer_1-width_3
-Xwire90@2 net@126 net@125 wire90-142_6-layer_1-width_3
-Xwire90@3 net@128 net@127 wire90-142_6-layer_1-width_3
-.ENDS reQueueB
+*** CELL: centersJ:ctrAND2in100LT{sch}
+.SUBCKT ctrAND2in100LT inA inB out
+Xinv@8 inB net@135 inv-X_10
+Xinv@9 inA net@139 inv-X_10
+Xinv@10 net@146 out inv-X_100
+Xnand2LT_@0 net@140 net@136 net@144 nand2LT_sy-X_30
+Xwire90@4 net@135 net@136 wire90-399_2-layer_1-width_3
+Xwire90@5 net@144 net@146 wire90-1013_8-layer_1-width_3
+Xwire90@6 net@139 net@140 wire90-468_3-layer_1-width_3
+.ENDS ctrAND2in100LT
*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_10 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_20
-XNMOS@1 net@0 g gnd NMOSx-X_20
-.ENDS nms2-X_10
+.SUBCKT nms2-X_20 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_40
+XNMOS@1 net@0 g gnd NMOSx-X_40
+.ENDS nms2-X_20
*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_10 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_10
-XPMOS@1 out inb vdd PMOSx-X_10
-Xnms2@0 out ina inb nms2-X_10
-.ENDS nand2-X_10
+.SUBCKT nand2-X_20 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_20
+XPMOS@1 out inb vdd PMOSx-X_20
+Xnms2@0 out ina inb nms2-X_20
+.ENDS nand2-X_20
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-252_6-R_34_667m a b
-Ccap@0 gnd net@14 0.926f
-Ccap@1 gnd net@8 0.926f
-Ccap@2 gnd net@11 0.926f
-Rres@0 net@14 a 1.459
-Rres@1 net@11 net@14 2.919
-Rres@2 b net@8 1.459
-Rres@3 net@8 net@11 2.919
-.ENDS wire-C_0_011f-252_6-R_34_667m
+.SUBCKT wire-C_0_011f-698_4-R_34_667m a b
+Ccap@0 gnd net@14 2.561f
+Ccap@1 gnd net@8 2.561f
+Ccap@2 gnd net@11 2.561f
+Rres@0 net@14 a 4.035
+Rres@1 net@11 net@14 8.07
+Rres@2 b net@8 4.035
+Rres@3 net@8 net@11 8.07
+.ENDS wire-C_0_011f-698_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-252_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-252_6-R_34_667m
-.ENDS wire90-252_6-layer_1-width_3
+.SUBCKT wire90-698_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-698_4-R_34_667m
+.ENDS wire90-698_4-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-366_8-R_34_667m a b
-Ccap@0 gnd net@14 1.345f
-Ccap@1 gnd net@8 1.345f
-Ccap@2 gnd net@11 1.345f
-Rres@0 net@14 a 2.119
-Rres@1 net@11 net@14 4.239
-Rres@2 b net@8 2.119
-Rres@3 net@8 net@11 4.239
-.ENDS wire-C_0_011f-366_8-R_34_667m
+*** CELL: driversL:dataDriver60{sch}
+.SUBCKT dataDriver60 inA inB out
+Xinv@0 net@8 out inv-X_60
+Xnand2@1 inA inB net@7 nand2-X_20
+Xwire90@0 net@7 net@8 wire90-698_4-layer_1-width_3
+.ENDS dataDriver60
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-366_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-366_8-R_34_667m
-.ENDS wire90-366_8-layer_1-width_3
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_9_999 d g s
+MPMOSf@0 d g s vdd pch W='59.994*(1+ABP/sqrt(59.994*2))' L='2'
++DELVTO='AVT0P/sqrt(59.994*2)'
+.ENDS PMOSx-X_9_999
+
+*** CELL: redFive:pms3{sch}
+.SUBCKT pms3-X_3_333 d g g2 g3
+XPMOS@0 d g3 net@2 PMOSx-X_9_999
+XPMOS@1 net@2 g2 net@5 PMOSx-X_9_999
+XPMOS@2 net@5 g vdd PMOSx-X_9_999
+.ENDS pms3-X_3_333
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-176_4-R_34_667m a b
-Ccap@0 gnd net@14 0.647f
-Ccap@1 gnd net@8 0.647f
-Ccap@2 gnd net@11 0.647f
-Rres@0 net@14 a 1.019
-Rres@1 net@11 net@14 2.038
-Rres@2 b net@8 1.019
-Rres@3 net@8 net@11 2.038
-.ENDS wire-C_0_011f-176_4-R_34_667m
+.SUBCKT wire-C_0_011f-243_6-R_34_667m a b
+Ccap@0 gnd net@14 0.893f
+Ccap@1 gnd net@8 0.893f
+Ccap@2 gnd net@11 0.893f
+Rres@0 net@14 a 1.407
+Rres@1 net@11 net@14 2.815
+Rres@2 b net@8 1.407
+Rres@3 net@8 net@11 2.815
+.ENDS wire-C_0_011f-243_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-176_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-176_4-R_34_667m
-.ENDS wire90-176_4-layer_1-width_3
+.SUBCKT wire90-243_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-243_6-R_34_667m
+.ENDS wire90-243_6-layer_1-width_3
-*** CELL: centersJ:ctrAND3in30{sch}
-.SUBCKT ctrAND3in30 inA inB inC out
-Xinv@4 inC net@30 inv-X_4
-Xinv@5 net@9 out inv-X_30
-Xnand2@0 net@19 net@15 net@27 nand2-X_10
-Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5
-Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
-Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
-Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
-.ENDS ctrAND3in30
+*** CELL: driversJ:predDri60wMC{sch}
+.SUBCKT driversJ__predDri60wMC in mc pred
+XNMOSx@0 pred in gnd NMOSx-X_60
+XNMOSx@1 pred mc gnd NMOSx-X_10
+Xinv@0 pred net@145 inv-X_10
+Xpms3@0 pred mc in net@174 pms3-X_3_333
+Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3
+.ENDS driversJ__predDri60wMC
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_3 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_6
-XNMOS@1 net@0 g gnd NMOSx-X_6
-.ENDS nms2-X_3
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_16 d g s
+MNMOSf@0 d g s gnd nch W='48*(1+ABN/sqrt(48*2))' L='2'
++DELVTO='AVT0N/sqrt(48*2)'
+.ENDS NMOSx-X_16
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_6 d g g2
-Xnms2@0 d g g2 nms2-X_3
-Xnms2@1 d g2 g nms2-X_3
-.ENDS nms2_sy-X_6
+*** CELL: redFive:nms2{sch}
+.SUBCKT nms2-X_8 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_16
+XNMOS@1 net@0 g gnd NMOSx-X_16
+.ENDS nms2-X_8
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_6 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_6
-XPMOS@1 out ina vdd PMOSx-X_6
-Xnms2_sy@0 out ina inb nms2_sy-X_6
-.ENDS nand2_sy-X_6
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-627_9-R_34_667m a b
+Ccap@0 gnd net@14 2.302f
+Ccap@1 gnd net@8 2.302f
+Ccap@2 gnd net@11 2.302f
+Rres@0 net@14 a 3.628
+Rres@1 net@11 net@14 7.256
+Rres@2 b net@8 3.628
+Rres@3 net@8 net@11 7.256
+.ENDS wire-C_0_011f-627_9-R_34_667m
-*** CELL: redFive:nand2n{sch}
-.SUBCKT nand2n-X_5 ina inb out
-Xnand2@0 ina inb out nand2-X_5
-.ENDS nand2n-X_5
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-627_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-627_9-R_34_667m
+.ENDS wire90-627_9-layer_1-width_3
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_20 d g g2
-Xnms2@0 d g g2 nms2-X_10
-Xnms2@1 d g2 g nms2-X_10
-.ENDS nms2_sy-X_20
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-124_7-R_34_667m a b
+Ccap@0 gnd net@14 0.457f
+Ccap@1 gnd net@8 0.457f
+Ccap@2 gnd net@11 0.457f
+Rres@0 net@14 a 0.72
+Rres@1 net@11 net@14 1.441
+Rres@2 b net@8 0.72
+Rres@3 net@8 net@11 1.441
+.ENDS wire-C_0_011f-124_7-R_34_667m
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_20 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_20
-XPMOS@1 out ina vdd PMOSx-X_20
-Xnms2_sy@0 out ina inb nms2_sy-X_20
-.ENDS nand2_sy-X_20
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-124_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-124_7-R_34_667m
+.ENDS wire90-124_7-layer_1-width_3
-*** CELL: redFive:nand2n_sy{sch}
-.SUBCKT nand2n_sy-X_20 ina inb out
-Xnand2_sy@0 ina inb out nand2_sy-X_20
-.ENDS nand2n_sy-X_20
+*** CELL: driversL:sucANDdri60{sch}
+.SUBCKT sucANDdri60 inA inB succ
+XPMOSx@0 succ net@51 vdd PMOSx-X_60
+Xinv@0 succ net@71 inv-X_5
+Xnand2@0 inA inB net@67 nand2-X_10
+Xnms2@0 succ net@51 net@72 nms2-X_8
+Xwire90@0 net@67 net@51 wire90-627_9-layer_1-width_3
+Xwire90@1 net@72 net@71 wire90-124_7-layer_1-width_3
+.ENDS sucANDdri60
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_9_999 d g s
-MNMOSf@0 d g s gnd nch W='29.997*(1+ABN/sqrt(29.997*2))' L='2'
-+DELVTO='AVT0N/sqrt(29.997*2)'
-.ENDS NMOSx-X_9_999
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-175-R_34_667m a b
+Ccap@0 gnd net@14 0.642f
+Ccap@1 gnd net@8 0.642f
+Ccap@2 gnd net@11 0.642f
+Rres@0 net@14 a 1.011
+Rres@1 net@11 net@14 2.022
+Rres@2 b net@8 1.011
+Rres@3 net@8 net@11 2.022
+.ENDS wire-C_0_011f-175-R_34_667m
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_3_333 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_9_999
-XNMOS@1 net@7 g gnd NMOSx-X_9_999
-XNMOS@2 net@6 g2 net@7 NMOSx-X_9_999
-.ENDS nms3-X_3_333
-
-*** CELL: gates3inM:nand3in6.6sym{sch}
-.SUBCKT nand3in6_6sym inA inB inC out
-XPMOSx@1 out inA vdd PMOSx-X_10
-XPMOSx@3 out inC vdd PMOSx-X_10
-XPMOSx@4 out inB vdd PMOSx-X_10
-Xnms3@0 out inA inB inC nms3-X_3_333
-Xnms3@2 out inC inB inA nms3-X_3_333
-.ENDS nand3in6_6sym
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_10 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_20
-XPMOS@1 d g2 net@2 PMOSx-X_20
-.ENDS pms2-X_10
-
-*** CELL: redFive:nor2{sch}
-.SUBCKT nor2-X_10 ina inb out
-XNMOS@0 out ina gnd NMOSx-X_10
-XNMOS@1 out inb gnd NMOSx-X_10
-Xpms2@0 out ina inb pms2-X_10
-.ENDS nor2-X_10
-
-*** CELL: redFive:nor2n{sch}
-.SUBCKT nor2n-X_10 ina inb out
-Xnor2@0 ina inb out nor2-X_10
-.ENDS nor2n-X_10
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-175-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-175-R_34_667m
+.ENDS wire90-175-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1001_8-R_34_667m a b
-Ccap@0 gnd net@14 3.673f
-Ccap@1 gnd net@8 3.673f
-Ccap@2 gnd net@11 3.673f
-Rres@0 net@14 a 5.788
-Rres@1 net@11 net@14 11.576
-Rres@2 b net@8 5.788
-Rres@3 net@8 net@11 11.576
-.ENDS wire-C_0_011f-1001_8-R_34_667m
+.SUBCKT wire-C_0_011f-516_9-R_34_667m a b
+Ccap@0 gnd net@14 1.895f
+Ccap@1 gnd net@8 1.895f
+Ccap@2 gnd net@11 1.895f
+Rres@0 net@14 a 2.987
+Rres@1 net@11 net@14 5.973
+Rres@2 b net@8 2.987
+Rres@3 net@8 net@11 5.973
+.ENDS wire-C_0_011f-516_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1001_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1001_8-R_34_667m
-.ENDS wire90-1001_8-layer_1-width_3
+.SUBCKT wire90-516_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-516_9-R_34_667m
+.ENDS wire90-516_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-209-R_34_667m a b
-Ccap@0 gnd net@14 0.766f
-Ccap@1 gnd net@8 0.766f
-Ccap@2 gnd net@11 0.766f
-Rres@0 net@14 a 1.208
-Rres@1 net@11 net@14 2.415
-Rres@2 b net@8 1.208
-Rres@3 net@8 net@11 2.415
-.ENDS wire-C_0_011f-209-R_34_667m
+.SUBCKT wire-C_0_011f-160_4-R_34_667m a b
+Ccap@0 gnd net@14 0.588f
+Ccap@1 gnd net@8 0.588f
+Ccap@2 gnd net@11 0.588f
+Rres@0 net@14 a 0.927
+Rres@1 net@11 net@14 1.854
+Rres@2 b net@8 0.927
+Rres@3 net@8 net@11 1.854
+.ENDS wire-C_0_011f-160_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-209-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-209-R_34_667m
-.ENDS wire90-209-layer_1-width_3
-
-*** CELL: driversL:sucORdri20{sch}
-.SUBCKT sucORdri20 inA inB succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_20
-Xinv@0 succ net@71 inv-X_4
-Xnms2@0 succ net@73 net@51 nms2-X_2
-Xnor2_sy@0 inA inB net@67 nor2_sy-X_5
-Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3
-Xwire90@1 net@73 net@71 wire90-209-layer_1-width_3
-.ENDS sucORdri20
+.SUBCKT wire90-160_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-160_4-R_34_667m
+.ENDS wire90-160_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-286_3-R_34_667m a b
-Ccap@0 gnd net@14 1.05f
-Ccap@1 gnd net@8 1.05f
-Ccap@2 gnd net@11 1.05f
-Rres@0 net@14 a 1.654
-Rres@1 net@11 net@14 3.308
-Rres@2 b net@8 1.654
-Rres@3 net@8 net@11 3.308
-.ENDS wire-C_0_011f-286_3-R_34_667m
+.SUBCKT wire-C_0_011f-130_1-R_34_667m a b
+Ccap@0 gnd net@14 0.477f
+Ccap@1 gnd net@8 0.477f
+Ccap@2 gnd net@11 0.477f
+Rres@0 net@14 a 0.752
+Rres@1 net@11 net@14 1.503
+Rres@2 b net@8 0.752
+Rres@3 net@8 net@11 1.503
+.ENDS wire-C_0_011f-130_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-286_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-286_3-R_34_667m
-.ENDS wire90-286_3-layer_1-width_3
+.SUBCKT wire90-130_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-130_1-R_34_667m
+.ENDS wire90-130_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-428_8-R_34_667m a b
-Ccap@0 gnd net@14 1.572f
-Ccap@1 gnd net@8 1.572f
-Ccap@2 gnd net@11 1.572f
-Rres@0 net@14 a 2.478
-Rres@1 net@11 net@14 4.955
-Rres@2 b net@8 2.478
-Rres@3 net@8 net@11 4.955
-.ENDS wire-C_0_011f-428_8-R_34_667m
+.SUBCKT wire-C_0_011f-142_6-R_34_667m a b
+Ccap@0 gnd net@14 0.523f
+Ccap@1 gnd net@8 0.523f
+Ccap@2 gnd net@11 0.523f
+Rres@0 net@14 a 0.824
+Rres@1 net@11 net@14 1.648
+Rres@2 b net@8 0.824
+Rres@3 net@8 net@11 1.648
+.ENDS wire-C_0_011f-142_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-428_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-428_8-R_34_667m
-.ENDS wire90-428_8-layer_1-width_3
+.SUBCKT wire90-142_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-142_6-R_34_667m
+.ENDS wire90-142_6-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-356_7-R_34_667m a b
-Ccap@0 gnd net@14 1.308f
-Ccap@1 gnd net@8 1.308f
-Ccap@2 gnd net@11 1.308f
-Rres@0 net@14 a 2.061
-Rres@1 net@11 net@14 4.122
-Rres@2 b net@8 2.061
-Rres@3 net@8 net@11 4.122
-.ENDS wire-C_0_011f-356_7-R_34_667m
+.SUBCKT wire-C_0_011f-350_6-R_34_667m a b
+Ccap@0 gnd net@14 1.286f
+Ccap@1 gnd net@8 1.286f
+Ccap@2 gnd net@11 1.286f
+Rres@0 net@14 a 2.026
+Rres@1 net@11 net@14 4.051
+Rres@2 b net@8 2.026
+Rres@3 net@8 net@11 4.051
+.ENDS wire-C_0_011f-350_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-356_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-356_7-R_34_667m
-.ENDS wire90-356_7-layer_1-width_3
+.SUBCKT wire90-350_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-350_6-R_34_667m
+.ENDS wire90-350_6-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-199_1-R_34_667m a b
-Ccap@0 gnd net@14 0.73f
-Ccap@1 gnd net@8 0.73f
-Ccap@2 gnd net@11 0.73f
-Rres@0 net@14 a 1.15
-Rres@1 net@11 net@14 2.301
-Rres@2 b net@8 1.15
-Rres@3 net@8 net@11 2.301
-.ENDS wire-C_0_011f-199_1-R_34_667m
+*** CELL: gaspM:gaspDrain{sch}
+.SUBCKT gaspDrain clear fire go pred s[1] s[2] silent succ take tok
+Xarbiter2@0 net@374 net@353 pred net@375 arbiter2
+XctrAND2i@5 net@241 succ fire ctrAND2in100LT
+XdataDriv@0 tok fire take dataDriver60
+Xinv@1 go net@360 inv-X_10
+Xinv@4 pred net@472 inv-X_5
+Xinv@5 silent net@463 inv-X_10
+XinvI@0 net@357 net@409 inv-X_10
+XinvI@1 net@475 s[1] inv-X_10
+XpredDri6@0 fire clear pred driversJ__predDri60wMC
+XsucANDdr@4 net@499 fire succ sucANDdri60
+Xwire90@1 net@374 net@241 wire90-175-layer_1-width_3
+Xwire90@7 net@375 net@360 wire90-516_9-layer_1-width_3
+Xwire90@10 net@357 net@353 wire90-160_4-layer_1-width_3
+Xwire90@11 s[2] net@409 wire90-130_1-layer_1-width_3
+Xwire90@15 net@472 net@475 wire90-142_6-layer_1-width_3
+Xwire90@16 net@463 net@499 wire90-350_6-layer_1-width_3
+.ENDS gaspDrain
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-199_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-199_1-R_34_667m
-.ENDS wire90-199_1-layer_1-width_3
+*** CELL: redFive:invLT{sch}
+.SUBCKT invLT-X_10 in out
+XNMOS@0 out in gnd NMOSx-X_20
+XPMOS@0 out in vdd PMOSx-X_10
+.ENDS invLT-X_10
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-702_4-R_34_667m a b
-Ccap@0 gnd net@14 2.575f
-Ccap@1 gnd net@8 2.575f
-Ccap@2 gnd net@11 2.575f
-Rres@0 net@14 a 4.058
-Rres@1 net@11 net@14 8.117
-Rres@2 b net@8 4.058
-Rres@3 net@8 net@11 8.117
-.ENDS wire-C_0_011f-702_4-R_34_667m
+.SUBCKT wire-C_0_011f-282-R_34_667m a b
+Ccap@0 gnd net@14 1.034f
+Ccap@1 gnd net@8 1.034f
+Ccap@2 gnd net@11 1.034f
+Rres@0 net@14 a 1.629
+Rres@1 net@11 net@14 3.259
+Rres@2 b net@8 1.629
+Rres@3 net@8 net@11 3.259
+.ENDS wire-C_0_011f-282-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-702_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-702_4-R_34_667m
-.ENDS wire90-702_4-layer_1-width_3
+.SUBCKT wire90-282-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-282-R_34_667m
+.ENDS wire90-282-layer_1-width_3
+
+*** CELL: latchesK:latch1in10A{sch}
+.SUBCKT latch1in10A hcl in[1] out[1]
+Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF
+XinvLT@0 net@18 out[1] invLT-X_10
+Xwire90@0 net@19 net@18 wire90-282-layer_1-width_3
+.ENDS latch1in10A
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-251_7-R_34_667m a b
-Ccap@0 gnd net@14 0.923f
-Ccap@1 gnd net@8 0.923f
-Ccap@2 gnd net@11 0.923f
-Rres@0 net@14 a 1.454
-Rres@1 net@11 net@14 2.909
-Rres@2 b net@8 1.454
-Rres@3 net@8 net@11 2.909
-.ENDS wire-C_0_011f-251_7-R_34_667m
+.SUBCKT wire-C_0_011f-311_7-R_34_667m a b
+Ccap@0 gnd net@14 1.143f
+Ccap@1 gnd net@8 1.143f
+Ccap@2 gnd net@11 1.143f
+Rres@0 net@14 a 1.801
+Rres@1 net@11 net@14 3.602
+Rres@2 b net@8 1.801
+Rres@3 net@8 net@11 3.602
+.ENDS wire-C_0_011f-311_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-251_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-251_7-R_34_667m
-.ENDS wire90-251_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-377-R_34_667m a b
-Ccap@0 gnd net@14 1.382f
-Ccap@1 gnd net@8 1.382f
-Ccap@2 gnd net@11 1.382f
-Rres@0 net@14 a 2.178
-Rres@1 net@11 net@14 4.356
-Rres@2 b net@8 2.178
-Rres@3 net@8 net@11 4.356
-.ENDS wire-C_0_011f-377-R_34_667m
+.SUBCKT wire90-311_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-311_7-R_34_667m
+.ENDS wire90-311_7-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-377-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-377-R_34_667m
-.ENDS wire90-377-layer_1-width_3
+*** CELL: latchesK:latch2in10Alo{sch}
+.SUBCKT latch2in10Alo hcl[A] hcl[B] inA[1] inB[1] out[1]
+Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF
+XinvLT@0 net@15 out[1] invLT-X_10
+Xwire90@0 dataBar net@15 wire90-311_7-layer_1-width_3
+.ENDS latch2in10Alo
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-593_4-R_34_667m a b
-Ccap@0 gnd net@14 2.176f
-Ccap@1 gnd net@8 2.176f
-Ccap@2 gnd net@11 2.176f
-Rres@0 net@14 a 3.429
-Rres@1 net@11 net@14 6.857
-Rres@2 b net@8 3.429
-Rres@3 net@8 net@11 6.857
-.ENDS wire-C_0_011f-593_4-R_34_667m
+.SUBCKT wire-C_0_011f-218_4-R_34_667m a b
+Ccap@0 gnd net@14 0.801f
+Ccap@1 gnd net@8 0.801f
+Ccap@2 gnd net@11 0.801f
+Rres@0 net@14 a 1.262
+Rres@1 net@11 net@14 2.524
+Rres@2 b net@8 1.262
+Rres@3 net@8 net@11 2.524
+.ENDS wire-C_0_011f-218_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-593_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-593_4-R_34_667m
-.ENDS wire90-593_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1158_7-R_34_667m a b
-Ccap@0 gnd net@14 4.249f
-Ccap@1 gnd net@8 4.249f
-Ccap@2 gnd net@11 4.249f
-Rres@0 net@14 a 6.695
-Rres@1 net@11 net@14 13.389
-Rres@2 b net@8 6.695
-Rres@3 net@8 net@11 13.389
-.ENDS wire-C_0_011f-1158_7-R_34_667m
+.SUBCKT wire90-218_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-218_4-R_34_667m
+.ENDS wire90-218_4-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1158_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1158_7-R_34_667m
-.ENDS wire90-1158_7-layer_1-width_3
+*** CELL: scanM:scanCellE{sch}
+.SUBCKT scanM__scanCellE dIn[1] p1p p2p rd sin sout
+Xlatch1in@0 p2p sin net@2 latch1in10A
+Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo
+Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3
+.ENDS scanM__scanCellE
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-487_9-R_34_667m a b
-Ccap@0 gnd net@14 1.789f
-Ccap@1 gnd net@8 1.789f
-Ccap@2 gnd net@11 1.789f
-Rres@0 net@14 a 2.819
-Rres@1 net@11 net@14 5.638
-Rres@2 b net@8 2.819
-Rres@3 net@8 net@11 5.638
-.ENDS wire-C_0_011f-487_9-R_34_667m
+.SUBCKT wire-C_0_011f-297_6-R_34_667m a b
+Ccap@0 gnd net@14 1.091f
+Ccap@1 gnd net@8 1.091f
+Ccap@2 gnd net@11 1.091f
+Rres@0 net@14 a 1.719
+Rres@1 net@11 net@14 3.439
+Rres@2 b net@8 1.719
+Rres@3 net@8 net@11 3.439
+.ENDS wire-C_0_011f-297_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-487_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-487_9-R_34_667m
-.ENDS wire90-487_9-layer_1-width_3
+.SUBCKT wire90-297_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-297_6-R_34_667m
+.ENDS wire90-297_6-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-214_3-R_34_667m a b
-Ccap@0 gnd net@14 0.786f
-Ccap@1 gnd net@8 0.786f
-Ccap@2 gnd net@11 0.786f
-Rres@0 net@14 a 1.238
-Rres@1 net@11 net@14 2.476
-Rres@2 b net@8 1.238
-Rres@3 net@8 net@11 2.476
-.ENDS wire-C_0_011f-214_3-R_34_667m
+*** CELL: scanM:scanEx2{sch}
+.SUBCKT scanEx2 dIn[1] dIn[2] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sor[1]
+XscanCell@3 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanM__scanCellE
+XscanCell@4 dIn[2] sir[3] sir[2] sir[5] net@27 sor[1] scanM__scanCellE
+Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
+.ENDS scanEx2
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-214_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-214_3-R_34_667m
-.ENDS wire90-214_3-layer_1-width_3
+*** CELL: latchPartsK:latchPointFmcHI{sch}
+.SUBCKT latchPointFmcHI mc x[F] x[T]
+XPMOSx@0 gnd mc x[T] NMOSx-X_3
+XPMOSx@1 vdd mc x[F] NMOSx-X_6
+.ENDS latchPointFmcHI
-*** CELL: oneHotM:reQueueC{sch}
-.SUBCKT reQueueC circulate epi[OTHER] fire[E] fire[R] mc od[ABORT] od[OTHER]
-+ps[do] ps[skip] s[1] s[2] succ
-XctrAND3i@0 succ net@361 circulate fire[E] ctrAND3in30
-Xinv@12 net@377 abortLO inv-X_10
-Xinv@13 epi[OTHER] net@440 inv-X_5
-Xinv@14 circulate net@320 inv-X_10
-XinvI@10 net@309 net@376 inv-X_5
-XinvI@11 net@394 net@396 inv-X_10
-XinvI@12 net@440 s[2] inv-X_10
-XinvI@13 net@320 s[1] inv-X_10
-Xnand2_sy@1 od[OTHER] ps[skip] net@274 nand2_sy-X_6
-Xnand2_sy@2 od[ABORT] ps[skip] net@277 nand2_sy-X_6
-Xnand2_sy@3 od[OTHER] ps[do] net@280 nand2_sy-X_6
-Xnand2_sy@4 od[ABORT] ps[do] net@283 nand2_sy-X_6
-Xnand2_sy@5 net@313 net@311 net@324 nand2_sy-X_6
-Xnand2n@0 circulate succ net@315 nand2n-X_5
-Xnand2n_s@0 net@324 abortLO fire[C] nand2n_sy-X_20
-Xnand3in6@1 net@303 net@418 net@306 net@420 nand3in6_6sym
-Xnor2n@1 net@326 net@322 fire[R] nor2n-X_10
-XpredDri2@2 net@243 mc od[ABORT] predDri20wMC
-XpredDri2@3 net@243 mc od[OTHER] predDri20wMC
-XpredDri2@4 net@243 mc ps[do] predDri20wMC
-XpredDri2@5 net@243 mc ps[skip] predDri20wMC
-XpredDri2@6 fire[E] mc epi[OTHER] predDri20wMC
-XpredDri2@7 net@399 mc circulate predDri20wMC
-XsucORdri@0 fire[R] fire[E] succ sucORdri20
-Xwire90@12 net@274 net@303 wire90-286_3-layer_1-width_3
-Xwire90@13 net@277 net@418 wire90-428_8-layer_1-width_3
-Xwire90@14 net@280 net@306 wire90-356_7-layer_1-width_3
-Xwire90@15 net@283 net@309 wire90-199_1-layer_1-width_3
-Xwire90@16 net@420 net@311 wire90-702_4-layer_1-width_3
-Xwire90@17 net@313 net@315 wire90-251_7-layer_1-width_3
-Xwire90@18 net@322 net@320 wire90-377-layer_1-width_3
-Xwire90@19 net@324 net@326 wire90-593_4-layer_1-width_3
-Xwire90@20 net@243 fire[C] wire90-1158_7-layer_1-width_3
-Xwire90@23 net@376 net@377 wire90-142_6-layer_1-width_3
-Xwire90@24 abortLO net@394 wire90-487_9-layer_1-width_3
-Xwire90@25 net@396 net@399 wire90-214_3-layer_1-width_3
-Xwire90@27 net@361 net@440 wire90-142_6-layer_1-width_3
-.ENDS reQueueC
+*** CELL: latchesK:raw2inLatchFmc{sch}
+.SUBCKT raw2inLatchFmc hcl inA[1] mc out[F]
+XlatchKee@0 out[F] net@63 latchKeep
+XlatchPoi@0 hcl inA[1] out[F] net@45 latchPointF
+XlatchPoi@1 mc out[F] net@45 latchPointFmcHI
+Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3
+.ENDS raw2inLatchFmc
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1041_2-R_34_667m a b
-Ccap@0 gnd net@14 3.818f
-Ccap@1 gnd net@8 3.818f
-Ccap@2 gnd net@11 3.818f
-Rres@0 net@14 a 6.016
-Rres@1 net@11 net@14 12.032
-Rres@2 b net@8 6.016
-Rres@3 net@8 net@11 12.032
-.ENDS wire-C_0_011f-1041_2-R_34_667m
+.SUBCKT wire-C_0_011f-283-R_34_667m a b
+Ccap@0 gnd net@14 1.038f
+Ccap@1 gnd net@8 1.038f
+Ccap@2 gnd net@11 1.038f
+Rres@0 net@14 a 1.635
+Rres@1 net@11 net@14 3.27
+Rres@2 b net@8 1.635
+Rres@3 net@8 net@11 3.27
+.ENDS wire-C_0_011f-283-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1041_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1041_2-R_34_667m
-.ENDS wire90-1041_2-layer_1-width_3
-
-*** CELL: oneHotM:reQueue{sch}
-.SUBCKT reQueue epi[OTHER] epi[TAIL] fire[E] fire[R] mc od[ABORT] od[HEAD]
-+od[OTHER] ps[do] ps[skip] rq[succ] s[1] s[2] s[3] s[4]
-XreQueueB@1 circulate epi[TAIL] mc od[HEAD] s[1] s[2] reQueueB
-XreQueueC@0 net@3 epi[OTHER] fire[E] fire[R] mc od[ABORT] od[OTHER] ps[do]
-+ps[skip] s[3] s[4] rq[succ] reQueueC
-Xwire90@0 circulate net@3 wire90-1041_2-layer_1-width_3
-.ENDS reQueue
+.SUBCKT wire90-283-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-283-R_34_667m
+.ENDS wire90-283-layer_1-width_3
-*** CELL: scanM:scanEx3plain{sch}
-.SUBCKT scanEx3plain dIn[1] dIn[2] dIn[3] sin sir[2] sir[3] sir[5] sout
-XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sin net@26 scanM__scanCellE
-XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanM__scanCellE
-XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sout scanM__scanCellE
-Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
-Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3
-.ENDS scanEx3plain
+*** CELL: latchesK:latch2in10Alomc{sch}
+.SUBCKT latch2in10Alomc hcl inA[1] mc out[1]
+Xhi2inLat@0 hcl inA[1] mc dataBar raw2inLatchFmc
+XinvLT@0 net@20 out[1] invLT-X_10
+Xwire90@0 dataBar net@20 wire90-283-layer_1-width_3
+.ENDS latch2in10Alomc
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1336_2-R_34_667m a b
-Ccap@0 gnd net@14 4.899f
-Ccap@1 gnd net@8 4.899f
-Ccap@2 gnd net@11 4.899f
-Rres@0 net@14 a 7.72
-Rres@1 net@11 net@14 15.441
-Rres@2 b net@8 7.72
-Rres@3 net@8 net@11 15.441
-.ENDS wire-C_0_011f-1336_2-R_34_667m
+*** CELL: scanM:scanCellF{sch}
+.SUBCKT scanCellF dout[1] mc p1p p2p rd sin sout wr
+Xlatch1in@0 p2p sin net@2 latch1in10A
+Xlatch2in@0 p1p rd net@10 dout[1] sout latch2in10Alo
+Xlatch2in@1 wr sout mc dout[1] latch2in10Alomc
+Xwire90@0 net@2 net@10 wire90-297_6-layer_1-width_3
+.ENDS scanCellF
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1336_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1336_2-R_34_667m
-.ENDS wire90-1336_2-layer_1-width_3
+*** CELL: scanM:scanFx3{sch}
+.SUBCKT scanFx3 dout[1] dout[2] dout[3] sic[1] sic[2] sic[3] sic[4] sic[5]
++sic[6] sic[7] sic[8] sic[9] soc[1]
+XscanCell@4 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4]
++scanCellF
+XscanCell@5 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 net@31 sic[4]
++scanCellF
+XscanCell@6 dout[3] sic[9] sic[3] sic[2] sic[5] net@33 soc[1] sic[4]
++scanCellF
+Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3
+Xwire90@1 net@31 net@33 wire90-297_6-layer_1-width_3
+.ENDS scanFx3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1307-R_34_667m a b
-Ccap@0 gnd net@14 4.792f
-Ccap@1 gnd net@8 4.792f
-Ccap@2 gnd net@11 4.792f
-Rres@0 net@14 a 7.552
-Rres@1 net@11 net@14 15.103
-Rres@2 b net@8 7.552
-Rres@3 net@8 net@11 15.103
-.ENDS wire-C_0_011f-1307-R_34_667m
+*** CELL: stagesM:drainStage{sch}
+.SUBCKT drainStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
++aout[7] aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15]
++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25]
++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35]
++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1]
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28]
++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36]
++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] sic[2]
++sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4]
++sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ
+Xaddr1in6@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
++aout[8] aout[9] aout[TT] net@4 addr1in60Cx15
+Xdata1in6@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3]
++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
++out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
++out[6] out[7] out[8] out[9] net@5 data1in60Cx37
+XgaspDrai@0 clear net@4 go pred net@17[1] net@17[0] silent succ net@5 ain[TT]
++gaspDrain
+XscanEx2v@1 net@17[1] net@17[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sor[1] scanEx2
+XscanFx3@0 go clear silent sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
++sic[8] sic[9] soc[1] scanFx3
+.ENDS drainStage
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-295_8-R_34_667m a b
+Ccap@0 gnd net@14 1.085f
+Ccap@1 gnd net@8 1.085f
+Ccap@2 gnd net@11 1.085f
+Rres@0 net@14 a 1.709
+Rres@1 net@11 net@14 3.418
+Rres@2 b net@8 1.709
+Rres@3 net@8 net@11 3.418
+.ENDS wire-C_0_011f-295_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1307-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1307-R_34_667m
-.ENDS wire90-1307-layer_1-width_3
+.SUBCKT wire90-295_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-295_8-R_34_667m
+.ENDS wire90-295_8-layer_1-width_3
-*** CELL: stagesM:rqDockStage{sch}
-.SUBCKT rqDockStage epi[OTHER] epi[TAIL] inE[10] inE[11] inE[12] inE[13]
-+inE[14] inE[15] inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21]
-+inE[22] inE[23] inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2]
-+inE[30] inE[31] inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5]
-+inE[6] inE[7] inE[8] inE[9] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15]
-+inP[16] inP[17] inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23]
-+inP[24] inP[25] inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31]
-+inP[32] inP[33] inP[34] inP[35] inP[36] inP[3] inP[4] inP[5] inP[6] inP[7]
-+inP[8] inP[9] od[ABORT] od[HEAD] od[OTHER] ps[do] ps[skip] rq[10] rq[11]
-+rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] rq[20] rq[21]
-+rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] rq[30] rq[31]
-+rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9]
-+rq[succ] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+sor[1] take[E] take[P]
-Xins2in20@0 take[E] take[P] inE[10] inE[11] inE[12] inE[13] inE[14] inE[15]
-+inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] inE[23]
-+inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] inE[31]
-+inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7]
-+inE[8] inE[9] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15] inP[16] inP[17]
-+inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23] inP[24] inP[25]
-+inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31] inP[32] inP[33]
-+inP[34] inP[35] inP[36] inP[3] inP[4] inP[5] inP[6] inP[7] inP[8] inP[9]
-+rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1]
-+rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2]
-+rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6]
-+rq[7] rq[8] rq[9] ins2in20Ax36
-XlatchDri@0 net@3 take[E] latchDriver60
-XlatchDri@1 net@7 take[P] latchDriver60
-XreQueue@0 epi[OTHER] epi[TAIL] fire[E] fire[R] sir[9] od[ABORT] od[HEAD]
-+od[OTHER] ps[do] ps[skip] rq[succ] s[1] s[2] s[3] s[4] reQueue
-XscanEx1v@0 s[1] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sin scanEx1vertA
-XscanEx3p@1 s[2] s[3] s[4] sin sir[2] sir[3] sir[5] sor[1] scanEx3plain
-Xwire90@0 net@7 fire[R] wire90-1336_2-layer_1-width_3
-Xwire90@1 net@3 fire[E] wire90-1307-layer_1-width_3
-.ENDS rqDockStage
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-555_8-R_34_667m a b
+Ccap@0 gnd net@14 2.038f
+Ccap@1 gnd net@8 2.038f
+Ccap@2 gnd net@11 2.038f
+Rres@0 net@14 a 3.211
+Rres@1 net@11 net@14 6.423
+Rres@2 b net@8 3.211
+Rres@3 net@8 net@11 6.423
+.ENDS wire-C_0_011f-555_8-R_34_667m
-*** CELL: stageGroupsM:epiRQod{sch}
-.SUBCKT epiRQod do[epi] do[od] epi[TORP] flag[A][clr] flag[A][set]
-+flag[D][clr] flag[D][set] in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] m1[10] m1[11] m1[12] m1[13]
-+m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23]
-+m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33]
-+m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ps[do]
-+ps[skip] rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18]
-+rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28]
-+rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4]
-+rq[5] rq[6] rq[7] rq[8] rq[9] rq[succ] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] sor[1]
-XepiDockS@0 do[epi] net@45[26] net@45[25] net@45[24] net@45[23] net@45[22]
-+net@45[21] net@45[20] net@45[19] net@45[18] net@45[17] net@45[35] net@45[16]
-+net@45[15] net@45[14] net@45[13] net@45[12] net@45[11] net@45[10] net@45[9]
-+net@45[8] net@45[7] net@45[34] net@45[6] net@45[5] net@45[4] net@45[3]
-+net@45[2] net@45[1] net@45[0] net@45[33] net@45[32] net@45[31] net@45[30]
-+net@45[29] net@45[28] net@45[27] net@44[0] net@44[1] epi[TORP] in[10] in[11]
-+in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21]
-+in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31]
-+in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9]
-+in[T] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@0[8]
-+take[epi] epiDockStage
-XonDeckDo@0 do[od] flag[A][clr] flag[A][set] flag[D][clr] flag[D][set] m1[10]
-+m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20]
-+m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30]
-+m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8]
-+m1[9] net@46[26] net@46[25] net@46[24] net@46[23] net@46[22] net@46[21]
-+net@46[20] net@46[19] net@46[18] net@46[17] net@46[35] net@46[16] net@46[15]
-+net@46[14] net@46[13] net@46[12] net@46[11] net@46[10] net@46[9] net@46[8]
-+net@46[7] net@46[34] net@46[6] net@46[5] net@46[4] net@46[3] net@46[2]
-+net@46[1] net@46[0] net@46[33] net@46[32] net@46[31] net@46[30] net@46[29]
-+net@46[28] net@46[27] od[ABORT] od[HEAD] od[OTHER] net@36[8] sir[2] sir[3]
-+sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] take[od] onDeckDockStage
-XrqDockSt@0 net@44[0] net@44[1] net@45[26] net@45[25] net@45[24] net@45[23]
-+net@45[22] net@45[21] net@45[20] net@45[19] net@45[18] net@45[17] net@45[35]
-+net@45[16] net@45[15] net@45[14] net@45[13] net@45[12] net@45[11] net@45[10]
-+net@45[9] net@45[8] net@45[7] net@45[34] net@45[6] net@45[5] net@45[4]
-+net@45[3] net@45[2] net@45[1] net@45[0] net@45[33] net@45[32] net@45[31]
-+net@45[30] net@45[29] net@45[28] net@45[27] net@46[26] net@46[25] net@46[24]
-+net@46[23] net@46[22] net@46[21] net@46[20] net@46[19] net@46[18] net@46[17]
-+net@46[35] net@46[16] net@46[15] net@46[14] net@46[13] net@46[12] net@46[11]
-+net@46[10] net@46[9] net@46[8] net@46[7] net@46[34] net@46[6] net@46[5]
-+net@46[4] net@46[3] net@46[2] net@46[1] net@46[0] net@46[33] net@46[32]
-+net@46[31] net@46[30] net@46[29] net@46[28] net@46[27] od[ABORT] od[HEAD]
-+od[OTHER] ps[do] ps[skip] rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16]
-+rq[17] rq[18] rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26]
-+rq[27] rq[28] rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36]
-+rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9] rq[succ] net@0[8] sir[2] sir[3]
-+sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@36[8] take[E] take[P]
-+rqDockStage
-.ENDS epiRQod
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-555_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-555_8-R_34_667m
+.ENDS wire90-555_8-layer_1-width_3
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_40 d g s
-MPMOSf@0 d g s vdd pch W='240*(1+ABP/sqrt(240*2))' L='2'
-+DELVTO='AVT0P/sqrt(240*2)'
-.ENDS PMOSx-X_40
+*** CELL: latchesK:latch2in60C{sch}
+.SUBCKT latch2in60C hcl[A] hcl[B] inA[1] inB[1] outS[1]
+Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@14 raw2inLatchF
+XinvLT@0 net@15 net@18 invLT-X_5
+XinvLT@1 net@16 net@19 inv-X_20
+XinvLT@2 net@17 outS[1] inv-X_60
+Xwire90@0 net@14 net@15 wire90-295_8-layer_1-width_3
+Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3
+Xwire90@2 net@19 net@17 wire90-555_8-layer_1-width_3
+.ENDS latch2in60C
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_20 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_40
-XPMOS@1 d g2 net@2 PMOSx-X_40
-.ENDS pms2-X_20
+*** CELL: scanJ:scanCellE{sch}
+.SUBCKT scanJ__scanCellE dIn[1] p1p p2p rd sin sout
+Xlatch1in@0 p2p sin net@2 latch1in10A
+Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo
+Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3
+.ENDS scanJ__scanCellE
-*** CELL: redFive:nor2{sch}
-.SUBCKT nor2-X_20 ina inb out
-XNMOS@0 out ina gnd NMOSx-X_20
-XNMOS@1 out inb gnd NMOSx-X_20
-Xpms2@0 out ina inb pms2-X_20
-.ENDS nor2-X_20
+*** CELL: latchGroupsK:latchWscM2{sch}
+.SUBCKT latchWscM2 hcl in[1] out[1] p1p p2p rd sin sout wr
+Xhi2inLat@1 hcl wr in[1] sout out[1] latch2in60C
+XscanCell@2 out[1] p1p p2p rd sin sout scanJ__scanCellE
+.ENDS latchWscM2
-*** CELL: redFive:nor2n{sch}
-.SUBCKT nor2n-X_20 ina inb out
-Xnor2@0 ina inb out nor2-X_20
-.ENDS nor2n-X_20
+*** CELL: registersM:addr1in60Cx7scan{sch}
+.SUBCKT addr1in60Cx7scan ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7]
++aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire p1p p2p rd sin
++sout wr[A]
+Xla[1] fire ain[1] aout[1] p1p p2p rd sin xin[2] wr[A] latchWscM2
+Xla[2] fire ain[2] aout[2] p1p p2p rd xin[2] xin[3] wr[A] latchWscM2
+Xla[3] fire ain[3] aout[3] p1p p2p rd xin[3] xin[4] wr[A] latchWscM2
+Xla[4] fire ain[4] aout[4] p1p p2p rd xin[4] xin[5] wr[A] latchWscM2
+Xla[5] fire ain[5] aout[5] p1p p2p rd xin[5] xin[6] wr[A] latchWscM2
+Xla[6] fire ain[6] aout[6] p1p p2p rd xin[6] xin[7] wr[A] latchWscM2
+Xla[7] fire ain[7] aout[7] p1p p2p rd xin[7] sout wr[A] latchWscM2
+.ENDS addr1in60Cx7scan
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_2 d g s
-MPMOSf@0 d g s vdd pch W='12*(1+ABP/sqrt(12*2))' L='2'
-+DELVTO='AVT0P/sqrt(12*2)'
-.ENDS PMOSx-X_2
+*** CELL: registersM:data1in60Cx18scan{sch}
+.SUBCKT data1in60Cx18scan dcl in[10] in[11] in[12] in[13] in[14] in[15]
++in[16] in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9]
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
++out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] p1p p2p rd sin
++sout wr[D]
+Xla[1] dcl in[1] out[1] p1p p2p rd sin xin[2] wr[D] latchWscM2
+Xla[2] dcl in[2] out[2] p1p p2p rd xin[2] xin[3] wr[D] latchWscM2
+Xla[3] dcl in[3] out[3] p1p p2p rd xin[3] xin[4] wr[D] latchWscM2
+Xla[4] dcl in[4] out[4] p1p p2p rd xin[4] xin[5] wr[D] latchWscM2
+Xla[5] dcl in[5] out[5] p1p p2p rd xin[5] xin[6] wr[D] latchWscM2
+Xla[6] dcl in[6] out[6] p1p p2p rd xin[6] xin[7] wr[D] latchWscM2
+Xla[7] dcl in[7] out[7] p1p p2p rd xin[7] xin[8] wr[D] latchWscM2
+Xla[8] dcl in[8] out[8] p1p p2p rd xin[8] xin[9] wr[D] latchWscM2
+Xla[9] dcl in[9] out[9] p1p p2p rd xin[9] xin[10] wr[D] latchWscM2
+Xla[10] dcl in[10] out[10] p1p p2p rd xin[10] xin[11] wr[D] latchWscM2
+Xla[11] dcl in[11] out[11] p1p p2p rd xin[11] xin[12] wr[D] latchWscM2
+Xla[12] dcl in[12] out[12] p1p p2p rd xin[12] xin[13] wr[D] latchWscM2
+Xla[13] dcl in[13] out[13] p1p p2p rd xin[13] xin[14] wr[D] latchWscM2
+Xla[14] dcl in[14] out[14] p1p p2p rd xin[14] xin[15] wr[D] latchWscM2
+Xla[15] dcl in[15] out[15] p1p p2p rd xin[15] xin[16] wr[D] latchWscM2
+Xla[16] dcl in[16] out[16] p1p p2p rd xin[16] xin[17] wr[D] latchWscM2
+Xla[17] dcl in[17] out[17] p1p p2p rd xin[17] xin[18] wr[D] latchWscM2
+Xla[18] dcl in[18] out[18] p1p p2p rd xin[18] sout wr[D] latchWscM2
+.ENDS data1in60Cx18scan
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_2 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_2
-XPMOS@1 out inb vdd PMOSx-X_2
-Xnms2@0 out ina inb nms2-X_2
-.ENDS nand2-X_2
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_4 d g s
+MNMOSf@0 d g s gnd nch W='12*(1+ABN/sqrt(12*2))' L='2'
++DELVTO='AVT0N/sqrt(12*2)'
+.ENDS NMOSx-X_4
-*** CELL: redFive:nms1{sch}
-.SUBCKT nms1-X_4 d g
-XNMOS@1 d g gnd NMOSx-X_4
-.ENDS nms1-X_4
+*** CELL: redFive:inv{sch}
+.SUBCKT inv-X_4 in out
+XNMOS@0 out in gnd NMOSx-X_4
+XPMOS@0 out in vdd PMOSx-X_4
+.ENDS inv-X_4
-*** CELL: redFive:pms1{sch}
-.SUBCKT pms1-X_10 d g
-XPMOS@0 d g vdd PMOSx-X_10
-.ENDS pms1-X_10
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_30 d g s
+MPMOSf@0 d g s vdd pch W='180*(1+ABP/sqrt(180*2))' L='2'
++DELVTO='AVT0P/sqrt(180*2)'
+.ENDS PMOSx-X_30
+
+*** CELL: redFive:inv{sch}
+.SUBCKT inv-X_30 in out
+XNMOS@0 out in gnd NMOSx-X_30
+XPMOS@0 out in vdd PMOSx-X_30
+.ENDS inv-X_30
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_2_5 d g s
+MNMOSf@0 d g s gnd nch W='7.5*(1+ABN/sqrt(7.5*2))' L='2'
++DELVTO='AVT0N/sqrt(7.5*2)'
+.ENDS NMOSx-X_2_5
+
+*** CELL: redFive:nor2HT_sy{sch}
+.SUBCKT nor2HT_sy-X_5 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_2_5
+XNMOS@1 out ina gnd NMOSx-X_2_5
+Xpms2_sy@0 out ina inb pms2_sy-X_5
+.ENDS nor2HT_sy-X_5
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-252_6-R_34_667m a b
+Ccap@0 gnd net@14 0.926f
+Ccap@1 gnd net@8 0.926f
+Ccap@2 gnd net@11 0.926f
+Rres@0 net@14 a 1.459
+Rres@1 net@11 net@14 2.919
+Rres@2 b net@8 1.459
+Rres@3 net@8 net@11 2.919
+.ENDS wire-C_0_011f-252_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-252_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-252_6-R_34_667m
+.ENDS wire90-252_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-366_8-R_34_667m a b
+Ccap@0 gnd net@14 1.345f
+Ccap@1 gnd net@8 1.345f
+Ccap@2 gnd net@11 1.345f
+Rres@0 net@14 a 2.119
+Rres@1 net@11 net@14 4.239
+Rres@2 b net@8 2.119
+Rres@3 net@8 net@11 4.239
+.ENDS wire-C_0_011f-366_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-366_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-366_8-R_34_667m
+.ENDS wire90-366_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-176_4-R_34_667m a b
+Ccap@0 gnd net@14 0.647f
+Ccap@1 gnd net@8 0.647f
+Ccap@2 gnd net@11 0.647f
+Rres@0 net@14 a 1.019
+Rres@1 net@11 net@14 2.038
+Rres@2 b net@8 1.019
+Rres@3 net@8 net@11 2.038
+.ENDS wire-C_0_011f-176_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-176_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-176_4-R_34_667m
+.ENDS wire90-176_4-layer_1-width_3
+
+*** CELL: centersJ:ctrAND3in30{sch}
+.SUBCKT ctrAND3in30 inA inB inC out
+Xinv@4 inC net@30 inv-X_4
+Xinv@5 net@9 out inv-X_30
+Xnand2@0 net@19 net@15 net@27 nand2-X_10
+Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5
+Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
+Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
+Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
+.ENDS ctrAND3in30
+
+*** CELL: redFive:nms2{sch}
+.SUBCKT nms2-X_30 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_60
+XNMOS@1 net@0 g gnd NMOSx-X_60
+.ENDS nms2-X_30
+
+*** CELL: redFive:nand2{sch}
+.SUBCKT nand2-X_30 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_30
+XPMOS@1 out inb vdd PMOSx-X_30
+Xnms2@0 out ina inb nms2-X_30
+.ENDS nand2-X_30
*** CELL: redFive:pms2{sch}
.SUBCKT pms2-X_5 d g g2
Xpms2@1 d g2 g pms2-X_5
.ENDS pms2_sy-X_10
+*** CELL: redFive:nor2HT_sy{sch}
+.SUBCKT nor2HT_sy-X_10 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_5
+XNMOS@1 out ina gnd NMOSx-X_5
+Xpms2_sy@0 out ina inb pms2_sy-X_10
+.ENDS nor2HT_sy-X_10
+
+*** CELL: centersJ:ctrAND3in100A{sch}
+.SUBCKT ctrAND3in100A inA inB inC out
+Xinv@4 inC net@30 inv-X_10
+Xinv@5 net@9 out inv-X_100
+Xnand2@0 net@19 net@15 net@27 nand2-X_30
+Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_10
+Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
+Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
+Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
+.ENDS ctrAND3in100A
+
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-403-R_34_667m a b
-Ccap@0 gnd net@14 1.478f
-Ccap@1 gnd net@8 1.478f
-Ccap@2 gnd net@11 1.478f
-Rres@0 net@14 a 2.328
-Rres@1 net@11 net@14 4.657
-Rres@2 b net@8 2.328
-Rres@3 net@8 net@11 4.657
-.ENDS wire-C_0_011f-403-R_34_667m
+.SUBCKT wire-C_0_011f-918_6-R_34_667m a b
+Ccap@0 gnd net@14 3.368f
+Ccap@1 gnd net@8 3.368f
+Ccap@2 gnd net@11 3.368f
+Rres@0 net@14 a 5.307
+Rres@1 net@11 net@14 10.615
+Rres@2 b net@8 5.307
+Rres@3 net@8 net@11 10.615
+.ENDS wire-C_0_011f-918_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-403-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-403-R_34_667m
-.ENDS wire90-403-layer_1-width_3
-
-*** CELL: oneHotM:sucDri10Pair{sch}
-.SUBCKT sucDri10Pair bit[1] out[1][F] out[1][T] when
-XNMOSx@2 out[1][F] net@105 net@139 NMOSx-X_4
-XNMOSx@3 out[1][F] bit[1] net@144 NMOSx-X_4
-Xinv@2 when net@66 inv-X_4
-Xinv@5 out[1][F] net@92 inv-X_4
-Xinv@6 out[1][T] net@112 inv-X_4
-Xnand2@1 when bit[1] net@64 nand2-X_2
-Xnms1@2 net@139 net@154 nms1-X_4
-Xnms2b@0 out[1][T] net@113 net@4 nms2-X_2
-Xpms1@0 out[1][T] net@4 pms1-X_10
-Xpms2_sy@0 out[1][F] net@105 bit[1] pms2_sy-X_10
-Xwire90@0 net@64 net@4 wire90-403-layer_1-width_3
-Xwire90@1 net@66 net@105 wire90-403-layer_1-width_3
-Xwire90@3 net@113 net@112 wire90-403-layer_1-width_3
-Xwire90@4 net@154 net@92 wire90-403-layer_1-width_3
-Xwire90@5 net@144 net@139 wire90-403-layer_1-width_3
-.ENDS sucDri10Pair
+.SUBCKT wire90-918_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-918_6-R_34_667m
+.ENDS wire90-918_6-layer_1-width_3
-*** CELL: oneHotM:sucDri10Pairx6{sch}
-.SUBCKT sucDri10Pairx6 bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] ready when
-Xdd[1] bit[1] m1cate[1][F] m1cate[1][T] when sucDri10Pair
-Xdd[2] bit[2] m1cate[2][F] m1cate[2][T] when sucDri10Pair
-Xdd[3] bit[3] m1cate[3][F] m1cate[3][T] when sucDri10Pair
-Xdd[4] bit[4] m1cate[4][F] m1cate[4][T] when sucDri10Pair
-Xdd[5] bit[5] m1cate[5][F] m1cate[5][T] when sucDri10Pair
-Xdd[6] bit[6] m1cate[6][F] m1cate[6][T] when sucDri10Pair
-Xnor2n_sy@0 m1cate[1][T] m1cate[1][F] ready nor2n_sy-X_5
-.ENDS sucDri10Pairx6
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1177-R_34_667m a b
+Ccap@0 gnd net@14 4.316f
+Ccap@1 gnd net@8 4.316f
+Ccap@2 gnd net@11 4.316f
+Rres@0 net@14 a 6.8
+Rres@1 net@11 net@14 13.601
+Rres@2 b net@8 6.8
+Rres@3 net@8 net@11 13.601
+.ENDS wire-C_0_011f-1177-R_34_667m
-*** CELL: oneHotM:minusOne{sch}
-.SUBCKT minusOne bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] fire[m1] headBit
-+m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T]
-+m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T]
-+mc pred s[1] succ[m1]
-Xinv@7 pred net@313 inv-X_5
-XinvI@0 net@235 s[1] inv-X_10
-XinvI@1 net@398 fire[m1] inv-X_10
-Xnand2@1 net@414 net@411 net@398 nand2-X_10
-Xnor2n@0 headBit net@405 net@406 nor2n-X_20
-Xnor2n_sy@1 succ[m1] net@235 net@391 nor2n_sy-X_5
-XpredDri2@0 fire[m1] mc pred predDri20wMC
-XsucDri10@1 bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] net@435
-+net@421 sucDri10Pairx6
-XsucDri20@1 net@407 succ[m1] sucDri20
-Xwire90@10 fire[m1] net@407 wire90-403-layer_1-width_3
-Xwire90@11 net@313 net@235 wire90-403-layer_1-width_3
-Xwire90@12 net@414 net@435 wire90-403-layer_1-width_3
-Xwire90@13 net@411 net@391 wire90-403-layer_1-width_3
-Xwire90@14 net@398 net@405 wire90-403-layer_1-width_3
-Xwire90@15 net@406 net@421 wire90-403-layer_1-width_3
-.ENDS minusOne
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1177-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1177-R_34_667m
+.ENDS wire90-1177-layer_1-width_3
-*** CELL: stagesM:mOneDockStage{sch}
-.SUBCKT mOneDockStage m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
-+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
-+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[R] ring[10] ring[11] ring[12]
-+ring[13] ring[14] ring[15] ring[16] ring[17] ring[18] ring[19] ring[1]
-+ring[20] ring[21] ring[22] ring[23] ring[24] ring[25] ring[26] ring[27]
-+ring[28] ring[29] ring[2] ring[30] ring[31] ring[32] ring[33] ring[34]
-+ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9]
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1]
-+succ[m1] take[m1]
-Xins1in20@0 take[m1] ring[10] ring[11] ring[12] ring[13] ring[14] ring[15]
-+ring[16] ring[17] ring[18] ring[19] ring[1] ring[20] ring[21] ring[22]
-+ring[23] ring[24] ring[25] ring[26] ring[27] ring[28] ring[29] ring[2]
-+ring[30] ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] ring[3]
-+ring[4] ring[5] ring[6] ring[7] ring[8] ring[9] m1[10] m1[11] m1[12] m1[13]
-+m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23]
-+m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33]
-+m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ins1in20Bx36
-XlatchDri@0 fire[1] take[m1] latchDriver60
-XminusOne@0 ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] net@11
-+ring[30] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F]
-+m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F]
-+m1cate[6][T] sir[9] pred[R] net@47 succ[m1] minusOne
-XscanEx1v@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1vertA
-Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3
-.ENDS mOneDockStage
-
-*** CELL: loopCountM:mux10/2{sch}
-.SUBCKT mux10/2 in[1] out[1] sF sT
-Xnms2b@0 out[1] sT in[1] nms2-X_10
-Xpms2@0 out[1] sF in[1] pms2-X_10
-.ENDS mux10/2
-
-*** CELL: loopCountM:mux10/2x7{sch}
-.SUBCKT mux10/2x7 in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2]
-+out[3] out[4] out[5] out[6] out[7] sF sT
-Xmux10/2@0 in[1] out[1] sF sT mux10/2
-Xmux10/2@1 in[2] out[2] sF sT mux10/2
-Xmux10/2@2 in[3] out[3] sF sT mux10/2
-Xmux10/2@3 in[4] out[4] sF sT mux10/2
-Xmux10/2@4 in[5] out[5] sF sT mux10/2
-Xmux10/2@5 in[6] out[6] sF sT mux10/2
-Xmux10/2@6 in[7] out[7] sF sT mux10/2
-.ENDS mux10/2x7
+*** CELL: gaspM:fillScanControl{sch}
+.SUBCKT fillScanControl si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9]
++so[1] wr[A] wr[D]
+XdataDriv@2 so[1] si[4] wr[D] dataDriver60
+XdataDriv@3 net@4 net@21 wr[A] dataDriver60
+XscanCell@2 scanCell@2_dIn[1] si[3] si[2] si[5] si[1] net@7 scanM__scanCellE
+XscanCell@3 scanCell@3_dIn[1] si[3] si[2] si[5] net@4 so[1] scanM__scanCellE
+Xwire90@0 net@7 net@4 wire90-918_6-layer_1-width_3
+Xwire90@1 net@21 si[4] wire90-1177-layer_1-width_3
+.ENDS fillScanControl
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-704_3-R_34_667m a b
-Ccap@0 gnd net@14 2.582f
-Ccap@1 gnd net@8 2.582f
-Ccap@2 gnd net@11 2.582f
-Rres@0 net@14 a 4.069
-Rres@1 net@11 net@14 8.139
-Rres@2 b net@8 4.069
-Rres@3 net@8 net@11 8.139
-.ENDS wire-C_0_011f-704_3-R_34_667m
+.SUBCKT wire-C_0_011f-544_2-R_34_667m a b
+Ccap@0 gnd net@14 1.995f
+Ccap@1 gnd net@8 1.995f
+Ccap@2 gnd net@11 1.995f
+Rres@0 net@14 a 3.144
+Rres@1 net@11 net@14 6.289
+Rres@2 b net@8 3.144
+Rres@3 net@8 net@11 6.289
+.ENDS wire-C_0_011f-544_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-704_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-704_3-R_34_667m
-.ENDS wire90-704_3-layer_1-width_3
+.SUBCKT wire90-544_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-544_2-R_34_667m
+.ENDS wire90-544_2-layer_1-width_3
-*** CELL: loopCountM:muxForPS{sch}
-.SUBCKT muxForPS in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2]
-+out[3] out[4] out[5] out[6] out[7] sel
-Xinv@0 sel net@0 inv-X_20
-Xinv@1 sT net@1 inv-X_20
-Xmux10/2x@0 in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] sF sT mux10/2x7
-Xwire90@0 net@0 sT wire90-704_3-layer_1-width_3
-Xwire90@1 net@1 sF wire90-704_3-layer_1-width_3
-.ENDS muxForPS
+*** CELL: driversJ:latchDriver60{sch}
+.SUBCKT latchDriver60 in out
+Xinv@1 in net@16 inv-X_20
+XinvI@0 net@8 out inv-X_60
+Xwire90@0 net@16 net@8 wire90-544_2-layer_1-width_3
+.ENDS latchDriver60
-*** CELL: registersM:dockPSreg{sch}
-.SUBCKT dockPSreg fire[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16]
-+m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26]
-+m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36]
-+m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] outLO[1] outLO[2] outLO[3] outLO[4]
-+outLO[5] outLO[6] outLO[7] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16]
-+ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26]
-+ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36]
-+ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[1]
-Xins1in20@0 take[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
-+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
-+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
-+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25]
-+ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35]
-+ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ins1in20Bx36
-XlatchDri@0 fire[1] net@0 latchDriver60
-XmuxForOD@0 ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[8] outLO[1] outLO[2]
-+outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForPS
-Xwire90@0 net@0 take[1] wire90-544_2-layer_1-width_3
-.ENDS dockPSreg
+*** CELL: driversL:predDri60wMC{sch}
+.SUBCKT driversL__predDri60wMC in mc pred
+XNMOSx@0 pred in gnd NMOSx-X_60
+XNMOSx@1 pred mc gnd NMOSx-X_10
+Xinv@0 pred net@145 inv-X_10
+Xpms3@0 pred mc in net@174 pms3-X_3_333
+Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3
+.ENDS driversL__predDri60wMC
-*** CELL: redFive:nand2n{sch}
-.SUBCKT nand2n-X_10 ina inb out
-Xnand2@0 ina inb out nand2-X_10
-.ENDS nand2n-X_10
+*** CELL: redFive:pms2{sch}
+.SUBCKT pms2-X_10 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_20
+XPMOS@1 d g2 net@2 PMOSx-X_20
+.ENDS pms2-X_10
-*** CELL: redFive:nor2_sy{sch}
-.SUBCKT nor2_sy-X_10 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_10
-XNMOS@1 out ina gnd NMOSx-X_10
-Xpms2_sy@0 out ina inb pms2_sy-X_10
-.ENDS nor2_sy-X_10
+*** CELL: redFive:pms2_sy{sch}
+.SUBCKT pms2_sy-X_20 d g g2
+Xpms2@0 d g g2 pms2-X_10
+Xpms2@1 d g2 g pms2-X_10
+.ENDS pms2_sy-X_20
-*** CELL: redFive:nor2n_sy{sch}
-.SUBCKT nor2n_sy-X_10 ina inb out
-Xnor2@0 ina inb out nor2_sy-X_10
-.ENDS nor2n_sy-X_10
+*** CELL: redFive:nor2_sy{sch}
+.SUBCKT nor2_sy-X_20 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_20
+XNMOS@1 out ina gnd NMOSx-X_20
+Xpms2_sy@0 out ina inb pms2_sy-X_20
+.ENDS nor2_sy-X_20
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-405_3-R_34_667m a b
-Ccap@0 gnd net@14 1.486f
-Ccap@1 gnd net@8 1.486f
-Ccap@2 gnd net@11 1.486f
-Rres@0 net@14 a 2.342
-Rres@1 net@11 net@14 4.683
-Rres@2 b net@8 2.342
-Rres@3 net@8 net@11 4.683
-.ENDS wire-C_0_011f-405_3-R_34_667m
+.SUBCKT wire-C_0_011f-1001_8-R_34_667m a b
+Ccap@0 gnd net@14 3.673f
+Ccap@1 gnd net@8 3.673f
+Ccap@2 gnd net@11 3.673f
+Rres@0 net@14 a 5.788
+Rres@1 net@11 net@14 11.576
+Rres@2 b net@8 5.788
+Rres@3 net@8 net@11 11.576
+.ENDS wire-C_0_011f-1001_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-405_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-405_3-R_34_667m
-.ENDS wire90-405_3-layer_1-width_3
+.SUBCKT wire90-1001_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1001_8-R_34_667m
+.ENDS wire90-1001_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-385_8-R_34_667m a b
-Ccap@0 gnd net@14 1.415f
-Ccap@1 gnd net@8 1.415f
-Ccap@2 gnd net@11 1.415f
-Rres@0 net@14 a 2.229
-Rres@1 net@11 net@14 4.458
-Rres@2 b net@8 2.229
-Rres@3 net@8 net@11 4.458
-.ENDS wire-C_0_011f-385_8-R_34_667m
+.SUBCKT wire-C_0_011f-209-R_34_667m a b
+Ccap@0 gnd net@14 0.766f
+Ccap@1 gnd net@8 0.766f
+Ccap@2 gnd net@11 0.766f
+Rres@0 net@14 a 1.208
+Rres@1 net@11 net@14 2.415
+Rres@2 b net@8 1.208
+Rres@3 net@8 net@11 2.415
+.ENDS wire-C_0_011f-209-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-385_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-385_8-R_34_667m
-.ENDS wire90-385_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-406_4-R_34_667m a b
-Ccap@0 gnd net@14 1.49f
-Ccap@1 gnd net@8 1.49f
-Ccap@2 gnd net@11 1.49f
-Rres@0 net@14 a 2.348
-Rres@1 net@11 net@14 4.696
-Rres@2 b net@8 2.348
-Rres@3 net@8 net@11 4.696
-.ENDS wire-C_0_011f-406_4-R_34_667m
+.SUBCKT wire90-209-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-209-R_34_667m
+.ENDS wire90-209-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-406_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-406_4-R_34_667m
-.ENDS wire90-406_4-layer_1-width_3
+*** CELL: driversJ:sucORdri60{sch}
+.SUBCKT sucORdri60 inA inB succ
+XPMOSx@0 succ net@51 vdd PMOSx-X_60
+Xinv@0 succ net@71 inv-X_5
+Xnms2@0 succ net@51 net@72 nms2-X_8
+Xnor2_sy@0 inA inB net@67 nor2_sy-X_20
+Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3
+Xwire90@1 net@72 net@71 wire90-209-layer_1-width_3
+.ENDS sucORdri60
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-329_2-R_34_667m a b
-Ccap@0 gnd net@14 1.207f
-Ccap@1 gnd net@8 1.207f
-Ccap@2 gnd net@11 1.207f
-Rres@0 net@14 a 1.902
-Rres@1 net@11 net@14 3.804
-Rres@2 b net@8 1.902
-Rres@3 net@8 net@11 3.804
-.ENDS wire-C_0_011f-329_2-R_34_667m
+.SUBCKT wire-C_0_011f-602_3-R_34_667m a b
+Ccap@0 gnd net@14 2.208f
+Ccap@1 gnd net@8 2.208f
+Ccap@2 gnd net@11 2.208f
+Rres@0 net@14 a 3.48
+Rres@1 net@11 net@14 6.96
+Rres@2 b net@8 3.48
+Rres@3 net@8 net@11 6.96
+.ENDS wire-C_0_011f-602_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-329_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-329_2-R_34_667m
-.ENDS wire90-329_2-layer_1-width_3
+.SUBCKT wire90-602_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-602_3-R_34_667m
+.ENDS wire90-602_3-layer_1-width_3
+
+*** CELL: gaspM:gaspFill{sch}
+.SUBCKT gaspFill block fill fire pred s[1] s[2] si[1] si[2] si[3] si[4] si[5]
++si[6] si[7] si[8] si[9] so[1] succ take wr[A] wr[D]
+XctrAND3i@1 net@602 succ fire fire[B] ctrAND3in30
+XctrAND3i@3 net@454 succ block fire ctrAND3in100A
+XfillScan@1 si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1] wr[A]
++wr[D] fillScanControl
+Xinv@0 pred net@533 inv-X_5
+Xinv@1 fill net@537 inv-X_5
+XinvI@0 net@454 s[1] inv-X_10
+XinvI@1 net@602 s[2] inv-X_10
+XlatchDri@0 fire take latchDriver60
+XpredDri6@2 fire si[9] pred driversL__predDri60wMC
+XsucORdri@1 fire net@320 succ sucORdri60
+Xwire90@1 net@537 net@602 wire90-602_3-layer_1-width_3
+Xwire90@12 net@533 net@454 wire90-602_3-layer_1-width_3
+Xwire90@15 fire[B] net@320 wire90-602_3-layer_1-width_3
+.ENDS gaspFill
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-407_9-R_34_667m a b
-Ccap@0 gnd net@14 1.496f
-Ccap@1 gnd net@8 1.496f
-Ccap@2 gnd net@11 1.496f
-Rres@0 net@14 a 2.357
-Rres@1 net@11 net@14 4.714
-Rres@2 b net@8 2.357
-Rres@3 net@8 net@11 4.714
-.ENDS wire-C_0_011f-407_9-R_34_667m
+.SUBCKT wire-C_0_011f-70-R_34_667m a b
+Ccap@0 gnd net@14 0.257f
+Ccap@1 gnd net@8 0.257f
+Ccap@2 gnd net@11 0.257f
+Rres@0 net@14 a 0.404
+Rres@1 net@11 net@14 0.809
+Rres@2 b net@8 0.404
+Rres@3 net@8 net@11 0.809
+.ENDS wire-C_0_011f-70-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-407_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-407_9-R_34_667m
-.ENDS wire90-407_9-layer_1-width_3
+.SUBCKT wire90-70-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-70-R_34_667m
+.ENDS wire90-70-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-247-R_34_667m a b
-Ccap@0 gnd net@14 0.906f
-Ccap@1 gnd net@8 0.906f
-Ccap@2 gnd net@11 0.906f
-Rres@0 net@14 a 1.427
-Rres@1 net@11 net@14 2.854
-Rres@2 b net@8 1.427
-Rres@3 net@8 net@11 2.854
-.ENDS wire-C_0_011f-247-R_34_667m
+*** CELL: scanJ:scanAmp{sch}
+.SUBCKT scanAmp in[1] out[1]
+Xinv@0 in[1] net@1 inv-X_10
+Xinv@1 net@2 out[1] inv-X_20
+Xwire90@0 net@1 net@2 wire90-70-layer_1-width_3
+.ENDS scanAmp
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-247-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-247-R_34_667m
-.ENDS wire90-247-layer_1-width_3
+*** CELL: gaspM:scanAMPx5{sch}
+.SUBCKT scanAMPx5 si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1]
++so[2] so[3] so[4] so[5]
+Xsa[1] si[1] so[1] scanAmp
+Xsa[2] si[2] so[2] scanAmp
+Xsa[3] si[3] so[3] scanAmp
+Xsa[4] si[4] so[4] scanAmp
+Xsa[5] si[5] so[5] scanAmp
+.ENDS scanAMPx5
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-456_8-R_34_667m a b
-Ccap@0 gnd net@14 1.675f
-Ccap@1 gnd net@8 1.675f
-Ccap@2 gnd net@11 1.675f
-Rres@0 net@14 a 2.639
-Rres@1 net@11 net@14 5.279
-Rres@2 b net@8 2.639
-Rres@3 net@8 net@11 5.279
-.ENDS wire-C_0_011f-456_8-R_34_667m
+.SUBCKT wire-C_0_011f-2500-R_34_667m a b
+Ccap@0 gnd net@14 9.167f
+Ccap@1 gnd net@8 9.167f
+Ccap@2 gnd net@11 9.167f
+Rres@0 net@14 a 14.444
+Rres@1 net@11 net@14 28.889
+Rres@2 b net@8 14.444
+Rres@3 net@8 net@11 28.889
+.ENDS wire-C_0_011f-2500-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-456_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-456_8-R_34_667m
-.ENDS wire90-456_8-layer_1-width_3
+.SUBCKT wire90-2500-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2500-R_34_667m
+.ENDS wire90-2500-layer_1-width_3
+
+*** CELL: stagesM:fillStage{sch}
+.SUBCKT fillStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
++aout[7] aout[8] aout[9] aout[TT] extra fire in[10] in[11] in[12] in[13]
++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
++in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
++succ
+Xaddr1in6@0 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
++aout[3] aout[4] aout[5] aout[6] aout[7] net@13 sx[3] sx[2] sx[5] net@61
++net@62 sx[A] addr1in60Cx7scan
+Xaddr1in6@1 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8]
++aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@16 sx[3] sx[2] sx[5]
++net@62 net@66 sx[A] addr1in60Cx7scan
+Xdata1in6@0 net@3 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
++out[4] out[5] out[6] out[7] out[8] out[9] sx[3] sx[2] sx[5] net@66 net@65
++sx[D] data1in60Cx18scan
+Xdata1in6@1 net@0 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
++in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29]
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20]
++out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] sx[3] sx[2]
++sx[5] net@64 sz[1] sx[D] data1in60Cx18scan
+XgaspFill@0 block fill fire pred s[1] s[2] sx[1] sx[2] sx[3] sx[4] sx[5]
++sid[6] sid[7] sid[8] sid[9] sy[1] succ net@8 sx[A] sx[D] gaspFill
+XlatchWsc@0 net@0 in[19] out[19] sx[3] sx[2] sx[5] net@65 net@64 sx[D]
++latchWscM2
+XlatchWsc@1 net@13 ain[TT] aout[TT] sx[3] sx[2] sx[5] sy[1] net@61 sx[A]
++latchWscM2
+XscanAMPx@0 sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9]
++sx[1] sx[2] sx[3] sx[4] sx[5] scanAMPx5
+XscanAMPx@1 sz[1] sx[2] sx[3] sx[4] sx[5] sid[6] sid[7] sid[8] sid[9] sod[1]
++sod[2] sod[3] sod[4] sod[5] scanAMPx5
+XscanEx2@0 s[1] s[2] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sor[1] scanEx2
+XscanFx3@0 block extra fill sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
++sic[8] sic[9] soc[1] scanFx3
+Xwire90@1 net@8 net@0 wire90-2550-layer_1-width_3
+Xwire90@3 fire net@16 wire90-2500-layer_1-width_3
+Xwire90@4 net@3 net@8 wire90-2550-layer_1-width_3
+Xwire90@5 net@13 fire wire90-2500-layer_1-width_3
+.ENDS fillStage
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-477_4-R_34_667m a b
-Ccap@0 gnd net@14 1.75f
-Ccap@1 gnd net@8 1.75f
-Ccap@2 gnd net@11 1.75f
-Rres@0 net@14 a 2.758
-Rres@1 net@11 net@14 5.517
-Rres@2 b net@8 2.758
-Rres@3 net@8 net@11 5.517
-.ENDS wire-C_0_011f-477_4-R_34_667m
+.SUBCKT wire-C_0_011f-2080_4-R_34_667m a b
+Ccap@0 gnd net@14 7.628f
+Ccap@1 gnd net@8 7.628f
+Ccap@2 gnd net@11 7.628f
+Rres@0 net@14 a 12.02
+Rres@1 net@11 net@14 24.04
+Rres@2 b net@8 12.02
+Rres@3 net@8 net@11 24.04
+.ENDS wire-C_0_011f-2080_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-477_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-477_4-R_34_667m
-.ENDS wire90-477_4-layer_1-width_3
+.SUBCKT wire90-2080_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2080_4-R_34_667m
+.ENDS wire90-2080_4-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-775_9-R_34_667m a b
-Ccap@0 gnd net@14 2.845f
-Ccap@1 gnd net@8 2.845f
-Ccap@2 gnd net@11 2.845f
-Rres@0 net@14 a 4.483
-Rres@1 net@11 net@14 8.966
-Rres@2 b net@8 4.483
-Rres@3 net@8 net@11 8.966
-.ENDS wire-C_0_011f-775_9-R_34_667m
+*** CELL: stageGroupsM:properStopper{sch}
+.SUBCKT properStopper ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
++aout[7] aout[8] aout[9] aout[TT] extra fire in[10] in[11] in[12] in[13]
++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
++in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
++succ
+XdrainSta@1 net@65[41] net@65[40] net@65[39] net@65[38] net@65[37] net@65[50]
++net@65[49] net@65[48] net@65[47] net@65[46] net@65[45] net@65[44] net@65[43]
++net@65[42] net@65[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
++net@65[27] net@65[26] net@65[25] net@65[24] net@65[23] net@65[22] net@65[21]
++net@65[20] net@65[19] net@65[18] net@65[36] net@65[17] net@65[16] net@65[15]
++net@65[14] net@65[13] net@65[12] net@65[11] net@65[10] net@65[9] net@65[8]
++net@65[35] net@65[7] net@65[6] net@65[5] net@65[4] net@65[3] net@65[2]
++net@65[1] net@65[0] net@65[34] net@65[33] net@65[32] net@65[31] net@65[30]
++net@65[29] net@65[28] out[10] out[11] out[12] out[13] out[14] out[15] out[16]
++out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24]
++out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32]
++out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7]
++out[8] out[9] net@42 net@3[8] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
++sic[8] sic[9] net@2[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
++sir[9] soc[1] sor[1] succ drainStage
+XfillStag@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] net@65[41] net@65[40]
++net@65[39] net@65[38] net@65[37] net@65[50] net@65[49] net@65[48] net@65[47]
++net@65[46] net@65[45] net@65[44] net@65[43] net@65[42] net@65[51] extra fire
++in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1]
++in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2]
++in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3] in[4] in[5]
++in[6] in[7] in[8] in[9] net@65[27] net@65[26] net@65[25] net@65[24]
++net@65[23] net@65[22] net@65[21] net@65[20] net@65[19] net@65[18] net@65[36]
++net@65[17] net@65[16] net@65[15] net@65[14] net@65[13] net@65[12] net@65[11]
++net@65[10] net@65[9] net@65[8] net@65[35] net@65[7] net@65[6] net@65[5]
++net@65[4] net@65[3] net@65[2] net@65[1] net@65[0] net@65[34] net@65[33]
++net@65[32] net@65[31] net@65[30] net@65[29] net@65[28] pred sic[1] sic[2]
++sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4]
++sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sir[9] net@3[8] sod[1] sod[2] sod[3] sod[4] sod[5] net@2[8]
++net@41 fillStage
+Xwire90@0 net@41 net@42 wire90-2080_4-layer_1-width_3
+.ENDS properStopper
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-775_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-775_9-R_34_667m
-.ENDS wire90-775_9-layer_1-width_3
+*** CELL: stageGroupsM:fillDrainCount{sch}
+.SUBCKT fillDrainCount ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
++aout[7] aout[8] aout[9] aout[TT] fin fout in[10] in[11] in[12] in[13] in[14]
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24]
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34]
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
++succ
+Xinstruct@0 net@53 net@48 fin fout net@61[8] sod[2] sod[3] sod[4] sod[5]
++sid[6] sid[7] sid[8] sid[9] sod[1] instructionCount
+XproperSt@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
++aout[8] aout[9] aout[TT] net@86 net@53 in[10] in[11] in[12] in[13] in[14]
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24]
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34]
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sir[9] soc[1] net@61[8] sod[2] sod[3] sod[4] sod[5]
++sor[1] succ properStopper
+Xwire90@1 net@86 net@48 wire90-2080_4-layer_1-width_3
+.ENDS fillDrainCount
+
+*** CELL: scanM:scanCap{sch}
+.SUBCKT scanCap si[1] si[2] si[3] si[4] si[5] si[9]
+.ENDS scanCap
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-480_2-R_34_667m a b
-Ccap@0 gnd net@14 1.761f
-Ccap@1 gnd net@8 1.761f
-Ccap@2 gnd net@11 1.761f
-Rres@0 net@14 a 2.774
-Rres@1 net@11 net@14 5.549
-Rres@2 b net@8 2.774
-Rres@3 net@8 net@11 5.549
-.ENDS wire-C_0_011f-480_2-R_34_667m
+.SUBCKT wire-C_0_011f-123_7-R_34_667m a b
+Ccap@0 gnd net@14 0.454f
+Ccap@1 gnd net@8 0.454f
+Ccap@2 gnd net@11 0.454f
+Rres@0 net@14 a 0.715
+Rres@1 net@11 net@14 1.429
+Rres@2 b net@8 0.715
+Rres@3 net@8 net@11 1.429
+.ENDS wire-C_0_011f-123_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-480_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-480_2-R_34_667m
-.ENDS wire90-480_2-layer_1-width_3
+.SUBCKT wire90-123_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-123_7-R_34_667m
+.ENDS wire90-123_7-layer_1-width_3
-*** CELL: redFive:xor2{sch}
-.SUBCKT xor2-X_5 ina inaB inb inbB out
-Xnms2@0 out inb ina nms2-X_5
-Xnms2@1 out inbB inaB nms2-X_5
-Xpms2@0 out inbB ina pms2-X_5
-Xpms2@1 out inb inaB pms2-X_5
-.ENDS xor2-X_5
-
-*** CELL: oneHotM:ohXor{sch}
-.SUBCKT ohXor flag[F] flag[T] in[1][F] in[1][T] out
-Xxor2@0 in[1][T] in[1][F] flag[T] flag[F] out xor2-X_5
-.ENDS ohXor
+*** CELL: latchPartsK:latchPointT{sch}
+.SUBCKT latchPointT hcl in[1] x[F] x[T]
+XPMOSx@0 in[1] hcl x[T] NMOSx-X_6
+XPMOSx@1 net@8 hcl x[F] NMOSx-X_3
+Xinv@0 in[1] net@105 invLT-X_5
+Xwire90@0 net@105 net@8 wire90-123_7-layer_1-width_3
+.ENDS latchPointT
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-357-R_34_667m a b
-Ccap@0 gnd net@14 1.309f
-Ccap@1 gnd net@8 1.309f
-Ccap@2 gnd net@11 1.309f
-Rres@0 net@14 a 2.063
-Rres@1 net@11 net@14 4.125
-Rres@2 b net@8 2.063
-Rres@3 net@8 net@11 4.125
-.ENDS wire-C_0_011f-357-R_34_667m
+.SUBCKT wire-C_0_011f-180_9-R_34_667m a b
+Ccap@0 gnd net@14 0.663f
+Ccap@1 gnd net@8 0.663f
+Ccap@2 gnd net@11 0.663f
+Rres@0 net@14 a 1.045
+Rres@1 net@11 net@14 2.09
+Rres@2 b net@8 1.045
+Rres@3 net@8 net@11 2.09
+.ENDS wire-C_0_011f-180_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-357-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-357-R_34_667m
-.ENDS wire90-357-layer_1-width_3
+.SUBCKT wire90-180_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-180_9-R_34_667m
+.ENDS wire90-180_9-layer_1-width_3
+
+*** CELL: latchesK:raw1inLatchT{sch}
+.SUBCKT raw1inLatchT hcl[A] inA[1] out[T]
+XlatchFlo@0 out[T] net@29 latchKeep
+XlatchPoi@0 hcl[A] inA[1] net@7 out[T] latchPointT
+Xwire90@0 net@7 net@29 wire90-180_9-layer_1-width_3
+.ENDS raw1inLatchT
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-394_5-R_34_667m a b
-Ccap@0 gnd net@14 1.447f
-Ccap@1 gnd net@8 1.447f
-Ccap@2 gnd net@11 1.447f
-Rres@0 net@14 a 2.279
-Rres@1 net@11 net@14 4.559
-Rres@2 b net@8 2.279
-Rres@3 net@8 net@11 4.559
-.ENDS wire-C_0_011f-394_5-R_34_667m
+.SUBCKT wire-C_0_011f-250_9-R_34_667m a b
+Ccap@0 gnd net@14 0.92f
+Ccap@1 gnd net@8 0.92f
+Ccap@2 gnd net@11 0.92f
+Rres@0 net@14 a 1.45
+Rres@1 net@11 net@14 2.899
+Rres@2 b net@8 1.45
+Rres@3 net@8 net@11 2.899
+.ENDS wire-C_0_011f-250_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-394_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-394_5-R_34_667m
-.ENDS wire90-394_5-layer_1-width_3
+.SUBCKT wire90-250_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-250_9-R_34_667m
+.ENDS wire90-250_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-372_2-R_34_667m a b
-Ccap@0 gnd net@14 1.365f
-Ccap@1 gnd net@8 1.365f
-Ccap@2 gnd net@11 1.365f
-Rres@0 net@14 a 2.15
-Rres@1 net@11 net@14 4.301
-Rres@2 b net@8 2.15
-Rres@3 net@8 net@11 4.301
-.ENDS wire-C_0_011f-372_2-R_34_667m
+.SUBCKT wire-C_0_011f-214_6-R_34_667m a b
+Ccap@0 gnd net@14 0.787f
+Ccap@1 gnd net@8 0.787f
+Ccap@2 gnd net@11 0.787f
+Rres@0 net@14 a 1.24
+Rres@1 net@11 net@14 2.48
+Rres@2 b net@8 1.24
+Rres@3 net@8 net@11 2.48
+.ENDS wire-C_0_011f-214_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-372_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-372_2-R_34_667m
-.ENDS wire90-372_2-layer_1-width_3
+.SUBCKT wire90-214_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-214_6-R_34_667m
+.ENDS wire90-214_6-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-319_8-R_34_667m a b
-Ccap@0 gnd net@14 1.173f
-Ccap@1 gnd net@8 1.173f
-Ccap@2 gnd net@11 1.173f
-Rres@0 net@14 a 1.848
-Rres@1 net@11 net@14 3.695
-Rres@2 b net@8 1.848
-Rres@3 net@8 net@11 3.695
-.ENDS wire-C_0_011f-319_8-R_34_667m
+*** CELL: latchesK:latch1in20B{sch}
+.SUBCKT latch1in20B hcl in[1] out[1]
+Xhi2inLat@0 hcl in[1] net@19 raw1inLatchT
+Xinv@0 net@23 out[1] inv-X_20
+XinvLT@0 net@18 net@25 inv-X_5
+Xwire90@0 net@19 net@18 wire90-250_9-layer_1-width_3
+Xwire90@1 net@25 net@23 wire90-214_6-layer_1-width_3
+.ENDS latch1in20B
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-319_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-319_8-R_34_667m
-.ENDS wire90-319_8-layer_1-width_3
+*** CELL: registersM:addr1in20Bx7{sch}
+.SUBCKT addr1in20Bx7 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1]
++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire
+Xlat[1] fire ain[1] aout[1] latch1in20B
+Xlat[2] fire ain[2] aout[2] latch1in20B
+Xlat[3] fire ain[3] aout[3] latch1in20B
+Xlat[4] fire ain[4] aout[4] latch1in20B
+Xlat[5] fire ain[5] aout[5] latch1in20B
+Xlat[6] fire ain[6] aout[6] latch1in20B
+Xlat[7] fire ain[7] aout[7] latch1in20B
+.ENDS addr1in20Bx7
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-386_5-R_34_667m a b
-Ccap@0 gnd net@14 1.417f
-Ccap@1 gnd net@8 1.417f
-Ccap@2 gnd net@11 1.417f
-Rres@0 net@14 a 2.233
-Rres@1 net@11 net@14 4.466
-Rres@2 b net@8 2.233
-Rres@3 net@8 net@11 4.466
-.ENDS wire-C_0_011f-386_5-R_34_667m
+*** CELL: registersM:addr1in20Bx15{sch}
+.SUBCKT addr1in20Bx15 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
++aout[7] aout[8] aout[9] aout[TT] fire
+Xaddr1in2@1 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8]
++aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@17 addr1in20Bx7
+Xaddr1in2@2 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
++aout[3] aout[4] aout[5] aout[6] aout[7] net@19 addr1in20Bx7
+Xlatch1in@1 fire ain[TT] aout[TT] latch1in20B
+Xwire90@0 net@19 fire wire90-2330-layer_1-width_3
+Xwire90@1 fire net@17 wire90-2330-layer_1-width_3
+.ENDS addr1in20Bx15
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-386_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-386_5-R_34_667m
-.ENDS wire90-386_5-layer_1-width_3
+*** CELL: registersM:ins1in20Bx18{sch}
+.SUBCKT ins1in20Bx18 hcl in[10] in[11] in[12] in[13] in[14] in[15] in[16]
++in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2]
++out[3] out[4] out[5] out[6] out[7] out[8] out[9]
+Xlx[1] hcl in[1] out[1] latch1in20B
+Xlx[2] hcl in[2] out[2] latch1in20B
+Xlx[3] hcl in[3] out[3] latch1in20B
+Xlx[4] hcl in[4] out[4] latch1in20B
+Xlx[5] hcl in[5] out[5] latch1in20B
+Xlx[6] hcl in[6] out[6] latch1in20B
+Xlx[7] hcl in[7] out[7] latch1in20B
+Xlx[8] hcl in[8] out[8] latch1in20B
+Xlx[9] hcl in[9] out[9] latch1in20B
+Xlx[10] hcl in[10] out[10] latch1in20B
+Xlx[11] hcl in[11] out[11] latch1in20B
+Xlx[12] hcl in[12] out[12] latch1in20B
+Xlx[13] hcl in[13] out[13] latch1in20B
+Xlx[14] hcl in[14] out[14] latch1in20B
+Xlx[15] hcl in[15] out[15] latch1in20B
+Xlx[16] hcl in[16] out[16] latch1in20B
+Xlx[17] hcl in[17] out[17] latch1in20B
+Xlx[18] hcl in[18] out[18] latch1in20B
+.ENDS ins1in20Bx18
+
+*** CELL: registersM:data1in20Bx37{sch}
+.SUBCKT data1in20Bx37 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37]
++in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4]
++out[5] out[6] out[7] out[8] out[9] take
+Xins1in20@0 net@17 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
++in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29]
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20]
++out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] ins1in20Bx18
+Xins1in20@1 net@19 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
++out[4] out[5] out[6] out[7] out[8] out[9] ins1in20Bx18
+Xlatch1in@1 take in[19] out[19] latch1in20B
+Xwire90@2 take net@17 wire90-2550-layer_1-width_3
+Xwire90@3 net@19 take wire90-2550-layer_1-width_3
+.ENDS data1in20Bx37
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_3_999 d g s
+MPMOSf@0 d g s vdd pch W='23.994*(1+ABP/sqrt(23.994*2))' L='2'
++DELVTO='AVT0P/sqrt(23.994*2)'
+.ENDS PMOSx-X_3_999
+
+*** CELL: redFive:pms3{sch}
+.SUBCKT pms3-X_1_333 d g g2 g3
+XPMOS@0 d g3 net@2 PMOSx-X_3_999
+XPMOS@1 net@2 g2 net@5 PMOSx-X_3_999
+XPMOS@2 net@5 g vdd PMOSx-X_3_999
+.ENDS pms3-X_1_333
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-297_8-R_34_667m a b
-Ccap@0 gnd net@14 1.092f
-Ccap@1 gnd net@8 1.092f
-Ccap@2 gnd net@11 1.092f
-Rres@0 net@14 a 1.721
-Rres@1 net@11 net@14 3.441
-Rres@2 b net@8 1.721
-Rres@3 net@8 net@11 3.441
-.ENDS wire-C_0_011f-297_8-R_34_667m
+.SUBCKT wire-C_0_011f-106_7-R_34_667m a b
+Ccap@0 gnd net@14 0.391f
+Ccap@1 gnd net@8 0.391f
+Ccap@2 gnd net@11 0.391f
+Rres@0 net@14 a 0.616
+Rres@1 net@11 net@14 1.233
+Rres@2 b net@8 0.616
+Rres@3 net@8 net@11 1.233
+.ENDS wire-C_0_011f-106_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-297_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-297_8-R_34_667m
-.ENDS wire90-297_8-layer_1-width_3
+.SUBCKT wire90-106_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-106_7-R_34_667m
+.ENDS wire90-106_7-layer_1-width_3
-*** CELL: oneHotM:xor6x12{sch}
-.SUBCKT xor6x12 all any flag[1][F] flag[1][T] flag[2][F] flag[2][T]
-+flag[3][F] flag[3][T] in[1][F] in[1][T] in[2][F] in[2][T] in[3][F] in[3][T]
-+in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T]
-Xnand3in6@2 match[12T] match[34T] match[56T] any nand3in6_6sym
-Xnor3in3_@1 match[56F] match[34F] match[12F] all nor3in6_6sym
-XohMux@6 flag[1][F] flag[1][T] in[2][F] in[1][F] net@84 ohXor
-XohMux@7 flag[1][F] flag[1][T] in[2][T] in[1][T] net@91 ohXor
-XohMux@8 flag[2][F] flag[2][T] in[4][F] in[3][F] net@94 ohXor
-XohMux@9 flag[2][F] flag[2][T] in[4][T] in[3][T] net@93 ohXor
-XohMux@10 flag[3][F] flag[3][T] in[6][F] in[5][F] net@102 ohXor
-XohMux@11 flag[3][F] flag[3][T] in[6][T] in[5][T] net@101 ohXor
-Xwire90@0 net@94 match[34F] wire90-357-layer_1-width_3
-Xwire90@1 match[34T] net@93 wire90-394_5-layer_1-width_3
-Xwire90@2 net@102 match[56F] wire90-372_2-layer_1-width_3
-Xwire90@3 match[56T] net@101 wire90-319_8-layer_1-width_3
-Xwire90@4 net@84 match[12F] wire90-386_5-layer_1-width_3
-Xwire90@5 match[12T] net@91 wire90-297_8-layer_1-width_3
-.ENDS xor6x12
+*** CELL: driversL:predDri20wMC{sch}
+.SUBCKT predDri20wMC in mc pred
+XNMOSx@0 pred in gnd NMOSx-X_20
+XNMOSx@1 pred mc gnd NMOSx-X_4
+Xinv@0 pred net@145 inv-X_4
+Xpms3@0 pred net@177 in mc pms3-X_1_333
+Xwire90@0 net@177 net@145 wire90-106_7-layer_1-width_3
+.ENDS predDri20wMC
-*** CELL: oneHotM:aFlag{sch}
-.SUBCKT aFlag flag[1][F] flag[1][T] flag[1][clr] flag[1][set] flag[A][F]
-+flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] in[1][T] in[2][T]
-+in[3][T] in[4][T] in[5][T] in[6][T] mc
-Xinv@0 net@257 flag[1][T] inv-X_20
-Xinv@2 net@258 flag[1][F] inv-X_20
-Xinv@3 net@2 net@267 inv-X_10
-Xinv@4 mc net@305 inv-X_10
-XinvI@10 net@9 net@308 inv-X_5
-XinvI@11 net@176 net@306 inv-X_5
-Xinv[1] in[1][T] in[1][F] inv-X_10
-Xinv[2] in[2][T] in[2][F] inv-X_10
-Xinv[3] in[3][T] in[3][F] inv-X_10
-Xinv[4] in[4][T] in[4][F] inv-X_10
-Xinv[5] in[5][T] in[5][F] inv-X_10
-Xinv[6] in[6][T] in[6][F] inv-X_10
-Xnand2@0 net@5 net@2 net@9 nand2-X_5
-Xnand2@1 net@69 net@71 net@176 nand2-X_5
-Xnand2@2 net@51 net@267 net@239 nand2-X_5
-Xnand2@3 net@22 net@265 net@240 nand2-X_5
-Xnand2n@0 net@64 net@49 net@51 nand2n-X_10
-Xnand2n@1 net@172 net@50 net@22 nand2n-X_10
-Xnand2n@2 net@236 net@235 net@258 nand2n-X_10
-Xnand2n@3 net@259 net@234 net@257 nand2n-X_10
-Xnor2n_sy@0 flag[1][clr] flag[1][set] net@2 nor2n_sy-X_10
-XsucANDdr@0 net@305 net@308 flag[1][set] sucANDdri20
-XsucANDdr@3 net@319 net@306 flag[1][clr] sucANDdri20
-Xwire90@1 net@8 net@5 wire90-405_3-layer_1-width_3
-Xwire90@4 net@22 net@49 wire90-385_8-layer_1-width_3
-Xwire90@5 net@50 net@51 wire90-406_4-layer_1-width_3
-Xwire90@6 net@64 net@9 wire90-329_2-layer_1-width_3
-Xwire90@8 net@69 net@68 wire90-407_9-layer_1-width_3
-Xwire90@19 net@176 net@172 wire90-329_2-layer_1-width_3
-Xwire90@22 net@240 net@259 wire90-247-layer_1-width_3
-Xwire90@23 net@236 net@239 wire90-247-layer_1-width_3
-Xwire90@24 net@257 net@235 wire90-456_8-layer_1-width_3
-Xwire90@25 net@234 net@258 wire90-477_4-layer_1-width_3
-Xwire90@26 net@71 net@2 wire90-775_9-layer_1-width_3
-Xwire90@27 net@265 net@267 wire90-480_2-layer_1-width_3
-Xwire90@28 net@319 net@305 wire90-385_8-layer_1-width_3
-Xxor6x12@0 net@68 net@8 flag[A][F] flag[A][T] flag[B][F] flag[B][T]
-+flag[C][F] flag[C][T] in[1][F] in[1][T] in[2][F] in[2][T] in[3][F] in[3][T]
-+in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T] xor6x12
-.ENDS aFlag
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_6 d g s
+MPMOSf@0 d g s vdd pch W='36*(1+ABP/sqrt(36*2))' L='2'
++DELVTO='AVT0P/sqrt(36*2)'
+.ENDS PMOSx-X_6
-*** CELL: oneHotM:flags{sch}
-.SUBCKT flags flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T]
-+m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc
-XaFlag@0 flag[A][F] flag[A][T] flag[A][clr] flag[A][set] flag[A][F]
-+flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] m1[1] m1[2] m1[3]
-+m1[4] m1[5] m1[6] mc aFlag
-XaFlag@1 flag[B][F] flag[B][T] flag[B][clr] flag[B][set] flag[A][F]
-+flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] m1[7] m1[8] m1[9]
-+m1[10] m1[11] m1[12] mc aFlag
-Xinv@0 flag[C][T] flag[C][F] inv-X_10
-.ENDS flags
+*** CELL: redFive:inv{sch}
+.SUBCKT inv-X_6 in out
+XNMOS@0 out in gnd NMOSx-X_6
+XPMOS@0 out in vdd PMOSx-X_6
+.ENDS inv-X_6
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-979-R_34_667m a b
-Ccap@0 gnd net@14 3.59f
-Ccap@1 gnd net@8 3.59f
-Ccap@2 gnd net@11 3.59f
-Rres@0 net@14 a 5.656
-Rres@1 net@11 net@14 11.313
-Rres@2 b net@8 5.656
-Rres@3 net@8 net@11 11.313
-.ENDS wire-C_0_011f-979-R_34_667m
+*** CELL: redFive:nms2{sch}
+.SUBCKT nms2-X_2 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_4
+XNMOS@1 net@0 g gnd NMOSx-X_4
+.ENDS nms2-X_2
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-979-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-979-R_34_667m
-.ENDS wire90-979-layer_1-width_3
+*** CELL: redFive:pms1{sch}
+.SUBCKT pms1-X_20 d g
+XPMOS@0 d g vdd PMOSx-X_20
+.ENDS pms1-X_20
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-704_9-R_34_667m a b
-Ccap@0 gnd net@14 2.585f
-Ccap@1 gnd net@8 2.585f
-Ccap@2 gnd net@11 2.585f
-Rres@0 net@14 a 4.073
-Rres@1 net@11 net@14 8.146
-Rres@2 b net@8 4.073
-Rres@3 net@8 net@11 8.146
-.ENDS wire-C_0_011f-704_9-R_34_667m
+.SUBCKT wire-C_0_011f-503_4-R_34_667m a b
+Ccap@0 gnd net@14 1.846f
+Ccap@1 gnd net@8 1.846f
+Ccap@2 gnd net@11 1.846f
+Rres@0 net@14 a 2.909
+Rres@1 net@11 net@14 5.817
+Rres@2 b net@8 2.909
+Rres@3 net@8 net@11 5.817
+.ENDS wire-C_0_011f-503_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-704_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-704_9-R_34_667m
-.ENDS wire90-704_9-layer_1-width_3
+.SUBCKT wire90-503_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-503_4-R_34_667m
+.ENDS wire90-503_4-layer_1-width_3
+
+*** CELL: driversL:sucDri20{sch}
+.SUBCKT sucDri20 in succ
+Xinv@1 succ net@94 inv-X_4
+Xinv@2 in net@110 inv-X_6
+Xnms2@0 succ net@117 net@109 nms2-X_2
+Xpms1@0 succ net@109 pms1-X_20
+Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3
+Xwire90@1 net@110 net@109 wire90-503_4-layer_1-width_3
+.ENDS sucDri20
+
+*** CELL: gaspM:gaspWeak{sch}
+.SUBCKT gaspWeak fire mc pred s[1] succ take tok
+XctrAND2i@0 net@10 succ fire ctrAND2in100LT
+XdataDriv@0 tok fire take dataDriver60
+Xinv@0 pred net@8 inv-X_5
+XinvI@0 net@10 s[1] inv-X_10
+XpredDri2@0 net@30 mc pred predDri20wMC
+XsucDri20@0 fire succ sucDri20
+Xwire90@0 net@8 net@10 wire90-602_3-layer_1-width_3
+Xwire90@1 net@30 fire wire90-602_3-layer_1-width_3
+.ENDS gaspWeak
+
+*** CELL: scanJ:scanEx1vertA{sch}
+.SUBCKT scanEx1vertA dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sor[1]
+XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanJ__scanCellE
+.ENDS scanEx1vertA
+
+*** CELL: stagesM:weakStage{sch}
+.SUBCKT weakStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
++aout[7] aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15]
++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25]
++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35]
++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1]
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28]
++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36]
++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sir[1] sir[2]
++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ
+Xaddr1in2@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
++aout[8] aout[9] aout[TT] net@59 addr1in20Bx15
+Xdata1in2@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3]
++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
++out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
++out[6] out[7] out[8] out[9] net@47 data1in20Bx37
+XgaspWeak@0 net@59 sir[9] pred net@39 succ net@47 ain[TT] gaspWeak
+XscanEx1v@0 net@39 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sor[1] scanEx1vertA
+.ENDS weakStage
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-784_7-R_34_667m a b
-Ccap@0 gnd net@14 2.877f
-Ccap@1 gnd net@8 2.877f
-Ccap@2 gnd net@11 2.877f
-Rres@0 net@14 a 4.534
-Rres@1 net@11 net@14 9.068
-Rres@2 b net@8 4.534
-Rres@3 net@8 net@11 9.068
-.ENDS wire-C_0_011f-784_7-R_34_667m
+.SUBCKT wire-C_0_011f-1243_9-R_34_667m a b
+Ccap@0 gnd net@14 4.561f
+Ccap@1 gnd net@8 4.561f
+Ccap@2 gnd net@11 4.561f
+Rres@0 net@14 a 7.187
+Rres@1 net@11 net@14 14.374
+Rres@2 b net@8 7.187
+Rres@3 net@8 net@11 14.374
+.ENDS wire-C_0_011f-1243_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-784_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-784_7-R_34_667m
-.ENDS wire90-784_7-layer_1-width_3
+.SUBCKT wire90-1243_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1243_9-R_34_667m
+.ENDS wire90-1243_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-631_7-R_34_667m a b
-Ccap@0 gnd net@14 2.316f
-Ccap@1 gnd net@8 2.316f
-Ccap@2 gnd net@11 2.316f
-Rres@0 net@14 a 3.65
-Rres@1 net@11 net@14 7.3
-Rres@2 b net@8 3.65
-Rres@3 net@8 net@11 7.3
-.ENDS wire-C_0_011f-631_7-R_34_667m
+.SUBCKT wire-C_0_011f-1185_9-R_34_667m a b
+Ccap@0 gnd net@14 4.348f
+Ccap@1 gnd net@8 4.348f
+Ccap@2 gnd net@11 4.348f
+Rres@0 net@14 a 6.852
+Rres@1 net@11 net@14 13.704
+Rres@2 b net@8 6.852
+Rres@3 net@8 net@11 13.704
+.ENDS wire-C_0_011f-1185_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-631_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-631_7-R_34_667m
-.ENDS wire90-631_7-layer_1-width_3
+.SUBCKT wire90-1185_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1185_9-R_34_667m
+.ENDS wire90-1185_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-328_2-R_34_667m a b
-Ccap@0 gnd net@14 1.203f
-Ccap@1 gnd net@8 1.203f
-Ccap@2 gnd net@11 1.203f
-Rres@0 net@14 a 1.896
-Rres@1 net@11 net@14 3.793
-Rres@2 b net@8 1.896
-Rres@3 net@8 net@11 3.793
-.ENDS wire-C_0_011f-328_2-R_34_667m
+.SUBCKT wire-C_0_011f-1249_9-R_34_667m a b
+Ccap@0 gnd net@14 4.583f
+Ccap@1 gnd net@8 4.583f
+Ccap@2 gnd net@11 4.583f
+Rres@0 net@14 a 7.222
+Rres@1 net@11 net@14 14.443
+Rres@2 b net@8 7.222
+Rres@3 net@8 net@11 14.443
+.ENDS wire-C_0_011f-1249_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-328_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-328_2-R_34_667m
-.ENDS wire90-328_2-layer_1-width_3
+.SUBCKT wire90-1249_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1249_9-R_34_667m
+.ENDS wire90-1249_9-layer_1-width_3
-*** CELL: loopCountM:calculate{sch}
-.SUBCKT calculate bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] do[2] do[3] do[4]
-+do[5] do[6] zero zoo
-Xinv@0 net@257 do[2] inv-X_10
-Xinv@1 bit[2] net@128 inv-X_10
-Xinv@2 bit[1] net@257 inv-X_10
-Xnand2@0 bit[3] bit[1] net@145 nand2-X_10
-Xnand2@1 bit[4] bit[2] net@195 nand2-X_10
-Xnand2@2 bit[3] bit[5] net@315 nand2-X_10
-Xnand3@0 bit[5] bit[3] bit[1] net@264 nand3-X_6_667
-Xnand3@1 bit[6] bit[4] bit[2] net@198 nand3-X_6_667
-Xnor2n@1 net@128 net@257 do[3] nor2n-X_10
-Xnor2n@2 net@145 net@146 do[4] nor2n-X_10
-Xnor2n@3 net@195 net@58 do[5] nor2n-X_10
-Xnor2n@4 net@221 net@56 do[6] nor2n-X_10
-Xnor2n@5 net@289 net@267 zoo nor2n-X_10
-Xnor2n@6 net@198 net@264 zero nor2n-X_10
-Xwire90@0 net@264 net@221 wire90-979-layer_1-width_3
-Xwire90@1 net@58 net@145 wire90-704_9-layer_1-width_3
-Xwire90@3 net@56 net@195 wire90-704_3-layer_1-width_3
-Xwire90@5 net@198 net@289 wire90-784_7-layer_1-width_3
-Xwire90@6 net@146 net@128 wire90-631_7-layer_1-width_3
-Xwire90@8 net@267 net@315 wire90-328_2-layer_1-width_3
-.ENDS calculate
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_1 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_2
-XPMOS@1 d g2 net@2 PMOSx-X_2
-.ENDS pms2-X_1
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_2 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_4
-XPMOS@1 d g2 net@2 PMOSx-X_4
-.ENDS pms2-X_2
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-185-R_34_667m a b
-Ccap@0 gnd net@14 0.678f
-Ccap@1 gnd net@8 0.678f
-Ccap@2 gnd net@11 0.678f
-Rres@0 net@14 a 1.069
-Rres@1 net@11 net@14 2.138
-Rres@2 b net@8 1.069
-Rres@3 net@8 net@11 2.138
-.ENDS wire-C_0_011f-185-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-185-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-185-R_34_667m
-.ENDS wire90-185-layer_1-width_3
-
-*** CELL: latchesK:mlat1in10{sch}
-.SUBCKT mlat1in10 cl[F] cl[T] in[1] out[1]
-Xinv@0 net@26 out[1] inv-X_10
-Xnms2@0 net@4 out[1] cl[F] nms2-X_2
-Xnms2@1 net@4 in[1] cl[T] nms2-X_2
-Xpms2@0 net@4 out[1] cl[T] pms2-X_1
-Xpms2@1 net@4 in[1] cl[F] pms2-X_2
-Xwire90@0 net@4 net@26 wire90-185-layer_1-width_3
-.ENDS mlat1in10
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_15 d g s
-MNMOSf@0 d g s gnd nch W='45*(1+ABN/sqrt(45*2))' L='2'
-+DELVTO='AVT0N/sqrt(45*2)'
-.ENDS NMOSx-X_15
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_15 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_30
-XPMOS@1 d g2 net@2 PMOSx-X_30
-.ENDS pms2-X_15
-
-*** CELL: redFive:nor2{sch}
-.SUBCKT nor2-X_15 ina inb out
-XNMOS@0 out ina gnd NMOSx-X_15
-XNMOS@1 out inb gnd NMOSx-X_15
-Xpms2@0 out ina inb pms2-X_15
-.ENDS nor2-X_15
-
-*** CELL: redFive:nor2n{sch}
-.SUBCKT nor2n-X_15 ina inb out
-Xnor2@0 ina inb out nor2-X_15
-.ENDS nor2n-X_15
-
-*** CELL: redFive:invLT{sch}
-.SUBCKT invLT-X_2 in out
-XNMOS@0 out in gnd NMOSx-X_4
-XPMOS@0 out in vdd PMOSx-X_2
-.ENDS invLT-X_2
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-133_8-R_34_667m a b
-Ccap@0 gnd net@14 0.491f
-Ccap@1 gnd net@8 0.491f
-Ccap@2 gnd net@11 0.491f
-Rres@0 net@14 a 0.773
-Rres@1 net@11 net@14 1.546
-Rres@2 b net@8 0.773
-Rres@3 net@8 net@11 1.546
-.ENDS wire-C_0_011f-133_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-133_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-133_8-R_34_667m
-.ENDS wire90-133_8-layer_1-width_3
-
-*** CELL: latchesK:mlat1in5i{sch}
-.SUBCKT mlat1in5i c[F] c[T] in out
-XinvLT@0 out net@119 invLT-X_2
-Xnms2@2 out in c[T] nms2-X_5
-Xnms2@3 out net@114 c[F] nms2-X_2
-Xpms2@0 out net@114 c[T] pms2-X_1
-Xpms2@1 out in c[F] pms2-X_5
-Xwire90@19 net@114 net@119 wire90-133_8-layer_1-width_3
-.ENDS mlat1in5i
-
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_2 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_6
-XNMOS@1 net@7 g gnd NMOSx-X_6
-XNMOS@2 net@6 g2 net@7 NMOSx-X_6
-.ENDS nms3-X_2
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_3 d g s
-MPMOSf@0 d g s vdd pch W='18*(1+ABP/sqrt(18*2))' L='2'
-+DELVTO='AVT0P/sqrt(18*2)'
-.ENDS PMOSx-X_3
-
-*** CELL: redFive:pms3{sch}
-.SUBCKT pms3-X_1 d g g2 g3
-XPMOS@0 d g3 net@2 PMOSx-X_3
-XPMOS@1 net@2 g2 net@5 PMOSx-X_3
-XPMOS@2 net@5 g vdd PMOSx-X_3
-.ENDS pms3-X_1
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-200_9-R_34_667m a b
-Ccap@0 gnd net@14 0.737f
-Ccap@1 gnd net@8 0.737f
-Ccap@2 gnd net@11 0.737f
-Rres@0 net@14 a 1.161
-Rres@1 net@11 net@14 2.322
-Rres@2 b net@8 1.161
-Rres@3 net@8 net@11 2.322
-.ENDS wire-C_0_011f-200_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-200_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-200_9-R_34_667m
-.ENDS wire90-200_9-layer_1-width_3
-
-*** CELL: latchesK:mlat2in10i{sch}
-.SUBCKT mlat2in10i clA[F] clA[T] clB[F] clB[T] inA inB out[1]
-Xinv@0 out[1] net@33 inv-X_4
-Xnms2@0 out[1] inB clB[T] nms2-X_10
-Xnms2@1 out[1] inA clA[T] nms2-X_10
-Xnms3@0 out[1] clB[F] clA[F] net@33 nms3-X_2
-Xpms2@0 out[1] inB clB[F] pms2-X_10
-Xpms2@1 out[1] inA clA[F] pms2-X_10
-Xpms3@0 out[1] clA[T] clB[T] net@81 pms3-X_1
-Xwire90@1 net@81 net@33 wire90-200_9-layer_1-width_3
-.ENDS mlat2in10i
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-173_2-R_34_667m a b
-Ccap@0 gnd net@14 0.635f
-Ccap@1 gnd net@8 0.635f
-Ccap@2 gnd net@11 0.635f
-Rres@0 net@14 a 1.001
-Rres@1 net@11 net@14 2.001
-Rres@2 b net@8 1.001
-Rres@3 net@8 net@11 2.001
-.ENDS wire-C_0_011f-173_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-173_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-173_2-R_34_667m
-.ENDS wire90-173_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-381_1-R_34_667m a b
-Ccap@0 gnd net@14 1.397f
-Ccap@1 gnd net@8 1.397f
-Ccap@2 gnd net@11 1.397f
-Rres@0 net@14 a 2.202
-Rres@1 net@11 net@14 4.404
-Rres@2 b net@8 2.202
-Rres@3 net@8 net@11 4.404
-.ENDS wire-C_0_011f-381_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-381_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-381_1-R_34_667m
-.ENDS wire90-381_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-981_4-R_34_667m a b
-Ccap@0 gnd net@14 3.598f
-Ccap@1 gnd net@8 3.598f
-Ccap@2 gnd net@11 3.598f
-Rres@0 net@14 a 5.67
-Rres@1 net@11 net@14 11.341
-Rres@2 b net@8 5.67
-Rres@3 net@8 net@11 11.341
-.ENDS wire-C_0_011f-981_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-981_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-981_4-R_34_667m
-.ENDS wire90-981_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-523_4-R_34_667m a b
-Ccap@0 gnd net@14 1.919f
-Ccap@1 gnd net@8 1.919f
-Ccap@2 gnd net@11 1.919f
-Rres@0 net@14 a 3.024
-Rres@1 net@11 net@14 6.048
-Rres@2 b net@8 3.024
-Rres@3 net@8 net@11 6.048
-.ENDS wire-C_0_011f-523_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-523_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-523_4-R_34_667m
-.ENDS wire90-523_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-535_1-R_34_667m a b
-Ccap@0 gnd net@14 1.962f
-Ccap@1 gnd net@8 1.962f
-Ccap@2 gnd net@11 1.962f
-Rres@0 net@14 a 3.092
-Rres@1 net@11 net@14 6.183
-Rres@2 b net@8 3.092
-Rres@3 net@8 net@11 6.183
-.ENDS wire-C_0_011f-535_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-535_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-535_1-R_34_667m
-.ENDS wire90-535_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-555_1-R_34_667m a b
-Ccap@0 gnd net@14 2.035f
-Ccap@1 gnd net@8 2.035f
-Ccap@2 gnd net@11 2.035f
-Rres@0 net@14 a 3.207
-Rres@1 net@11 net@14 6.414
-Rres@2 b net@8 3.207
-Rres@3 net@8 net@11 6.414
-.ENDS wire-C_0_011f-555_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-555_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-555_1-R_34_667m
-.ENDS wire90-555_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-677_1-R_34_667m a b
-Ccap@0 gnd net@14 2.483f
-Ccap@1 gnd net@8 2.483f
-Ccap@2 gnd net@11 2.483f
-Rres@0 net@14 a 3.912
-Rres@1 net@11 net@14 7.824
-Rres@2 b net@8 3.912
-Rres@3 net@8 net@11 7.824
-.ENDS wire-C_0_011f-677_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-677_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-677_1-R_34_667m
-.ENDS wire90-677_1-layer_1-width_3
-
-*** CELL: loopCountM:ringB{sch}
-.SUBCKT ringB bit[1] count[F] count[T] do[1] inLO[1] load[F] load[T]
-Xinv@0 net@60 bit[1] inv-X_20
-Xinv@1 bit[1] net@67 inv-X_5
-Xinv@2 net@68 net@65 inv-X_10
-Xinv@3 xx[T] net@64 inv-X_10
-Xmlat1in5@0 xx[T] xx[F] net@66 net@9 mlat1in5i
-Xmlat1in5@1 count[T] count[F] do[1] net@77 mlat1in5i
-Xmlat2in1@0 load[F] load[T] xx[F] xx[T] inLO[1] net@63 net@61 mlat2in10i
-Xnor2n@0 net@78 count[F] net@84 nor2n-X_10
-Xwire90@1 net@67 net@68 wire90-173_2-layer_1-width_3
-Xwire90@2 net@65 net@66 wire90-381_1-layer_1-width_3
-Xwire90@3 net@60 net@61 wire90-981_4-layer_1-width_3
-Xwire90@5 net@63 net@9 wire90-523_4-layer_1-width_3
-Xwire90@6 net@64 xx[F] wire90-535_1-layer_1-width_3
-Xwire90@7 net@77 net@78 wire90-555_1-layer_1-width_3
-Xwire90@8 net@84 xx[T] wire90-677_1-layer_1-width_3
-.ENDS ringB
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1588-R_34_667m a b
-Ccap@0 gnd net@14 5.823f
-Ccap@1 gnd net@8 5.823f
-Ccap@2 gnd net@11 5.823f
-Rres@0 net@14 a 9.175
-Rres@1 net@11 net@14 18.35
-Rres@2 b net@8 9.175
-Rres@3 net@8 net@11 18.35
-.ENDS wire-C_0_011f-1588-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1588-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1588-R_34_667m
-.ENDS wire90-1588-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1317_1-R_34_667m a b
-Ccap@0 gnd net@14 4.829f
-Ccap@1 gnd net@8 4.829f
-Ccap@2 gnd net@11 4.829f
-Rres@0 net@14 a 7.61
-Rres@1 net@11 net@14 15.22
-Rres@2 b net@8 7.61
-Rres@3 net@8 net@11 15.22
-.ENDS wire-C_0_011f-1317_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1317_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1317_1-R_34_667m
-.ENDS wire90-1317_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1283_3-R_34_667m a b
-Ccap@0 gnd net@14 4.705f
-Ccap@1 gnd net@8 4.705f
-Ccap@2 gnd net@11 4.705f
-Rres@0 net@14 a 7.415
-Rres@1 net@11 net@14 14.829
-Rres@2 b net@8 7.415
-Rres@3 net@8 net@11 14.829
-.ENDS wire-C_0_011f-1283_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1283_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1283_3-R_34_667m
-.ENDS wire90-1283_3-layer_1-width_3
-
-*** CELL: loopCountM:ilcEven{sch}
-.SUBCKT ilcEven bit[2] bit[4] bit[6] bit[8] do[2] do[4] do[6] ilc[decLO]
-+inLO[2] inLO[4] inLO[6] inLO[8] load[T] zero
-Xinv@7 count[T] net@273 inv-X_30
-Xinv@8 load[T] net@275 inv-X_30
-Xmlat1in1@1 load[F] load[T] inLO[8] bit[8] mlat1in10
-Xnor2n@0 zero ilc[decLO] net@365 nor2n-X_15
-XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
-XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
-XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
-Xwire90@8 net@273 count[F] wire90-1588-layer_1-width_3
-Xwire90@9 net@275 load[F] wire90-1317_1-layer_1-width_3
-Xwire90@10 net@365 count[T] wire90-1283_3-layer_1-width_3
-.ENDS ilcEven
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1458_1-R_34_667m a b
-Ccap@0 gnd net@14 5.346f
-Ccap@1 gnd net@8 5.346f
-Ccap@2 gnd net@11 5.346f
-Rres@0 net@14 a 8.425
-Rres@1 net@11 net@14 16.849
-Rres@2 b net@8 8.425
-Rres@3 net@8 net@11 16.849
-.ENDS wire-C_0_011f-1458_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1458_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1458_1-R_34_667m
-.ENDS wire90-1458_1-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-341_1-R_34_667m a b
-Ccap@0 gnd net@14 1.251f
-Ccap@1 gnd net@8 1.251f
-Ccap@2 gnd net@11 1.251f
-Rres@0 net@14 a 1.971
-Rres@1 net@11 net@14 3.942
-Rres@2 b net@8 1.971
-Rres@3 net@8 net@11 3.942
-.ENDS wire-C_0_011f-341_1-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-341_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-341_1-R_34_667m
-.ENDS wire90-341_1-layer_1-width_3
-
-*** CELL: loopCountM:ilcOdd{sch}
-.SUBCKT ilcOdd bit[1] bit[3] bit[5] bit[7] do[3] do[5] do[7] ilc[decLO]
-+inLO[1] inLO[3] inLO[5] load[T] zero
-Xinv@5 count[T] net@273 inv-X_30
-Xinv@6 load[T] net@275 inv-X_30
-Xinv@7 ilc[decLO] net@441 inv-X_5
-Xmlat2in1@1 load[F] load[T] ilc[decLO] check[T] gnd do[7] bit[7] mlat2in10i
-Xnor2n@0 zero ilc[decLO] net@454 nor2n-X_15
-XringB@3 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB
-XringB@4 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB
-XringB@5 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB
-Xwire90@4 net@273 count[F] wire90-1588-layer_1-width_3
-Xwire90@5 net@275 load[F] wire90-1458_1-layer_1-width_3
-Xwire90@6 net@441 check[T] wire90-341_1-layer_1-width_3
-Xwire90@7 net@454 count[T] wire90-1283_3-layer_1-width_3
-.ENDS ilcOdd
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-349_2-R_34_667m a b
-Ccap@0 gnd net@14 1.28f
-Ccap@1 gnd net@8 1.28f
-Ccap@2 gnd net@11 1.28f
-Rres@0 net@14 a 2.018
-Rres@1 net@11 net@14 4.035
-Rres@2 b net@8 2.018
-Rres@3 net@8 net@11 4.035
-.ENDS wire-C_0_011f-349_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-349_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-349_2-R_34_667m
-.ENDS wire90-349_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-475_3-R_34_667m a b
-Ccap@0 gnd net@14 1.743f
-Ccap@1 gnd net@8 1.743f
-Ccap@2 gnd net@11 1.743f
-Rres@0 net@14 a 2.746
-Rres@1 net@11 net@14 5.492
-Rres@2 b net@8 2.746
-Rres@3 net@8 net@11 5.492
-.ENDS wire-C_0_011f-475_3-R_34_667m
+*** CELL: stageGroupsM:upDown8weak{sch}
+.SUBCKT upDown8weak ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1]
++ainD[2] ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[TT]
++ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] ainU[3] ainU[4]
++ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[TT] aoutD[10] aoutD[11]
++aoutD[12] aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5]
++aoutD[6] aoutD[7] aoutD[8] aoutD[9] aoutD[TT] aoutU[10] aoutU[11] aoutU[12]
++aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6]
++aoutU[7] aoutU[8] aoutU[9] aoutU[TT] inD[10] inD[11] inD[12] inD[13] inD[14]
++inD[15] inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22]
++inD[23] inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30]
++inD[31] inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5]
++inD[6] inD[7] inD[8] inD[9] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15]
++inU[16] inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23]
++inU[24] inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31]
++inU[32] inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6]
++inU[7] inU[8] inU[9] outD[10] outD[11] outD[12] outD[13] outD[14] outD[15]
++outD[16] outD[17] outD[18] outD[19] outD[1] outD[20] outD[21] outD[22]
++outD[23] outD[24] outD[25] outD[26] outD[27] outD[28] outD[29] outD[2]
++outD[30] outD[31] outD[32] outD[33] outD[34] outD[35] outD[36] outD[37]
++outD[3] outD[4] outD[5] outD[6] outD[7] outD[8] outD[9] outU[10] outU[11]
++outU[12] outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19]
++outU[1] outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26]
++outU[27] outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33]
++outU[34] outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7]
++outU[8] outU[9] predD predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sir[9] sor[1] succD succU
+XweakStag@18 ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2]
++ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[TT] net@189[41]
++net@189[40] net@189[39] net@189[38] net@189[37] net@189[50] net@189[49]
++net@189[48] net@189[47] net@189[46] net@189[45] net@189[44] net@189[43]
++net@189[42] net@189[51] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15]
++inU[16] inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23]
++inU[24] inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31]
++inU[32] inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6]
++inU[7] inU[8] inU[9] net@189[27] net@189[26] net@189[25] net@189[24]
++net@189[23] net@189[22] net@189[21] net@189[20] net@189[19] net@189[18]
++net@189[36] net@189[17] net@189[16] net@189[15] net@189[14] net@189[13]
++net@189[12] net@189[11] net@189[10] net@189[9] net@189[8] net@189[35]
++net@189[7] net@189[6] net@189[5] net@189[4] net@189[3] net@189[2] net@189[1]
++net@189[0] net@189[34] net@189[33] net@189[32] net@189[31] net@189[30]
++net@189[29] net@189[28] predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sir[9] net@117[8] net@28 weakStage
+XweakStag@19 net@189[41] net@189[40] net@189[39] net@189[38] net@189[37]
++net@189[50] net@189[49] net@189[48] net@189[47] net@189[46] net@189[45]
++net@189[44] net@189[43] net@189[42] net@189[51] net@190[41] net@190[40]
++net@190[39] net@190[38] net@190[37] net@190[50] net@190[49] net@190[48]
++net@190[47] net@190[46] net@190[45] net@190[44] net@190[43] net@190[42]
++net@190[51] net@189[27] net@189[26] net@189[25] net@189[24] net@189[23]
++net@189[22] net@189[21] net@189[20] net@189[19] net@189[18] net@189[36]
++net@189[17] net@189[16] net@189[15] net@189[14] net@189[13] net@189[12]
++net@189[11] net@189[10] net@189[9] net@189[8] net@189[35] net@189[7]
++net@189[6] net@189[5] net@189[4] net@189[3] net@189[2] net@189[1] net@189[0]
++net@189[34] net@189[33] net@189[32] net@189[31] net@189[30] net@189[29]
++net@189[28] net@190[27] net@190[26] net@190[25] net@190[24] net@190[23]
++net@190[22] net@190[21] net@190[20] net@190[19] net@190[18] net@190[36]
++net@190[17] net@190[16] net@190[15] net@190[14] net@190[13] net@190[12]
++net@190[11] net@190[10] net@190[9] net@190[8] net@190[35] net@190[7]
++net@190[6] net@190[5] net@190[4] net@190[3] net@190[2] net@190[1] net@190[0]
++net@190[34] net@190[33] net@190[32] net@190[31] net@190[30] net@190[29]
++net@190[28] net@46 net@120[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sir[9] net@123[8] net@62 weakStage
+XweakStag@20 net@190[41] net@190[40] net@190[39] net@190[38] net@190[37]
++net@190[50] net@190[49] net@190[48] net@190[47] net@190[46] net@190[45]
++net@190[44] net@190[43] net@190[42] net@190[51] net@191[41] net@191[40]
++net@191[39] net@191[38] net@191[37] net@191[50] net@191[49] net@191[48]
++net@191[47] net@191[46] net@191[45] net@191[44] net@191[43] net@191[42]
++net@191[51] net@190[27] net@190[26] net@190[25] net@190[24] net@190[23]
++net@190[22] net@190[21] net@190[20] net@190[19] net@190[18] net@190[36]
++net@190[17] net@190[16] net@190[15] net@190[14] net@190[13] net@190[12]
++net@190[11] net@190[10] net@190[9] net@190[8] net@190[35] net@190[7]
++net@190[6] net@190[5] net@190[4] net@190[3] net@190[2] net@190[1] net@190[0]
++net@190[34] net@190[33] net@190[32] net@190[31] net@190[30] net@190[29]
++net@190[28] net@191[27] net@191[26] net@191[25] net@191[24] net@191[23]
++net@191[22] net@191[21] net@191[20] net@191[19] net@191[18] net@191[36]
++net@191[17] net@191[16] net@191[15] net@191[14] net@191[13] net@191[12]
++net@191[11] net@191[10] net@191[9] net@191[8] net@191[35] net@191[7]
++net@191[6] net@191[5] net@191[4] net@191[3] net@191[2] net@191[1] net@191[0]
++net@191[34] net@191[33] net@191[32] net@191[31] net@191[30] net@191[29]
++net@191[28] net@63 net@126[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sir[9] net@129[8] net@64 weakStage
+XweakStag@21 net@191[41] net@191[40] net@191[39] net@191[38] net@191[37]
++net@191[50] net@191[49] net@191[48] net@191[47] net@191[46] net@191[45]
++net@191[44] net@191[43] net@191[42] net@191[51] aoutU[10] aoutU[11] aoutU[12]
++aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6]
++aoutU[7] aoutU[8] aoutU[9] aoutU[TT] net@191[27] net@191[26] net@191[25]
++net@191[24] net@191[23] net@191[22] net@191[21] net@191[20] net@191[19]
++net@191[18] net@191[36] net@191[17] net@191[16] net@191[15] net@191[14]
++net@191[13] net@191[12] net@191[11] net@191[10] net@191[9] net@191[8]
++net@191[35] net@191[7] net@191[6] net@191[5] net@191[4] net@191[3] net@191[2]
++net@191[1] net@191[0] net@191[34] net@191[33] net@191[32] net@191[31]
++net@191[30] net@191[29] net@191[28] outU[10] outU[11] outU[12] outU[13]
++outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] outU[1] outU[20]
++outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] outU[27] outU[28]
++outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] outU[34] outU[35]
++outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] outU[8] outU[9]
++net@65 net@132[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
++net@135[8] succU weakStage
+XweakStag@22 net@192[41] net@192[40] net@192[39] net@192[38] net@192[37]
++net@192[50] net@192[49] net@192[48] net@192[47] net@192[46] net@192[45]
++net@192[44] net@192[43] net@192[42] net@192[51] aoutD[10] aoutD[11] aoutD[12]
++aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5] aoutD[6]
++aoutD[7] aoutD[8] aoutD[9] aoutD[TT] net@192[27] net@192[26] net@192[25]
++net@192[24] net@192[23] net@192[22] net@192[21] net@192[20] net@192[19]
++net@192[18] net@192[36] net@192[17] net@192[16] net@192[15] net@192[14]
++net@192[13] net@192[12] net@192[11] net@192[10] net@192[9] net@192[8]
++net@192[35] net@192[7] net@192[6] net@192[5] net@192[4] net@192[3] net@192[2]
++net@192[1] net@192[0] net@192[34] net@192[33] net@192[32] net@192[31]
++net@192[30] net@192[29] net@192[28] outD[10] outD[11] outD[12] outD[13]
++outD[14] outD[15] outD[16] outD[17] outD[18] outD[19] outD[1] outD[20]
++outD[21] outD[22] outD[23] outD[24] outD[25] outD[26] outD[27] outD[28]
++outD[29] outD[2] outD[30] outD[31] outD[32] outD[33] outD[34] outD[35]
++outD[36] outD[37] outD[3] outD[4] outD[5] outD[6] outD[7] outD[8] outD[9]
++net@50 net@117[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
++net@120[8] succD weakStage
+XweakStag@23 net@193[41] net@193[40] net@193[39] net@193[38] net@193[37]
++net@193[50] net@193[49] net@193[48] net@193[47] net@193[46] net@193[45]
++net@193[44] net@193[43] net@193[42] net@193[51] net@192[41] net@192[40]
++net@192[39] net@192[38] net@192[37] net@192[50] net@192[49] net@192[48]
++net@192[47] net@192[46] net@192[45] net@192[44] net@192[43] net@192[42]
++net@192[51] net@193[27] net@193[26] net@193[25] net@193[24] net@193[23]
++net@193[22] net@193[21] net@193[20] net@193[19] net@193[18] net@193[36]
++net@193[17] net@193[16] net@193[15] net@193[14] net@193[13] net@193[12]
++net@193[11] net@193[10] net@193[9] net@193[8] net@193[35] net@193[7]
++net@193[6] net@193[5] net@193[4] net@193[3] net@193[2] net@193[1] net@193[0]
++net@193[34] net@193[33] net@193[32] net@193[31] net@193[30] net@193[29]
++net@193[28] net@192[27] net@192[26] net@192[25] net@192[24] net@192[23]
++net@192[22] net@192[21] net@192[20] net@192[19] net@192[18] net@192[36]
++net@192[17] net@192[16] net@192[15] net@192[14] net@192[13] net@192[12]
++net@192[11] net@192[10] net@192[9] net@192[8] net@192[35] net@192[7]
++net@192[6] net@192[5] net@192[4] net@192[3] net@192[2] net@192[1] net@192[0]
++net@192[34] net@192[33] net@192[32] net@192[31] net@192[30] net@192[29]
++net@192[28] net@44 net@123[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sir[9] net@126[8] net@51 weakStage
+XweakStag@24 net@194[41] net@194[40] net@194[39] net@194[38] net@194[37]
++net@194[50] net@194[49] net@194[48] net@194[47] net@194[46] net@194[45]
++net@194[44] net@194[43] net@194[42] net@194[51] net@193[41] net@193[40]
++net@193[39] net@193[38] net@193[37] net@193[50] net@193[49] net@193[48]
++net@193[47] net@193[46] net@193[45] net@193[44] net@193[43] net@193[42]
++net@193[51] net@194[27] net@194[26] net@194[25] net@194[24] net@194[23]
++net@194[22] net@194[21] net@194[20] net@194[19] net@194[18] net@194[36]
++net@194[17] net@194[16] net@194[15] net@194[14] net@194[13] net@194[12]
++net@194[11] net@194[10] net@194[9] net@194[8] net@194[35] net@194[7]
++net@194[6] net@194[5] net@194[4] net@194[3] net@194[2] net@194[1] net@194[0]
++net@194[34] net@194[33] net@194[32] net@194[31] net@194[30] net@194[29]
++net@194[28] net@193[27] net@193[26] net@193[25] net@193[24] net@193[23]
++net@193[22] net@193[21] net@193[20] net@193[19] net@193[18] net@193[36]
++net@193[17] net@193[16] net@193[15] net@193[14] net@193[13] net@193[12]
++net@193[11] net@193[10] net@193[9] net@193[8] net@193[35] net@193[7]
++net@193[6] net@193[5] net@193[4] net@193[3] net@193[2] net@193[1] net@193[0]
++net@193[34] net@193[33] net@193[32] net@193[31] net@193[30] net@193[29]
++net@193[28] net@52 net@129[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sir[9] net@132[8] net@43 weakStage
+XweakStag@25 ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] ainD[2]
++ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[TT] net@194[41]
++net@194[40] net@194[39] net@194[38] net@194[37] net@194[50] net@194[49]
++net@194[48] net@194[47] net@194[46] net@194[45] net@194[44] net@194[43]
++net@194[42] net@194[51] inD[10] inD[11] inD[12] inD[13] inD[14] inD[15]
++inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] inD[23]
++inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] inD[31]
++inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] inD[6]
++inD[7] inD[8] inD[9] net@194[27] net@194[26] net@194[25] net@194[24]
++net@194[23] net@194[22] net@194[21] net@194[20] net@194[19] net@194[18]
++net@194[36] net@194[17] net@194[16] net@194[15] net@194[14] net@194[13]
++net@194[12] net@194[11] net@194[10] net@194[9] net@194[8] net@194[35]
++net@194[7] net@194[6] net@194[5] net@194[4] net@194[3] net@194[2] net@194[1]
++net@194[0] net@194[34] net@194[33] net@194[32] net@194[31] net@194[30]
++net@194[29] net@194[28] predD net@135[8] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sir[9] sor[1] net@53 weakStage
+Xwire90@1 net@44 net@43 wire90-1243_9-layer_1-width_3
+Xwire90@2 net@28 net@46 wire90-1185_9-layer_1-width_3
+Xwire90@3 net@62 net@63 wire90-1185_9-layer_1-width_3
+Xwire90@4 net@64 net@65 wire90-1185_9-layer_1-width_3
+Xwire90@5 net@50 net@51 wire90-1249_9-layer_1-width_3
+Xwire90@6 net@52 net@53 wire90-1249_9-layer_1-width_3
+.ENDS upDown8weak
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-475_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-475_3-R_34_667m
-.ENDS wire90-475_3-layer_1-width_3
+*** CELL: stageGroupsM:northFifo{sch}
+.SUBCKT northFifo ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
++aout[7] aout[8] aout[9] aout[TT] fin fout in[10] in[11] in[12] in[13] in[14]
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24]
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34]
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
++sic[2] sic[3] sic[4] sic[5] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5]
++sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[8] sir[9]
++succ
+XfillDrai@1 net@256[41] net@256[40] net@256[39] net@256[38] net@256[37]
++net@256[50] net@256[49] net@256[48] net@256[47] net@256[46] net@256[45]
++net@256[44] net@256[43] net@256[42] net@256[51] net@259[41] net@259[40]
++net@259[39] net@259[38] net@259[37] net@259[50] net@259[49] net@259[48]
++net@259[47] net@259[46] net@259[45] net@259[44] net@259[43] net@259[42]
++net@259[51] fin fout net@256[27] net@256[26] net@256[25] net@256[24]
++net@256[23] net@256[22] net@256[21] net@256[20] net@256[19] net@256[18]
++net@256[36] net@256[17] net@256[16] net@256[15] net@256[14] net@256[13]
++net@256[12] net@256[11] net@256[10] net@256[9] net@256[8] net@256[35]
++net@256[7] net@256[6] net@256[5] net@256[4] net@256[3] net@256[2] net@256[1]
++net@256[0] net@256[34] net@256[33] net@256[32] net@256[31] net@256[30]
++net@256[29] net@256[28] net@259[27] net@259[26] net@259[25] net@259[24]
++net@259[23] net@259[22] net@259[21] net@259[20] net@259[19] net@259[18]
++net@259[36] net@259[17] net@259[16] net@259[15] net@259[14] net@259[13]
++net@259[12] net@259[11] net@259[10] net@259[9] net@259[8] net@259[35]
++net@259[7] net@259[6] net@259[5] net@259[4] net@259[3] net@259[2] net@259[1]
++net@259[0] net@259[34] net@259[33] net@259[32] net@259[31] net@259[30]
++net@259[29] net@259[28] net@263 sic[1] sic[2] sic[3] sic[4] sic[5] sic[3]
++sic[2] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8]
++sid[9] net@254[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] sir[9]
++sic[8] sid[8] sid[7] sid[6] net@235[5] net@235[4] sir[8] net@267
++fillDrainCount
+XscanCap@5 sid[8] sid[7] sid[6] net@235[5] net@235[4] sid[9] scanCap
+XscanCap@6 sic[8] sic[2] sic[3] sic[4] sic[5] sic[9] scanCap
+XscanCap@7 sir[8] sir[2] sir[3] sir[4] sir[5] sir[9] scanCap
+XupDown8w@2 net@259[41] net@259[40] net@259[39] net@259[38] net@259[37]
++net@259[50] net@259[49] net@259[48] net@259[47] net@259[46] net@259[45]
++net@259[44] net@259[43] net@259[42] net@259[51] ain[10] ain[11] ain[12]
++ain[13] ain[14] ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] ain[8]
++ain[9] ain[TT] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
++aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] net@256[41]
++net@256[40] net@256[39] net@256[38] net@256[37] net@256[50] net@256[49]
++net@256[48] net@256[47] net@256[46] net@256[45] net@256[44] net@256[43]
++net@256[42] net@256[51] net@259[27] net@259[26] net@259[25] net@259[24]
++net@259[23] net@259[22] net@259[21] net@259[20] net@259[19] net@259[18]
++net@259[36] net@259[17] net@259[16] net@259[15] net@259[14] net@259[13]
++net@259[12] net@259[11] net@259[10] net@259[9] net@259[8] net@259[35]
++net@259[7] net@259[6] net@259[5] net@259[4] net@259[3] net@259[2] net@259[1]
++net@259[0] net@259[34] net@259[33] net@259[32] net@259[31] net@259[30]
++net@259[29] net@259[28] in[10] in[11] in[12] in[13] in[14] in[15] in[16]
++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
++in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12]
++out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20]
++out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29]
++out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3]
++out[4] out[5] out[6] out[7] out[8] out[9] net@256[27] net@256[26] net@256[25]
++net@256[24] net@256[23] net@256[22] net@256[21] net@256[20] net@256[19]
++net@256[18] net@256[36] net@256[17] net@256[16] net@256[15] net@256[14]
++net@256[13] net@256[12] net@256[11] net@256[10] net@256[9] net@256[8]
++net@256[35] net@256[7] net@256[6] net@256[5] net@256[4] net@256[3] net@256[2]
++net@256[1] net@256[0] net@256[34] net@256[33] net@256[32] net@256[31]
++net@256[30] net@256[29] net@256[28] net@229 pred sir[1] sir[2] sir[3] sir[4]
++sir[5] sir[3] sir[2] sir[8] sir[9] net@254[8] succ net@264 upDown8weak
+Xwire90@6 net@229 net@267 wire90-1185_9-layer_1-width_3
+Xwire90@18 net@264 net@263 wire90-1185_9-layer_1-width_3
+.ENDS northFifo
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-422_8-R_34_667m a b
-Ccap@0 gnd net@14 1.55f
-Ccap@1 gnd net@8 1.55f
-Ccap@2 gnd net@11 1.55f
-Rres@0 net@14 a 2.443
-Rres@1 net@11 net@14 4.886
-Rres@2 b net@8 2.443
-Rres@3 net@8 net@11 4.886
-.ENDS wire-C_0_011f-422_8-R_34_667m
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_2 d g s
+MNMOSf@0 d g s gnd nch W='6*(1+ABN/sqrt(6*2))' L='2' DELVTO='AVT0N/sqrt(6*2)'
+.ENDS NMOSx-X_2
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-422_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-422_8-R_34_667m
-.ENDS wire90-422_8-layer_1-width_3
+*** CELL: redFive:pms2{sch}
+.SUBCKT pms2-X_2 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_4
+XPMOS@1 d g2 net@2 PMOSx-X_4
+.ENDS pms2-X_2
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-484_8-R_34_667m a b
-Ccap@0 gnd net@14 1.778f
-Ccap@1 gnd net@8 1.778f
-Ccap@2 gnd net@11 1.778f
-Rres@0 net@14 a 2.801
-Rres@1 net@11 net@14 5.602
-Rres@2 b net@8 2.801
-Rres@3 net@8 net@11 5.602
-.ENDS wire-C_0_011f-484_8-R_34_667m
+*** CELL: redFive:pms2_sy{sch}
+.SUBCKT pms2_sy-X_4 d g g2
+Xpms2@0 d g g2 pms2-X_2
+Xpms2@1 d g2 g pms2-X_2
+.ENDS pms2_sy-X_4
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-484_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-484_8-R_34_667m
-.ENDS wire90-484_8-layer_1-width_3
+*** CELL: redFive:nor2HT_sy{sch}
+.SUBCKT nor2HT_sy-X_4 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_2
+XNMOS@1 out ina gnd NMOSx-X_2
+Xpms2_sy@0 out ina inb pms2_sy-X_4
+.ENDS nor2HT_sy-X_4
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-407_8-R_34_667m a b
-Ccap@0 gnd net@14 1.495f
-Ccap@1 gnd net@8 1.495f
-Ccap@2 gnd net@11 1.495f
-Rres@0 net@14 a 2.356
-Rres@1 net@11 net@14 4.712
-Rres@2 b net@8 2.356
-Rres@3 net@8 net@11 4.712
-.ENDS wire-C_0_011f-407_8-R_34_667m
+*** CELL: redFive:nor2{sch}
+.SUBCKT nor2-X_5 ina inb out
+XNMOS@0 out ina gnd NMOSx-X_5
+XNMOS@1 out inb gnd NMOSx-X_5
+Xpms2@0 out ina inb pms2-X_5
+.ENDS nor2-X_5
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-407_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-407_8-R_34_667m
-.ENDS wire90-407_8-layer_1-width_3
+*** CELL: redFive:nor2n{sch}
+.SUBCKT nor2n-X_5 ina inb out
+Xnor2@0 ina inb out nor2-X_5
+.ENDS nor2n-X_5
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-999_1-R_34_667m a b
-Ccap@0 gnd net@14 3.663f
-Ccap@1 gnd net@8 3.663f
-Ccap@2 gnd net@11 3.663f
-Rres@0 net@14 a 5.773
-Rres@1 net@11 net@14 11.545
-Rres@2 b net@8 5.773
-Rres@3 net@8 net@11 11.545
-.ENDS wire-C_0_011f-999_1-R_34_667m
+.SUBCKT wire-C_0_011f-238_2-R_34_667m a b
+Ccap@0 gnd net@14 0.873f
+Ccap@1 gnd net@8 0.873f
+Ccap@2 gnd net@11 0.873f
+Rres@0 net@14 a 1.376
+Rres@1 net@11 net@14 2.753
+Rres@2 b net@8 1.376
+Rres@3 net@8 net@11 2.753
+.ENDS wire-C_0_011f-238_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-999_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-999_1-R_34_667m
-.ENDS wire90-999_1-layer_1-width_3
+.SUBCKT wire90-238_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-238_2-R_34_667m
+.ENDS wire90-238_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1276_9-R_34_667m a b
-Ccap@0 gnd net@14 4.682f
-Ccap@1 gnd net@8 4.682f
-Ccap@2 gnd net@11 4.682f
-Rres@0 net@14 a 7.378
-Rres@1 net@11 net@14 14.755
-Rres@2 b net@8 7.378
-Rres@3 net@8 net@11 14.755
-.ENDS wire-C_0_011f-1276_9-R_34_667m
+.SUBCKT wire-C_0_011f-520-R_34_667m a b
+Ccap@0 gnd net@14 1.907f
+Ccap@1 gnd net@8 1.907f
+Ccap@2 gnd net@11 1.907f
+Rres@0 net@14 a 3.004
+Rres@1 net@11 net@14 6.009
+Rres@2 b net@8 3.004
+Rres@3 net@8 net@11 6.009
+.ENDS wire-C_0_011f-520-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1276_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1276_9-R_34_667m
-.ENDS wire90-1276_9-layer_1-width_3
-
-*** CELL: loopCountM:ilc{sch}
-.SUBCKT ilc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8]
-+ilc[decLO] ilc[do] ilc[load] ilc[mo] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
-+inLO[6] inLO[8]
-Xcalculat@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4]
-+do[5] do[6] net@422 do[7] calculate
-XilcEven@0 bitt[2] bitt[4] bitt[6] bitt[8] do[2] do[4] do[6] ilc[decLO]
-+inLO[2] inLO[4] inLO[6] inLO[8] ilc[load] zero ilcEven
-XilcOdd@0 bitt[1] bitt[3] bitt[5] bitt[7] do[3] do[5] do[7] ilc[decLO]
-+inLO[1] inLO[3] inLO[5] ilc[load] zero ilcOdd
-Xnand2@0 bitt[8] do[7] ilc[mo] nand2-X_10
-Xnand3@0 bitt[8] bitt[7] zero ilc[do] nand3-X_6_667
-Xwire90@1 wire90@1_a do[2] wire90-349_2-layer_1-width_3
-Xwire90@2 wire90@2_a do[3] wire90-475_3-layer_1-width_3
-Xwire90@3 wire90@3_a do[4] wire90-422_8-layer_1-width_3
-Xwire90@4 wire90@4_a do[5] wire90-484_8-layer_1-width_3
-Xwire90@5 wire90@5_a do[6] wire90-407_8-layer_1-width_3
-Xwire90@6 wire90@6_a do[7] wire90-999_1-layer_1-width_3
-Xwire90@41 zero net@422 wire90-1276_9-layer_1-width_3
-.ENDS ilc
+.SUBCKT wire90-520-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-520-R_34_667m
+.ENDS wire90-520-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-243_6-R_34_667m a b
-Ccap@0 gnd net@14 0.893f
-Ccap@1 gnd net@8 0.893f
-Ccap@2 gnd net@11 0.893f
-Rres@0 net@14 a 1.407
-Rres@1 net@11 net@14 2.815
-Rres@2 b net@8 1.407
-Rres@3 net@8 net@11 2.815
-.ENDS wire-C_0_011f-243_6-R_34_667m
+.SUBCKT wire-C_0_011f-222_3-R_34_667m a b
+Ccap@0 gnd net@14 0.815f
+Ccap@1 gnd net@8 0.815f
+Ccap@2 gnd net@11 0.815f
+Rres@0 net@14 a 1.284
+Rres@1 net@11 net@14 2.569
+Rres@2 b net@8 1.284
+Rres@3 net@8 net@11 2.569
+.ENDS wire-C_0_011f-222_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-243_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-243_6-R_34_667m
-.ENDS wire90-243_6-layer_1-width_3
+.SUBCKT wire90-222_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-222_3-R_34_667m
+.ENDS wire90-222_3-layer_1-width_3
-*** CELL: driversL:predORdri20wMC{sch}
-.SUBCKT predORdri20wMC inA inB mc pred
-XNMOSx@0 pred inA gnd NMOSx-X_20
-XNMOSx@1 pred mc gnd NMOSx-X_4
-XNMOSx@2 pred inB gnd NMOSx-X_20
-XPMOSx@1 pred net@217 net@203 PMOSx-X_4
-XPMOSx@2 net@203 inB net@204 PMOSx-X_4
-XPMOSx@3 net@204 inA net@205 PMOSx-X_4
-XPMOSx@4 net@205 mc vdd PMOSx-X_4
-Xinv@0 pred net@145 inv-X_4
-Xwire90@0 net@217 net@145 wire90-243_6-layer_1-width_3
-.ENDS predORdri20wMC
+*** CELL: centersJ:ctrAND4in30{sch}
+.SUBCKT ctrAND4in30 inA inB inC inD out
+Xinv@1 net@3 out inv-X_30
+Xnand2@1 net@43 net@58 net@67 nand2-X_10
+Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4
+Xnor2n@0 inD inC net@64 nor2n-X_5
+Xwire90@0 net@64 net@43 wire90-238_2-layer_1-width_3
+Xwire90@1 net@67 net@3 wire90-520-layer_1-width_3
+Xwire90@2 net@61 net@58 wire90-222_3-layer_1-width_3
+.ENDS ctrAND4in30
*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_25 d g s
-MPMOSf@0 d g s vdd pch W='150*(1+ABP/sqrt(150*2))' L='2'
-+DELVTO='AVT0P/sqrt(150*2)'
-.ENDS PMOSx-X_25
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_50 d g s
-MNMOSf@0 d g s gnd nch W='150*(1+ABN/sqrt(150*2))' L='2'
-+DELVTO='AVT0N/sqrt(150*2)'
-.ENDS NMOSx-X_50
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_25 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_50
-XNMOS@1 net@0 g gnd NMOSx-X_50
-.ENDS nms2-X_25
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_25 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_25
-XPMOS@1 out inb vdd PMOSx-X_25
-Xnms2@0 out ina inb nms2-X_25
-.ENDS nand2-X_25
-
-*** CELL: arbiterM:half2inArb{sch}
-.SUBCKT half2inArb cross grant[B] inA req[B]
-XNMOSx@0 vdd req[B] grant[B] PMOSx-X_10
-XPMOSx@0 cross inA grant[B] NMOSx-X_10
-Xnor2n@0 inA req[B] cross nand2-X_25
-.ENDS half2inArb
+.SUBCKT PMOSx-X_3 d g s
+MPMOSf@0 d g s vdd pch W='18*(1+ABP/sqrt(18*2))' L='2'
++DELVTO='AVT0P/sqrt(18*2)'
+.ENDS PMOSx-X_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-830_7-R_34_667m a b
-Ccap@0 gnd net@14 3.046f
-Ccap@1 gnd net@8 3.046f
-Ccap@2 gnd net@11 3.046f
-Rres@0 net@14 a 4.8
-Rres@1 net@11 net@14 9.599
-Rres@2 b net@8 4.8
-Rres@3 net@8 net@11 9.599
-.ENDS wire-C_0_011f-830_7-R_34_667m
+*** CELL: redFive:pms3{sch}
+.SUBCKT pms3-X_1 d g g2 g3
+XPMOS@0 d g3 net@2 PMOSx-X_3
+XPMOS@1 net@2 g2 net@5 PMOSx-X_3
+XPMOS@2 net@5 g vdd PMOSx-X_3
+.ENDS pms3-X_1
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-162_4-R_34_667m a b
+Ccap@0 gnd net@14 0.595f
+Ccap@1 gnd net@8 0.595f
+Ccap@2 gnd net@11 0.595f
+Rres@0 net@14 a 0.938
+Rres@1 net@11 net@14 1.877
+Rres@2 b net@8 0.938
+Rres@3 net@8 net@11 1.877
+.ENDS wire-C_0_011f-162_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-830_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-830_7-R_34_667m
-.ENDS wire90-830_7-layer_1-width_3
+.SUBCKT wire90-162_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-162_4-R_34_667m
+.ENDS wire90-162_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-834_6-R_34_667m a b
-Ccap@0 gnd net@14 3.06f
-Ccap@1 gnd net@8 3.06f
-Ccap@2 gnd net@11 3.06f
-Rres@0 net@14 a 4.822
-Rres@1 net@11 net@14 9.644
-Rres@2 b net@8 4.822
-Rres@3 net@8 net@11 9.644
-.ENDS wire-C_0_011f-834_6-R_34_667m
+.SUBCKT wire-C_0_011f-228_5-R_34_667m a b
+Ccap@0 gnd net@14 0.838f
+Ccap@1 gnd net@8 0.838f
+Ccap@2 gnd net@11 0.838f
+Rres@0 net@14 a 1.32
+Rres@1 net@11 net@14 2.64
+Rres@2 b net@8 1.32
+Rres@3 net@8 net@11 2.64
+.ENDS wire-C_0_011f-228_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-834_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-834_6-R_34_667m
-.ENDS wire90-834_6-layer_1-width_3
+.SUBCKT wire90-228_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-228_5-R_34_667m
+.ENDS wire90-228_5-layer_1-width_3
-*** CELL: arbiterM:arbiter2{sch}
-.SUBCKT arbiter2 grant[A] grant[B] req[A] req[B]
-XhalfArb@2 net@12 grant[A] net@5 req[A] half2inArb
-XhalfArb@3 net@13 grant[B] net@8 req[B] half2inArb
-Xwire90@0 net@12 net@8 wire90-830_7-layer_1-width_3
-Xwire90@1 net@5 net@13 wire90-834_6-layer_1-width_3
-.ENDS arbiter2
+*** CELL: latchesK:rsLatchA{sch}
+.SUBCKT rsLatchA mc out outBar reset set
+XNMOSx@0 net@193 reset gnd NMOSx-X_10
+XNMOSx@1 net@188 mc gnd NMOSx-X_4
+XPMOSx@3 net@188 net@177 vdd PMOSx-X_10
+Xinv@0 net@193 outBar inv-X_10
+Xinv@1 set net@213 inv-X_4
+Xinv@2 outBar out inv-X_10
+Xnms2@0 net@188 outBar net@177 nms2-X_2
+Xpms3@0 net@193 mc outBar reset pms3-X_1
+Xwire90@0 net@213 net@177 wire90-162_4-layer_1-width_3
+Xwire90@1 net@188 net@193 wire90-228_5-layer_1-width_3
+.ENDS rsLatchA
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_40 d g s
-MNMOSf@0 d g s gnd nch W='120*(1+ABN/sqrt(120*2))' L='2'
-+DELVTO='AVT0N/sqrt(120*2)'
-.ENDS NMOSx-X_40
+*** CELL: driversL:sucORdri20{sch}
+.SUBCKT sucORdri20 inA inB succ
+XPMOSx@0 succ net@51 vdd PMOSx-X_20
+Xinv@0 succ net@71 inv-X_4
+Xnms2@0 succ net@73 net@51 nms2-X_2
+Xnor2_sy@0 inA inB net@67 nor2_sy-X_5
+Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3
+Xwire90@1 net@73 net@71 wire90-209-layer_1-width_3
+.ENDS sucORdri20
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_20 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_40
-XNMOS@1 net@0 g gnd NMOSx-X_40
-.ENDS nms2-X_20
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-468-R_34_667m a b
+Ccap@0 gnd net@14 1.716f
+Ccap@1 gnd net@8 1.716f
+Ccap@2 gnd net@11 1.716f
+Rres@0 net@14 a 2.704
+Rres@1 net@11 net@14 5.408
+Rres@2 b net@8 2.704
+Rres@3 net@8 net@11 5.408
+.ENDS wire-C_0_011f-468-R_34_667m
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_20 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_20
-XPMOS@1 out inb vdd PMOSx-X_20
-Xnms2@0 out ina inb nms2-X_20
-.ENDS nand2-X_20
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-468-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-468-R_34_667m
+.ENDS wire90-468-layer_1-width_3
-*** CELL: redFive:nand2n{sch}
-.SUBCKT nand2n-X_20 ina inb out
-Xnand2@0 ina inb out nand2-X_20
-.ENDS nand2n-X_20
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-347_9-R_34_667m a b
+Ccap@0 gnd net@14 1.276f
+Ccap@1 gnd net@8 1.276f
+Ccap@2 gnd net@11 1.276f
+Rres@0 net@14 a 2.01
+Rres@1 net@11 net@14 4.02
+Rres@2 b net@8 2.01
+Rres@3 net@8 net@11 4.02
+.ENDS wire-C_0_011f-347_9-R_34_667m
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_22 d g s
-MPMOSf@0 d g s vdd pch W='132*(1+ABP/sqrt(132*2))' L='2'
-+DELVTO='AVT0P/sqrt(132*2)'
-.ENDS PMOSx-X_22
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-347_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-347_9-R_34_667m
+.ENDS wire90-347_9-layer_1-width_3
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_66 d g s
-MNMOSf@0 d g s gnd nch W='198*(1+ABN/sqrt(198*2))' L='2'
-+DELVTO='AVT0N/sqrt(198*2)'
-.ENDS NMOSx-X_66
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-450_6-R_34_667m a b
+Ccap@0 gnd net@14 1.652f
+Ccap@1 gnd net@8 1.652f
+Ccap@2 gnd net@11 1.652f
+Rres@0 net@14 a 2.603
+Rres@1 net@11 net@14 5.207
+Rres@2 b net@8 2.603
+Rres@3 net@8 net@11 5.207
+.ENDS wire-C_0_011f-450_6-R_34_667m
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_22 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_66
-XNMOS@1 net@7 g gnd NMOSx-X_66
-XNMOS@2 net@6 g2 net@7 NMOSx-X_66
-.ENDS nms3-X_22
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-450_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-450_6-R_34_667m
+.ENDS wire90-450_6-layer_1-width_3
-*** CELL: redFive:nand3{sch}
-.SUBCKT nand3-X_22 ina inb inc out
-XPMOS@0 out inc vdd PMOSx-X_22
-XPMOS@1 out inb vdd PMOSx-X_22
-XPMOS@2 out ina vdd PMOSx-X_22
-Xnms3@0 out ina inb inc nms3-X_22
-.ENDS nand3-X_22
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-603_6-R_34_667m a b
+Ccap@0 gnd net@14 2.213f
+Ccap@1 gnd net@8 2.213f
+Ccap@2 gnd net@11 2.213f
+Rres@0 net@14 a 3.487
+Rres@1 net@11 net@14 6.975
+Rres@2 b net@8 3.487
+Rres@3 net@8 net@11 6.975
+.ENDS wire-C_0_011f-603_6-R_34_667m
-*** CELL: gates3inM:nand3in44s{sch}
-.SUBCKT nand3in44s inA inB inC out
-Xnand3@0 inA inB inC out nand3-X_22
-Xnand3@1 inB inA inC out nand3-X_22
-.ENDS nand3in44s
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-603_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-603_6-R_34_667m
+.ENDS wire90-603_6-layer_1-width_3
-*** CELL: redFive:pms2_sy{sch}
-.SUBCKT pms2_sy-X_20 d g g2
-Xpms2@0 d g g2 pms2-X_10
-Xpms2@1 d g2 g pms2-X_10
-.ENDS pms2_sy-X_20
+*** CELL: gaspM:anAltEnd{sch}
+.SUBCKT anAltEnd fire[A] fire[B] mc predA predB s[1] s[2] s[3] succ
+XctrAND4i@2 net@1013 succ net@1133 fire[B] fire[A] ctrAND4in30
+XctrAND4i@3 net@1007 succ fire[A] net@1155 fire[B] ctrAND4in30
+Xinv@3 net@822 s[1] inv-X_10
+Xinv@4 net@824 s[3] inv-X_10
+Xinv@5 predA net@822 inv-X_5
+Xinv@6 predB net@824 inv-X_5
+Xinv@7 net@1133 s[2] inv-X_10
+XpredDri2@0 fire[A] mc predA predDri20wMC
+XpredDri2@1 fire[B] mc predB predDri20wMC
+XrsLatchA@1 mc net@1040 net@1082 fire[B] fire[A] rsLatchA
+XsucORdri@0 fire[A] fire[B] succ sucORdri20
+Xwire90@34 net@824 net@1007 wire90-468-layer_1-width_3
+Xwire90@35 net@822 net@1013 wire90-347_9-layer_1-width_3
+Xwire90@36 net@1155 net@1082 wire90-450_6-layer_1-width_3
+Xwire90@37 net@1133 net@1040 wire90-603_6-layer_1-width_3
+.ENDS anAltEnd
-*** CELL: redFive:nor2_sy{sch}
-.SUBCKT nor2_sy-X_20 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_20
-XNMOS@1 out ina gnd NMOSx-X_20
-Xpms2_sy@0 out ina inb pms2_sy-X_20
-.ENDS nor2_sy-X_20
+*** CELL: latchesK:latch2in20A{sch}
+.SUBCKT latch2in20A hcl[A] hcl[B] inA[1] inB[1] out[1]
+Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@36 raw2inLatchF
+XinvLT@1 net@16 out[1] inv-X_20
+Xwire90@1 net@36 net@16 wire90-242_1-layer_1-width_3
+.ENDS latch2in20A
-*** CELL: redFive:nor2{sch}
-.SUBCKT nor2-X_5 ina inb out
-XNMOS@0 out ina gnd NMOSx-X_5
-XNMOS@1 out inb gnd NMOSx-X_5
-Xpms2@0 out ina inb pms2-X_5
-.ENDS nor2-X_5
+*** CELL: registersM:ins2in20Ax18{sch}
+.SUBCKT ins2in20Ax18 hcl[A] hcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
++inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6]
++inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16]
++inB[17] inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
++inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
++out[18] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
+Xlx[1] hcl[A] hcl[B] inA[1] inB[1] out[1] latch2in20A
+Xlx[2] hcl[A] hcl[B] inA[2] inB[2] out[2] latch2in20A
+Xlx[3] hcl[A] hcl[B] inA[3] inB[3] out[3] latch2in20A
+Xlx[4] hcl[A] hcl[B] inA[4] inB[4] out[4] latch2in20A
+Xlx[5] hcl[A] hcl[B] inA[5] inB[5] out[5] latch2in20A
+Xlx[6] hcl[A] hcl[B] inA[6] inB[6] out[6] latch2in20A
+Xlx[7] hcl[A] hcl[B] inA[7] inB[7] out[7] latch2in20A
+Xlx[8] hcl[A] hcl[B] inA[8] inB[8] out[8] latch2in20A
+Xlx[9] hcl[A] hcl[B] inA[9] inB[9] out[9] latch2in20A
+Xlx[10] hcl[A] hcl[B] inA[10] inB[10] out[10] latch2in20A
+Xlx[11] hcl[A] hcl[B] inA[11] inB[11] out[11] latch2in20A
+Xlx[12] hcl[A] hcl[B] inA[12] inB[12] out[12] latch2in20A
+Xlx[13] hcl[A] hcl[B] inA[13] inB[13] out[13] latch2in20A
+Xlx[14] hcl[A] hcl[B] inA[14] inB[14] out[14] latch2in20A
+Xlx[15] hcl[A] hcl[B] inA[15] inB[15] out[15] latch2in20A
+Xlx[16] hcl[A] hcl[B] inA[16] inB[16] out[16] latch2in20A
+Xlx[17] hcl[A] hcl[B] inA[17] inB[17] out[17] latch2in20A
+Xlx[18] hcl[A] hcl[B] inA[18] inB[18] out[18] latch2in20A
+.ENDS ins2in20Ax18
+
+*** CELL: registersM:ins2in20Ax36{sch}
+.SUBCKT ins2in20Ax36 hcl[A] hcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
++inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22]
++inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30]
++inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6]
++inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16]
++inB[17] inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24]
++inB[25] inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32]
++inB[33] inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
++inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
++out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25]
++out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33]
++out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
+Xins2in20@2 net@178 net@162 inA[28] inA[29] inA[30] inA[31] inA[32] inA[33]
++inA[34] inA[35] inA[36] inA[19] inA[20] inA[21] inA[22] inA[23] inA[24]
++inA[25] inA[26] inA[27] inB[28] inB[29] inB[30] inB[31] inB[32] inB[33]
++inB[34] inB[35] inB[36] inB[19] inB[20] inB[21] inB[22] inB[23] inB[24]
++inB[25] inB[26] inB[27] out[28] out[29] out[30] out[31] out[32] out[33]
++out[34] out[35] out[36] out[19] out[20] out[21] out[22] out[23] out[24]
++out[25] out[26] out[27] ins2in20Ax18
+Xins2in20@3 net@157 net@177 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
++inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inA[7]
++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
++inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
++out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax18
+Xwire90@0 net@178 hcl[A] wire90-2550-layer_1-width_3
+Xwire90@1 hcl[A] net@157 wire90-2550-layer_1-width_3
+Xwire90@2 net@162 hcl[B] wire90-2550-layer_1-width_3
+Xwire90@3 hcl[B] net@177 wire90-2550-layer_1-width_3
+.ENDS ins2in20Ax36
-*** CELL: redFive:nor2n{sch}
-.SUBCKT nor2n-X_5 ina inb out
-Xnor2@0 ina inb out nor2-X_5
-.ENDS nor2n-X_5
+*** CELL: scanM:scanEx3{sch}
+.SUBCKT scanEx3 dIn[1] dIn[2] dIn[3] mc sir[1] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sor[1]
+XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanM__scanCellE
+XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanM__scanCellE
+XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sor[1] scanM__scanCellE
+Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
+Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3
+.ENDS scanEx3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-321_9-R_34_667m a b
-Ccap@0 gnd net@14 1.18f
-Ccap@1 gnd net@8 1.18f
-Ccap@2 gnd net@11 1.18f
-Rres@0 net@14 a 1.86
-Rres@1 net@11 net@14 3.72
-Rres@2 b net@8 1.86
-Rres@3 net@8 net@11 3.72
-.ENDS wire-C_0_011f-321_9-R_34_667m
+.SUBCKT wire-C_0_011f-1336_2-R_34_667m a b
+Ccap@0 gnd net@14 4.899f
+Ccap@1 gnd net@8 4.899f
+Ccap@2 gnd net@11 4.899f
+Rres@0 net@14 a 7.72
+Rres@1 net@11 net@14 15.441
+Rres@2 b net@8 7.72
+Rres@3 net@8 net@11 15.441
+.ENDS wire-C_0_011f-1336_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-321_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-321_9-R_34_667m
-.ENDS wire90-321_9-layer_1-width_3
+.SUBCKT wire90-1336_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1336_2-R_34_667m
+.ENDS wire90-1336_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-294-R_34_667m a b
-Ccap@0 gnd net@14 1.078f
-Ccap@1 gnd net@8 1.078f
-Ccap@2 gnd net@11 1.078f
-Rres@0 net@14 a 1.699
-Rres@1 net@11 net@14 3.397
-Rres@2 b net@8 1.699
-Rres@3 net@8 net@11 3.397
-.ENDS wire-C_0_011f-294-R_34_667m
+.SUBCKT wire-C_0_011f-1307-R_34_667m a b
+Ccap@0 gnd net@14 4.792f
+Ccap@1 gnd net@8 4.792f
+Ccap@2 gnd net@11 4.792f
+Rres@0 net@14 a 7.552
+Rres@1 net@11 net@14 15.103
+Rres@2 b net@8 7.552
+Rres@3 net@8 net@11 15.103
+.ENDS wire-C_0_011f-1307-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-294-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-294-R_34_667m
-.ENDS wire90-294-layer_1-width_3
+.SUBCKT wire90-1307-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1307-R_34_667m
+.ENDS wire90-1307-layer_1-width_3
+
+*** CELL: stagesM:altEndDockStage{sch}
+.SUBCKT altEndDockStage inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
++inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23]
++inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31]
++inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7]
++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
++inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
++inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33]
++inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26]
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34]
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] predA predB
++sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ
+XanAltEnd@1 fire[A] fire[B] sir[9] predA predB s[1] s[2] s[3] succ anAltEnd
+Xins2in20@0 take[A] take[B] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
++inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23]
++inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31]
++inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7]
++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
++inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
++inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33]
++inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26]
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34]
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax36
+XlatchDri@0 net@3 net@27 latchDriver60
+XlatchDri@1 net@7 net@23 latchDriver60
+XscanEx3@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sor[1] scanEx3
+Xwire90@0 net@7 fire[B] wire90-1336_2-layer_1-width_3
+Xwire90@1 net@3 fire[A] wire90-1307-layer_1-width_3
+Xwire90@2 net@23 take[B] wire90-1336_2-layer_1-width_3
+Xwire90@3 net@27 take[A] wire90-1307-layer_1-width_3
+.ENDS altEndDockStage
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-572_3-R_34_667m a b
-Ccap@0 gnd net@14 2.098f
-Ccap@1 gnd net@8 2.098f
-Ccap@2 gnd net@11 2.098f
-Rres@0 net@14 a 3.307
-Rres@1 net@11 net@14 6.613
-Rres@2 b net@8 3.307
-Rres@3 net@8 net@11 6.613
-.ENDS wire-C_0_011f-572_3-R_34_667m
+.SUBCKT wire-C_0_011f-237_2-R_34_667m a b
+Ccap@0 gnd net@14 0.87f
+Ccap@1 gnd net@8 0.87f
+Ccap@2 gnd net@11 0.87f
+Rres@0 net@14 a 1.37
+Rres@1 net@11 net@14 2.741
+Rres@2 b net@8 1.37
+Rres@3 net@8 net@11 2.741
+.ENDS wire-C_0_011f-237_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-572_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-572_3-R_34_667m
-.ENDS wire90-572_3-layer_1-width_3
+.SUBCKT wire90-237_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-237_2-R_34_667m
+.ENDS wire90-237_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-741_5-R_34_667m a b
-Ccap@0 gnd net@14 2.719f
-Ccap@1 gnd net@8 2.719f
-Ccap@2 gnd net@11 2.719f
-Rres@0 net@14 a 4.284
-Rres@1 net@11 net@14 8.568
-Rres@2 b net@8 4.284
-Rres@3 net@8 net@11 8.568
-.ENDS wire-C_0_011f-741_5-R_34_667m
+.SUBCKT wire-C_0_011f-221_8-R_34_667m a b
+Ccap@0 gnd net@14 0.813f
+Ccap@1 gnd net@8 0.813f
+Ccap@2 gnd net@11 0.813f
+Rres@0 net@14 a 1.282
+Rres@1 net@11 net@14 2.563
+Rres@2 b net@8 1.282
+Rres@3 net@8 net@11 2.563
+.ENDS wire-C_0_011f-221_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-741_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-741_5-R_34_667m
-.ENDS wire90-741_5-layer_1-width_3
+.SUBCKT wire90-221_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-221_8-R_34_667m
+.ENDS wire90-221_8-layer_1-width_3
+
+*** CELL: centersJ:ctrAND4in30M{sch}
+.SUBCKT ctrAND4in30M inA inB inC inD out outM
+Xinv@1 outM out inv-X_30
+Xnand2@1 net@43 net@58 outM nand2-X_10
+Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4
+Xnor2n@0 inD inC net@64 nor2n-X_5
+Xwire90@0 net@64 net@43 wire90-237_2-layer_1-width_3
+Xwire90@2 net@61 net@58 wire90-221_8-layer_1-width_3
+.ENDS ctrAND4in30M
+
+*** CELL: redFive:nms2_sy{sch}
+.SUBCKT nms2_sy-X_10 d g g2
+Xnms2@0 d g g2 nms2-X_5
+Xnms2@1 d g2 g nms2-X_5
+.ENDS nms2_sy-X_10
+
+*** CELL: redFive:nand2_sy{sch}
+.SUBCKT nand2_sy-X_10 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_10
+XPMOS@1 out ina vdd PMOSx-X_10
+Xnms2_sy@0 out ina inb nms2_sy-X_10
+.ENDS nand2_sy-X_10
+
+*** CELL: redFive:nand2n_sy{sch}
+.SUBCKT nand2n_sy-X_10 ina inb out
+Xnand2_sy@0 ina inb out nand2_sy-X_10
+.ENDS nand2n_sy-X_10
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-783-R_34_667m a b
-Ccap@0 gnd net@14 2.871f
-Ccap@1 gnd net@8 2.871f
-Ccap@2 gnd net@11 2.871f
-Rres@0 net@14 a 4.524
-Rres@1 net@11 net@14 9.048
-Rres@2 b net@8 4.524
-Rres@3 net@8 net@11 9.048
-.ENDS wire-C_0_011f-783-R_34_667m
+.SUBCKT wire-C_0_011f-700-R_34_667m a b
+Ccap@0 gnd net@14 2.567f
+Ccap@1 gnd net@8 2.567f
+Ccap@2 gnd net@11 2.567f
+Rres@0 net@14 a 4.044
+Rres@1 net@11 net@14 8.089
+Rres@2 b net@8 4.044
+Rres@3 net@8 net@11 8.089
+.ENDS wire-C_0_011f-700-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-783-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-783-R_34_667m
-.ENDS wire90-783-layer_1-width_3
+.SUBCKT wire90-700-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-700-R_34_667m
+.ENDS wire90-700-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1254_1-R_34_667m a b
-Ccap@0 gnd net@14 4.598f
-Ccap@1 gnd net@8 4.598f
-Ccap@2 gnd net@11 4.598f
-Rres@0 net@14 a 7.246
-Rres@1 net@11 net@14 14.492
-Rres@2 b net@8 7.246
-Rres@3 net@8 net@11 14.492
-.ENDS wire-C_0_011f-1254_1-R_34_667m
+.SUBCKT wire-C_0_011f-839_6-R_34_667m a b
+Ccap@0 gnd net@14 3.079f
+Ccap@1 gnd net@8 3.079f
+Ccap@2 gnd net@11 3.079f
+Rres@0 net@14 a 4.851
+Rres@1 net@11 net@14 9.702
+Rres@2 b net@8 4.851
+Rres@3 net@8 net@11 9.702
+.ENDS wire-C_0_011f-839_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1254_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1254_1-R_34_667m
-.ENDS wire90-1254_1-layer_1-width_3
+.SUBCKT wire90-839_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-839_6-R_34_667m
+.ENDS wire90-839_6-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1300_1-R_34_667m a b
-Ccap@0 gnd net@14 4.767f
-Ccap@1 gnd net@8 4.767f
-Ccap@2 gnd net@11 4.767f
-Rres@0 net@14 a 7.512
-Rres@1 net@11 net@14 15.023
-Rres@2 b net@8 7.512
-Rres@3 net@8 net@11 15.023
-.ENDS wire-C_0_011f-1300_1-R_34_667m
+.SUBCKT wire-C_0_011f-438_2-R_34_667m a b
+Ccap@0 gnd net@14 1.607f
+Ccap@1 gnd net@8 1.607f
+Ccap@2 gnd net@11 1.607f
+Rres@0 net@14 a 2.532
+Rres@1 net@11 net@14 5.064
+Rres@2 b net@8 2.532
+Rres@3 net@8 net@11 5.064
+.ENDS wire-C_0_011f-438_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1300_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1300_1-R_34_667m
-.ENDS wire90-1300_1-layer_1-width_3
+.SUBCKT wire90-438_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-438_2-R_34_667m
+.ENDS wire90-438_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-392_9-R_34_667m a b
-Ccap@0 gnd net@14 1.441f
-Ccap@1 gnd net@8 1.441f
-Ccap@2 gnd net@11 1.441f
-Rres@0 net@14 a 2.27
-Rres@1 net@11 net@14 4.54
-Rres@2 b net@8 2.27
-Rres@3 net@8 net@11 4.54
-.ENDS wire-C_0_011f-392_9-R_34_667m
+.SUBCKT wire-C_0_011f-257_4-R_34_667m a b
+Ccap@0 gnd net@14 0.944f
+Ccap@1 gnd net@8 0.944f
+Ccap@2 gnd net@11 0.944f
+Rres@0 net@14 a 1.487
+Rres@1 net@11 net@14 2.974
+Rres@2 b net@8 1.487
+Rres@3 net@8 net@11 2.974
+.ENDS wire-C_0_011f-257_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-392_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-392_9-R_34_667m
-.ENDS wire90-392_9-layer_1-width_3
+.SUBCKT wire90-257_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-257_4-R_34_667m
+.ENDS wire90-257_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-174_7-R_34_667m a b
-Ccap@0 gnd net@14 0.641f
-Ccap@1 gnd net@8 0.641f
-Ccap@2 gnd net@11 0.641f
-Rres@0 net@14 a 1.009
-Rres@1 net@11 net@14 2.019
-Rres@2 b net@8 1.009
-Rres@3 net@8 net@11 2.019
-.ENDS wire-C_0_011f-174_7-R_34_667m
+.SUBCKT wire-C_0_011f-458_8-R_34_667m a b
+Ccap@0 gnd net@14 1.682f
+Ccap@1 gnd net@8 1.682f
+Ccap@2 gnd net@11 1.682f
+Rres@0 net@14 a 2.651
+Rres@1 net@11 net@14 5.302
+Rres@2 b net@8 2.651
+Rres@3 net@8 net@11 5.302
+.ENDS wire-C_0_011f-458_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-174_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-174_7-R_34_667m
-.ENDS wire90-174_7-layer_1-width_3
+.SUBCKT wire90-458_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-458_8-R_34_667m
+.ENDS wire90-458_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1154_9-R_34_667m a b
-Ccap@0 gnd net@14 4.235f
-Ccap@1 gnd net@8 4.235f
-Ccap@2 gnd net@11 4.235f
-Rres@0 net@14 a 6.673
-Rres@1 net@11 net@14 13.346
-Rres@2 b net@8 6.673
-Rres@3 net@8 net@11 13.346
-.ENDS wire-C_0_011f-1154_9-R_34_667m
+.SUBCKT wire-C_0_011f-744_5-R_34_667m a b
+Ccap@0 gnd net@14 2.73f
+Ccap@1 gnd net@8 2.73f
+Ccap@2 gnd net@11 2.73f
+Rres@0 net@14 a 4.302
+Rres@1 net@11 net@14 8.603
+Rres@2 b net@8 4.302
+Rres@3 net@8 net@11 8.603
+.ENDS wire-C_0_011f-744_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1154_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1154_9-R_34_667m
-.ENDS wire90-1154_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-590_5-R_34_667m a b
-Ccap@0 gnd net@14 2.165f
-Ccap@1 gnd net@8 2.165f
-Ccap@2 gnd net@11 2.165f
-Rres@0 net@14 a 3.412
-Rres@1 net@11 net@14 6.824
-Rres@2 b net@8 3.412
-Rres@3 net@8 net@11 6.824
-.ENDS wire-C_0_011f-590_5-R_34_667m
+.SUBCKT wire90-744_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-744_5-R_34_667m
+.ENDS wire90-744_5-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-590_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-590_5-R_34_667m
-.ENDS wire90-590_5-layer_1-width_3
+*** CELL: gaspL:anAltStart{sch}
+.SUBCKT anAltStart fire[A] fire[B] mc pred s[1] s[2] succA succB
+XctrAND4i@1 net@634 succA fire[B] net@912 fire[A] net@866 ctrAND4in30M
+XctrAND4i@3 net@634 succB net@909 fire[A] fire[B] net@885 ctrAND4in30M
+Xinv@3 net@634 s[1] inv-X_10
+Xinv@4 pred net@787 inv-X_10
+Xinv@5 net@912 s[2] inv-X_10
+Xnand2n_s@0 net@143 net@410 net@422 nand2n_sy-X_10
+XpredDri2@0 net@815 mc pred predDri20wMC
+XrsLatchA@1 mc net@905 net@911 fire[B] fire[A] rsLatchA
+XsucDri20@0 fire[A] succA sucDri20
+XsucDri20@1 fire[B] succB sucDri20
+Xwire90@16 net@410 net@866 wire90-700-layer_1-width_3
+Xwire90@17 net@143 net@885 wire90-839_6-layer_1-width_3
+Xwire90@19 net@912 net@905 wire90-438_2-layer_1-width_3
+Xwire90@20 net@815 net@422 wire90-257_4-layer_1-width_3
+Xwire90@27 net@909 net@911 wire90-458_8-layer_1-width_3
+Xwire90@28 net@787 net@634 wire90-744_5-layer_1-width_3
+.ENDS anAltStart
-*** CELL: moveM:races{sch}
-.SUBCKT races bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] in[D] in[T] succ torp
-+winHI[M] winLO[M]
-Xarbiter2@0 net@131 net@128 torp in[D] arbiter2
-Xarbiter2@1 net@130 net@129 torp in[T] arbiter2
-XinvI@0 net@150 fire[T] inv-X_20
-Xnand2@0 bit[Di] do[Tp] net@35 nand2-X_10
-Xnand2@1 bit[Ti] do[Tp] net@42 nand2-X_10
-Xnand2@2 net@94 do[Mv] net@86 nand2-X_5
-Xnand2@3 winLO[M] winLO[M] winHI[M] nand2-X_5
-Xnand2n@0 bit[Di] net@11 net@57 nand2n-X_20
-Xnand2n@1 bit[Ti] net@53 net@60 nand2n-X_20
-Xnand3in4@0 net@159 net@123 net@98 winLO[M] nand3in44s
-Xnor2_sy@0 net@48 net@45 net@151 nor2_sy-X_20
-Xnor2n@0 net@39 net@12 net@44 nor2n-X_20
-Xnor2n@1 net@36 net@32 net@43 nor2n-X_20
-Xnor2n@2 succ net@153 net@152 nor2n-X_20
-Xnor2n@3 net@171 net@171 net@176 nor2n-X_5
-Xwire90@0 net@131 net@12 wire90-321_9-layer_1-width_3
-Xwire90@1 net@130 net@32 wire90-321_9-layer_1-width_3
-Xwire90@2 net@129 net@53 wire90-294-layer_1-width_3
-Xwire90@3 net@128 net@11 wire90-294-layer_1-width_3
-Xwire90@4 net@35 net@39 wire90-572_3-layer_1-width_3
-Xwire90@5 net@42 net@36 wire90-572_3-layer_1-width_3
-Xwire90@6 net@44 net@45 wire90-741_5-layer_1-width_3
-Xwire90@7 net@43 net@48 wire90-783-layer_1-width_3
-Xwire90@8 net@60 net@123 wire90-1254_1-layer_1-width_3
-Xwire90@9 net@57 net@159 wire90-1300_1-layer_1-width_3
-Xwire90@11 net@86 net@153 wire90-392_9-layer_1-width_3
-Xwire90@12 net@94 net@176 wire90-174_7-layer_1-width_3
-Xwire90@13 net@152 net@98 wire90-1154_9-layer_1-width_3
-Xwire90@15 net@151 net@150 wire90-590_5-layer_1-width_3
-Xwire90@17 net@171 winHI[M] wire90-174_7-layer_1-width_3
-.ENDS races
+*** CELL: registersM:ins1in20Bx36{sch}
+.SUBCKT ins1in20Bx36 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16]
++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
++in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5]
++out[6] out[7] out[8] out[9]
+Xins1in20@0 net@13 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
++out[4] out[5] out[6] out[7] out[8] out[9] ins1in20Bx18
+Xins1in20@1 net@11 in[28] in[29] in[30] in[31] in[32] in[33] in[34] in[35]
++in[36] in[19] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] out[28]
++out[29] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[19]
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] ins1in20Bx18
+Xwire90@0 hcl[1] net@13 wire90-2550-layer_1-width_3
+Xwire90@1 hcl[1] net@11 wire90-2550-layer_1-width_3
+.ENDS ins1in20Bx36
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-362_9-R_34_667m a b
-Ccap@0 gnd net@14 1.331f
-Ccap@1 gnd net@8 1.331f
-Ccap@2 gnd net@11 1.331f
-Rres@0 net@14 a 2.097
-Rres@1 net@11 net@14 4.194
-Rres@2 b net@8 2.097
-Rres@3 net@8 net@11 4.194
-.ENDS wire-C_0_011f-362_9-R_34_667m
+.SUBCKT wire-C_0_011f-1300-R_34_667m a b
+Ccap@0 gnd net@14 4.767f
+Ccap@1 gnd net@8 4.767f
+Ccap@2 gnd net@11 4.767f
+Rres@0 net@14 a 7.511
+Rres@1 net@11 net@14 15.022
+Rres@2 b net@8 7.511
+Rres@3 net@8 net@11 15.022
+.ENDS wire-C_0_011f-1300-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-362_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-362_9-R_34_667m
-.ENDS wire90-362_9-layer_1-width_3
+.SUBCKT wire90-1300-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1300-R_34_667m
+.ENDS wire90-1300-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-602_7-R_34_667m a b
-Ccap@0 gnd net@14 2.21f
-Ccap@1 gnd net@8 2.21f
-Ccap@2 gnd net@11 2.21f
-Rres@0 net@14 a 3.482
-Rres@1 net@11 net@14 6.965
-Rres@2 b net@8 3.482
-Rres@3 net@8 net@11 6.965
-.ENDS wire-C_0_011f-602_7-R_34_667m
+.SUBCKT wire-C_0_011f-1301_9-R_34_667m a b
+Ccap@0 gnd net@14 4.774f
+Ccap@1 gnd net@8 4.774f
+Ccap@2 gnd net@11 4.774f
+Rres@0 net@14 a 7.522
+Rres@1 net@11 net@14 15.044
+Rres@2 b net@8 7.522
+Rres@3 net@8 net@11 15.044
+.ENDS wire-C_0_011f-1301_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-602_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-602_7-R_34_667m
-.ENDS wire90-602_7-layer_1-width_3
+.SUBCKT wire90-1301_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1301_9-R_34_667m
+.ENDS wire90-1301_9-layer_1-width_3
+
+*** CELL: stagesM:altStartDockStage{sch}
+.SUBCKT altStartDockStage in[10] in[11] in[12] in[13] in[14] in[15] in[16]
++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
++in[3] in[4] in[5] in[6] in[7] in[8] in[9] outA[10] outA[11] outA[12] outA[13]
++outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20]
++outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28]
++outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35]
++outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] outB[10]
++outB[11] outB[12] outB[13] outB[14] outB[15] outB[16] outB[17] outB[18]
++outB[19] outB[1] outB[20] outB[21] outB[22] outB[23] outB[24] outB[25]
++outB[26] outB[27] outB[28] outB[29] outB[2] outB[30] outB[31] outB[32]
++outB[33] outB[34] outB[35] outB[36] outB[3] outB[4] outB[5] outB[6] outB[7]
++outB[8] outB[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
++sir[9] sor[1] succA succB
+XanAltSta@0 fire[A] fire[B] sir[9] pred net@48[1] net@48[0] succA succB
++anAltStart
+Xins1in20@0 net@23 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
++in[4] in[5] in[6] in[7] in[8] in[9] outA[10] outA[11] outA[12] outA[13]
++outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20]
++outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28]
++outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35]
++outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] ins1in20Bx36
+Xins1in20@1 net@25 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
++in[4] in[5] in[6] in[7] in[8] in[9] outB[10] outB[11] outB[12] outB[13]
++outB[14] outB[15] outB[16] outB[17] outB[18] outB[19] outB[1] outB[20]
++outB[21] outB[22] outB[23] outB[24] outB[25] outB[26] outB[27] outB[28]
++outB[29] outB[2] outB[30] outB[31] outB[32] outB[33] outB[34] outB[35]
++outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] outB[8] outB[9] ins1in20Bx36
+XlatchDri@0 net@5 net@20 latchDriver60
+XlatchDri@1 net@6 net@22 latchDriver60
+XscanEx2v@1 net@48[1] net@48[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sor[1] scanEx2
+Xwire90@0 fire[A] net@5 wire90-1300-layer_1-width_3
+Xwire90@1 fire[B] net@6 wire90-1301_9-layer_1-width_3
+Xwire90@2 net@20 net@23 wire90-1300-layer_1-width_3
+Xwire90@3 net@22 net@25 wire90-1300-layer_1-width_3
+.ENDS altStartDockStage
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-269_9-R_34_667m a b
-Ccap@0 gnd net@14 0.99f
-Ccap@1 gnd net@8 0.99f
-Ccap@2 gnd net@11 0.99f
-Rres@0 net@14 a 1.559
-Rres@1 net@11 net@14 3.119
-Rres@2 b net@8 1.559
-Rres@3 net@8 net@11 3.119
-.ENDS wire-C_0_011f-269_9-R_34_667m
+.SUBCKT wire-C_0_011f-249_5-R_34_667m a b
+Ccap@0 gnd net@14 0.915f
+Ccap@1 gnd net@8 0.915f
+Ccap@2 gnd net@11 0.915f
+Rres@0 net@14 a 1.442
+Rres@1 net@11 net@14 2.883
+Rres@2 b net@8 1.442
+Rres@3 net@8 net@11 2.883
+.ENDS wire-C_0_011f-249_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-269_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-269_9-R_34_667m
-.ENDS wire90-269_9-layer_1-width_3
+.SUBCKT wire90-249_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-249_5-R_34_667m
+.ENDS wire90-249_5-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-709_6-R_34_667m a b
-Ccap@0 gnd net@14 2.602f
-Ccap@1 gnd net@8 2.602f
-Ccap@2 gnd net@11 2.602f
-Rres@0 net@14 a 4.1
-Rres@1 net@11 net@14 8.2
-Rres@2 b net@8 4.1
-Rres@3 net@8 net@11 8.2
-.ENDS wire-C_0_011f-709_6-R_34_667m
+.SUBCKT wire-C_0_011f-355_8-R_34_667m a b
+Ccap@0 gnd net@14 1.305f
+Ccap@1 gnd net@8 1.305f
+Ccap@2 gnd net@11 1.305f
+Rres@0 net@14 a 2.056
+Rres@1 net@11 net@14 4.111
+Rres@2 b net@8 2.056
+Rres@3 net@8 net@11 4.111
+.ENDS wire-C_0_011f-355_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-709_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-709_6-R_34_667m
-.ENDS wire90-709_6-layer_1-width_3
+.SUBCKT wire90-355_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-355_8-R_34_667m
+.ENDS wire90-355_8-layer_1-width_3
-*** CELL: moveM:moveOut{sch}
-.SUBCKT moveOut bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp]
-+fire[M] flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4]
-+s[5] succ[sf] winLO[M]
-Xinv@0 net@28 s[4] inv-X_10
-Xinv@1 net@29 s[3] inv-X_10
-Xinv@2 net@50 s[5] inv-X_10
-Xinv@9 fire[T] net@186 inv-X_5
-Xinv@10 ilc[do] net@221 inv-X_5
-Xinv@11 net@227 s[2] inv-X_10
-Xinv@12 net@194 s[1] inv-X_10
-XinvI@0 do[Tp] net@28 inv-X_5
-XinvI@1 epi[torp] net@29 inv-X_5
-XinvI@2 do[Mv] net@50 inv-X_5
-XinvI@7 pred[D] net@227 inv-X_5
-XinvI@8 pred[T] net@194 inv-X_5
-Xnand2@2 ilc[do] bit[Di] net@208 nand2-X_5
-Xnand2@3 ilc[do] bit[Ti] net@207 nand2-X_5
-Xnor2n@1 ilc[mo] winLO[M] net@250 nor2n-X_10
-Xnor2n@5 net@206 winLO[M] net@203 nor2n-X_10
-Xnor2n@6 net@205 winLO[M] net@204 nor2n-X_10
-Xnor2n@7 net@220 winLO[M] fire[M] nor2n-X_20
-Xpms1@0 flag[D][set] net@186 pms1-X_20
-XpredDri2@0 fire[T] mc epi[torp] predDri20wMC
-XpredDri2@3 net@201 mc pred[D] predDri20wMC
-XpredDri2@4 net@200 mc pred[T] predDri20wMC
-XpredORdr@0 fire[T] done[M] mc do[Tp] predORdri20wMC
-XpredORdr@1 fire[T] done[M] mc do[Mv] predORdri20wMC
-Xraces@0 bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] pred[D] pred[T] succ[sf]
-+epi[torp] races@0_winHI[M] winLO[M] races
-XsucDri20@0 done[M] do[reD] sucDri20
-Xwire90@9 net@206 net@208 wire90-362_9-layer_1-width_3
-Xwire90@10 net@220 net@221 wire90-602_7-layer_1-width_3
-Xwire90@11 net@200 net@204 wire90-269_9-layer_1-width_3
-Xwire90@12 net@201 net@203 wire90-269_9-layer_1-width_3
-Xwire90@13 net@205 net@207 wire90-362_9-layer_1-width_3
-Xwire90@15 done[M] net@250 wire90-709_6-layer_1-width_3
-.ENDS moveOut
+*** CELL: centersJ:ctrAND2in30{sch}
+.SUBCKT ctrAND2in30 inA inB out
+Xinv@0 net@7 net@8 inv-X_10
+Xinv@1 net@9 out inv-X_30
+Xnor2HT_s@1 inA inB net@6 nor2HT_sy-X_4
+Xwire90@0 net@6 net@7 wire90-249_5-layer_1-width_3
+Xwire90@1 net@8 net@9 wire90-355_8-layer_1-width_3
+.ENDS ctrAND2in30
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-297_9-R_34_667m a b
-Ccap@0 gnd net@14 1.092f
-Ccap@1 gnd net@8 1.092f
-Ccap@2 gnd net@11 1.092f
-Rres@0 net@14 a 1.721
-Rres@1 net@11 net@14 3.442
-Rres@2 b net@8 1.721
-Rres@3 net@8 net@11 3.442
-.ENDS wire-C_0_011f-297_9-R_34_667m
+.SUBCKT wire-C_0_011f-291_8-R_34_667m a b
+Ccap@0 gnd net@14 1.07f
+Ccap@1 gnd net@8 1.07f
+Ccap@2 gnd net@11 1.07f
+Rres@0 net@14 a 1.686
+Rres@1 net@11 net@14 3.372
+Rres@2 b net@8 1.686
+Rres@3 net@8 net@11 3.372
+.ENDS wire-C_0_011f-291_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-297_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-297_9-R_34_667m
-.ENDS wire90-297_9-layer_1-width_3
+.SUBCKT wire90-291_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-291_8-R_34_667m
+.ENDS wire90-291_8-layer_1-width_3
-*** CELL: scanM:scanEx2h{sch}
-.SUBCKT scanEx2h dIn[1] dIn[2] mc p1p p2p rd sin sout
-XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanM__scanCellE
-XscanCell@11 dIn[2] p1p p2p rd net@31 sout scanM__scanCellE
-Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
-.ENDS scanEx2h
+*** CELL: gaspM:aStage{sch}
+.SUBCKT gaspM__aStage fire mc pred s[1] succ
+XctrAND2i@4 net@494 succ fire ctrAND2in30
+Xinv@4 net@987 s[1] inv-X_10
+Xinv@5 pred net@987 inv-X_5
+XpredDri2@1 fire mc pred predDri20wMC
+XsucDri20@1 fire succ sucDri20
+Xwire90@0 net@987 net@494 wire90-291_8-layer_1-width_3
+.ENDS gaspM__aStage
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-218_6-R_34_667m a b
-Ccap@0 gnd net@14 0.802f
-Ccap@1 gnd net@8 0.802f
-Ccap@2 gnd net@11 0.802f
-Rres@0 net@14 a 1.263
-Rres@1 net@11 net@14 2.526
-Rres@2 b net@8 1.263
-Rres@3 net@8 net@11 2.526
-.ENDS wire-C_0_011f-218_6-R_34_667m
+.SUBCKT wire-C_0_011f-791_7-R_34_667m a b
+Ccap@0 gnd net@14 2.903f
+Ccap@1 gnd net@8 2.903f
+Ccap@2 gnd net@11 2.903f
+Rres@0 net@14 a 4.574
+Rres@1 net@11 net@14 9.149
+Rres@2 b net@8 4.574
+Rres@3 net@8 net@11 9.149
+.ENDS wire-C_0_011f-791_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-218_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-218_6-R_34_667m
-.ENDS wire90-218_6-layer_1-width_3
-
-*** CELL: scanM:scanEx3h{sch}
-.SUBCKT scanEx3h dIn[1] dIn[2] dIn[3] mc p1p p2p rd sin sout
-XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanM__scanCellE
-XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanM__scanCellE
-XscanCell@12 dIn[3] p1p p2p rd net@32 sout scanM__scanCellE
-Xwire90@0 net@18 net@31 wire90-218_6-layer_1-width_3
-Xwire90@1 net@20 net@32 wire90-218_6-layer_1-width_3
-.ENDS scanEx3h
-
-*** CELL: scanM:scanEx4h{sch}
-.SUBCKT scanEx4h dIn[1] dIn[2] dIn[3] dIn[4] mc p1p p2p rd sin sout
-XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanM__scanCellE
-XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanM__scanCellE
-XscanCell@12 dIn[3] p1p p2p rd net@32 net@24 scanM__scanCellE
-XscanCell@13 dIn[4] p1p p2p rd net@33 sout scanM__scanCellE
-Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
-Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3
-Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3
-.ENDS scanEx4h
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4243_4-R_34_667m a b
-Ccap@0 gnd net@14 15.559f
-Ccap@1 gnd net@8 15.559f
-Ccap@2 gnd net@11 15.559f
-Rres@0 net@14 a 24.517
-Rres@1 net@11 net@14 49.035
-Rres@2 b net@8 24.517
-Rres@3 net@8 net@11 49.035
-.ENDS wire-C_0_011f-4243_4-R_34_667m
+.SUBCKT wire90-791_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-791_7-R_34_667m
+.ENDS wire90-791_7-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4243_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4243_4-R_34_667m
-.ENDS wire90-4243_4-layer_1-width_3
+*** CELL: stagesM:plainDockStage{sch}
+.SUBCKT plainDockStage in[10] in[11] in[12] in[13] in[14] in[15] in[16]
++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
++in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5]
++out[6] out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sir[9] sor[1] succ take[1]
+XaStage@1 net@1 sir[9] pred net@41 succ gaspM__aStage
+Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
++out[7] out[8] out[9] ins1in20Bx36
+XlatchDri@0 fire[1] take[1] latchDriver60
+XscanEx1v@0 net@41 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sor[1] scanEx1vertA
+Xwire90@1 net@1 fire[1] wire90-791_7-layer_1-width_3
+.ENDS plainDockStage
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-467_9-R_34_667m a b
-Ccap@0 gnd net@14 1.716f
-Ccap@1 gnd net@8 1.716f
-Ccap@2 gnd net@11 1.716f
-Rres@0 net@14 a 2.703
-Rres@1 net@11 net@14 5.407
-Rres@2 b net@8 2.703
-Rres@3 net@8 net@11 5.407
-.ENDS wire-C_0_011f-467_9-R_34_667m
+.SUBCKT wire-C_0_011f-414-R_34_667m a b
+Ccap@0 gnd net@14 1.518f
+Ccap@1 gnd net@8 1.518f
+Ccap@2 gnd net@11 1.518f
+Rres@0 net@14 a 2.392
+Rres@1 net@11 net@14 4.784
+Rres@2 b net@8 2.392
+Rres@3 net@8 net@11 4.784
+.ENDS wire-C_0_011f-414-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-467_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-467_9-R_34_667m
-.ENDS wire90-467_9-layer_1-width_3
+.SUBCKT wire90-414-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-414-R_34_667m
+.ENDS wire90-414-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-574_7-R_34_667m a b
-Ccap@0 gnd net@14 2.107f
-Ccap@1 gnd net@8 2.107f
-Ccap@2 gnd net@11 2.107f
-Rres@0 net@14 a 3.32
-Rres@1 net@11 net@14 6.641
-Rres@2 b net@8 3.32
-Rres@3 net@8 net@11 6.641
-.ENDS wire-C_0_011f-574_7-R_34_667m
+*** CELL: stageGroupsM:dockWagNine{sch}
+.SUBCKT dockWagNine in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
++out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sir[9] sor[1] succ take[1] take[2] take[3] take[4] take[5] take[6]
+XaltEndDo@0 net@16[26] net@16[25] net@16[24] net@16[23] net@16[22] net@16[21]
++net@16[20] net@16[19] net@16[18] net@16[17] net@16[35] net@16[16] net@16[15]
++net@16[14] net@16[13] net@16[12] net@16[11] net@16[10] net@16[9] net@16[8]
++net@16[7] net@16[34] net@16[6] net@16[5] net@16[4] net@16[3] net@16[2]
++net@16[1] net@16[0] net@16[33] net@16[32] net@16[31] net@16[30] net@16[29]
++net@16[28] net@16[27] net@19[26] net@19[25] net@19[24] net@19[23] net@19[22]
++net@19[21] net@19[20] net@19[19] net@19[18] net@19[17] net@19[35] net@19[16]
++net@19[15] net@19[14] net@19[13] net@19[12] net@19[11] net@19[10] net@19[9]
++net@19[8] net@19[7] net@19[34] net@19[6] net@19[5] net@19[4] net@19[3]
++net@19[2] net@19[1] net@19[0] net@19[33] net@19[32] net@19[31] net@19[30]
++net@19[29] net@19[28] net@19[27] out[10] out[11] out[12] out[13] out[14]
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
++out[7] out[8] out[9] net@69 net@58 net@134[8] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sir[9] sor[1] succ altEndDockStage
+XaltStart@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4]
++in[5] in[6] in[7] in[8] in[9] net@21[26] net@21[25] net@21[24] net@21[23]
++net@21[22] net@21[21] net@21[20] net@21[19] net@21[18] net@21[17] net@21[35]
++net@21[16] net@21[15] net@21[14] net@21[13] net@21[12] net@21[11] net@21[10]
++net@21[9] net@21[8] net@21[7] net@21[34] net@21[6] net@21[5] net@21[4]
++net@21[3] net@21[2] net@21[1] net@21[0] net@21[33] net@21[32] net@21[31]
++net@21[30] net@21[29] net@21[28] net@21[27] net@20[26] net@20[25] net@20[24]
++net@20[23] net@20[22] net@20[21] net@20[20] net@20[19] net@20[18] net@20[17]
++net@20[35] net@20[16] net@20[15] net@20[14] net@20[13] net@20[12] net@20[11]
++net@20[10] net@20[9] net@20[8] net@20[7] net@20[34] net@20[6] net@20[5]
++net@20[4] net@20[3] net@20[2] net@20[1] net@20[0] net@20[33] net@20[32]
++net@20[31] net@20[30] net@20[29] net@20[28] net@20[27] pred sir[1] sir[2]
++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@116[8] net@97 net@100
++altStartDockStage
+XplainDoc@0 net@2[26] net@2[25] net@2[24] net@2[23] net@2[22] net@2[21]
++net@2[20] net@2[19] net@2[18] net@2[17] net@2[35] net@2[16] net@2[15]
++net@2[14] net@2[13] net@2[12] net@2[11] net@2[10] net@2[9] net@2[8] net@2[7]
++net@2[34] net@2[6] net@2[5] net@2[4] net@2[3] net@2[2] net@2[1] net@2[0]
++net@2[33] net@2[32] net@2[31] net@2[30] net@2[29] net@2[28] net@2[27]
++net@3[26] net@3[25] net@3[24] net@3[23] net@3[22] net@3[21] net@3[20]
++net@3[19] net@3[18] net@3[17] net@3[35] net@3[16] net@3[15] net@3[14]
++net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7] net@3[34]
++net@3[6] net@3[5] net@3[4] net@3[3] net@3[2] net@3[1] net@3[0] net@3[33]
++net@3[32] net@3[31] net@3[30] net@3[29] net@3[28] net@3[27] net@107
++net@131[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@130[8]
++net@106 take[5] plainDockStage
+XplainDoc@1 net@20[26] net@20[25] net@20[24] net@20[23] net@20[22] net@20[21]
++net@20[20] net@20[19] net@20[18] net@20[17] net@20[35] net@20[16] net@20[15]
++net@20[14] net@20[13] net@20[12] net@20[11] net@20[10] net@20[9] net@20[8]
++net@20[7] net@20[34] net@20[6] net@20[5] net@20[4] net@20[3] net@20[2]
++net@20[1] net@20[0] net@20[33] net@20[32] net@20[31] net@20[30] net@20[29]
++net@20[28] net@20[27] net@2[26] net@2[25] net@2[24] net@2[23] net@2[22]
++net@2[21] net@2[20] net@2[19] net@2[18] net@2[17] net@2[35] net@2[16]
++net@2[15] net@2[14] net@2[13] net@2[12] net@2[11] net@2[10] net@2[9] net@2[8]
++net@2[7] net@2[34] net@2[6] net@2[5] net@2[4] net@2[3] net@2[2] net@2[1]
++net@2[0] net@2[33] net@2[32] net@2[31] net@2[30] net@2[29] net@2[28]
++net@2[27] net@60 net@125[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
++sir[9] net@131[8] net@108 take[4] plainDockStage
+XplainDoc@2 net@3[26] net@3[25] net@3[24] net@3[23] net@3[22] net@3[21]
++net@3[20] net@3[19] net@3[18] net@3[17] net@3[35] net@3[16] net@3[15]
++net@3[14] net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7]
++net@3[34] net@3[6] net@3[5] net@3[4] net@3[3] net@3[2] net@3[1] net@3[0]
++net@3[33] net@3[32] net@3[31] net@3[30] net@3[29] net@3[28] net@3[27]
++net@19[26] net@19[25] net@19[24] net@19[23] net@19[22] net@19[21] net@19[20]
++net@19[19] net@19[18] net@19[17] net@19[35] net@19[16] net@19[15] net@19[14]
++net@19[13] net@19[12] net@19[11] net@19[10] net@19[9] net@19[8] net@19[7]
++net@19[34] net@19[6] net@19[5] net@19[4] net@19[3] net@19[2] net@19[1]
++net@19[0] net@19[33] net@19[32] net@19[31] net@19[30] net@19[29] net@19[28]
++net@19[27] net@105 net@130[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sir[9] net@134[8] net@104 take[6] plainDockStage
+XplainDoc@3 net@0[26] net@0[25] net@0[24] net@0[23] net@0[22] net@0[21]
++net@0[20] net@0[19] net@0[18] net@0[17] net@0[35] net@0[16] net@0[15]
++net@0[14] net@0[13] net@0[12] net@0[11] net@0[10] net@0[9] net@0[8] net@0[7]
++net@0[34] net@0[6] net@0[5] net@0[4] net@0[3] net@0[2] net@0[1] net@0[0]
++net@0[33] net@0[32] net@0[31] net@0[30] net@0[29] net@0[28] net@0[27]
++net@1[26] net@1[25] net@1[24] net@1[23] net@1[22] net@1[21] net@1[20]
++net@1[19] net@1[18] net@1[17] net@1[35] net@1[16] net@1[15] net@1[14]
++net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] net@1[7] net@1[34]
++net@1[6] net@1[5] net@1[4] net@1[3] net@1[2] net@1[1] net@1[0] net@1[33]
++net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] net@1[27] net@109
++net@127[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@128[8]
++net@111 take[2] plainDockStage
+XplainDoc@4 net@21[26] net@21[25] net@21[24] net@21[23] net@21[22] net@21[21]
++net@21[20] net@21[19] net@21[18] net@21[17] net@21[35] net@21[16] net@21[15]
++net@21[14] net@21[13] net@21[12] net@21[11] net@21[10] net@21[9] net@21[8]
++net@21[7] net@21[34] net@21[6] net@21[5] net@21[4] net@21[3] net@21[2]
++net@21[1] net@21[0] net@21[33] net@21[32] net@21[31] net@21[30] net@21[29]
++net@21[28] net@21[27] net@0[26] net@0[25] net@0[24] net@0[23] net@0[22]
++net@0[21] net@0[20] net@0[19] net@0[18] net@0[17] net@0[35] net@0[16]
++net@0[15] net@0[14] net@0[13] net@0[12] net@0[11] net@0[10] net@0[9] net@0[8]
++net@0[7] net@0[34] net@0[6] net@0[5] net@0[4] net@0[3] net@0[2] net@0[1]
++net@0[0] net@0[33] net@0[32] net@0[31] net@0[30] net@0[29] net@0[28]
++net@0[27] net@64 net@116[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
++sir[9] net@127[8] net@110 take[1] plainDockStage
+XplainDoc@5 net@1[26] net@1[25] net@1[24] net@1[23] net@1[22] net@1[21]
++net@1[20] net@1[19] net@1[18] net@1[17] net@1[35] net@1[16] net@1[15]
++net@1[14] net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] net@1[7]
++net@1[34] net@1[6] net@1[5] net@1[4] net@1[3] net@1[2] net@1[1] net@1[0]
++net@1[33] net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] net@1[27]
++net@16[26] net@16[25] net@16[24] net@16[23] net@16[22] net@16[21] net@16[20]
++net@16[19] net@16[18] net@16[17] net@16[35] net@16[16] net@16[15] net@16[14]
++net@16[13] net@16[12] net@16[11] net@16[10] net@16[9] net@16[8] net@16[7]
++net@16[34] net@16[6] net@16[5] net@16[4] net@16[3] net@16[2] net@16[1]
++net@16[0] net@16[33] net@16[32] net@16[31] net@16[30] net@16[29] net@16[28]
++net@16[27] net@112 net@128[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sir[9] net@125[8] net@102 take[3] plainDockStage
+Xwire90@0 net@97 net@64 wire90-414-layer_1-width_3
+Xwire90@1 net@100 net@60 wire90-414-layer_1-width_3
+Xwire90@2 net@110 net@109 wire90-414-layer_1-width_3
+Xwire90@3 net@106 net@105 wire90-414-layer_1-width_3
+Xwire90@4 net@111 net@112 wire90-414-layer_1-width_3
+Xwire90@5 net@104 net@58 wire90-414-layer_1-width_3
+Xwire90@6 net@108 net@107 wire90-414-layer_1-width_3
+Xwire90@7 net@102 net@69 wire90-414-layer_1-width_3
+.ENDS dockWagNine
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-574_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-574_7-R_34_667m
-.ENDS wire90-574_7-layer_1-width_3
+*** CELL: centersJ:ctrAND3in30A{sch}
+.SUBCKT ctrAND3in30A inA inB inC out outM
+Xinv@1 outM out inv-X_30
+Xnand2_sy@0 net@15 inC outM nand2_sy-X_10
+Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5
+Xwire90@0 net@6 net@15 wire90-414-layer_1-width_3
+.ENDS ctrAND3in30A
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1674_7-R_34_667m a b
-Ccap@0 gnd net@14 6.141f
-Ccap@1 gnd net@8 6.141f
-Ccap@2 gnd net@11 6.141f
-Rres@0 net@14 a 9.676
-Rres@1 net@11 net@14 19.352
-Rres@2 b net@8 9.676
-Rres@3 net@8 net@11 19.352
-.ENDS wire-C_0_011f-1674_7-R_34_667m
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_6_667 d g s
+MPMOSf@0 d g s vdd pch W='40.002*(1+ABP/sqrt(40.002*2))' L='2'
++DELVTO='AVT0P/sqrt(40.002*2)'
+.ENDS PMOSx-X_6_667
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1674_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1674_7-R_34_667m
-.ENDS wire90-1674_7-layer_1-width_3
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_20_001 d g s
+MNMOSf@0 d g s gnd nch W='60.003*(1+ABN/sqrt(60.003*2))' L='2'
++DELVTO='AVT0N/sqrt(60.003*2)'
+.ENDS NMOSx-X_20_001
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1625_5-R_34_667m a b
-Ccap@0 gnd net@14 5.96f
-Ccap@1 gnd net@8 5.96f
-Ccap@2 gnd net@11 5.96f
-Rres@0 net@14 a 9.392
-Rres@1 net@11 net@14 18.784
-Rres@2 b net@8 9.392
-Rres@3 net@8 net@11 18.784
-.ENDS wire-C_0_011f-1625_5-R_34_667m
+*** CELL: redFive:nms3{sch}
+.SUBCKT nms3-X_6_667 d g g2 g3
+XNMOS@0 d g3 net@6 NMOSx-X_20_001
+XNMOS@1 net@7 g gnd NMOSx-X_20_001
+XNMOS@2 net@6 g2 net@7 NMOSx-X_20_001
+.ENDS nms3-X_6_667
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1625_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1625_5-R_34_667m
-.ENDS wire90-1625_5-layer_1-width_3
+*** CELL: redFive:nand3{sch}
+.SUBCKT nand3-X_6_667 ina inb inc out
+XPMOS@0 out inc vdd PMOSx-X_6_667
+XPMOS@1 out inb vdd PMOSx-X_6_667
+XPMOS@2 out ina vdd PMOSx-X_6_667
+Xnms3@0 out ina inb inc nms3-X_6_667
+.ENDS nand3-X_6_667
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1899_2-R_34_667m a b
-Ccap@0 gnd net@14 6.964f
-Ccap@1 gnd net@8 6.964f
-Ccap@2 gnd net@11 6.964f
-Rres@0 net@14 a 10.973
-Rres@1 net@11 net@14 21.946
-Rres@2 b net@8 10.973
-Rres@3 net@8 net@11 21.946
-.ENDS wire-C_0_011f-1899_2-R_34_667m
+.SUBCKT wire-C_0_011f-309-R_34_667m a b
+Ccap@0 gnd net@14 1.133f
+Ccap@1 gnd net@8 1.133f
+Ccap@2 gnd net@11 1.133f
+Rres@0 net@14 a 1.785
+Rres@1 net@11 net@14 3.571
+Rres@2 b net@8 1.785
+Rres@3 net@8 net@11 3.571
+.ENDS wire-C_0_011f-309-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1899_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1899_2-R_34_667m
-.ENDS wire90-1899_2-layer_1-width_3
+.SUBCKT wire90-309-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-309-R_34_667m
+.ENDS wire90-309-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1577_6-R_34_667m a b
-Ccap@0 gnd net@14 5.785f
-Ccap@1 gnd net@8 5.785f
-Ccap@2 gnd net@11 5.785f
-Rres@0 net@14 a 9.115
-Rres@1 net@11 net@14 18.23
-Rres@2 b net@8 9.115
-Rres@3 net@8 net@11 18.23
-.ENDS wire-C_0_011f-1577_6-R_34_667m
+.SUBCKT wire-C_0_011f-114_9-R_34_667m a b
+Ccap@0 gnd net@14 0.421f
+Ccap@1 gnd net@8 0.421f
+Ccap@2 gnd net@11 0.421f
+Rres@0 net@14 a 0.664
+Rres@1 net@11 net@14 1.328
+Rres@2 b net@8 0.664
+Rres@3 net@8 net@11 1.328
+.ENDS wire-C_0_011f-114_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1577_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1577_6-R_34_667m
-.ENDS wire90-1577_6-layer_1-width_3
+.SUBCKT wire90-114_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-114_9-R_34_667m
+.ENDS wire90-114_9-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1661-R_34_667m a b
-Ccap@0 gnd net@14 6.09f
-Ccap@1 gnd net@8 6.09f
-Ccap@2 gnd net@11 6.09f
-Rres@0 net@14 a 9.597
-Rres@1 net@11 net@14 19.194
-Rres@2 b net@8 9.597
-Rres@3 net@8 net@11 19.194
-.ENDS wire-C_0_011f-1661-R_34_667m
+*** CELL: driversL:suc3ANDdri20{sch}
+.SUBCKT suc3ANDdri20 inA inB inC succ
+XPMOSx@0 succ net@51 vdd PMOSx-X_20
+Xinv@0 succ net@71 inv-X_4
+Xnand3@0 inA inB inC net@67 nand3-X_6_667
+Xnms2@0 succ net@75 net@51 nms2-X_2
+Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3
+Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3
+.ENDS suc3ANDdri20
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1661-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1661-R_34_667m
-.ENDS wire90-1661-layer_1-width_3
+*** CELL: driversL:sucANDdri20{sch}
+.SUBCKT sucANDdri20 inA inB succ
+XPMOSx@0 succ net@51 vdd PMOSx-X_20
+Xinv@0 succ net@71 inv-X_4
+Xnand2@0 inA inB net@67 nand2-X_5
+Xnms2@0 succ net@75 net@51 nms2-X_2
+Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3
+Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3
+.ENDS sucANDdri20
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1338_5-R_34_667m a b
-Ccap@0 gnd net@14 4.908f
-Ccap@1 gnd net@8 4.908f
-Ccap@2 gnd net@11 4.908f
-Rres@0 net@14 a 7.734
-Rres@1 net@11 net@14 15.467
-Rres@2 b net@8 7.734
-Rres@3 net@8 net@11 15.467
-.ENDS wire-C_0_011f-1338_5-R_34_667m
+.SUBCKT wire-C_0_011f-372_8-R_34_667m a b
+Ccap@0 gnd net@14 1.367f
+Ccap@1 gnd net@8 1.367f
+Ccap@2 gnd net@11 1.367f
+Rres@0 net@14 a 2.154
+Rres@1 net@11 net@14 4.308
+Rres@2 b net@8 2.154
+Rres@3 net@8 net@11 4.308
+.ENDS wire-C_0_011f-372_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1338_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1338_5-R_34_667m
-.ENDS wire90-1338_5-layer_1-width_3
+.SUBCKT wire90-372_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-372_8-R_34_667m
+.ENDS wire90-372_8-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1486_5-R_34_667m a b
-Ccap@0 gnd net@14 5.451f
-Ccap@1 gnd net@8 5.451f
-Ccap@2 gnd net@11 5.451f
-Rres@0 net@14 a 8.589
-Rres@1 net@11 net@14 17.177
-Rres@2 b net@8 8.589
-Rres@3 net@8 net@11 17.177
-.ENDS wire-C_0_011f-1486_5-R_34_667m
+*** CELL: gaspM:gaspEpi{sch}
+.SUBCKT gaspEpi epi[OTHER] epi[TAIL] epi[TORP] fire mc pred s[1] tailBit
++tokenLO
+XctrAND3i@3 net@1068 epi[TORP] net@1082 fire net@1119 ctrAND3in30A
+Xinv@5 pred net@987 inv-X_5
+XinvI@0 net@987 s[1] inv-X_10
+XinvI@1 tokenLO net@1146 inv-X_5
+XinvI@3 tailBit net@1147 inv-X_5
+Xnor2n_sy@0 epi[TAIL] epi[OTHER] net@1079 nor2n_sy-X_5
+XpredDri2@0 fire mc pred predDri20wMC
+Xsuc3ANDd@0 tokenLO net@1148 fire epi[OTHER] suc3ANDdri20
+Xsuc3ANDd@1 tokenLO tailBit fire epi[TAIL] suc3ANDdri20
+XsucANDdr@1 net@1139 fire epi[TORP] sucANDdri20
+Xwire90@0 net@987 net@1068 wire90-372_8-layer_1-width_3
+Xwire90@3 net@1079 net@1082 wire90-372_8-layer_1-width_3
+Xwire90@4 net@1139 net@1146 wire90-372_8-layer_1-width_3
+Xwire90@6 net@1148 net@1147 wire90-372_8-layer_1-width_3
+.ENDS gaspEpi
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1486_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1486_5-R_34_667m
-.ENDS wire90-1486_5-layer_1-width_3
+*** CELL: stagesM:epiDockStage{sch}
+.SUBCKT epiDockStage do[epi] epi[10] epi[11] epi[12] epi[13] epi[14] epi[15]
++epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] epi[21] epi[22] epi[23]
++epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30] epi[31]
++epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6] epi[7]
++epi[8] epi[9] epi[OTHER] epi[TAIL] epi[TORP] in[10] in[11] in[12] in[13]
++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
++in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] sir[1]
++sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] take[epi]
+XanEpiSta@1 epi[OTHER] epi[TAIL] epi[TORP] net@5 sir[9] do[epi] net@47 in[28]
++in[T] gaspEpi
+Xins1in20@0 take[epi] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
++in[4] in[5] in[6] in[7] in[8] in[9] epi[10] epi[11] epi[12] epi[13] epi[14]
++epi[15] epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] epi[21] epi[22]
++epi[23] epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30]
++epi[31] epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6]
++epi[7] epi[8] epi[9] ins1in20Bx36
+XlatchDri@0 net@0 take[epi] latchDriver60
+XscanEx1v@1 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sor[1] scanEx1vertA
+Xwire90@0 net@0 net@5 wire90-372_8-layer_1-width_3
+.ENDS epiDockStage
+
+*** CELL: redFive:nand2LT_sy{sch}
+.SUBCKT nand2LT_sy-X_10 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_5
+XPMOS@1 out inb vdd PMOSx-X_5
+Xnms2_sy@0 out ina inb nms2_sy-X_10
+.ENDS nand2LT_sy-X_10
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_12 d g s
+MNMOSf@0 d g s gnd nch W='36*(1+ABN/sqrt(36*2))' L='2'
++DELVTO='AVT0N/sqrt(36*2)'
+.ENDS NMOSx-X_12
+
+*** CELL: gates3inM:nor3in6.6sym{sch}
+.SUBCKT nor3in6_6sym inA inB inC out
+XNMOSx@0 out inC gnd NMOSx-X_12
+XNMOSx@7 out inB gnd NMOSx-X_12
+XNMOSx@8 out inA gnd NMOSx-X_12
+Xpms3@0 out inA inB inC pms3-X_3_333
+Xpms3@1 out inC inB inA pms3-X_3_333
+.ENDS nor3in6_6sym
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1831_6-R_34_667m a b
-Ccap@0 gnd net@14 6.716f
-Ccap@1 gnd net@8 6.716f
-Ccap@2 gnd net@11 6.716f
-Rres@0 net@14 a 10.583
-Rres@1 net@11 net@14 21.165
-Rres@2 b net@8 10.583
-Rres@3 net@8 net@11 21.165
-.ENDS wire-C_0_011f-1831_6-R_34_667m
+.SUBCKT wire-C_0_011f-956_7-R_34_667m a b
+Ccap@0 gnd net@14 3.508f
+Ccap@1 gnd net@8 3.508f
+Ccap@2 gnd net@11 3.508f
+Rres@0 net@14 a 5.528
+Rres@1 net@11 net@14 11.055
+Rres@2 b net@8 5.528
+Rres@3 net@8 net@11 11.055
+.ENDS wire-C_0_011f-956_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1831_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1831_6-R_34_667m
-.ENDS wire90-1831_6-layer_1-width_3
+.SUBCKT wire90-956_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-956_7-R_34_667m
+.ENDS wire90-956_7-layer_1-width_3
-*** CELL: moveM:ilcMoveOut{sch}
-.SUBCKT ilcMoveOut bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp]
-+fire[M] flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
-+inLO[6] inLO[8] mc p1p p2p pred[D] pred[T] rd sin sout succ[sf]
-Xilc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8]
-+ilc[decLO] ilc[do] ilc[load] ilc[mo] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
-+inLO[6] inLO[8] ilc
-XoutDockM@0 bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M]
-+flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4] s[5]
-+succ[sf] net@72 moveOut
-XscanEx2h@0 s[1] s[5] mc p1p p2p rd net@51 net@58 scanEx2h
-XscanEx3h@0 s[4] s[3] s[2] mc p1p p2p rd net@58 sout scanEx3h
-XscanEx4h@0 bitt[1] bitt[3] bitt[5] bitt[7] mc p1p p2p rd sin net@50 scanEx4h
-XscanEx4h@1 bitt[2] bitt[4] bitt[6] bitt[8] mc p1p p2p rd net@50 net@51
-+scanEx4h
-Xwire90@0 net@72 ilc[decLO] wire90-4243_4-layer_1-width_3
-Xwire90@1 wire90@1_a ilc[mo] wire90-467_9-layer_1-width_3
-Xwire90@2 wire90@2_a ilc[do] wire90-574_7-layer_1-width_3
-Xwire90@3 wire90@3_a bitt[8] wire90-1674_7-layer_1-width_3
-Xwire90@4 wire90@4_a bitt[1] wire90-1625_5-layer_1-width_3
-Xwire90@5 wire90@5_a bitt[2] wire90-1899_2-layer_1-width_3
-Xwire90@6 wire90@6_a bitt[3] wire90-1577_6-layer_1-width_3
-Xwire90@7 wire90@7_a bitt[4] wire90-1661-layer_1-width_3
-Xwire90@8 wire90@8_a bitt[5] wire90-1338_5-layer_1-width_3
-Xwire90@9 wire90@9_a bitt[6] wire90-1486_5-layer_1-width_3
-Xwire90@10 wire90@10_a bitt[7] wire90-1831_6-layer_1-width_3
-.ENDS ilcMoveOut
+*** CELL: oneHotM:onDeck{sch}
+.SUBCKT onDeck bits[ABORT] bits[HEAD] fire[od] flag[A][clr] flag[A][set]
++flag[D][clr] flag[D][set] mc od[ABORT] od[HEAD] od[OTHER] pred s[1] s[2]
+Xinv@8 pred net@358 inv-X_5
+Xinv@9 bits[HEAD] net@441 inv-X_5
+Xinv@10 bits[ABORT] net@463 inv-X_5
+XinvI@1 net@368 fire[od] inv-X_30
+XinvI@2 net@317 s[2] inv-X_10
+XinvI@3 net@314 s[1] inv-X_10
+Xnand2LT_@0 net@371 net@374 net@367 nand2LT_sy-X_10
+Xnor2_sy@4 flag[A][set] flag[A][clr] net@305 nor2_sy-X_5
+Xnor2_sy@5 flag[D][set] flag[D][clr] net@297 nor2_sy-X_5
+Xnor3in3_@2 net@317 net@436 net@314 net@322 nor3in6_6sym
+Xnor3in3_@5 od[ABORT] od[OTHER] od[HEAD] net@476 nor3in6_6sym
+XpredDri2@2 fire[od] mc pred predDri20wMC
+Xsuc3ANDd@1 net@438 net@485 fire[od] od[OTHER] suc3ANDdri20
+XsucANDdr@0 bits[HEAD] net@444 od[HEAD] sucANDdri20
+XsucANDdr@4 bits[ABORT] fire[od] od[ABORT] sucANDdri20
+Xwire90@10 fire[od] net@444 wire90-956_7-layer_1-width_3
+Xwire90@11 net@322 net@374 wire90-294_8-layer_1-width_3
+Xwire90@13 net@297 net@317 wire90-294_8-layer_1-width_3
+Xwire90@15 net@305 net@436 wire90-294_8-layer_1-width_3
+Xwire90@16 net@358 net@314 wire90-294_8-layer_1-width_3
+Xwire90@18 net@371 net@476 wire90-294_8-layer_1-width_3
+Xwire90@19 net@368 net@367 wire90-294_8-layer_1-width_3
+Xwire90@20 net@441 net@438 wire90-294_8-layer_1-width_3
+Xwire90@21 net@463 net@485 wire90-294_8-layer_1-width_3
+.ENDS onDeck
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_40 in out
-XNMOS@0 out in gnd NMOSx-X_40
-XPMOS@0 out in vdd PMOSx-X_40
-.ENDS inv-X_40
+*** CELL: stagesM:onDeckDockStage{sch}
+.SUBCKT onDeckDockStage do[od] flag[A][clr] flag[A][set] flag[D][clr]
++flag[D][set] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18]
++m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28]
++m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4]
++m1[5] m1[6] m1[7] m1[8] m1[9] od[10] od[11] od[12] od[13] od[14] od[15]
++od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25]
++od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35]
++od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] od[ABORT] od[HEAD] od[OTHER]
++sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1]
++take[od]
+Xins1in20@0 take[od] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
++m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
++m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
++m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] od[10] od[11] od[12] od[13] od[14] od[15]
++od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25]
++od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35]
++od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] ins1in20Bx36
+XlatchDri@0 fire[1] take[od] latchDriver60
+XonDeck@0 m1[29] m1[30] net@11 flag[A][clr] flag[A][set] flag[D][clr]
++flag[D][set] sir[9] od[ABORT] od[HEAD] od[OTHER] do[od] net@62[1] net@62[0]
++onDeck
+XscanEx2v@2 net@62[1] net@62[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sor[1] scanEx2
+Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3
+.ENDS onDeckDockStage
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_15 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_30
-XNMOS@1 net@0 g gnd NMOSx-X_30
-.ENDS nms2-X_15
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-927-R_34_667m a b
+Ccap@0 gnd net@14 3.399f
+Ccap@1 gnd net@8 3.399f
+Ccap@2 gnd net@11 3.399f
+Rres@0 net@14 a 5.356
+Rres@1 net@11 net@14 10.712
+Rres@2 b net@8 5.356
+Rres@3 net@8 net@11 10.712
+.ENDS wire-C_0_011f-927-R_34_667m
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_30 d g g2
-Xnms2@0 d g g2 nms2-X_15
-Xnms2@1 d g2 g nms2-X_15
-.ENDS nms2_sy-X_30
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-927-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-927-R_34_667m
+.ENDS wire90-927-layer_1-width_3
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_30 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_30
-XPMOS@1 out ina vdd PMOSx-X_30
-Xnms2_sy@0 out ina inb nms2_sy-X_30
-.ENDS nand2_sy-X_30
+*** CELL: centersJ:ctrAND1in30{sch}
+.SUBCKT ctrAND1in30 in out
+Xinv@11 net@125 net@120 inv-X_10
+XinvI@1 net@82 out inv-X_30
+XinvI@2 in net@101 inv-X_5
+Xwire90@1 net@101 net@125 wire90-414-layer_1-width_3
+Xwire90@2 net@120 net@82 wire90-927-layer_1-width_3
+.ENDS ctrAND1in30
-*** CELL: redFive:nand2n_sy{sch}
-.SUBCKT nand2n_sy-X_30 ina inb out
-Xnand2_sy@0 ina inb out nand2_sy-X_30
-.ENDS nand2n_sy-X_30
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-301_8-R_34_667m a b
+Ccap@0 gnd net@14 1.107f
+Ccap@1 gnd net@8 1.107f
+Ccap@2 gnd net@11 1.107f
+Rres@0 net@14 a 1.744
+Rres@1 net@11 net@14 3.487
+Rres@2 b net@8 1.744
+Rres@3 net@8 net@11 3.487
+.ENDS wire-C_0_011f-301_8-R_34_667m
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_20 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_60
-XNMOS@1 net@7 g gnd NMOSx-X_60
-XNMOS@2 net@6 g2 net@7 NMOSx-X_60
-.ENDS nms3-X_20
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-301_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-301_8-R_34_667m
+.ENDS wire90-301_8-layer_1-width_3
-*** CELL: redFive:pms1{sch}
-.SUBCKT pms1-X_3 d g
-XPMOS@0 d g vdd PMOSx-X_3
-.ENDS pms1-X_3
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-732_5-R_34_667m a b
+Ccap@0 gnd net@14 2.686f
+Ccap@1 gnd net@8 2.686f
+Ccap@2 gnd net@11 2.686f
+Rres@0 net@14 a 4.232
+Rres@1 net@11 net@14 8.464
+Rres@2 b net@8 4.232
+Rres@3 net@8 net@11 8.464
+.ENDS wire-C_0_011f-732_5-R_34_667m
-*** CELL: predicateM:nand3in20sr{sch}
-.SUBCKT nand3in20sr inA inB inC out resetLO
-Xnms3a@0 out inA inB inC nms3-X_20
-Xpms1@0 out inC pms1-X_3
-Xpms1@1 out inB pms1-X_3
-Xpms1@2 out inA pms1-X_3
-Xpms1@3 out resetLO pms1-X_20
-.ENDS nand3in20sr
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-732_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-732_5-R_34_667m
+.ENDS wire90-732_5-layer_1-width_3
-*** CELL: driversL:sucDri20plain{sch}
-.SUBCKT sucDri20plain in succ
-XPMOSx@0 succ in vdd PMOSx-X_20
-Xinv@1 succ net@94 inv-X_4
-Xnms2@0 succ net@127 in nms2-X_2
-Xwire90@0 net@127 net@94 wire90-124_7-layer_1-width_3
-.ENDS sucDri20plain
+*** CELL: oneHotM:reQueueB{sch}
+.SUBCKT reQueueB circulate epi[TAIL] mc od[HEAD] s[1] s[2]
+XctrAND1i@0 net@1 net@7 ctrAND1in30
+Xinv@2 od[HEAD] net@127 inv-X_5
+Xinv@3 epi[TAIL] net@125 inv-X_5
+XinvI@3 net@128 s[1] inv-X_10
+XinvI@4 net@126 s[2] inv-X_10
+Xnand2@0 od[HEAD] epi[TAIL] net@0 nand2-X_5
+XpredDri2@1 net@7 mc epi[TAIL] predDri20wMC
+XpredDri2@2 net@7 mc od[HEAD] predDri20wMC
+XsucDri20@0 net@9 circulate sucDri20
+Xwire90@0 net@0 net@1 wire90-301_8-layer_1-width_3
+Xwire90@1 net@7 net@9 wire90-732_5-layer_1-width_3
+Xwire90@2 net@126 net@125 wire90-142_6-layer_1-width_3
+Xwire90@3 net@128 net@127 wire90-142_6-layer_1-width_3
+.ENDS reQueueB
-*** CELL: predicateM:predSucDri{sch}
-.SUBCKT predSucDri do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] sel[Co]
-+sel[Ld] sel[Lt] sel[Mv] sel[Tp]
-Xna[1] sel[Ld] fire[do] w[1] nand2-X_10
-Xna[2] sel[Co] fire[do] w[2] nand2-X_10
-Xna[3] sel[Mv] fire[do] w[3] nand2-X_10
-Xna[4] sel[Tp] fire[do] w[4] nand2-X_10
-Xna[5] sel[Lt] fire[do] w[5] nand2-X_10
-Xsd[1] w[1] do[Ld] sucDri20plain
-Xsd[2] w[2] do[Co] sucDri20plain
-Xsd[3] w[3] do[Mv] sucDri20plain
-Xsd[4] w[4] do[Tp] sucDri20plain
-Xsd[5] w[5] do[Lt] sucDri20plain
-Xwire90@0 w[1] wire90@0_b wire90-503_4-layer_1-width_3
-Xwire90@1 w[2] wire90@1_b wire90-503_4-layer_1-width_3
-Xwire90@2 w[3] wire90@2_b wire90-503_4-layer_1-width_3
-Xwire90@3 w[4] wire90@3_b wire90-503_4-layer_1-width_3
-Xwire90@4 w[5] wire90@4_b wire90-503_4-layer_1-width_3
-.ENDS predSucDri
+*** CELL: redFive:nms2{sch}
+.SUBCKT nms2-X_3 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_6
+XNMOS@1 net@0 g gnd NMOSx-X_6
+.ENDS nms2-X_3
-*** CELL: orangeTSMC090nm:PMOS4x{sch}
-.SUBCKT PMOS4x-X_3 b d g s
-MPMOS4f@0 d g s b pch W='18*(1+ABP/sqrt(18*2))' L='2'
-+DELVTO='AVT0P/sqrt(18*2)'
-.ENDS PMOS4x-X_3
+*** CELL: redFive:nms2_sy{sch}
+.SUBCKT nms2_sy-X_6 d g g2
+Xnms2@0 d g g2 nms2-X_3
+Xnms2@1 d g2 g nms2-X_3
+.ENDS nms2_sy-X_6
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_1_5 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_3
-XPMOS@1 d g2 net@2 PMOSx-X_3
-.ENDS pms2-X_1_5
+*** CELL: redFive:nand2_sy{sch}
+.SUBCKT nand2_sy-X_6 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_6
+XPMOS@1 out ina vdd PMOSx-X_6
+Xnms2_sy@0 out ina inb nms2_sy-X_6
+.ENDS nand2_sy-X_6
-*** CELL: driversL:predCond20wMC{sch}
-.SUBCKT predCond20wMC cond in mc pred
-XNMOSx@1 pred mc gnd NMOSx-X_10
-XPMOS4x@0 PMOS4x@0_b pred in net@217 PMOS4x-X_3
-XPMOS4x@1 PMOS4x@1_b pred cond net@210 PMOS4x-X_3
-Xinv@0 pred net@145 inv-X_10
-Xnms2@0 pred cond in nms2-X_20
-Xpms2a@0 net@217 mc net@200 pms2-X_1_5
-Xwire90@0 net@200 net@145 wire90-243_6-layer_1-width_3
-Xwire90@1 net@217 net@210 wire90-243_6-layer_1-width_3
-.ENDS predCond20wMC
+*** CELL: redFive:nand2n{sch}
+.SUBCKT nand2n-X_5 ina inb out
+Xnand2@0 ina inb out nand2-X_5
+.ENDS nand2n-X_5
-*** CELL: driversL:predCond20wMS{sch}
-.SUBCKT predCond20wMS cond in mc pred
-XPMOSx@0 pred cond net@210 PMOSx-X_3
-XPMOSx@1 pred in net@217 PMOSx-X_3
-Xinv@0 pred net@145 inv-X_10
-XinvLT@0 mc net@240 invLT-X_5
-Xnms2@0 pred cond in nms2-X_20
-Xpms1@0 pred net@240 pms1-X_3
-Xpms2a@0 net@217 mc net@200 pms2-X_1_5
-Xwire90@0 net@200 net@145 wire90-243_6-layer_1-width_3
-Xwire90@1 net@217 net@210 wire90-243_6-layer_1-width_3
-.ENDS predCond20wMS
+*** CELL: redFive:nand2n_sy{sch}
+.SUBCKT nand2n_sy-X_20 ina inb out
+Xnand2_sy@0 ina inb out nand2_sy-X_20
+.ENDS nand2n_sy-X_20
-*** CELL: predicateM:predFlagDri{sch}
-.SUBCKT predFlagDri fire[do] flag[A][clr] flag[A][set] flag[B][clr]
-+flag[B][set] flag[D][clr] flag[D][set] mc sel[Fl] sel[rD]
-XbitAssig@0 bitAssignments
-Xpc[1] sel[Fl] fire[do] mc flag[A][set] predCond20wMC
-Xpc[2] sel[Fl] fire[do] mc flag[A][clr] predCond20wMC
-Xpc[3] sel[Fl] fire[do] mc flag[B][set] predCond20wMC
-Xpc[4] sel[Fl] fire[do] mc flag[B][clr] predCond20wMC
-XpredCond@0 sel[rD] fire[do] mc flag[D][clr] predCond20wMC
-XpredCond@1 sel[rD] fire[do] mc flag[D][set] predCond20wMS
-.ENDS predFlagDri
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_9_999 d g s
+MNMOSf@0 d g s gnd nch W='29.997*(1+ABN/sqrt(29.997*2))' L='2'
++DELVTO='AVT0N/sqrt(29.997*2)'
+.ENDS NMOSx-X_9_999
-*** CELL: predicateM:ohPredDo{sch}
-.SUBCKT ohPredDo do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] fire[skip]
-+flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set]
-+mc ps[do] ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD]
-XbitAssig@0 bitAssignments
-XohPredDo@3 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] sel[Co] sel[Ld]
-+sel[Lt] sel[Mv] sel[Tp] predSucDri
-XpredFlag@1 fire[do] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
-+flag[D][clr] flag[D][set] mc sel[Fl] sel[rD] predFlagDri
-XsucDri20@0 net@55 ps[skip] sucDri20
-XsucDri20@1 fire[do] ps[do] sucDri20
-Xwire90@2 fire[skip] net@55 wire90-309-layer_1-width_3
-.ENDS ohPredDo
+*** CELL: redFive:nms3{sch}
+.SUBCKT nms3-X_3_333 d g g2 g3
+XNMOS@0 d g3 net@6 NMOSx-X_9_999
+XNMOS@1 net@7 g gnd NMOSx-X_9_999
+XNMOS@2 net@6 g2 net@7 NMOSx-X_9_999
+.ENDS nms3-X_3_333
-*** CELL: redFive:pms1{sch}
-.SUBCKT pms1-X_5 d g
-XPMOS@0 d g vdd PMOSx-X_5
-.ENDS pms1-X_5
+*** CELL: gates3inM:nand3in6.6sym{sch}
+.SUBCKT nand3in6_6sym inA inB inC out
+XPMOSx@1 out inA vdd PMOSx-X_10
+XPMOSx@3 out inC vdd PMOSx-X_10
+XPMOSx@4 out inB vdd PMOSx-X_10
+Xnms3@0 out inA inB inC nms3-X_3_333
+Xnms3@2 out inC inB inA nms3-X_3_333
+.ENDS nand3in6_6sym
-*** CELL: predicateM:ohSRxor{sch}
-.SUBCKT ohSRxor flag[F] flag[T] out resetLO sel[1] sel[2]
-Xnms2b@4 out flag[T] sel[1] nms2-X_5
-Xnms2b@5 out flag[F] sel[2] nms2-X_5
-Xpms1@0 out resetLO pms1-X_5
-Xpms2@0 out flag[T] sel[2] pms2-X_1
-Xpms2@1 out flag[F] sel[1] pms2-X_1
-.ENDS ohSRxor
+*** CELL: redFive:nor2{sch}
+.SUBCKT nor2-X_10 ina inb out
+XNMOS@0 out ina gnd NMOSx-X_10
+XNMOS@1 out inb gnd NMOSx-X_10
+Xpms2@0 out ina inb pms2-X_10
+.ENDS nor2-X_10
+
+*** CELL: redFive:nor2n{sch}
+.SUBCKT nor2n-X_10 ina inb out
+Xnor2@0 ina inb out nor2-X_10
+.ENDS nor2n-X_10
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-395_6-R_34_667m a b
-Ccap@0 gnd net@14 1.451f
-Ccap@1 gnd net@8 1.451f
-Ccap@2 gnd net@11 1.451f
-Rres@0 net@14 a 2.286
-Rres@1 net@11 net@14 4.571
-Rres@2 b net@8 2.286
-Rres@3 net@8 net@11 4.571
-.ENDS wire-C_0_011f-395_6-R_34_667m
+.SUBCKT wire-C_0_011f-286_3-R_34_667m a b
+Ccap@0 gnd net@14 1.05f
+Ccap@1 gnd net@8 1.05f
+Ccap@2 gnd net@11 1.05f
+Rres@0 net@14 a 1.654
+Rres@1 net@11 net@14 3.308
+Rres@2 b net@8 1.654
+Rres@3 net@8 net@11 3.308
+.ENDS wire-C_0_011f-286_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-395_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-395_6-R_34_667m
-.ENDS wire90-395_6-layer_1-width_3
+.SUBCKT wire90-286_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-286_3-R_34_667m
+.ENDS wire90-286_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-313_6-R_34_667m a b
-Ccap@0 gnd net@14 1.15f
-Ccap@1 gnd net@8 1.15f
-Ccap@2 gnd net@11 1.15f
-Rres@0 net@14 a 1.812
-Rres@1 net@11 net@14 3.624
-Rres@2 b net@8 1.812
-Rres@3 net@8 net@11 3.624
-.ENDS wire-C_0_011f-313_6-R_34_667m
+.SUBCKT wire-C_0_011f-428_8-R_34_667m a b
+Ccap@0 gnd net@14 1.572f
+Ccap@1 gnd net@8 1.572f
+Ccap@2 gnd net@11 1.572f
+Rres@0 net@14 a 2.478
+Rres@1 net@11 net@14 4.955
+Rres@2 b net@8 2.478
+Rres@3 net@8 net@11 4.955
+.ENDS wire-C_0_011f-428_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-313_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-313_6-R_34_667m
-.ENDS wire90-313_6-layer_1-width_3
+.SUBCKT wire90-428_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-428_8-R_34_667m
+.ENDS wire90-428_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-339-R_34_667m a b
-Ccap@0 gnd net@14 1.243f
-Ccap@1 gnd net@8 1.243f
-Ccap@2 gnd net@11 1.243f
-Rres@0 net@14 a 1.959
-Rres@1 net@11 net@14 3.917
-Rres@2 b net@8 1.959
-Rres@3 net@8 net@11 3.917
-.ENDS wire-C_0_011f-339-R_34_667m
+.SUBCKT wire-C_0_011f-356_7-R_34_667m a b
+Ccap@0 gnd net@14 1.308f
+Ccap@1 gnd net@8 1.308f
+Ccap@2 gnd net@11 1.308f
+Rres@0 net@14 a 2.061
+Rres@1 net@11 net@14 4.122
+Rres@2 b net@8 2.061
+Rres@3 net@8 net@11 4.122
+.ENDS wire-C_0_011f-356_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-339-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-339-R_34_667m
-.ENDS wire90-339-layer_1-width_3
+.SUBCKT wire90-356_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-356_7-R_34_667m
+.ENDS wire90-356_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-286_1-R_34_667m a b
-Ccap@0 gnd net@14 1.049f
-Ccap@1 gnd net@8 1.049f
-Ccap@2 gnd net@11 1.049f
-Rres@0 net@14 a 1.653
-Rres@1 net@11 net@14 3.306
-Rres@2 b net@8 1.653
-Rres@3 net@8 net@11 3.306
-.ENDS wire-C_0_011f-286_1-R_34_667m
+.SUBCKT wire-C_0_011f-199_1-R_34_667m a b
+Ccap@0 gnd net@14 0.73f
+Ccap@1 gnd net@8 0.73f
+Ccap@2 gnd net@11 0.73f
+Rres@0 net@14 a 1.15
+Rres@1 net@11 net@14 2.301
+Rres@2 b net@8 1.15
+Rres@3 net@8 net@11 2.301
+.ENDS wire-C_0_011f-199_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-286_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-286_1-R_34_667m
-.ENDS wire90-286_1-layer_1-width_3
+.SUBCKT wire90-199_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-199_1-R_34_667m
+.ENDS wire90-199_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-358_1-R_34_667m a b
-Ccap@0 gnd net@14 1.313f
-Ccap@1 gnd net@8 1.313f
-Ccap@2 gnd net@11 1.313f
-Rres@0 net@14 a 2.069
-Rres@1 net@11 net@14 4.138
-Rres@2 b net@8 2.069
-Rres@3 net@8 net@11 4.138
-.ENDS wire-C_0_011f-358_1-R_34_667m
+.SUBCKT wire-C_0_011f-702_4-R_34_667m a b
+Ccap@0 gnd net@14 2.575f
+Ccap@1 gnd net@8 2.575f
+Ccap@2 gnd net@11 2.575f
+Rres@0 net@14 a 4.058
+Rres@1 net@11 net@14 8.117
+Rres@2 b net@8 4.058
+Rres@3 net@8 net@11 8.117
+.ENDS wire-C_0_011f-702_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-358_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-358_1-R_34_667m
-.ENDS wire90-358_1-layer_1-width_3
+.SUBCKT wire90-702_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-702_4-R_34_667m
+.ENDS wire90-702_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-415_1-R_34_667m a b
-Ccap@0 gnd net@14 1.522f
-Ccap@1 gnd net@8 1.522f
-Ccap@2 gnd net@11 1.522f
-Rres@0 net@14 a 2.398
-Rres@1 net@11 net@14 4.797
-Rres@2 b net@8 2.398
-Rres@3 net@8 net@11 4.797
-.ENDS wire-C_0_011f-415_1-R_34_667m
+.SUBCKT wire-C_0_011f-251_7-R_34_667m a b
+Ccap@0 gnd net@14 0.923f
+Ccap@1 gnd net@8 0.923f
+Ccap@2 gnd net@11 0.923f
+Rres@0 net@14 a 1.454
+Rres@1 net@11 net@14 2.909
+Rres@2 b net@8 1.454
+Rres@3 net@8 net@11 2.909
+.ENDS wire-C_0_011f-251_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-415_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-415_1-R_34_667m
-.ENDS wire90-415_1-layer_1-width_3
-
-*** CELL: predicateM:ohSRxor6x12{sch}
-.SUBCKT ohSRxor6x12 all any flag[A][clr] flag[A][set] flag[B][clr]
-+flag[B][set] flag[D][clr] flag[D][set] in[1][F] in[1][T] in[2][F] in[2][T]
-+in[3][F] in[3][T] in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T]
-+resetLO
-Xnand3in6@3 match[12T] match[34T] match[56T] any nand3in6_6sym
-Xnor3in3_@2 match[12F] match[34F] match[56F] all nor3in6_6sym
-XohSRxor@6 flag[A][clr] flag[A][set] net@106 resetLO in[1][T] in[2][T]
-+ohSRxor
-XohSRxor@7 flag[A][clr] flag[A][set] net@107 resetLO in[1][F] in[2][F]
-+ohSRxor
-XohSRxor@8 flag[B][clr] flag[B][set] net@125 resetLO in[3][F] in[4][F]
-+ohSRxor
-XohSRxor@9 flag[B][clr] flag[B][set] net@122 resetLO in[3][T] in[4][T]
-+ohSRxor
-XohSRxor@10 flag[D][clr] flag[D][set] net@177 resetLO in[5][F] in[6][F]
-+ohSRxor
-XohSRxor@11 flag[D][clr] flag[D][set] net@178 resetLO in[5][T] in[6][T]
-+ohSRxor
-Xwire90@1 match[34T] net@122 wire90-395_6-layer_1-width_3
-Xwire90@3 match[56T] net@178 wire90-313_6-layer_1-width_3
-Xwire90@4 net@107 match[12F] wire90-339-layer_1-width_3
-Xwire90@5 match[12T] net@106 wire90-286_1-layer_1-width_3
-Xwire90@6 match[34F] net@125 wire90-358_1-layer_1-width_3
-Xwire90@7 net@177 match[56F] wire90-415_1-layer_1-width_3
-.ENDS ohSRxor6x12
+.SUBCKT wire90-251_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-251_7-R_34_667m
+.ENDS wire90-251_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-625_1-R_34_667m a b
-Ccap@0 gnd net@14 2.292f
-Ccap@1 gnd net@8 2.292f
-Ccap@2 gnd net@11 2.292f
-Rres@0 net@14 a 3.612
-Rres@1 net@11 net@14 7.223
-Rres@2 b net@8 3.612
-Rres@3 net@8 net@11 7.223
-.ENDS wire-C_0_011f-625_1-R_34_667m
+.SUBCKT wire-C_0_011f-377-R_34_667m a b
+Ccap@0 gnd net@14 1.382f
+Ccap@1 gnd net@8 1.382f
+Ccap@2 gnd net@11 1.382f
+Rres@0 net@14 a 2.178
+Rres@1 net@11 net@14 4.356
+Rres@2 b net@8 2.178
+Rres@3 net@8 net@11 4.356
+.ENDS wire-C_0_011f-377-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-625_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-625_1-R_34_667m
-.ENDS wire90-625_1-layer_1-width_3
+.SUBCKT wire90-377-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-377-R_34_667m
+.ENDS wire90-377-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-215_4-R_34_667m a b
-Ccap@0 gnd net@14 0.79f
-Ccap@1 gnd net@8 0.79f
-Ccap@2 gnd net@11 0.79f
-Rres@0 net@14 a 1.245
-Rres@1 net@11 net@14 2.489
-Rres@2 b net@8 1.245
-Rres@3 net@8 net@11 2.489
-.ENDS wire-C_0_011f-215_4-R_34_667m
+.SUBCKT wire-C_0_011f-593_4-R_34_667m a b
+Ccap@0 gnd net@14 2.176f
+Ccap@1 gnd net@8 2.176f
+Ccap@2 gnd net@11 2.176f
+Rres@0 net@14 a 3.429
+Rres@1 net@11 net@14 6.857
+Rres@2 b net@8 3.429
+Rres@3 net@8 net@11 6.857
+.ENDS wire-C_0_011f-593_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-215_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-215_4-R_34_667m
-.ENDS wire90-215_4-layer_1-width_3
-
-*** CELL: predicateM:ohPredPred{sch}
-.SUBCKT ohPredPred any do fire[both] flag[A][clr] flag[A][set] flag[B][clr]
-+flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] mc resetLO s[1] s[2]
-Xinv@0 net@51 resetLO inv-X_10
-Xinv@2 fire[both] net@54 inv-X_10
-XinvI@0 net@18 net@49 inv-X_5
-XinvI@1 net@66 s[1] inv-X_10
-XinvI@2 net@71 s[2] inv-X_10
-Xnor2_sy@2 m1cate[1][F] m1cate[1][T] net@62 nor2_sy-X_5
-Xnor2_sy@3 flag[A][clr] flag[A][set] net@67 nor2_sy-X_5
-XohSRxor6@1 do any flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
-+flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T]
-+m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T]
-+m1cate[6][F] m1cate[6][T] net@18 ohSRxor6x12
-Xpp[1] fire[both] mc m1cate[1][T] predDri20wMC
-Xpp[2] fire[both] mc m1cate[1][F] predDri20wMC
-Xpp[3] fire[both] mc m1cate[2][T] predDri20wMC
-Xpp[4] fire[both] mc m1cate[2][F] predDri20wMC
-Xpp[5] fire[both] mc m1cate[3][T] predDri20wMC
-Xpp[6] fire[both] mc m1cate[3][F] predDri20wMC
-Xpp[7] fire[both] mc m1cate[4][T] predDri20wMC
-Xpp[8] fire[both] mc m1cate[4][F] predDri20wMC
-Xpp[9] fire[both] mc m1cate[5][T] predDri20wMC
-Xpp[10] fire[both] mc m1cate[5][F] predDri20wMC
-Xpp[11] fire[both] mc m1cate[6][T] predDri20wMC
-Xpp[12] fire[both] mc m1cate[6][F] predDri20wMC
-Xwire90@1 net@54 net@18 wire90-625_1-layer_1-width_3
-Xwire90@3 net@49 net@51 wire90-142_6-layer_1-width_3
-Xwire90@4 net@62 net@66 wire90-215_4-layer_1-width_3
-Xwire90@5 net@67 net@71 wire90-215_4-layer_1-width_3
-.ENDS ohPredPred
+.SUBCKT wire90-593_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-593_4-R_34_667m
+.ENDS wire90-593_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-556_1-R_34_667m a b
-Ccap@0 gnd net@14 2.039f
-Ccap@1 gnd net@8 2.039f
-Ccap@2 gnd net@11 2.039f
-Rres@0 net@14 a 3.213
-Rres@1 net@11 net@14 6.426
-Rres@2 b net@8 3.213
-Rres@3 net@8 net@11 6.426
-.ENDS wire-C_0_011f-556_1-R_34_667m
+.SUBCKT wire-C_0_011f-1158_7-R_34_667m a b
+Ccap@0 gnd net@14 4.249f
+Ccap@1 gnd net@8 4.249f
+Ccap@2 gnd net@11 4.249f
+Rres@0 net@14 a 6.695
+Rres@1 net@11 net@14 13.389
+Rres@2 b net@8 6.695
+Rres@3 net@8 net@11 13.389
+.ENDS wire-C_0_011f-1158_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-556_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-556_1-R_34_667m
-.ENDS wire90-556_1-layer_1-width_3
+.SUBCKT wire90-1158_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1158_7-R_34_667m
+.ENDS wire90-1158_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-557-R_34_667m a b
-Ccap@0 gnd net@14 2.042f
-Ccap@1 gnd net@8 2.042f
-Ccap@2 gnd net@11 2.042f
-Rres@0 net@14 a 3.218
-Rres@1 net@11 net@14 6.436
-Rres@2 b net@8 3.218
-Rres@3 net@8 net@11 6.436
-.ENDS wire-C_0_011f-557-R_34_667m
+.SUBCKT wire-C_0_011f-487_9-R_34_667m a b
+Ccap@0 gnd net@14 1.789f
+Ccap@1 gnd net@8 1.789f
+Ccap@2 gnd net@11 1.789f
+Rres@0 net@14 a 2.819
+Rres@1 net@11 net@14 5.638
+Rres@2 b net@8 2.819
+Rres@3 net@8 net@11 5.638
+.ENDS wire-C_0_011f-487_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-557-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-557-R_34_667m
-.ENDS wire90-557-layer_1-width_3
+.SUBCKT wire90-487_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-487_9-R_34_667m
+.ENDS wire90-487_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-318_8-R_34_667m a b
-Ccap@0 gnd net@14 1.169f
-Ccap@1 gnd net@8 1.169f
-Ccap@2 gnd net@11 1.169f
-Rres@0 net@14 a 1.842
-Rres@1 net@11 net@14 3.684
-Rres@2 b net@8 1.842
-Rres@3 net@8 net@11 3.684
-.ENDS wire-C_0_011f-318_8-R_34_667m
+.SUBCKT wire-C_0_011f-214_3-R_34_667m a b
+Ccap@0 gnd net@14 0.786f
+Ccap@1 gnd net@8 0.786f
+Ccap@2 gnd net@11 0.786f
+Rres@0 net@14 a 1.238
+Rres@1 net@11 net@14 2.476
+Rres@2 b net@8 1.238
+Rres@3 net@8 net@11 2.476
+.ENDS wire-C_0_011f-214_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-318_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-318_8-R_34_667m
-.ENDS wire90-318_8-layer_1-width_3
+.SUBCKT wire90-214_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-214_3-R_34_667m
+.ENDS wire90-214_3-layer_1-width_3
+
+*** CELL: oneHotM:reQueueC{sch}
+.SUBCKT reQueueC circulate epi[OTHER] fire[E] fire[R] mc od[ABORT] od[OTHER]
++ps[do] ps[skip] s[1] s[2] succ
+XctrAND3i@0 succ net@361 circulate fire[E] ctrAND3in30
+Xinv@12 net@377 abortLO inv-X_10
+Xinv@13 epi[OTHER] net@440 inv-X_5
+Xinv@14 circulate net@320 inv-X_10
+XinvI@10 net@309 net@376 inv-X_5
+XinvI@11 net@394 net@396 inv-X_10
+XinvI@12 net@440 s[2] inv-X_10
+XinvI@13 net@320 s[1] inv-X_10
+Xnand2_sy@1 od[OTHER] ps[skip] net@274 nand2_sy-X_6
+Xnand2_sy@2 od[ABORT] ps[skip] net@277 nand2_sy-X_6
+Xnand2_sy@3 od[OTHER] ps[do] net@280 nand2_sy-X_6
+Xnand2_sy@4 od[ABORT] ps[do] net@283 nand2_sy-X_6
+Xnand2_sy@5 net@313 net@311 net@324 nand2_sy-X_6
+Xnand2n@0 circulate succ net@315 nand2n-X_5
+Xnand2n_s@0 net@324 abortLO fire[C] nand2n_sy-X_20
+Xnand3in6@1 net@303 net@418 net@306 net@420 nand3in6_6sym
+Xnor2n@1 net@326 net@322 fire[R] nor2n-X_10
+XpredDri2@2 net@243 mc od[ABORT] predDri20wMC
+XpredDri2@3 net@243 mc od[OTHER] predDri20wMC
+XpredDri2@4 net@243 mc ps[do] predDri20wMC
+XpredDri2@5 net@243 mc ps[skip] predDri20wMC
+XpredDri2@6 fire[E] mc epi[OTHER] predDri20wMC
+XpredDri2@7 net@399 mc circulate predDri20wMC
+XsucORdri@0 fire[R] fire[E] succ sucORdri20
+Xwire90@12 net@274 net@303 wire90-286_3-layer_1-width_3
+Xwire90@13 net@277 net@418 wire90-428_8-layer_1-width_3
+Xwire90@14 net@280 net@306 wire90-356_7-layer_1-width_3
+Xwire90@15 net@283 net@309 wire90-199_1-layer_1-width_3
+Xwire90@16 net@420 net@311 wire90-702_4-layer_1-width_3
+Xwire90@17 net@313 net@315 wire90-251_7-layer_1-width_3
+Xwire90@18 net@322 net@320 wire90-377-layer_1-width_3
+Xwire90@19 net@324 net@326 wire90-593_4-layer_1-width_3
+Xwire90@20 net@243 fire[C] wire90-1158_7-layer_1-width_3
+Xwire90@23 net@376 net@377 wire90-142_6-layer_1-width_3
+Xwire90@24 abortLO net@394 wire90-487_9-layer_1-width_3
+Xwire90@25 net@396 net@399 wire90-214_3-layer_1-width_3
+Xwire90@27 net@361 net@440 wire90-142_6-layer_1-width_3
+.ENDS reQueueC
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1035_5-R_34_667m a b
-Ccap@0 gnd net@14 3.797f
-Ccap@1 gnd net@8 3.797f
-Ccap@2 gnd net@11 3.797f
-Rres@0 net@14 a 5.983
-Rres@1 net@11 net@14 11.966
-Rres@2 b net@8 5.983
-Rres@3 net@8 net@11 11.966
-.ENDS wire-C_0_011f-1035_5-R_34_667m
+.SUBCKT wire-C_0_011f-1041_2-R_34_667m a b
+Ccap@0 gnd net@14 3.818f
+Ccap@1 gnd net@8 3.818f
+Ccap@2 gnd net@11 3.818f
+Rres@0 net@14 a 6.016
+Rres@1 net@11 net@14 12.032
+Rres@2 b net@8 6.016
+Rres@3 net@8 net@11 12.032
+.ENDS wire-C_0_011f-1041_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1035_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1035_5-R_34_667m
-.ENDS wire90-1035_5-layer_1-width_3
+.SUBCKT wire90-1041_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1041_2-R_34_667m
+.ENDS wire90-1041_2-layer_1-width_3
+
+*** CELL: oneHotM:reQueue{sch}
+.SUBCKT reQueue epi[OTHER] epi[TAIL] fire[E] fire[R] mc od[ABORT] od[HEAD]
++od[OTHER] ps[do] ps[skip] rq[succ] s[1] s[2] s[3] s[4]
+XreQueueB@1 circulate epi[TAIL] mc od[HEAD] s[1] s[2] reQueueB
+XreQueueC@0 net@3 epi[OTHER] fire[E] fire[R] mc od[ABORT] od[OTHER] ps[do]
++ps[skip] s[3] s[4] rq[succ] reQueueC
+Xwire90@0 circulate net@3 wire90-1041_2-layer_1-width_3
+.ENDS reQueue
+
+*** CELL: scanM:scanEx3plain{sch}
+.SUBCKT scanEx3plain dIn[1] dIn[2] dIn[3] sin sir[2] sir[3] sir[5] sout
+XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sin net@26 scanM__scanCellE
+XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanM__scanCellE
+XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sout scanM__scanCellE
+Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
+Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3
+.ENDS scanEx3plain
+
+*** CELL: stagesM:rqDockStage{sch}
+.SUBCKT rqDockStage epi[OTHER] epi[TAIL] inE[10] inE[11] inE[12] inE[13]
++inE[14] inE[15] inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21]
++inE[22] inE[23] inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2]
++inE[30] inE[31] inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5]
++inE[6] inE[7] inE[8] inE[9] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15]
++inP[16] inP[17] inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23]
++inP[24] inP[25] inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31]
++inP[32] inP[33] inP[34] inP[35] inP[36] inP[3] inP[4] inP[5] inP[6] inP[7]
++inP[8] inP[9] od[ABORT] od[HEAD] od[OTHER] ps[do] ps[skip] rq[10] rq[11]
++rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] rq[20] rq[21]
++rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] rq[30] rq[31]
++rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9]
++rq[succ] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
++sor[1] take[E] take[P]
+Xins2in20@0 take[E] take[P] inE[10] inE[11] inE[12] inE[13] inE[14] inE[15]
++inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] inE[23]
++inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] inE[31]
++inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7]
++inE[8] inE[9] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15] inP[16] inP[17]
++inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23] inP[24] inP[25]
++inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31] inP[32] inP[33]
++inP[34] inP[35] inP[36] inP[3] inP[4] inP[5] inP[6] inP[7] inP[8] inP[9]
++rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1]
++rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2]
++rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6]
++rq[7] rq[8] rq[9] ins2in20Ax36
+XlatchDri@0 net@3 take[E] latchDriver60
+XlatchDri@1 net@7 take[P] latchDriver60
+XreQueue@0 epi[OTHER] epi[TAIL] fire[E] fire[R] sir[9] od[ABORT] od[HEAD]
++od[OTHER] ps[do] ps[skip] rq[succ] s[1] s[2] s[3] s[4] reQueue
+XscanEx1v@0 s[1] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sin scanEx1vertA
+XscanEx3p@1 s[2] s[3] s[4] sin sir[2] sir[3] sir[5] sor[1] scanEx3plain
+Xwire90@0 net@7 fire[R] wire90-1336_2-layer_1-width_3
+Xwire90@1 net@3 fire[E] wire90-1307-layer_1-width_3
+.ENDS rqDockStage
+
+*** CELL: stageGroupsM:epiRQod{sch}
+.SUBCKT epiRQod do[epi] do[od] epi[TORP] flag[A][clr] flag[A][set]
++flag[D][clr] flag[D][set] in[10] in[11] in[12] in[13] in[14] in[15] in[16]
++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
++in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] m1[10] m1[11] m1[12] m1[13]
++m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23]
++m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33]
++m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ps[do]
++ps[skip] rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18]
++rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28]
++rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4]
++rq[5] rq[6] rq[7] rq[8] rq[9] rq[succ] sir[1] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sir[9] sor[1]
+XepiDockS@0 do[epi] net@45[26] net@45[25] net@45[24] net@45[23] net@45[22]
++net@45[21] net@45[20] net@45[19] net@45[18] net@45[17] net@45[35] net@45[16]
++net@45[15] net@45[14] net@45[13] net@45[12] net@45[11] net@45[10] net@45[9]
++net@45[8] net@45[7] net@45[34] net@45[6] net@45[5] net@45[4] net@45[3]
++net@45[2] net@45[1] net@45[0] net@45[33] net@45[32] net@45[31] net@45[30]
++net@45[29] net@45[28] net@45[27] epi[OTHER] epi[TAIL] epi[TORP] in[10] in[11]
++in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21]
++in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31]
++in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9]
++in[T] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@0[8]
++take[epi] epiDockStage
+XonDeckDo@0 do[od] flag[A][clr] flag[A][set] flag[D][clr] flag[D][set] m1[10]
++m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20]
++m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30]
++m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8]
++m1[9] net@46[26] net@46[25] net@46[24] net@46[23] net@46[22] net@46[21]
++net@46[20] net@46[19] net@46[18] net@46[17] net@46[35] net@46[16] net@46[15]
++net@46[14] net@46[13] net@46[12] net@46[11] net@46[10] net@46[9] net@46[8]
++net@46[7] net@46[34] net@46[6] net@46[5] net@46[4] net@46[3] net@46[2]
++net@46[1] net@46[0] net@46[33] net@46[32] net@46[31] net@46[30] net@46[29]
++net@46[28] net@46[27] od[ABORT] od[HEAD] od[OTHER] net@36[8] sir[2] sir[3]
++sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] take[od] onDeckDockStage
+XrqDockSt@0 epi[OTHER] epi[TAIL] net@45[26] net@45[25] net@45[24] net@45[23]
++net@45[22] net@45[21] net@45[20] net@45[19] net@45[18] net@45[17] net@45[35]
++net@45[16] net@45[15] net@45[14] net@45[13] net@45[12] net@45[11] net@45[10]
++net@45[9] net@45[8] net@45[7] net@45[34] net@45[6] net@45[5] net@45[4]
++net@45[3] net@45[2] net@45[1] net@45[0] net@45[33] net@45[32] net@45[31]
++net@45[30] net@45[29] net@45[28] net@45[27] net@46[26] net@46[25] net@46[24]
++net@46[23] net@46[22] net@46[21] net@46[20] net@46[19] net@46[18] net@46[17]
++net@46[35] net@46[16] net@46[15] net@46[14] net@46[13] net@46[12] net@46[11]
++net@46[10] net@46[9] net@46[8] net@46[7] net@46[34] net@46[6] net@46[5]
++net@46[4] net@46[3] net@46[2] net@46[1] net@46[0] net@46[33] net@46[32]
++net@46[31] net@46[30] net@46[29] net@46[28] net@46[27] od[ABORT] od[HEAD]
++od[OTHER] ps[do] ps[skip] rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16]
++rq[17] rq[18] rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26]
++rq[27] rq[28] rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36]
++rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9] rq[succ] net@0[8] sir[2] sir[3]
++sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@36[8] take[E] take[P]
++rqDockStage
+.ENDS epiRQod
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-945_6-R_34_667m a b
-Ccap@0 gnd net@14 3.467f
-Ccap@1 gnd net@8 3.467f
-Ccap@2 gnd net@11 3.467f
-Rres@0 net@14 a 5.463
-Rres@1 net@11 net@14 10.927
-Rres@2 b net@8 5.463
-Rres@3 net@8 net@11 10.927
-.ENDS wire-C_0_011f-945_6-R_34_667m
+.SUBCKT wire-C_0_011f-161_8-R_34_667m a b
+Ccap@0 gnd net@14 0.593f
+Ccap@1 gnd net@8 0.593f
+Ccap@2 gnd net@11 0.593f
+Rres@0 net@14 a 0.935
+Rres@1 net@11 net@14 1.87
+Rres@2 b net@8 0.935
+Rres@3 net@8 net@11 1.87
+.ENDS wire-C_0_011f-161_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-945_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-945_6-R_34_667m
-.ENDS wire90-945_6-layer_1-width_3
+.SUBCKT wire90-161_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-161_8-R_34_667m
+.ENDS wire90-161_8-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1126_1-R_34_667m a b
-Ccap@0 gnd net@14 4.129f
-Ccap@1 gnd net@8 4.129f
-Ccap@2 gnd net@11 4.129f
-Rres@0 net@14 a 6.506
-Rres@1 net@11 net@14 13.013
-Rres@2 b net@8 6.506
-Rres@3 net@8 net@11 13.013
-.ENDS wire-C_0_011f-1126_1-R_34_667m
+*** CELL: centersJ:ctrAND2in30A{sch}
+.SUBCKT ctrAND2in30A inA inB out
+Xinv@1 net@9 out inv-X_30
+Xinv@2 inA net@27 inv-X_5
+Xnand2LT_@0 net@32 inB net@24 nand2LT_sy-X_10
+Xwire90@0 net@27 net@32 wire90-161_8-layer_1-width_3
+Xwire90@1 net@24 net@9 wire90-372_8-layer_1-width_3
+.ENDS ctrAND2in30A
+
+*** CELL: gaspM:gaspLit{sch}
+.SUBCKT gaspLit do[L] fire[L] mc ready s[1]
+XctrAND2i@0 net@189 ready fire[L] ctrAND2in30A
+Xinv@1 do[L] net@190 inv-X_5
+XinvI@0 net@189 s[1] inv-X_10
+XpredDri2@1 fire[L] mc do[L] predDri20wMC
+Xwire90@1 net@190 net@189 wire90-414-layer_1-width_3
+.ENDS gaspLit
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1126_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1126_1-R_34_667m
-.ENDS wire90-1126_1-layer_1-width_3
+*** CELL: driversJ:latchAndDriver60{sch}
+.SUBCKT latchAndDriver60 inA inB out
+Xinv@0 net@8 out inv-X_60
+Xnand2@0 inA inB net@26 nand2-X_20
+Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3
+.ENDS latchAndDriver60
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-361_6-R_34_667m a b
-Ccap@0 gnd net@14 1.326f
-Ccap@1 gnd net@8 1.326f
-Ccap@2 gnd net@11 1.326f
-Rres@0 net@14 a 2.089
-Rres@1 net@11 net@14 4.178
-Rres@2 b net@8 2.089
-Rres@3 net@8 net@11 4.178
-.ENDS wire-C_0_011f-361_6-R_34_667m
+.SUBCKT wire-C_0_011f-387_3-R_34_667m a b
+Ccap@0 gnd net@14 1.42f
+Ccap@1 gnd net@8 1.42f
+Ccap@2 gnd net@11 1.42f
+Rres@0 net@14 a 2.238
+Rres@1 net@11 net@14 4.475
+Rres@2 b net@8 2.238
+Rres@3 net@8 net@11 4.475
+.ENDS wire-C_0_011f-387_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-361_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-361_6-R_34_667m
-.ENDS wire90-361_6-layer_1-width_3
+.SUBCKT wire90-387_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-387_3-R_34_667m
+.ENDS wire90-387_3-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2526_6-R_34_667m a b
-Ccap@0 gnd net@14 9.264f
-Ccap@1 gnd net@8 9.264f
-Ccap@2 gnd net@11 9.264f
-Rres@0 net@14 a 14.598
-Rres@1 net@11 net@14 29.196
-Rres@2 b net@8 14.598
-Rres@3 net@8 net@11 29.196
-.ENDS wire-C_0_011f-2526_6-R_34_667m
+*** CELL: driversJ:latchAndDriver30{sch}
+.SUBCKT latchAndDriver30 inA inB out
+Xinv@0 net@8 out inv-X_30
+Xnand2@0 inA inB net@26 nand2-X_10
+Xwire90@0 net@26 net@8 wire90-387_3-layer_1-width_3
+.ENDS latchAndDriver30
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2526_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2526_6-R_34_667m
-.ENDS wire90-2526_6-layer_1-width_3
+*** CELL: loopCountM:mux10/2{sch}
+.SUBCKT mux10/2 in[1] out[1] sF sT
+Xnms2b@0 out[1] sT in[1] nms2-X_10
+Xpms2@0 out[1] sF in[1] pms2-X_10
+.ENDS mux10/2
-*** CELL: predicateM:ohPredAll{sch}
-.SUBCKT ohPredAll do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr]
-+flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p
-+ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD]
-+sin sout
-XbitAssig@0 bitAssignments
-XinvI@0 net@82 fire[do] inv-X_40
-XinvI@1 net@63 fire[skip] inv-X_10
-Xnand2_sy@0 net@94 net@11 net@63 nand2_sy-X_10
-Xnand2n_s@0 net@147 net@84 fire[both] nand2n_sy-X_30
-Xnand3in2@1 net@46 net@41 net@11 net@82 net@21 nand3in20sr
-Xnor2n_sy@0 ps[skip] ps[do] net@39 nor2n_sy-X_5
-Xnor2n_sy@2 do[Lt] do[Mv] net@38 nor2n_sy-X_5
-XohPredDo@1 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] net@149 flag[A][clr]
-+flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] mc ps[do]
-+ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] ohPredDo
-XohPredPr@1 net@92 net@139 net@160 flag[A][clr] flag[A][set] flag[B][clr]
-+flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] mc net@19 s[1] s[2] ohPredPred
-XscanEx2h@0 s[1] s[2] mc p1p p2p rd sin sout scanEx2h
-Xwire90@0 net@39 net@11 wire90-556_1-layer_1-width_3
-Xwire90@1 net@38 net@41 wire90-557-layer_1-width_3
-Xwire90@2 net@46 net@139 wire90-775_9-layer_1-width_3
-Xwire90@3 net@21 net@19 wire90-318_8-layer_1-width_3
-Xwire90@4 net@82 net@84 wire90-1035_5-layer_1-width_3
-Xwire90@5 net@147 net@63 wire90-945_6-layer_1-width_3
-Xwire90@6 net@92 net@94 wire90-1126_1-layer_1-width_3
-Xwire90@7 net@149 fire[skip] wire90-361_6-layer_1-width_3
-Xwire90@9 fire[both] net@160 wire90-2526_6-layer_1-width_3
-.ENDS ohPredAll
+*** CELL: loopCountM:mux10/2x7{sch}
+.SUBCKT mux10/2x7 in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2]
++out[3] out[4] out[5] out[6] out[7] sF sT
+Xmux10/2@0 in[1] out[1] sF sT mux10/2
+Xmux10/2@1 in[2] out[2] sF sT mux10/2
+Xmux10/2@2 in[3] out[3] sF sT mux10/2
+Xmux10/2@3 in[4] out[4] sF sT mux10/2
+Xmux10/2@4 in[5] out[5] sF sT mux10/2
+Xmux10/2@5 in[6] out[6] sF sT mux10/2
+Xmux10/2@6 in[7] out[7] sF sT mux10/2
+.ENDS mux10/2x7
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b
-Ccap@0 gnd net@14 6.469f
-Ccap@1 gnd net@8 6.469f
-Ccap@2 gnd net@11 6.469f
-Rres@0 net@14 a 10.194
-Rres@1 net@11 net@14 20.389
-Rres@2 b net@8 10.194
-Rres@3 net@8 net@11 20.389
-.ENDS wire-C_0_011f-1764_4-R_34_667m
+.SUBCKT wire-C_0_011f-704_3-R_34_667m a b
+Ccap@0 gnd net@14 2.582f
+Ccap@1 gnd net@8 2.582f
+Ccap@2 gnd net@11 2.582f
+Rres@0 net@14 a 4.069
+Rres@1 net@11 net@14 8.139
+Rres@2 b net@8 4.069
+Rres@3 net@8 net@11 8.139
+.ENDS wire-C_0_011f-704_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1764_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m
-.ENDS wire90-1764_4-layer_1-width_3
+.SUBCKT wire90-704_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-704_3-R_34_667m
+.ENDS wire90-704_3-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b
-Ccap@0 gnd net@14 5.036f
-Ccap@1 gnd net@8 5.036f
-Ccap@2 gnd net@11 5.036f
-Rres@0 net@14 a 7.935
-Rres@1 net@11 net@14 15.87
-Rres@2 b net@8 7.935
-Rres@3 net@8 net@11 15.87
-.ENDS wire-C_0_011f-1373_4-R_34_667m
+*** CELL: loopCountM:muxForD{sch}
+.SUBCKT muxForD in[1] in[2] in[3] in[4] in[5] in[6] out[1] out[2] out[3]
++out[4] out[5] out[6] out[7] sel
+Xinv@0 sel net@0 inv-X_20
+Xinv@1 sF net@1 inv-X_20
+Xmux10/2x@0 in[1] in[2] in[3] in[4] in[5] in[6] gnd out[1] out[2] out[3]
++out[4] out[5] out[6] out[7] sF sT mux10/2x7
+Xwire90@0 net@0 sF wire90-704_3-layer_1-width_3
+Xwire90@1 net@1 sT wire90-704_3-layer_1-width_3
+.ENDS muxForD
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1373_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m
-.ENDS wire90-1373_4-layer_1-width_3
+*** CELL: registersM:data2in60Cx18{sch}
+.SUBCKT data2in60Cx18 dcl[A] dcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
++inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6]
++inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16]
++inB[17] inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
++inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
++out[18] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
+XhiL[1] dcl[A] dcl[B] inA[1] inB[1] out[1] latch2in60C
+XhiL[2] dcl[A] dcl[B] inA[2] inB[2] out[2] latch2in60C
+XhiL[3] dcl[A] dcl[B] inA[3] inB[3] out[3] latch2in60C
+XhiL[4] dcl[A] dcl[B] inA[4] inB[4] out[4] latch2in60C
+XhiL[5] dcl[A] dcl[B] inA[5] inB[5] out[5] latch2in60C
+XhiL[6] dcl[A] dcl[B] inA[6] inB[6] out[6] latch2in60C
+XhiL[7] dcl[A] dcl[B] inA[7] inB[7] out[7] latch2in60C
+XhiL[8] dcl[A] dcl[B] inA[8] inB[8] out[8] latch2in60C
+XhiL[9] dcl[A] dcl[B] inA[9] inB[9] out[9] latch2in60C
+XhiL[10] dcl[A] dcl[B] inA[10] inB[10] out[10] latch2in60C
+XhiL[11] dcl[A] dcl[B] inA[11] inB[11] out[11] latch2in60C
+XhiL[12] dcl[A] dcl[B] inA[12] inB[12] out[12] latch2in60C
+XhiL[13] dcl[A] dcl[B] inA[13] inB[13] out[13] latch2in60C
+XhiL[14] dcl[A] dcl[B] inA[14] inB[14] out[14] latch2in60C
+XhiL[15] dcl[A] dcl[B] inA[15] inB[15] out[15] latch2in60C
+XhiL[16] dcl[A] dcl[B] inA[16] inB[16] out[16] latch2in60C
+XhiL[17] dcl[A] dcl[B] inA[17] inB[17] out[17] latch2in60C
+XhiL[18] dcl[A] dcl[B] inA[18] inB[18] out[18] latch2in60C
+.ENDS data2in60Cx18
-*** CELL: loopCountM:olcEven{sch}
-.SUBCKT olcEven bit[2] bit[4] bit[6] count[T] do[2] do[4] do[6] inLO[2]
-+inLO[4] inLO[6] load[T]
-Xinv@2 count[T] net@210 inv-X_30
-Xinv@3 load[T] net@211 inv-X_30
-XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
-XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
-XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
-Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3
-Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3
-.ENDS olcEven
+*** CELL: registersM:data2in60Cx37{sch}
+.SUBCKT data2in60Cx37 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] inA[16]
++inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] inA[24]
++inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] inA[32]
++inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] inA[5] inA[6] inA[7]
++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
++inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
++inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33]
++inB[34] inB[35] inB[36] inB[37] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
++inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
++out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25]
++out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33]
++out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8]
++out[9] take[A] take[B]
+Xdata2in6@1 take[A2] take[B2] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
++inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inA[7]
++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
++inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
++out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] data2in60Cx18
+Xdata2in6@2 take[A1] take[B1] inA[29] inA[30] inA[31] inA[32] inA[33] inA[34]
++inA[35] inA[36] inA[37] inA[20] inA[21] inA[22] inA[23] inA[24] inA[25]
++inA[26] inA[27] inA[28] inB[29] inB[30] inB[31] inB[32] inB[33] inB[34]
++inB[35] inB[36] inB[37] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
++inB[26] inB[27] inB[28] out[29] out[30] out[31] out[32] out[33] out[34]
++out[35] out[36] out[37] out[20] out[21] out[22] out[23] out[24] out[25]
++out[26] out[27] out[28] data2in60Cx18
+Xlatch2in@4 take[A] take[B] inA[19] inB[19] out[19] latch2in60C
+Xwire90@0 take[A] take[A2] wire90-2550-layer_1-width_3
+Xwire90@4 take[B] take[B2] wire90-2550-layer_1-width_3
+Xwire90@5 take[B] take[B1] wire90-2550-layer_1-width_3
+Xwire90@6 take[A] take[A1] wire90-2550-layer_1-width_3
+.ENDS data2in60Cx37
-*** CELL: loopCountM:olcOdd{sch}
-.SUBCKT olcOdd bit[1] bit[3] bit[5] count[T] do[3] do[5] inLO[1] inLO[3]
-+inLO[5] load[T]
-Xinv@2 load[T] net@307 inv-X_30
-Xinv@3 count[T] net@310 inv-X_30
-XringB@3 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB
-XringB@4 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB
-XringB@5 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB
-Xwire90@2 net@307 load[F] wire90-1373_4-layer_1-width_3
-Xwire90@3 net@310 count[F] wire90-1764_4-layer_1-width_3
-.ENDS olcOdd
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_9_6 d g s
+MNMOSf@0 d g s gnd nch W='28.8*(1+ABN/sqrt(28.8*2))' L='2'
++DELVTO='AVT0N/sqrt(28.8*2)'
+.ENDS NMOSx-X_9_6
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-380_7-R_34_667m a b
-Ccap@0 gnd net@14 1.396f
-Ccap@1 gnd net@8 1.396f
-Ccap@2 gnd net@11 1.396f
-Rres@0 net@14 a 2.2
-Rres@1 net@11 net@14 4.399
-Rres@2 b net@8 2.2
-Rres@3 net@8 net@11 4.399
-.ENDS wire-C_0_011f-380_7-R_34_667m
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_9_6 d g s
+MPMOSf@0 d g s vdd pch W='57.6*(1+ABP/sqrt(57.6*2))' L='2'
++DELVTO='AVT0P/sqrt(57.6*2)'
+.ENDS PMOSx-X_9_6
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-380_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-380_7-R_34_667m
-.ENDS wire90-380_7-layer_1-width_3
+*** CELL: redFive:inv{sch}
+.SUBCKT inv-X_9_6 in out
+XNMOS@0 out in gnd NMOSx-X_9_6
+XPMOS@0 out in vdd PMOSx-X_9_6
+.ENDS inv-X_9_6
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-544_8-R_34_667m a b
-Ccap@0 gnd net@14 1.998f
-Ccap@1 gnd net@8 1.998f
-Ccap@2 gnd net@11 1.998f
-Rres@0 net@14 a 3.148
-Rres@1 net@11 net@14 6.295
-Rres@2 b net@8 3.148
-Rres@3 net@8 net@11 6.295
-.ENDS wire-C_0_011f-544_8-R_34_667m
+.SUBCKT wire-C_0_011f-277_3-R_34_667m a b
+Ccap@0 gnd net@14 1.017f
+Ccap@1 gnd net@8 1.017f
+Ccap@2 gnd net@11 1.017f
+Rres@0 net@14 a 1.602
+Rres@1 net@11 net@14 3.204
+Rres@2 b net@8 1.602
+Rres@3 net@8 net@11 3.204
+.ENDS wire-C_0_011f-277_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-544_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-544_8-R_34_667m
-.ENDS wire90-544_8-layer_1-width_3
+.SUBCKT wire90-277_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-277_3-R_34_667m
+.ENDS wire90-277_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-478_3-R_34_667m a b
-Ccap@0 gnd net@14 1.754f
-Ccap@1 gnd net@8 1.754f
-Ccap@2 gnd net@11 1.754f
-Rres@0 net@14 a 2.764
-Rres@1 net@11 net@14 5.527
-Rres@2 b net@8 2.764
-Rres@3 net@8 net@11 5.527
-.ENDS wire-C_0_011f-478_3-R_34_667m
+.SUBCKT wire-C_0_011f-114_7-R_34_667m a b
+Ccap@0 gnd net@14 0.421f
+Ccap@1 gnd net@8 0.421f
+Ccap@2 gnd net@11 0.421f
+Rres@0 net@14 a 0.663
+Rres@1 net@11 net@14 1.325
+Rres@2 b net@8 0.663
+Rres@3 net@8 net@11 1.325
+.ENDS wire-C_0_011f-114_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-478_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-478_3-R_34_667m
-.ENDS wire90-478_3-layer_1-width_3
+.SUBCKT wire90-114_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-114_7-R_34_667m
+.ENDS wire90-114_7-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-554_3-R_34_667m a b
-Ccap@0 gnd net@14 2.032f
-Ccap@1 gnd net@8 2.032f
-Ccap@2 gnd net@11 2.032f
-Rres@0 net@14 a 3.203
-Rres@1 net@11 net@14 6.405
-Rres@2 b net@8 3.203
-Rres@3 net@8 net@11 6.405
-.ENDS wire-C_0_011f-554_3-R_34_667m
+*** CELL: latchesK:latch1in09.6Bi{sch}
+.SUBCKT latch1in09_6Bi hcl in[1] out[1]
+Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF
+Xinv@0 net@23 out[1] inv-X_9_6
+XinvLT@0 net@18 net@25 inv-X_4
+Xwire90@0 net@19 net@18 wire90-277_3-layer_1-width_3
+Xwire90@1 net@25 net@23 wire90-114_7-layer_1-width_3
+.ENDS latch1in09_6Bi
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-554_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-554_3-R_34_667m
-.ENDS wire90-554_3-layer_1-width_3
+*** CELL: redFive:triInv{sch}
+.SUBCKT triInv-X_5 en enB in out
+Xnms2@0 out in en nms2-X_5
+Xpms2@0 out in enB pms2-X_5
+.ENDS triInv-X_5
+
+*** CELL: gates2inM:mux5{sch}
+.SUBCKT mux5 inA[1] inB[1] out[1] s[F] s[T]
+XtriInv@0 s[T] s[F] inA[1] out[1] triInv-X_5
+XtriInv@1 s[F] s[T] inB[1] out[1] triInv-X_5
+.ENDS mux5
+
+*** CELL: latchGroupsK:dataMux{sch}
+.SUBCKT dataMux hcl inB[1] in[1] out[1] s[F] s[T]
+Xlatch1in@1 hcl in[1] net@5 latch1in09_6Bi
+Xmux5@0 net@6 inB[1] out[1] s[F] s[T] mux5
+Xwire90@0 net@5 net@6 wire90-277_3-layer_1-width_3
+.ENDS dataMux
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-463_3-R_34_667m a b
-Ccap@0 gnd net@14 1.699f
-Ccap@1 gnd net@8 1.699f
-Ccap@2 gnd net@11 1.699f
-Rres@0 net@14 a 2.677
-Rres@1 net@11 net@14 5.354
-Rres@2 b net@8 2.677
-Rres@3 net@8 net@11 5.354
-.ENDS wire-C_0_011f-463_3-R_34_667m
+.SUBCKT wire-C_0_011f-251_8-R_34_667m a b
+Ccap@0 gnd net@14 0.923f
+Ccap@1 gnd net@8 0.923f
+Ccap@2 gnd net@11 0.923f
+Rres@0 net@14 a 1.455
+Rres@1 net@11 net@14 2.91
+Rres@2 b net@8 1.455
+Rres@3 net@8 net@11 2.91
+.ENDS wire-C_0_011f-251_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-463_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-463_3-R_34_667m
-.ENDS wire90-463_3-layer_1-width_3
+.SUBCKT wire90-251_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-251_8-R_34_667m
+.ENDS wire90-251_8-layer_1-width_3
-*** CELL: loopCountM:olc{sch}
-.SUBCKT olc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2]
-+inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo]
-XcountLog@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4]
-+do[5] do[6] olc[zero] olc[zoo] calculate
-XolcEven@1 bitt[2] bitt[4] bitt[6] olc[dec] do[2] do[4] do[6] inLO[2] inLO[4]
-+inLO[6] olc[load] olcEven
-XolcOdd@2 bitt[1] bitt[3] bitt[5] olc[dec] do[3] do[5] inLO[1] inLO[3]
-+inLO[5] olc[load] olcOdd
-Xwire90@1 wire90@1_a do[2] wire90-380_7-layer_1-width_3
-Xwire90@2 wire90@2_a do[3] wire90-544_8-layer_1-width_3
-Xwire90@3 wire90@3_a do[4] wire90-478_3-layer_1-width_3
-Xwire90@4 wire90@4_a do[5] wire90-554_3-layer_1-width_3
-Xwire90@5 wire90@5_a do[6] wire90-463_3-layer_1-width_3
-.ENDS olc
+*** CELL: registersM:shadowMux4{sch}
+.SUBCKT shadowMux4 in[1] in[2] in[3] in[4] out[1] out[2] out[3] out[4] s[F]
++s[T] sign
+Xi[1] in[1] x[1] inv-X_10
+Xi[2] in[2] x[2] inv-X_10
+Xi[3] in[3] x[3] inv-X_10
+Xi[4] in[4] x[4] inv-X_10
+Xm[1] x[1] sign out[1] s[F] s[T] mux5
+Xm[2] x[2] sign out[2] s[F] s[T] mux5
+Xm[3] x[3] sign out[3] s[F] s[T] mux5
+Xm[4] x[4] sign out[4] s[F] s[T] mux5
+Xwire90@0 x[1] wire90@0_b wire90-251_8-layer_1-width_3
+Xwire90@1 x[2] wire90@1_b wire90-251_8-layer_1-width_3
+Xwire90@2 x[3] wire90@2_b wire90-251_8-layer_1-width_3
+Xwire90@3 x[4] wire90@3_b wire90-251_8-layer_1-width_3
+.ENDS shadowMux4
*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_100 d g s
-MNMOSf@0 d g s gnd nch W='300*(1+ABN/sqrt(300*2))' L='2'
-+DELVTO='AVT0N/sqrt(300*2)'
-.ENDS NMOSx-X_100
+.SUBCKT NMOSx-X_80 d g s
+MNMOSf@0 d g s gnd nch W='240*(1+ABN/sqrt(240*2))' L='2'
++DELVTO='AVT0N/sqrt(240*2)'
+.ENDS NMOSx-X_80
*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_100 d g s
-MPMOSf@0 d g s vdd pch W='600*(1+ABP/sqrt(600*2))' L='2'
-+DELVTO='AVT0P/sqrt(600*2)'
-.ENDS PMOSx-X_100
+.SUBCKT PMOSx-X_80 d g s
+MPMOSf@0 d g s vdd pch W='480*(1+ABP/sqrt(480*2))' L='2'
++DELVTO='AVT0P/sqrt(480*2)'
+.ENDS PMOSx-X_80
*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_100 in out
-XNMOS@0 out in gnd NMOSx-X_100
-XPMOS@0 out in vdd PMOSx-X_100
-.ENDS inv-X_100
+.SUBCKT inv-X_80 in out
+XNMOS@0 out in gnd NMOSx-X_80
+XPMOS@0 out in vdd PMOSx-X_80
+.ENDS inv-X_80
-*** CELL: centersJ:ctrAND1in100{sch}
-.SUBCKT ctrAND1in100 in out
-Xinv@11 net@125 net@120 inv-X_30
-XinvI@3 in net@101 inv-X_10
-XinvI@4 net@82 out inv-X_100
-Xwire90@1 net@101 net@125 wire90-414-layer_1-width_3
-Xwire90@2 net@120 net@82 wire90-927-layer_1-width_3
-.ENDS ctrAND1in100
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-817_9-R_34_667m a b
+Ccap@0 gnd net@14 2.999f
+Ccap@1 gnd net@8 2.999f
+Ccap@2 gnd net@11 2.999f
+Rres@0 net@14 a 4.726
+Rres@1 net@11 net@14 9.451
+Rres@2 b net@8 4.726
+Rres@3 net@8 net@11 9.451
+.ENDS wire-C_0_011f-817_9-R_34_667m
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_15 d g s
-MPMOSf@0 d g s vdd pch W='90*(1+ABP/sqrt(90*2))' L='2'
-+DELVTO='AVT0P/sqrt(90*2)'
-.ENDS PMOSx-X_15
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-817_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-817_9-R_34_667m
+.ENDS wire90-817_9-layer_1-width_3
-*** CELL: redFive:nand2LT_sy{sch}
-.SUBCKT nand2LT_sy-X_30 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_15
-XPMOS@1 out inb vdd PMOSx-X_15
-Xnms2_sy@0 out ina inb nms2_sy-X_30
-.ENDS nand2LT_sy-X_30
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1334_3-R_34_667m a b
+Ccap@0 gnd net@14 4.892f
+Ccap@1 gnd net@8 4.892f
+Ccap@2 gnd net@11 4.892f
+Rres@0 net@14 a 7.709
+Rres@1 net@11 net@14 15.419
+Rres@2 b net@8 7.709
+Rres@3 net@8 net@11 15.419
+.ENDS wire-C_0_011f-1334_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1334_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1334_3-R_34_667m
+.ENDS wire90-1334_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-399_2-R_34_667m a b
-Ccap@0 gnd net@14 1.464f
-Ccap@1 gnd net@8 1.464f
-Ccap@2 gnd net@11 1.464f
-Rres@0 net@14 a 2.306
-Rres@1 net@11 net@14 4.613
-Rres@2 b net@8 2.306
-Rres@3 net@8 net@11 4.613
-.ENDS wire-C_0_011f-399_2-R_34_667m
+.SUBCKT wire-C_0_011f-540-R_34_667m a b
+Ccap@0 gnd net@14 1.98f
+Ccap@1 gnd net@8 1.98f
+Ccap@2 gnd net@11 1.98f
+Rres@0 net@14 a 3.12
+Rres@1 net@11 net@14 6.24
+Rres@2 b net@8 3.12
+Rres@3 net@8 net@11 6.24
+.ENDS wire-C_0_011f-540-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-399_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-399_2-R_34_667m
-.ENDS wire90-399_2-layer_1-width_3
+.SUBCKT wire90-540-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-540-R_34_667m
+.ENDS wire90-540-layer_1-width_3
+
+*** CELL: registersM:signLogic{sch}
+.SUBCKT signLogic inB[15] inB[20] s[F] s[T] sign
+Xinv@0 net@12 sign inv-X_80
+Xinv@2 inB[20] net@19 inv-X_30
+Xinv@3 net@7 s[T] inv-X_100
+Xinv@4 s[T] s[F] inv-X_80
+Xinv@5 net@14 net@13 inv-X_30
+Xnand2_sy@0 net@7 inB[15] net@21 nand2_sy-X_20
+Xwire90@2 net@13 net@12 wire90-817_9-layer_1-width_3
+Xwire90@4 net@19 net@7 wire90-1334_3-layer_1-width_3
+Xwire90@5 net@21 net@14 wire90-540-layer_1-width_3
+.ENDS signLogic
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1013_8-R_34_667m a b
-Ccap@0 gnd net@14 3.717f
-Ccap@1 gnd net@8 3.717f
-Ccap@2 gnd net@11 3.717f
-Rres@0 net@14 a 5.858
-Rres@1 net@11 net@14 11.715
-Rres@2 b net@8 5.858
-Rres@3 net@8 net@11 11.715
-.ENDS wire-C_0_011f-1013_8-R_34_667m
+.SUBCKT wire-C_0_011f-4861_7-R_34_667m a b
+Ccap@0 gnd net@14 17.826f
+Ccap@1 gnd net@8 17.826f
+Ccap@2 gnd net@11 17.826f
+Rres@0 net@14 a 28.09
+Rres@1 net@11 net@14 56.18
+Rres@2 b net@8 28.09
+Rres@3 net@8 net@11 56.18
+.ENDS wire-C_0_011f-4861_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1013_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1013_8-R_34_667m
-.ENDS wire90-1013_8-layer_1-width_3
+.SUBCKT wire90-4861_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4861_7-R_34_667m
+.ENDS wire90-4861_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-468_3-R_34_667m a b
-Ccap@0 gnd net@14 1.717f
-Ccap@1 gnd net@8 1.717f
-Ccap@2 gnd net@11 1.717f
-Rres@0 net@14 a 2.706
-Rres@1 net@11 net@14 5.411
-Rres@2 b net@8 2.706
-Rres@3 net@8 net@11 5.411
-.ENDS wire-C_0_011f-468_3-R_34_667m
+.SUBCKT wire-C_0_011f-5555_8-R_34_667m a b
+Ccap@0 gnd net@14 20.371f
+Ccap@1 gnd net@8 20.371f
+Ccap@2 gnd net@11 20.371f
+Rres@0 net@14 a 32.1
+Rres@1 net@11 net@14 64.2
+Rres@2 b net@8 32.1
+Rres@3 net@8 net@11 64.2
+.ENDS wire-C_0_011f-5555_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-468_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-468_3-R_34_667m
-.ENDS wire90-468_3-layer_1-width_3
-
-*** CELL: centersJ:ctrAND2in100LT{sch}
-.SUBCKT ctrAND2in100LT inA inB out
-Xinv@8 inB net@135 inv-X_10
-Xinv@9 inA net@139 inv-X_10
-Xinv@10 net@146 out inv-X_100
-Xnand2LT_@0 net@140 net@136 net@144 nand2LT_sy-X_30
-Xwire90@4 net@135 net@136 wire90-399_2-layer_1-width_3
-Xwire90@5 net@144 net@146 wire90-1013_8-layer_1-width_3
-Xwire90@6 net@139 net@140 wire90-468_3-layer_1-width_3
-.ENDS ctrAND2in100LT
-
-*** CELL: centersJ:ctrAND2in100{sch}
-.SUBCKT ctrAND2in100 inA inB out
-Xinv@9 net@163 net@161 inv-X_30
-XinvI@1 net@162 out inv-X_100
-Xnor2n_sy@0 inA inB net@158 nor2n_sy-X_10
-Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3
-Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3
-.ENDS ctrAND2in100
+.SUBCKT wire90-5555_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-5555_8-R_34_667m
+.ENDS wire90-5555_8-layer_1-width_3
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_3_999 d g s
-MNMOSf@0 d g s gnd nch W='11.997*(1+ABN/sqrt(11.997*2))' L='2'
-+DELVTO='AVT0N/sqrt(11.997*2)'
-.ENDS NMOSx-X_3_999
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5262_9-R_34_667m a b
+Ccap@0 gnd net@14 19.297f
+Ccap@1 gnd net@8 19.297f
+Ccap@2 gnd net@11 19.297f
+Rres@0 net@14 a 30.408
+Rres@1 net@11 net@14 60.816
+Rres@2 b net@8 30.408
+Rres@3 net@8 net@11 60.816
+.ENDS wire-C_0_011f-5262_9-R_34_667m
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_1_333 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_3_999
-XNMOS@1 net@7 g gnd NMOSx-X_3_999
-XNMOS@2 net@6 g2 net@7 NMOSx-X_3_999
-.ENDS nms3-X_1_333
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5262_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-5262_9-R_34_667m
+.ENDS wire90-5262_9-layer_1-width_3
-*** CELL: driversL:sucDri20or{sch}
-.SUBCKT sucDri20or inA inB succ
-Xinv@1 succ net@94 inv-X_4
-Xnms3b@0 succ net@142 inB inA nms3-X_1_333
-Xpms1@0 succ inA pms1-X_20
-Xpms1@1 succ inB pms1-X_20
-Xwire90@0 net@142 net@94 wire90-124_7-layer_1-width_3
-.ENDS sucDri20or
+*** CELL: registersM:shadow{sch}
+.SUBCKT shadow dd[1] dd[2] dd[3] dd[4] dd[5] dd[6] hcl inB[15] inB[16]
++inB[17] inB[18] inB[19] inB[20] inn[10] inn[11] inn[12] inn[13] inn[14]
++inn[15] inn[16] inn[17] inn[18] inn[7] inn[8] inn[9] outt[16] outt[17]
++outt[18] outt[19] outt[20] outt[21] outt[22] outt[23] outt[24] outt[25]
++outt[26] outt[27] outt[28] outt[29] outt[30] outt[31] outt[32] outt[33]
++outt[34] outt[35] outt[36] outt[37]
+Xdl[1] hcl sign dd[1] outt[20] s[F] s[T] dataMux
+Xdl[2] hcl sign dd[2] outt[21] s[F] s[T] dataMux
+Xdl[3] hcl sign dd[3] outt[22] s[F] s[T] dataMux
+Xdl[4] hcl sign dd[4] outt[23] s[F] s[T] dataMux
+Xdl[5] hcl sign dd[5] outt[24] s[F] s[T] dataMux
+Xdl[6] hcl sign dd[6] outt[25] s[F] s[T] dataMux
+Xdl[7] hcl sign inn[7] outt[26] s[F] s[T] dataMux
+Xdl[8] hcl sign inn[8] outt[27] s[F] s[T] dataMux
+Xdl[9] hcl sign inn[9] outt[28] s[F] s[T] dataMux
+Xdr[1] hcl sign inn[18] outt[37] s[F] s[T] dataMux
+Xdr[2] hcl sign inn[17] outt[36] s[F] s[T] dataMux
+Xdr[3] hcl sign inn[16] outt[35] s[F] s[T] dataMux
+Xdr[4] hcl sign inn[15] outt[34] s[F] s[T] dataMux
+Xdr[5] hcl sign inn[14] outt[33] s[F] s[T] dataMux
+Xdr[6] hcl sign inn[13] outt[32] s[F] s[T] dataMux
+Xdr[7] hcl sign inn[12] outt[31] s[F] s[T] dataMux
+Xdr[8] hcl sign inn[11] outt[30] s[F] s[T] dataMux
+Xdr[9] hcl sign inn[10] outt[29] s[F] s[T] dataMux
+XshadowMu@1 inB[16] inB[17] inB[18] inB[19] outt[16] outt[17] outt[18]
++outt[19] s[F] s[T] sign shadowMux4
+XsignLogi@0 inB[15] inB[20] s[F] s[T] sign signLogic
+Xwire90@1 s[F] wire90@1_b wire90-4861_7-layer_1-width_3
+Xwire90@2 s[T] wire90@2_b wire90-5555_8-layer_1-width_3
+Xwire90@3 sign wire90@3_b wire90-5262_9-layer_1-width_3
+.ENDS shadow
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-802-R_34_667m a b
-Ccap@0 gnd net@14 2.941f
-Ccap@1 gnd net@8 2.941f
-Ccap@2 gnd net@11 2.941f
-Rres@0 net@14 a 4.634
-Rres@1 net@11 net@14 9.268
-Rres@2 b net@8 4.634
-Rres@3 net@8 net@11 9.268
-.ENDS wire-C_0_011f-802-R_34_667m
+.SUBCKT wire-C_0_011f-4175_4-R_34_667m a b
+Ccap@0 gnd net@14 15.31f
+Ccap@1 gnd net@8 15.31f
+Ccap@2 gnd net@11 15.31f
+Rres@0 net@14 a 24.125
+Rres@1 net@11 net@14 48.249
+Rres@2 b net@8 24.125
+Rres@3 net@8 net@11 48.249
+.ENDS wire-C_0_011f-4175_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-802-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-802-R_34_667m
-.ENDS wire90-802-layer_1-width_3
+.SUBCKT wire90-4175_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4175_4-R_34_667m
+.ENDS wire90-4175_4-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-911_4-R_34_667m a b
-Ccap@0 gnd net@14 3.342f
-Ccap@1 gnd net@8 3.342f
-Ccap@2 gnd net@11 3.342f
-Rres@0 net@14 a 5.266
-Rres@1 net@11 net@14 10.532
-Rres@2 b net@8 5.266
-Rres@3 net@8 net@11 10.532
-.ENDS wire-C_0_011f-911_4-R_34_667m
+*** CELL: registersM:newDregister{sch}
+.SUBCKT newDregister dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17]
++dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27]
++dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37]
++dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] out[10] out[11] out[12] out[13]
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4]
++out[5] out[6] out[7] out[8] out[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7]
++ps[8] ps[9] take[A] take[B]
+Xdata2in6@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
++dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28]
++dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3]
++dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
++ss[16] ss[17] ss[18] ss[19] ps[1] ss[20] ss[21] ss[22] ss[23] ss[24] ss[25]
++ss[26] ss[27] ss[28] ss[29] ps[2] ss[30] ss[31] ss[32] ss[33] ss[34] ss[35]
++ss[36] ss[37] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] out[10] out[11]
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1]
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28]
++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36]
++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] take[A] take[B]
++data2in60Cx37
+Xinv@0 take[B] net@66 inv-X_40
+Xshadow@0 out[1] out[2] out[3] out[4] out[5] out[6] net@66 ps[15] ps[16]
++ps[17] ps[18] ps[19] ps[20] out[10] out[11] out[12] out[13] out[14] out[15]
++out[16] out[17] out[18] out[7] out[8] out[9] ss[16] ss[17] ss[18] ss[19]
++ss[20] ss[21] ss[22] ss[23] ss[24] ss[25] ss[26] ss[27] ss[28] ss[29] ss[30]
++ss[31] ss[32] ss[33] ss[34] ss[35] ss[36] ss[37] shadow
+Xwire90@0 net@66 wire90@0_b wire90-4175_4-layer_1-width_3
+.ENDS newDregister
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-911_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-911_4-R_34_667m
-.ENDS wire90-911_4-layer_1-width_3
+*** CELL: registersM:addr2in60Cx7{sch}
+.SUBCKT addr2in60Cx7 ainA[1] ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7]
++ainB[1] ainB[2] ainB[3] ainB[4] ainB[5] ainB[6] ainB[7] aout[1] aout[2]
++aout[3] aout[4] aout[5] aout[6] aout[7] fire[A] fire[B]
+XhiL[1] fire[A] fire[B] ainA[1] ainB[1] aout[1] latch2in60C
+XhiL[2] fire[A] fire[B] ainA[2] ainB[2] aout[2] latch2in60C
+XhiL[3] fire[A] fire[B] ainA[3] ainB[3] aout[3] latch2in60C
+XhiL[4] fire[A] fire[B] ainA[4] ainB[4] aout[4] latch2in60C
+XhiL[5] fire[A] fire[B] ainA[5] ainB[5] aout[5] latch2in60C
+XhiL[6] fire[A] fire[B] ainA[6] ainB[6] aout[6] latch2in60C
+XhiL[7] fire[A] fire[B] ainA[7] ainB[7] aout[7] latch2in60C
+.ENDS addr2in60Cx7
+
+*** CELL: registersM:addr2in60Cx15{sch}
+.SUBCKT addr2in60Cx15 ainA[10] ainA[11] ainA[12] ainA[13] ainA[14] ainA[1]
++ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ainA[8] ainA[9] ainA[TT]
++ainB[10] ainB[11] ainB[12] ainB[13] ainB[14] ainB[1] ainB[2] ainB[3] ainB[4]
++ainB[5] ainB[6] ainB[7] ainB[8] ainB[9] ainB[TT] aout[10] aout[11] aout[12]
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
++aout[8] aout[9] aout[TT] fire[A] fire[B]
+Xaddr2in6@1 ainA[1] ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ainB[1]
++ainB[2] ainB[3] ainB[4] ainB[5] ainB[6] ainB[7] aout[1] aout[2] aout[3]
++aout[4] aout[5] aout[6] aout[7] fire[A2] fire[B2] addr2in60Cx7
+Xaddr2in6@2 ainA[8] ainA[9] ainA[10] ainA[11] ainA[12] ainA[13] ainA[14]
++ainB[8] ainB[9] ainB[10] ainB[11] ainB[12] ainB[13] ainB[14] aout[8] aout[9]
++aout[10] aout[11] aout[12] aout[13] aout[14] fire[A1] fire[B1] addr2in60Cx7
+Xlatch2in@4 fire[A2] fire[B2] ainA[TT] ainB[TT] aout[TT] latch2in60C
+Xwire90@3 fire[A] fire[A1] wire90-2330-layer_1-width_3
+Xwire90@4 fire[B] fire[B1] wire90-2330-layer_1-width_3
+Xwire90@5 fire[B] fire[B2] wire90-2330-layer_1-width_3
+Xwire90@6 fire[A] fire[A2] wire90-2330-layer_1-width_3
+.ENDS addr2in60Cx15
+
+*** CELL: gates3inM:nand3in6.6{sch}
+.SUBCKT nand3in6_6 inA inB inC out
+Xnand3@0 inA inB inC out nand3-X_6_667
+.ENDS nand3in6_6
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-405-R_34_667m a b
-Ccap@0 gnd net@14 1.485f
-Ccap@1 gnd net@8 1.485f
-Ccap@2 gnd net@11 1.485f
-Rres@0 net@14 a 2.34
-Rres@1 net@11 net@14 4.68
-Rres@2 b net@8 2.34
-Rres@3 net@8 net@11 4.68
-.ENDS wire-C_0_011f-405-R_34_667m
+.SUBCKT wire-C_0_011f-3616_3-R_34_667m a b
+Ccap@0 gnd net@14 13.26f
+Ccap@1 gnd net@8 13.26f
+Ccap@2 gnd net@11 13.26f
+Rres@0 net@14 a 20.894
+Rres@1 net@11 net@14 41.788
+Rres@2 b net@8 20.894
+Rres@3 net@8 net@11 41.788
+.ENDS wire-C_0_011f-3616_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-405-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-405-R_34_667m
-.ENDS wire90-405-layer_1-width_3
+.SUBCKT wire90-3616_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3616_3-R_34_667m
+.ENDS wire90-3616_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-472_9-R_34_667m a b
-Ccap@0 gnd net@14 1.734f
-Ccap@1 gnd net@8 1.734f
-Ccap@2 gnd net@11 1.734f
-Rres@0 net@14 a 2.732
-Rres@1 net@11 net@14 5.465
-Rres@2 b net@8 2.732
-Rres@3 net@8 net@11 5.465
-.ENDS wire-C_0_011f-472_9-R_34_667m
+.SUBCKT wire-C_0_011f-3495_7-R_34_667m a b
+Ccap@0 gnd net@14 12.818f
+Ccap@1 gnd net@8 12.818f
+Ccap@2 gnd net@11 12.818f
+Rres@0 net@14 a 20.197
+Rres@1 net@11 net@14 40.395
+Rres@2 b net@8 20.197
+Rres@3 net@8 net@11 40.395
+.ENDS wire-C_0_011f-3495_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-472_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-472_9-R_34_667m
-.ENDS wire90-472_9-layer_1-width_3
+.SUBCKT wire90-3495_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3495_7-R_34_667m
+.ENDS wire90-3495_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-346_7-R_34_667m a b
-Ccap@0 gnd net@14 1.271f
-Ccap@1 gnd net@8 1.271f
-Ccap@2 gnd net@11 1.271f
-Rres@0 net@14 a 2.003
-Rres@1 net@11 net@14 4.006
-Rres@2 b net@8 2.003
-Rres@3 net@8 net@11 4.006
-.ENDS wire-C_0_011f-346_7-R_34_667m
+.SUBCKT wire-C_0_011f-270-R_34_667m a b
+Ccap@0 gnd net@14 0.99f
+Ccap@1 gnd net@8 0.99f
+Ccap@2 gnd net@11 0.99f
+Rres@0 net@14 a 1.56
+Rres@1 net@11 net@14 3.12
+Rres@2 b net@8 1.56
+Rres@3 net@8 net@11 3.12
+.ENDS wire-C_0_011f-270-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-346_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-346_7-R_34_667m
-.ENDS wire90-346_7-layer_1-width_3
+.SUBCKT wire90-270-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-270-R_34_667m
+.ENDS wire90-270-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-438_9-R_34_667m a b
-Ccap@0 gnd net@14 1.609f
-Ccap@1 gnd net@8 1.609f
-Ccap@2 gnd net@11 1.609f
-Rres@0 net@14 a 2.536
-Rres@1 net@11 net@14 5.072
-Rres@2 b net@8 2.536
-Rres@3 net@8 net@11 5.072
-.ENDS wire-C_0_011f-438_9-R_34_667m
+.SUBCKT wire-C_0_011f-358-R_34_667m a b
+Ccap@0 gnd net@14 1.313f
+Ccap@1 gnd net@8 1.313f
+Ccap@2 gnd net@11 1.313f
+Rres@0 net@14 a 2.068
+Rres@1 net@11 net@14 4.137
+Rres@2 b net@8 2.068
+Rres@3 net@8 net@11 4.137
+.ENDS wire-C_0_011f-358-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-438_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-438_9-R_34_667m
-.ENDS wire90-438_9-layer_1-width_3
+.SUBCKT wire90-358-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-358-R_34_667m
+.ENDS wire90-358-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-143_2-R_34_667m a b
-Ccap@0 gnd net@14 0.525f
-Ccap@1 gnd net@8 0.525f
-Ccap@2 gnd net@11 0.525f
-Rres@0 net@14 a 0.827
-Rres@1 net@11 net@14 1.655
-Rres@2 b net@8 0.827
-Rres@3 net@8 net@11 1.655
-.ENDS wire-C_0_011f-143_2-R_34_667m
+*** CELL: registersM:newPathReg{sch}
+.SUBCKT newPathReg aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
++dp[10] dp[11] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9]
++fire[M] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4]
++ps[5] ps[6] ps[7] ps[8] ps[9]
+Xaddr2in6@0 dp[10] dp[11] dp[12] dp[12] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5]
++dp[6] dp[7] dp[8] dp[9] ps[15] ps[10] ps[11] ps[12] ps[13] ps[13] ps[1] ps[2]
++ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[15] aout[10] aout[11] aout[12]
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
++aout[8] aout[9] aout[TT] take[dp] take[ps] addr2in60Cx15
+Xinv@1 ps[13] net@46 inv-X_10
+Xinv@2 ps[14] net@47 inv-X_10
+XinvI@0 net@19 net@40 inv-X_30
+XlatchAnd@0 ps[14] fire[M] net@43 latchAndDriver30
+Xnand3in6@1 net@25 net@28 fire[M] net@19 nand3in6_6
+Xwire90@0 net@43 take[dp] wire90-3616_3-layer_1-width_3
+Xwire90@1 net@40 take[ps] wire90-3495_7-layer_1-width_3
+Xwire90@3 net@46 net@28 wire90-270-layer_1-width_3
+Xwire90@4 net@47 net@25 wire90-358-layer_1-width_3
+.ENDS newPathReg
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-143_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-143_2-R_34_667m
-.ENDS wire90-143_2-layer_1-width_3
+*** CELL: redFive:nor2_sy{sch}
+.SUBCKT nor2_sy-X_10 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_10
+XNMOS@1 out ina gnd NMOSx-X_10
+Xpms2_sy@0 out ina inb pms2_sy-X_10
+.ENDS nor2_sy-X_10
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-144_3-R_34_667m a b
-Ccap@0 gnd net@14 0.529f
-Ccap@1 gnd net@8 0.529f
-Ccap@2 gnd net@11 0.529f
-Rres@0 net@14 a 0.834
-Rres@1 net@11 net@14 1.667
-Rres@2 b net@8 0.834
-Rres@3 net@8 net@11 1.667
-.ENDS wire-C_0_011f-144_3-R_34_667m
+*** CELL: redFive:nor2n_sy{sch}
+.SUBCKT nor2n_sy-X_10 ina inb out
+Xnor2@0 ina inb out nor2_sy-X_10
+.ENDS nor2n_sy-X_10
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-144_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-144_3-R_34_667m
-.ENDS wire90-144_3-layer_1-width_3
+*** CELL: stagesM:litDockStage{sch}
+.SUBCKT litDockStage aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
++do[L] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18] dp[19]
++dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28] dp[29]
++dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3] dp[4]
++dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] ds[10] ds[11] ds[12] ds[13] ds[14] ds[15]
++ds[16] ds[17] ds[18] ds[19] ds[1] ds[20] ds[21] ds[22] ds[23] ds[24] ds[25]
++ds[26] ds[27] ds[28] ds[29] ds[2] ds[30] ds[31] ds[32] ds[33] ds[34] ds[35]
++ds[36] ds[37] ds[3] ds[4] ds[5] ds[6] ds[7] ds[8] ds[9] fire[M] flag[C]
++outLO[1] outLO[2] outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[10] ps[11]
++ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2]
++ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ready
++signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sir[9] sor[1] succ[D] succ[T]
+XgaspLit@0 do[L] net@10 sir[9] ready net@27 gaspLit
+Xinv@0 ps[17] net@77 inv-X_10
+Xlatch2in@0 take[A] net@81 dp[B] signalBitFromInboundSwitchFabric flag[C]
++latch2in60C
+XlatchAnd@1 ps[17] fire[M] take[A] latchAndDriver60
+XlatchAnd@2 net@77 fire[M] net@81 latchAndDriver30
+XlatchDri@0 net@13 take[B] latchDriver60
+XmuxForD@0 out[1] out[2] out[3] out[4] out[5] out[6] outLO[1] outLO[2]
++outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForD
+XnewDregi@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
++dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28]
++dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3]
++dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] ds[10] ds[11] ds[12] ds[13] ds[14] ds[15]
++ds[16] ds[17] ds[18] ds[19] ds[1] ds[20] ds[21] ds[22] ds[23] ds[24] ds[25]
++ds[26] ds[27] ds[28] ds[29] ds[2] ds[30] ds[31] ds[32] ds[33] ds[34] ds[35]
++ds[36] ds[37] ds[3] ds[4] ds[5] ds[6] ds[7] ds[8] ds[9] ps[10] ps[11] ps[12]
++ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3]
++ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[A] take[B] newDregister
+XnewPathR@0 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
++aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] dp[10]
++dp[11] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] fire[M]
++ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] ps[5] ps[6]
++ps[7] ps[8] ps[9] newPathReg
+Xnor2n_sy@0 succ[T] succ[D] ready nor2n_sy-X_10
+XscanEx1v@0 net@27 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sor[1] scanEx1vertA
+XsucANDdr@0 ps[16] fire[M] succ[D] sucANDdri60
+XsucANDdr@1 ps[15] fire[M] succ[T] sucANDdri60
+Xwire90@0 net@10 net@13 wire90-4175_4-layer_1-width_3
+.ENDS litDockStage
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-431_3-R_34_667m a b
-Ccap@0 gnd net@14 1.581f
-Ccap@1 gnd net@8 1.581f
-Ccap@2 gnd net@11 1.581f
-Rres@0 net@14 a 2.492
-Rres@1 net@11 net@14 4.984
-Rres@2 b net@8 2.492
-Rres@3 net@8 net@11 4.984
-.ENDS wire-C_0_011f-431_3-R_34_667m
+*** CELL: redFive:pms2{sch}
+.SUBCKT pms2-X_20 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_40
+XPMOS@1 d g2 net@2 PMOSx-X_40
+.ENDS pms2-X_20
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-431_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-431_3-R_34_667m
-.ENDS wire90-431_3-layer_1-width_3
+*** CELL: redFive:nor2{sch}
+.SUBCKT nor2-X_20 ina inb out
+XNMOS@0 out ina gnd NMOSx-X_20
+XNMOS@1 out inb gnd NMOSx-X_20
+Xpms2@0 out ina inb pms2-X_20
+.ENDS nor2-X_20
+
+*** CELL: redFive:nor2n{sch}
+.SUBCKT nor2n-X_20 ina inb out
+Xnor2@0 ina inb out nor2-X_20
+.ENDS nor2n-X_20
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_2 d g s
+MPMOSf@0 d g s vdd pch W='12*(1+ABP/sqrt(12*2))' L='2'
++DELVTO='AVT0P/sqrt(12*2)'
+.ENDS PMOSx-X_2
+
+*** CELL: redFive:nand2{sch}
+.SUBCKT nand2-X_2 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_2
+XPMOS@1 out inb vdd PMOSx-X_2
+Xnms2@0 out ina inb nms2-X_2
+.ENDS nand2-X_2
+
+*** CELL: redFive:nms1{sch}
+.SUBCKT nms1-X_4 d g
+XNMOS@1 d g gnd NMOSx-X_4
+.ENDS nms1-X_4
+
+*** CELL: redFive:pms1{sch}
+.SUBCKT pms1-X_10 d g
+XPMOS@0 d g vdd PMOSx-X_10
+.ENDS pms1-X_10
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-485_9-R_34_667m a b
-Ccap@0 gnd net@14 1.782f
-Ccap@1 gnd net@8 1.782f
-Ccap@2 gnd net@11 1.782f
-Rres@0 net@14 a 2.807
-Rres@1 net@11 net@14 5.615
-Rres@2 b net@8 2.807
-Rres@3 net@8 net@11 5.615
-.ENDS wire-C_0_011f-485_9-R_34_667m
+.SUBCKT wire-C_0_011f-403-R_34_667m a b
+Ccap@0 gnd net@14 1.478f
+Ccap@1 gnd net@8 1.478f
+Ccap@2 gnd net@11 1.478f
+Rres@0 net@14 a 2.328
+Rres@1 net@11 net@14 4.657
+Rres@2 b net@8 2.328
+Rres@3 net@8 net@11 4.657
+.ENDS wire-C_0_011f-403-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-485_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-485_9-R_34_667m
-.ENDS wire90-485_9-layer_1-width_3
+.SUBCKT wire90-403-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-403-R_34_667m
+.ENDS wire90-403-layer_1-width_3
+
+*** CELL: oneHotM:sucDri10Pair{sch}
+.SUBCKT sucDri10Pair bit[1] out[1][F] out[1][T] when
+XNMOSx@2 out[1][F] net@105 net@139 NMOSx-X_4
+XNMOSx@3 out[1][F] bit[1] net@144 NMOSx-X_4
+Xinv@2 when net@66 inv-X_4
+Xinv@5 out[1][F] net@92 inv-X_4
+Xinv@6 out[1][T] net@112 inv-X_4
+Xnand2@1 when bit[1] net@64 nand2-X_2
+Xnms1@2 net@139 net@154 nms1-X_4
+Xnms2b@0 out[1][T] net@113 net@4 nms2-X_2
+Xpms1@0 out[1][T] net@4 pms1-X_10
+Xpms2_sy@0 out[1][F] net@105 bit[1] pms2_sy-X_10
+Xwire90@0 net@64 net@4 wire90-403-layer_1-width_3
+Xwire90@1 net@66 net@105 wire90-403-layer_1-width_3
+Xwire90@3 net@113 net@112 wire90-403-layer_1-width_3
+Xwire90@4 net@154 net@92 wire90-403-layer_1-width_3
+Xwire90@5 net@144 net@139 wire90-403-layer_1-width_3
+.ENDS sucDri10Pair
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-208_9-R_34_667m a b
-Ccap@0 gnd net@14 0.766f
-Ccap@1 gnd net@8 0.766f
-Ccap@2 gnd net@11 0.766f
-Rres@0 net@14 a 1.207
-Rres@1 net@11 net@14 2.414
-Rres@2 b net@8 1.207
-Rres@3 net@8 net@11 2.414
-.ENDS wire-C_0_011f-208_9-R_34_667m
+*** CELL: oneHotM:sucDri10Pairx6{sch}
+.SUBCKT sucDri10Pairx6 bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] m1cate[1][F]
++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] ready when
+Xdd[1] bit[1] m1cate[1][F] m1cate[1][T] when sucDri10Pair
+Xdd[2] bit[2] m1cate[2][F] m1cate[2][T] when sucDri10Pair
+Xdd[3] bit[3] m1cate[3][F] m1cate[3][T] when sucDri10Pair
+Xdd[4] bit[4] m1cate[4][F] m1cate[4][T] when sucDri10Pair
+Xdd[5] bit[5] m1cate[5][F] m1cate[5][T] when sucDri10Pair
+Xdd[6] bit[6] m1cate[6][F] m1cate[6][T] when sucDri10Pair
+Xnor2n_sy@0 m1cate[1][T] m1cate[1][F] ready nor2n_sy-X_5
+.ENDS sucDri10Pairx6
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-208_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-208_9-R_34_667m
-.ENDS wire90-208_9-layer_1-width_3
+*** CELL: oneHotM:minusOne{sch}
+.SUBCKT minusOne bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] fire[m1] headBit
++m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T]
++m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T]
++mc pred s[1] succ[m1]
+Xinv@7 pred net@313 inv-X_5
+XinvI@0 net@235 s[1] inv-X_10
+XinvI@1 net@398 fire[m1] inv-X_10
+Xnand2@1 net@414 net@411 net@398 nand2-X_10
+Xnor2n@0 headBit net@405 net@406 nor2n-X_20
+Xnor2n_sy@1 succ[m1] net@235 net@391 nor2n_sy-X_5
+XpredDri2@0 fire[m1] mc pred predDri20wMC
+XsucDri10@1 bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] m1cate[1][F]
++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] net@435
++net@421 sucDri10Pairx6
+XsucDri20@1 net@407 succ[m1] sucDri20
+Xwire90@10 fire[m1] net@407 wire90-403-layer_1-width_3
+Xwire90@11 net@313 net@235 wire90-403-layer_1-width_3
+Xwire90@12 net@414 net@435 wire90-403-layer_1-width_3
+Xwire90@13 net@411 net@391 wire90-403-layer_1-width_3
+Xwire90@14 net@398 net@405 wire90-403-layer_1-width_3
+Xwire90@15 net@406 net@421 wire90-403-layer_1-width_3
+.ENDS minusOne
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-127_4-R_34_667m a b
-Ccap@0 gnd net@14 0.467f
-Ccap@1 gnd net@8 0.467f
-Ccap@2 gnd net@11 0.467f
-Rres@0 net@14 a 0.736
-Rres@1 net@11 net@14 1.472
-Rres@2 b net@8 0.736
-Rres@3 net@8 net@11 1.472
-.ENDS wire-C_0_011f-127_4-R_34_667m
+*** CELL: stagesM:mOneDockStage{sch}
+.SUBCKT mOneDockStage m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
++m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
++m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
++m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
++m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[R] ring[10] ring[11] ring[12]
++ring[13] ring[14] ring[15] ring[16] ring[17] ring[18] ring[19] ring[1]
++ring[20] ring[21] ring[22] ring[23] ring[24] ring[25] ring[26] ring[27]
++ring[28] ring[29] ring[2] ring[30] ring[31] ring[32] ring[33] ring[34]
++ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9]
++sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1]
++succ[m1] take[m1]
+Xins1in20@0 take[m1] ring[10] ring[11] ring[12] ring[13] ring[14] ring[15]
++ring[16] ring[17] ring[18] ring[19] ring[1] ring[20] ring[21] ring[22]
++ring[23] ring[24] ring[25] ring[26] ring[27] ring[28] ring[29] ring[2]
++ring[30] ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] ring[3]
++ring[4] ring[5] ring[6] ring[7] ring[8] ring[9] m1[10] m1[11] m1[12] m1[13]
++m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23]
++m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33]
++m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ins1in20Bx36
+XlatchDri@0 fire[1] take[m1] latchDriver60
+XminusOne@0 ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] net@11
++ring[30] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F]
++m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F]
++m1cate[6][T] sir[9] pred[R] net@47 succ[m1] minusOne
+XscanEx1v@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++sir[8] sor[1] scanEx1vertA
+Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3
+.ENDS mOneDockStage
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-127_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-127_4-R_34_667m
-.ENDS wire90-127_4-layer_1-width_3
+*** CELL: loopCountM:muxForPS{sch}
+.SUBCKT muxForPS in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2]
++out[3] out[4] out[5] out[6] out[7] sel
+Xinv@0 sel net@0 inv-X_20
+Xinv@1 sT net@1 inv-X_20
+Xmux10/2x@0 in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2] out[3]
++out[4] out[5] out[6] out[7] sF sT mux10/2x7
+Xwire90@0 net@0 sT wire90-704_3-layer_1-width_3
+Xwire90@1 net@1 sF wire90-704_3-layer_1-width_3
+.ENDS muxForPS
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-215_9-R_34_667m a b
-Ccap@0 gnd net@14 0.792f
-Ccap@1 gnd net@8 0.792f
-Ccap@2 gnd net@11 0.792f
-Rres@0 net@14 a 1.247
-Rres@1 net@11 net@14 2.495
-Rres@2 b net@8 1.247
-Rres@3 net@8 net@11 2.495
-.ENDS wire-C_0_011f-215_9-R_34_667m
+*** CELL: registersM:dockPSreg{sch}
+.SUBCKT dockPSreg fire[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16]
++m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26]
++m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36]
++m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] outLO[1] outLO[2] outLO[3] outLO[4]
++outLO[5] outLO[6] outLO[7] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16]
++ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26]
++ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36]
++ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[1]
+Xins1in20@0 take[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
++m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
++m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
++m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25]
++ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35]
++ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ins1in20Bx36
+XlatchDri@0 fire[1] net@0 latchDriver60
+XmuxForOD@0 ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[8] outLO[1] outLO[2]
++outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForPS
+Xwire90@0 net@0 take[1] wire90-544_2-layer_1-width_3
+.ENDS dockPSreg
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-215_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-215_9-R_34_667m
-.ENDS wire90-215_9-layer_1-width_3
+*** CELL: redFive:nand2n{sch}
+.SUBCKT nand2n-X_10 ina inb out
+Xnand2@0 ina inb out nand2-X_10
+.ENDS nand2n-X_10
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-140_6-R_34_667m a b
-Ccap@0 gnd net@14 0.516f
-Ccap@1 gnd net@8 0.516f
-Ccap@2 gnd net@11 0.516f
-Rres@0 net@14 a 0.812
-Rres@1 net@11 net@14 1.625
-Rres@2 b net@8 0.812
-Rres@3 net@8 net@11 1.625
-.ENDS wire-C_0_011f-140_6-R_34_667m
+.SUBCKT wire-C_0_011f-405_3-R_34_667m a b
+Ccap@0 gnd net@14 1.486f
+Ccap@1 gnd net@8 1.486f
+Ccap@2 gnd net@11 1.486f
+Rres@0 net@14 a 2.342
+Rres@1 net@11 net@14 4.683
+Rres@2 b net@8 2.342
+Rres@3 net@8 net@11 4.683
+.ENDS wire-C_0_011f-405_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-140_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-140_6-R_34_667m
-.ENDS wire90-140_6-layer_1-width_3
-
-*** CELL: loopCountM:olcControl{sch}
-.SUBCKT olcControl Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set]
-+ilc[load] mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3]
-XctrAND1i@0 net@527 net@165 ctrAND1in30
-XctrAND1i@3 net@519 ilc[load] ctrAND1in100
-XctrAND1i@4 net@547 net@162 ctrAND1in30
-XctrAND2i@3 do[2] net@339 olc[load] ctrAND2in100LT
-XctrAND2i@5 olc[zero] net@547 olc[dec] ctrAND2in100
-Xinv@6 olc[zoo] net@180 inv-X_5
-Xinv@7 olc[zero] net@184 inv-X_5
-Xinv@14 do[Co] net@386 inv-X_10
-Xinv@16 Dvoid net@451 inv-X_5
-Xinv@18 flag[D][set] net@535 inv-X_5
-Xinv@19 flag[D][clr] net@539 inv-X_5
-Xinv@20 do[Ld] net@576 inv-X_5
-XinvI@2 net@538 s[3] inv-X_10
-XinvI@3 net@534 s[2] inv-X_10
-XinvI@4 net@575 s[1] inv-X_10
-Xnand2@0 net@288 net@162 net@286 nand2-X_5
-Xnand2@1 net@289 net@165 net@284 nand2-X_5
-Xnand2@2 olc[zoo] net@162 net@279 nand2-X_5
-Xnand2@3 olc[zero] net@165 net@281 nand2-X_5
-Xnand2@4 Dvoid do[Ld] net@471 nand2-X_5
-Xnand2@5 net@455 do[Ld] net@438 nand2-X_5
-Xnor2_sy@1 do[reD] do[2] net@556 nor2_sy-X_5
-XpredDri2@0 net@358 mc do[2] predDri20wMC
-XpredDri2@2 net@162 mc do[Co] predDri20wMC
-XpredDri2@3 net@165 mc do[reD] predDri20wMC
-XpredORdr@0 ilc[load] olc[load] mc do[Ld] predORdri20wMC
-XsucDri20@0 olc[load] net@278 sucDri20
-XsucDri20@3 net@428 net@424 flag[D][clr] sucDri20or
-XsucDri20@4 net@426 net@422 flag[D][set] sucDri20or
-Xwire90@6 net@358 net@165 wire90-802-layer_1-width_3
-Xwire90@8 net@278 do[2] wire90-911_4-layer_1-width_3
-Xwire90@9 net@281 net@422 wire90-405-layer_1-width_3
-Xwire90@10 net@279 net@426 wire90-472_9-layer_1-width_3
-Xwire90@11 net@286 net@428 wire90-346_7-layer_1-width_3
-Xwire90@12 net@284 net@424 wire90-438_9-layer_1-width_3
-Xwire90@13 net@180 net@288 wire90-143_2-layer_1-width_3
-Xwire90@14 net@184 net@289 wire90-144_3-layer_1-width_3
-Xwire90@17 net@471 net@339 wire90-431_3-layer_1-width_3
-Xwire90@19 net@386 net@547 wire90-485_9-layer_1-width_3
-Xwire90@20 net@438 net@519 wire90-208_9-layer_1-width_3
-Xwire90@21 net@455 net@451 wire90-127_4-layer_1-width_3
-Xwire90@22 net@556 net@527 wire90-215_9-layer_1-width_3
-Xwire90@23 net@535 net@534 wire90-140_6-layer_1-width_3
-Xwire90@24 net@539 net@538 wire90-140_6-layer_1-width_3
-Xwire90@25 net@576 net@575 wire90-140_6-layer_1-width_3
-.ENDS olcControl
+.SUBCKT wire90-405_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-405_3-R_34_667m
+.ENDS wire90-405_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1022_9-R_34_667m a b
-Ccap@0 gnd net@14 3.751f
-Ccap@1 gnd net@8 3.751f
-Ccap@2 gnd net@11 3.751f
-Rres@0 net@14 a 5.91
-Rres@1 net@11 net@14 11.82
-Rres@2 b net@8 5.91
-Rres@3 net@8 net@11 11.82
-.ENDS wire-C_0_011f-1022_9-R_34_667m
+.SUBCKT wire-C_0_011f-385_8-R_34_667m a b
+Ccap@0 gnd net@14 1.415f
+Ccap@1 gnd net@8 1.415f
+Ccap@2 gnd net@11 1.415f
+Rres@0 net@14 a 2.229
+Rres@1 net@11 net@14 4.458
+Rres@2 b net@8 2.229
+Rres@3 net@8 net@11 4.458
+.ENDS wire-C_0_011f-385_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1022_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1022_9-R_34_667m
-.ENDS wire90-1022_9-layer_1-width_3
+.SUBCKT wire90-385_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-385_8-R_34_667m
+.ENDS wire90-385_8-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-810_8-R_34_667m a b
-Ccap@0 gnd net@14 2.973f
-Ccap@1 gnd net@8 2.973f
-Ccap@2 gnd net@11 2.973f
-Rres@0 net@14 a 4.685
-Rres@1 net@11 net@14 9.369
-Rres@2 b net@8 4.685
-Rres@3 net@8 net@11 9.369
-.ENDS wire-C_0_011f-810_8-R_34_667m
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-406_4-R_34_667m a b
+Ccap@0 gnd net@14 1.49f
+Ccap@1 gnd net@8 1.49f
+Ccap@2 gnd net@11 1.49f
+Rres@0 net@14 a 2.348
+Rres@1 net@11 net@14 4.696
+Rres@2 b net@8 2.348
+Rres@3 net@8 net@11 4.696
+.ENDS wire-C_0_011f-406_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-810_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-810_8-R_34_667m
-.ENDS wire90-810_8-layer_1-width_3
+.SUBCKT wire90-406_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-406_4-R_34_667m
+.ENDS wire90-406_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4437_9-R_34_667m a b
-Ccap@0 gnd net@14 16.272f
-Ccap@1 gnd net@8 16.272f
-Ccap@2 gnd net@11 16.272f
-Rres@0 net@14 a 25.641
-Rres@1 net@11 net@14 51.282
-Rres@2 b net@8 25.641
-Rres@3 net@8 net@11 51.282
-.ENDS wire-C_0_011f-4437_9-R_34_667m
+.SUBCKT wire-C_0_011f-329_2-R_34_667m a b
+Ccap@0 gnd net@14 1.207f
+Ccap@1 gnd net@8 1.207f
+Ccap@2 gnd net@11 1.207f
+Rres@0 net@14 a 1.902
+Rres@1 net@11 net@14 3.804
+Rres@2 b net@8 1.902
+Rres@3 net@8 net@11 3.804
+.ENDS wire-C_0_011f-329_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4437_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4437_9-R_34_667m
-.ENDS wire90-4437_9-layer_1-width_3
+.SUBCKT wire90-329_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-329_2-R_34_667m
+.ENDS wire90-329_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3501_1-R_34_667m a b
-Ccap@0 gnd net@14 12.837f
-Ccap@1 gnd net@8 12.837f
-Ccap@2 gnd net@11 12.837f
-Rres@0 net@14 a 20.229
-Rres@1 net@11 net@14 40.457
-Rres@2 b net@8 20.229
-Rres@3 net@8 net@11 40.457
-.ENDS wire-C_0_011f-3501_1-R_34_667m
+.SUBCKT wire-C_0_011f-407_9-R_34_667m a b
+Ccap@0 gnd net@14 1.496f
+Ccap@1 gnd net@8 1.496f
+Ccap@2 gnd net@11 1.496f
+Rres@0 net@14 a 2.357
+Rres@1 net@11 net@14 4.714
+Rres@2 b net@8 2.357
+Rres@3 net@8 net@11 4.714
+.ENDS wire-C_0_011f-407_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3501_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3501_1-R_34_667m
-.ENDS wire90-3501_1-layer_1-width_3
+.SUBCKT wire90-407_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-407_9-R_34_667m
+.ENDS wire90-407_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1686-R_34_667m a b
-Ccap@0 gnd net@14 6.182f
-Ccap@1 gnd net@8 6.182f
-Ccap@2 gnd net@11 6.182f
-Rres@0 net@14 a 9.741
-Rres@1 net@11 net@14 19.483
-Rres@2 b net@8 9.741
-Rres@3 net@8 net@11 19.483
-.ENDS wire-C_0_011f-1686-R_34_667m
+.SUBCKT wire-C_0_011f-247-R_34_667m a b
+Ccap@0 gnd net@14 0.906f
+Ccap@1 gnd net@8 0.906f
+Ccap@2 gnd net@11 0.906f
+Rres@0 net@14 a 1.427
+Rres@1 net@11 net@14 2.854
+Rres@2 b net@8 1.427
+Rres@3 net@8 net@11 2.854
+.ENDS wire-C_0_011f-247-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1686-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1686-R_34_667m
-.ENDS wire90-1686-layer_1-width_3
+.SUBCKT wire90-247-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-247-R_34_667m
+.ENDS wire90-247-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1399-R_34_667m a b
-Ccap@0 gnd net@14 5.13f
-Ccap@1 gnd net@8 5.13f
-Ccap@2 gnd net@11 5.13f
-Rres@0 net@14 a 8.083
-Rres@1 net@11 net@14 16.166
-Rres@2 b net@8 8.083
-Rres@3 net@8 net@11 16.166
-.ENDS wire-C_0_011f-1399-R_34_667m
+.SUBCKT wire-C_0_011f-456_8-R_34_667m a b
+Ccap@0 gnd net@14 1.675f
+Ccap@1 gnd net@8 1.675f
+Ccap@2 gnd net@11 1.675f
+Rres@0 net@14 a 2.639
+Rres@1 net@11 net@14 5.279
+Rres@2 b net@8 2.639
+Rres@3 net@8 net@11 5.279
+.ENDS wire-C_0_011f-456_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1399-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1399-R_34_667m
-.ENDS wire90-1399-layer_1-width_3
+.SUBCKT wire90-456_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-456_8-R_34_667m
+.ENDS wire90-456_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1408_5-R_34_667m a b
-Ccap@0 gnd net@14 5.164f
-Ccap@1 gnd net@8 5.164f
-Ccap@2 gnd net@11 5.164f
-Rres@0 net@14 a 8.138
-Rres@1 net@11 net@14 16.276
-Rres@2 b net@8 8.138
-Rres@3 net@8 net@11 16.276
-.ENDS wire-C_0_011f-1408_5-R_34_667m
+.SUBCKT wire-C_0_011f-477_4-R_34_667m a b
+Ccap@0 gnd net@14 1.75f
+Ccap@1 gnd net@8 1.75f
+Ccap@2 gnd net@11 1.75f
+Rres@0 net@14 a 2.758
+Rres@1 net@11 net@14 5.517
+Rres@2 b net@8 2.758
+Rres@3 net@8 net@11 5.517
+.ENDS wire-C_0_011f-477_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1408_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1408_5-R_34_667m
-.ENDS wire90-1408_5-layer_1-width_3
+.SUBCKT wire90-477_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-477_4-R_34_667m
+.ENDS wire90-477_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1925_2-R_34_667m a b
-Ccap@0 gnd net@14 7.059f
-Ccap@1 gnd net@8 7.059f
-Ccap@2 gnd net@11 7.059f
-Rres@0 net@14 a 11.123
-Rres@1 net@11 net@14 22.247
-Rres@2 b net@8 11.123
-Rres@3 net@8 net@11 22.247
-.ENDS wire-C_0_011f-1925_2-R_34_667m
+.SUBCKT wire-C_0_011f-775_9-R_34_667m a b
+Ccap@0 gnd net@14 2.845f
+Ccap@1 gnd net@8 2.845f
+Ccap@2 gnd net@11 2.845f
+Rres@0 net@14 a 4.483
+Rres@1 net@11 net@14 8.966
+Rres@2 b net@8 4.483
+Rres@3 net@8 net@11 8.966
+.ENDS wire-C_0_011f-775_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1925_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1925_2-R_34_667m
-.ENDS wire90-1925_2-layer_1-width_3
+.SUBCKT wire90-775_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-775_9-R_34_667m
+.ENDS wire90-775_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1638_1-R_34_667m a b
-Ccap@0 gnd net@14 6.006f
-Ccap@1 gnd net@8 6.006f
-Ccap@2 gnd net@11 6.006f
-Rres@0 net@14 a 9.465
-Rres@1 net@11 net@14 18.929
-Rres@2 b net@8 9.465
-Rres@3 net@8 net@11 18.929
-.ENDS wire-C_0_011f-1638_1-R_34_667m
+.SUBCKT wire-C_0_011f-480_2-R_34_667m a b
+Ccap@0 gnd net@14 1.761f
+Ccap@1 gnd net@8 1.761f
+Ccap@2 gnd net@11 1.761f
+Rres@0 net@14 a 2.774
+Rres@1 net@11 net@14 5.549
+Rres@2 b net@8 2.774
+Rres@3 net@8 net@11 5.549
+.ENDS wire-C_0_011f-480_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1638_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1638_1-R_34_667m
-.ENDS wire90-1638_1-layer_1-width_3
+.SUBCKT wire90-480_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-480_2-R_34_667m
+.ENDS wire90-480_2-layer_1-width_3
-*** CELL: loopCountM:olcWcont{sch}
-.SUBCKT olcWcont Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set]
-+ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sin
-+sout
-Xolc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2]
-+inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo] olc
-XolcContr@0 Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] ilc[load]
-+mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3] olcControl
-XscanEx3h@1 bitt[1] bitt[3] bitt[5] mc p1p p2p rd sin net@46 scanEx3h
-XscanEx3h@2 bitt[2] bitt[4] bitt[6] mc p1p p2p rd net@46 net@48 scanEx3h
-XscanEx3h@3 s[3] s[2] s[1] mc p1p p2p rd net@48 sout scanEx3h
-Xwire90@1 olc[zero] wire90@1_b wire90-1022_9-layer_1-width_3
-Xwire90@2 olc[zoo] wire90@2_b wire90-810_8-layer_1-width_3
-Xwire90@3 olc[load] wire90@3_b wire90-4437_9-layer_1-width_3
-Xwire90@4 olc[dec] wire90@4_b wire90-3501_1-layer_1-width_3
-Xwire90@5 wire90@5_a bitt[4] wire90-1686-layer_1-width_3
-Xwire90@6 wire90@6_a bitt[5] wire90-1399-layer_1-width_3
-Xwire90@7 wire90@7_a bitt[6] wire90-1408_5-layer_1-width_3
-Xwire90@8 wire90@8_a bitt[1] wire90-1686-layer_1-width_3
-Xwire90@9 wire90@9_a bitt[2] wire90-1925_2-layer_1-width_3
-Xwire90@10 wire90@10_a bitt[3] wire90-1638_1-layer_1-width_3
-.ENDS olcWcont
+*** CELL: redFive:xor2{sch}
+.SUBCKT xor2-X_5 ina inaB inb inbB out
+Xnms2@0 out inb ina nms2-X_5
+Xnms2@1 out inbB inaB nms2-X_5
+Xpms2@0 out inbB ina pms2-X_5
+Xpms2@1 out inb inaB pms2-X_5
+.ENDS xor2-X_5
+
+*** CELL: oneHotM:ohXor{sch}
+.SUBCKT ohXor flag[F] flag[T] in[1][F] in[1][T] out
+Xxor2@0 in[1][T] in[1][F] flag[T] flag[F] out xor2-X_5
+.ENDS ohXor
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3750-R_34_667m a b
-Ccap@0 gnd net@14 13.75f
-Ccap@1 gnd net@8 13.75f
-Ccap@2 gnd net@11 13.75f
-Rres@0 net@14 a 21.667
-Rres@1 net@11 net@14 43.333
-Rres@2 b net@8 21.667
-Rres@3 net@8 net@11 43.333
-.ENDS wire-C_0_011f-3750-R_34_667m
+.SUBCKT wire-C_0_011f-357-R_34_667m a b
+Ccap@0 gnd net@14 1.309f
+Ccap@1 gnd net@8 1.309f
+Ccap@2 gnd net@11 1.309f
+Rres@0 net@14 a 2.063
+Rres@1 net@11 net@14 4.125
+Rres@2 b net@8 2.063
+Rres@3 net@8 net@11 4.125
+.ENDS wire-C_0_011f-357-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3750-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3750-R_34_667m
-.ENDS wire90-3750-layer_1-width_3
+.SUBCKT wire90-357-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-357-R_34_667m
+.ENDS wire90-357-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3560-R_34_667m a b
-Ccap@0 gnd net@14 13.053f
-Ccap@1 gnd net@8 13.053f
-Ccap@2 gnd net@11 13.053f
-Rres@0 net@14 a 20.569
-Rres@1 net@11 net@14 41.138
-Rres@2 b net@8 20.569
-Rres@3 net@8 net@11 41.138
-.ENDS wire-C_0_011f-3560-R_34_667m
+.SUBCKT wire-C_0_011f-394_5-R_34_667m a b
+Ccap@0 gnd net@14 1.447f
+Ccap@1 gnd net@8 1.447f
+Ccap@2 gnd net@11 1.447f
+Rres@0 net@14 a 2.279
+Rres@1 net@11 net@14 4.559
+Rres@2 b net@8 2.279
+Rres@3 net@8 net@11 4.559
+.ENDS wire-C_0_011f-394_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3560-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3560-R_34_667m
-.ENDS wire90-3560-layer_1-width_3
+.SUBCKT wire90-394_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-394_5-R_34_667m
+.ENDS wire90-394_5-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3611-R_34_667m a b
-Ccap@0 gnd net@14 13.24f
-Ccap@1 gnd net@8 13.24f
-Ccap@2 gnd net@11 13.24f
-Rres@0 net@14 a 20.864
-Rres@1 net@11 net@14 41.727
-Rres@2 b net@8 20.864
-Rres@3 net@8 net@11 41.727
-.ENDS wire-C_0_011f-3611-R_34_667m
+.SUBCKT wire-C_0_011f-372_2-R_34_667m a b
+Ccap@0 gnd net@14 1.365f
+Ccap@1 gnd net@8 1.365f
+Ccap@2 gnd net@11 1.365f
+Rres@0 net@14 a 2.15
+Rres@1 net@11 net@14 4.301
+Rres@2 b net@8 2.15
+Rres@3 net@8 net@11 4.301
+.ENDS wire-C_0_011f-372_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3611-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3611-R_34_667m
-.ENDS wire90-3611-layer_1-width_3
+.SUBCKT wire90-372_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-372_2-R_34_667m
+.ENDS wire90-372_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1850-R_34_667m a b
-Ccap@0 gnd net@14 6.783f
-Ccap@1 gnd net@8 6.783f
-Ccap@2 gnd net@11 6.783f
-Rres@0 net@14 a 10.689
-Rres@1 net@11 net@14 21.378
-Rres@2 b net@8 10.689
-Rres@3 net@8 net@11 21.378
-.ENDS wire-C_0_011f-1850-R_34_667m
+.SUBCKT wire-C_0_011f-319_8-R_34_667m a b
+Ccap@0 gnd net@14 1.173f
+Ccap@1 gnd net@8 1.173f
+Ccap@2 gnd net@11 1.173f
+Rres@0 net@14 a 1.848
+Rres@1 net@11 net@14 3.695
+Rres@2 b net@8 1.848
+Rres@3 net@8 net@11 3.695
+.ENDS wire-C_0_011f-319_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1850-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1850-R_34_667m
-.ENDS wire90-1850-layer_1-width_3
+.SUBCKT wire90-319_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-319_8-R_34_667m
+.ENDS wire90-319_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1852-R_34_667m a b
-Ccap@0 gnd net@14 6.791f
-Ccap@1 gnd net@8 6.791f
-Ccap@2 gnd net@11 6.791f
-Rres@0 net@14 a 10.7
-Rres@1 net@11 net@14 21.401
-Rres@2 b net@8 10.7
-Rres@3 net@8 net@11 21.401
-.ENDS wire-C_0_011f-1852-R_34_667m
+.SUBCKT wire-C_0_011f-386_5-R_34_667m a b
+Ccap@0 gnd net@14 1.417f
+Ccap@1 gnd net@8 1.417f
+Ccap@2 gnd net@11 1.417f
+Rres@0 net@14 a 2.233
+Rres@1 net@11 net@14 4.466
+Rres@2 b net@8 2.233
+Rres@3 net@8 net@11 4.466
+.ENDS wire-C_0_011f-386_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1852-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1852-R_34_667m
-.ENDS wire90-1852-layer_1-width_3
+.SUBCKT wire90-386_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-386_5-R_34_667m
+.ENDS wire90-386_5-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-867_8-R_34_667m a b
-Ccap@0 gnd net@14 3.182f
-Ccap@1 gnd net@8 3.182f
-Ccap@2 gnd net@11 3.182f
-Rres@0 net@14 a 5.014
-Rres@1 net@11 net@14 10.028
-Rres@2 b net@8 5.014
-Rres@3 net@8 net@11 10.028
-.ENDS wire-C_0_011f-867_8-R_34_667m
+.SUBCKT wire-C_0_011f-297_8-R_34_667m a b
+Ccap@0 gnd net@14 1.092f
+Ccap@1 gnd net@8 1.092f
+Ccap@2 gnd net@11 1.092f
+Rres@0 net@14 a 1.721
+Rres@1 net@11 net@14 3.441
+Rres@2 b net@8 1.721
+Rres@3 net@8 net@11 3.441
+.ENDS wire-C_0_011f-297_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-867_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-867_8-R_34_667m
-.ENDS wire90-867_8-layer_1-width_3
-
-*** CELL: stagesM:outDockCenter{sch}
-.SUBCKT outDockCenter bit[Di] bit[Do] bit[Ti] do[Lt] epi[torp] fire[M]
-+fire[do] flag[A][clr] flag[A][set] flag[C][T] flag[D][clr] flag[D][set]
-+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] m1[10] m1[11] m1[12]
-+m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p
-+pred[D] pred[T] ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv]
-+sel[Tp] sel[rD] sin sout succ[sf]
-Xflags@0 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T]
-+m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc
-+flags
-XilcMoveO@0 bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M]
-+flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6]
-+inLO[8] mc p1p p2p pred[D] pred[T] rd net@249 sout succ[sf] ilcMoveOut
-XohPredAl@0 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr]
-+flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p
-+ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD]
-+net@244 net@249 ohPredAll
-XolcWcont@0 sel[rD] do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] net@165
-+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sin net@244
-+olcWcont
-Xwire90@5 wire90@5_a flag[A][set] wire90-3750-layer_1-width_3
-Xwire90@6 wire90@6_a flag[A][clr] wire90-3560-layer_1-width_3
-Xwire90@7 wire90@7_a flag[B][set] wire90-3750-layer_1-width_3
-Xwire90@8 wire90@8_a flag[B][clr] wire90-3611-layer_1-width_3
-Xwire90@9 wire90@9_a flag[D][set] wire90-1850-layer_1-width_3
-Xwire90@10 wire90@10_a flag[D][clr] wire90-1852-layer_1-width_3
-Xwire90@24 net@165 ilc[load] wire90-867_8-layer_1-width_3
-.ENDS outDockCenter
+.SUBCKT wire90-297_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-297_8-R_34_667m
+.ENDS wire90-297_8-layer_1-width_3
-*** CELL: stagesM:outDockPredStage{sch}
-.SUBCKT outDockPredStage do[Lt] epi[torp] fire[M] flag[A][clr] flag[A][set]
-+flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
-+inLO[6] inLO[8] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
-+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
-+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12]
-+ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22]
-+ps[23] ps[24] ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32]
-+ps[33] ps[34] ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do]
-+ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+sor[1] succ[sf] take[ps]
-XdockPSre@0 net@39 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
-+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
-+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
-+inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17]
-+ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27]
-+ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3]
-+ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[ps] dockPSreg
-XoutDockC@0 ps[18] ps[16] ps[19] do[Lt] epi[torp] fire[M] net@6 flag[A][clr]
-+flag[A][set] flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[8] m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4]
-+m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
-+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
-+m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] sir[3] sir[2] pred[D] pred[T]
-+ps[do] ps[skip] sir[5] m1[24] m1[22] m1[23] m1[27] m1[25] m1[26] m1[21]
-+sir[1] sor[1] succ[sf] outDockCenter
-Xwire90@0 net@6 net@39 wire90-791_7-layer_1-width_3
-.ENDS outDockPredStage
+*** CELL: oneHotM:xor6x12{sch}
+.SUBCKT xor6x12 all any flag[1][F] flag[1][T] flag[2][F] flag[2][T]
++flag[3][F] flag[3][T] in[1][F] in[1][T] in[2][F] in[2][T] in[3][F] in[3][T]
++in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T]
+Xnand3in6@2 match[12T] match[34T] match[56T] any nand3in6_6sym
+Xnor3in3_@1 match[56F] match[34F] match[12F] all nor3in6_6sym
+XohMux@6 flag[1][F] flag[1][T] in[2][F] in[1][F] net@84 ohXor
+XohMux@7 flag[1][F] flag[1][T] in[2][T] in[1][T] net@91 ohXor
+XohMux@8 flag[2][F] flag[2][T] in[4][F] in[3][F] net@94 ohXor
+XohMux@9 flag[2][F] flag[2][T] in[4][T] in[3][T] net@93 ohXor
+XohMux@10 flag[3][F] flag[3][T] in[6][F] in[5][F] net@102 ohXor
+XohMux@11 flag[3][F] flag[3][T] in[6][T] in[5][T] net@101 ohXor
+Xwire90@0 net@94 match[34F] wire90-357-layer_1-width_3
+Xwire90@1 match[34T] net@93 wire90-394_5-layer_1-width_3
+Xwire90@2 net@102 match[56F] wire90-372_2-layer_1-width_3
+Xwire90@3 match[56T] net@101 wire90-319_8-layer_1-width_3
+Xwire90@4 net@84 match[12F] wire90-386_5-layer_1-width_3
+Xwire90@5 match[12T] net@91 wire90-297_8-layer_1-width_3
+.ENDS xor6x12
-*** CELL: stageGroupsM:m1predicate{sch}
-.SUBCKT m1predicate do[Lt] epi[torp] fire[M] flag[A][clr] flag[A][set]
-+flag[C][F] flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[8] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15]
-+m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25]
-+m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35]
-+m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1[succ] pred[D] pred[R]
-+pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19]
-+ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27] ps[28] ps[29]
-+ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3] ps[4] ps[5]
-+ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] ring[10] ring[11] ring[12] ring[13]
-+ring[14] ring[15] ring[16] ring[17] ring[18] ring[19] ring[1] ring[20]
-+ring[21] ring[22] ring[23] ring[24] ring[25] ring[26] ring[27] ring[28]
-+ring[29] ring[2] ring[30] ring[31] ring[32] ring[33] ring[34] ring[35]
-+ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9] sf[succ]
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1]
-XmOneDock@0 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18]
-+m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28]
-+m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4]
-+m1[5] m1[6] m1[7] m1[8] m1[9] net@54[10] net@54[11] net@54[8] net@54[9]
-+net@54[6] net@54[7] net@54[4] net@54[5] net@54[2] net@54[3] net@54[0]
-+net@54[1] pred[R] ring[10] ring[11] ring[12] ring[13] ring[14] ring[15]
-+ring[16] ring[17] ring[18] ring[19] ring[1] ring[20] ring[21] ring[22]
-+ring[23] ring[24] ring[25] ring[26] ring[27] ring[28] ring[29] ring[2]
-+ring[30] ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] ring[3]
-+ring[4] ring[5] ring[6] ring[7] ring[8] ring[9] sir[1] sir[2] sir[3] sir[4]
-+sir[5] sir[6] sir[7] sir[8] sir[9] net@55[8] m1[succ] take[m1] mOneDockStage
-XoutDockP@0 do[Lt] epi[torp] fire[M] flag[A][clr] flag[A][set]
-+outDockP@0_flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[8] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15]
-+m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25]
-+m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35]
-+m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] net@54[10] net@54[11]
-+net@54[8] net@54[9] net@54[6] net@54[7] net@54[4] net@54[5] net@54[2]
-+net@54[3] net@54[0] net@54[1] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13]
-+ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23]
-+ps[24] ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33]
-+ps[34] ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do]
-+ps[skip] net@55[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+sor[1] outDockP@0_succ[sf] take[ps] outDockPredStage
-.ENDS m1predicate
-
-*** CELL: stageGroupsM:centerFive{sch}
-.SUBCKT centerFive do[Lt] do[epi] fire[M] flag[C][F] flag[C][T] inLO[1]
-+inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] in[10] in[11] in[12] in[13]
-+in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
-+in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
-+in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] pred[D]
-+pred[R] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17]
-+ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27]
-+ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3]
-+ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ring[10] ring[11] ring[12] ring[13]
-+ring[14] ring[15] ring[16] ring[17] ring[18] ring[19] ring[1] ring[20]
-+ring[21] ring[22] ring[23] ring[24] ring[25] ring[26] ring[27] ring[28]
-+ring[29] ring[2] ring[30] ring[31] ring[32] ring[33] ring[34] ring[35]
-+ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9] rq[10]
-+rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] rq[20]
-+rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] rq[30]
-+rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] rq[7] rq[8]
-+rq[9] rq[succ] sf[succ] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] sor[1]
-XepiRQod@0 do[epi] net@57 epi[torp] flag[A][clr] flag[A][set] flag[D][clr]
-+flag[D][set] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4]
-+in[5] in[6] in[7] in[8] in[9] in[T] net@71[26] net@71[25] net@71[24]
-+net@71[23] net@71[22] net@71[21] net@71[20] net@71[19] net@71[18] net@71[17]
-+net@71[35] net@71[16] net@71[15] net@71[14] net@71[13] net@71[12] net@71[11]
-+net@71[10] net@71[9] net@71[8] net@71[7] net@71[34] net@71[6] net@71[5]
-+net@71[4] net@71[3] net@71[2] net@71[1] net@71[0] net@71[33] net@71[32]
-+net@71[31] net@71[30] net@71[29] net@71[28] net@71[27] ps[do] ps[skip] rq[10]
-+rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] rq[20]
-+rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] rq[30]
-+rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] rq[7] rq[8]
-+rq[9] rq[succ] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+net@35[8] epiRQod
-Xm1predic@0 do[Lt] epi[torp] fire[M] flag[A][clr] flag[A][set] flag[C][F]
-+flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
-+inLO[6] inLO[8] net@71[26] net@71[25] net@71[24] net@71[23] net@71[22]
-+net@71[21] net@71[20] net@71[19] net@71[18] net@71[17] net@71[35] net@71[16]
-+net@71[15] net@71[14] net@71[13] net@71[12] net@71[11] net@71[10] net@71[9]
-+net@71[8] net@71[7] net@71[34] net@71[6] net@71[5] net@71[4] net@71[3]
-+net@71[2] net@71[1] net@71[0] net@71[33] net@71[32] net@71[31] net@71[30]
-+net@71[29] net@71[28] net@71[27] net@70 pred[D] pred[R] pred[T] ps[10] ps[11]
-+ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21]
-+ps[22] ps[23] ps[24] ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31]
-+ps[32] ps[33] ps[34] ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9]
-+ps[do] ps[skip] ring[10] ring[11] ring[12] ring[13] ring[14] ring[15]
-+ring[16] ring[17] ring[18] ring[19] ring[1] ring[20] ring[21] ring[22]
-+ring[23] ring[24] ring[25] ring[26] ring[27] ring[28] ring[29] ring[2]
-+ring[30] ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] ring[3]
-+ring[4] ring[5] ring[6] ring[7] ring[8] ring[9] sf[succ] net@35[8] sir[2]
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] m1predicate
-Xwire90@0 net@70 net@57 wire90-791_7-layer_1-width_3
-.ENDS centerFive
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-407_4-R_34_667m a b
-Ccap@0 gnd net@14 1.494f
-Ccap@1 gnd net@8 1.494f
-Ccap@2 gnd net@11 1.494f
-Rres@0 net@14 a 2.354
-Rres@1 net@11 net@14 4.708
-Rres@2 b net@8 2.354
-Rres@3 net@8 net@11 4.708
-.ENDS wire-C_0_011f-407_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-407_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-407_4-R_34_667m
-.ENDS wire90-407_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-416_9-R_34_667m a b
-Ccap@0 gnd net@14 1.529f
-Ccap@1 gnd net@8 1.529f
-Ccap@2 gnd net@11 1.529f
-Rres@0 net@14 a 2.409
-Rres@1 net@11 net@14 4.818
-Rres@2 b net@8 2.409
-Rres@3 net@8 net@11 4.818
-.ENDS wire-C_0_011f-416_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-416_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-416_9-R_34_667m
-.ENDS wire90-416_9-layer_1-width_3
-
-*** CELL: arbiterM:mutex{sch}
-.SUBCKT mutex in[A] in[B] out[A] out[B] reset[A] reset[B]
-XNMOSx@2 gnd reset[A] net@0 NMOSx-X_4
-XNMOSx@3 net@1 reset[B] gnd NMOSx-X_4
-XPMOSx@0 net@0 net@1 in[A] PMOSx-X_20
-XPMOSx@4 net@1 net@0 in[B] PMOSx-X_20
-XPMOSx@5 out[B] net@33 net@1 PMOSx-X_20
-XPMOSx@6 out[A] net@35 net@0 PMOSx-X_20
-Xnms1@0 net@0 net@1 nms1-X_4
-Xnms1@2 net@1 net@0 nms1-X_4
-Xwire90@0 net@35 net@1 wire90-407_4-layer_1-width_3
-Xwire90@1 net@0 net@33 wire90-416_9-layer_1-width_3
-.ENDS mutex
+*** CELL: oneHotM:aFlag{sch}
+.SUBCKT aFlag flag[1][F] flag[1][T] flag[1][clr] flag[1][set] flag[A][F]
++flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] in[1][T] in[2][T]
++in[3][T] in[4][T] in[5][T] in[6][T] mc
+Xinv@0 net@257 flag[1][T] inv-X_20
+Xinv@2 net@258 flag[1][F] inv-X_20
+Xinv@3 net@2 net@267 inv-X_10
+Xinv@4 mc net@305 inv-X_10
+XinvI@10 net@9 net@308 inv-X_5
+XinvI@11 net@176 net@306 inv-X_5
+Xinv[1] in[1][T] in[1][F] inv-X_10
+Xinv[2] in[2][T] in[2][F] inv-X_10
+Xinv[3] in[3][T] in[3][F] inv-X_10
+Xinv[4] in[4][T] in[4][F] inv-X_10
+Xinv[5] in[5][T] in[5][F] inv-X_10
+Xinv[6] in[6][T] in[6][F] inv-X_10
+Xnand2@0 net@5 net@2 net@9 nand2-X_5
+Xnand2@1 net@69 net@71 net@176 nand2-X_5
+Xnand2@2 net@51 net@267 net@239 nand2-X_5
+Xnand2@3 net@22 net@265 net@240 nand2-X_5
+Xnand2n@0 net@64 net@49 net@51 nand2n-X_10
+Xnand2n@1 net@172 net@50 net@22 nand2n-X_10
+Xnand2n@2 net@236 net@235 net@258 nand2n-X_10
+Xnand2n@3 net@259 net@234 net@257 nand2n-X_10
+Xnor2n_sy@0 flag[1][clr] flag[1][set] net@2 nor2n_sy-X_10
+XsucANDdr@0 net@305 net@308 flag[1][set] sucANDdri20
+XsucANDdr@3 net@319 net@306 flag[1][clr] sucANDdri20
+Xwire90@1 net@8 net@5 wire90-405_3-layer_1-width_3
+Xwire90@4 net@22 net@49 wire90-385_8-layer_1-width_3
+Xwire90@5 net@50 net@51 wire90-406_4-layer_1-width_3
+Xwire90@6 net@64 net@9 wire90-329_2-layer_1-width_3
+Xwire90@8 net@69 net@68 wire90-407_9-layer_1-width_3
+Xwire90@19 net@176 net@172 wire90-329_2-layer_1-width_3
+Xwire90@22 net@240 net@259 wire90-247-layer_1-width_3
+Xwire90@23 net@236 net@239 wire90-247-layer_1-width_3
+Xwire90@24 net@257 net@235 wire90-456_8-layer_1-width_3
+Xwire90@25 net@234 net@258 wire90-477_4-layer_1-width_3
+Xwire90@26 net@71 net@2 wire90-775_9-layer_1-width_3
+Xwire90@27 net@265 net@267 wire90-480_2-layer_1-width_3
+Xwire90@28 net@319 net@305 wire90-385_8-layer_1-width_3
+Xxor6x12@0 net@68 net@8 flag[A][F] flag[A][T] flag[B][F] flag[B][T]
++flag[C][F] flag[C][T] in[1][F] in[1][T] in[2][F] in[2][T] in[3][F] in[3][T]
++in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T] xor6x12
+.ENDS aFlag
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_30 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_60
-XPMOS@1 d g2 net@2 PMOSx-X_60
-.ENDS pms2-X_30
+*** CELL: oneHotM:flags{sch}
+.SUBCKT flags flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T]
++m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc
+XaFlag@0 flag[A][F] flag[A][T] flag[A][clr] flag[A][set] flag[A][F]
++flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] m1[1] m1[2] m1[3]
++m1[4] m1[5] m1[6] mc aFlag
+XaFlag@1 flag[B][F] flag[B][T] flag[B][clr] flag[B][set] flag[A][F]
++flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] m1[7] m1[8] m1[9]
++m1[10] m1[11] m1[12] mc aFlag
+Xinv@0 flag[C][T] flag[C][F] inv-X_10
+.ENDS flags
-*** CELL: redFive:nor2{sch}
-.SUBCKT nor2-X_30 ina inb out
-XNMOS@0 out ina gnd NMOSx-X_30
-XNMOS@1 out inb gnd NMOSx-X_30
-Xpms2@0 out ina inb pms2-X_30
-.ENDS nor2-X_30
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-979-R_34_667m a b
+Ccap@0 gnd net@14 3.59f
+Ccap@1 gnd net@8 3.59f
+Ccap@2 gnd net@11 3.59f
+Rres@0 net@14 a 5.656
+Rres@1 net@11 net@14 11.313
+Rres@2 b net@8 5.656
+Rres@3 net@8 net@11 11.313
+.ENDS wire-C_0_011f-979-R_34_667m
-*** CELL: redFive:nor2n{sch}
-.SUBCKT nor2n-X_30 ina inb out
-Xnor2@0 ina inb out nor2-X_30
-.ENDS nor2n-X_30
-
-*** CELL: arbiterM:outputNand{sch}
-.SUBCKT outputNand inA inB out
-XPMOSx@0 out inB vdd PMOSx-X_20
-XPMOSx@1 out inA vdd PMOSx-X_20
-Xnms2b@2 out inA inB nms2-X_20
-.ENDS outputNand
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-376-R_34_667m a b
-Ccap@0 gnd net@14 1.379f
-Ccap@1 gnd net@8 1.379f
-Ccap@2 gnd net@11 1.379f
-Rres@0 net@14 a 2.172
-Rres@1 net@11 net@14 4.345
-Rres@2 b net@8 2.172
-Rres@3 net@8 net@11 4.345
-.ENDS wire-C_0_011f-376-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-376-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-376-R_34_667m
-.ENDS wire90-376-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-711_9-R_34_667m a b
-Ccap@0 gnd net@14 2.61f
-Ccap@1 gnd net@8 2.61f
-Ccap@2 gnd net@11 2.61f
-Rres@0 net@14 a 4.113
-Rres@1 net@11 net@14 8.226
-Rres@2 b net@8 4.113
-Rres@3 net@8 net@11 8.226
-.ENDS wire-C_0_011f-711_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-711_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-711_9-R_34_667m
-.ENDS wire90-711_9-layer_1-width_3
-
-*** CELL: arbiterM:meArbiter{sch}
-.SUBCKT meArbiter in[A] in[B] out[A] out[B] req[A1] req[A2] req[B1] req[B2]
-Xmutex@0 net@9 net@11 net@5 net@0 req[A1] req[B1] mutex
-Xnms1@0 net@19 req[A2] nms1-X_4
-Xnms1@1 net@19 req[A1] nms1-X_4
-Xnms1@2 net@33 req[B1] nms1-X_4
-Xnms1@3 net@33 req[B2] nms1-X_4
-Xnor2n@0 req[A2] req[A1] net@13 nor2n-X_30
-Xnor2n@2 req[B2] req[B1] net@17 nor2n-X_30
-XoutputNa@0 in[A] net@19 out[A] outputNand
-XoutputNa@1 in[B] net@33 out[B] outputNand
-Xwire90@0 net@0 net@33 wire90-376-layer_1-width_3
-Xwire90@1 net@19 net@5 wire90-376-layer_1-width_3
-Xwire90@2 net@11 net@17 wire90-711_9-layer_1-width_3
-Xwire90@3 net@13 net@9 wire90-711_9-layer_1-width_3
-.ENDS meArbiter
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-495_9-R_34_667m a b
-Ccap@0 gnd net@14 1.818f
-Ccap@1 gnd net@8 1.818f
-Ccap@2 gnd net@11 1.818f
-Rres@0 net@14 a 2.865
-Rres@1 net@11 net@14 5.73
-Rres@2 b net@8 2.865
-Rres@3 net@8 net@11 5.73
-.ENDS wire-C_0_011f-495_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-495_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-495_9-R_34_667m
-.ENDS wire90-495_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-224_6-R_34_667m a b
-Ccap@0 gnd net@14 0.824f
-Ccap@1 gnd net@8 0.824f
-Ccap@2 gnd net@11 0.824f
-Rres@0 net@14 a 1.298
-Rres@1 net@11 net@14 2.595
-Rres@2 b net@8 1.298
-Rres@3 net@8 net@11 2.595
-.ENDS wire-C_0_011f-224_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-224_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-224_6-R_34_667m
-.ENDS wire90-224_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-222_9-R_34_667m a b
-Ccap@0 gnd net@14 0.817f
-Ccap@1 gnd net@8 0.817f
-Ccap@2 gnd net@11 0.817f
-Rres@0 net@14 a 1.288
-Rres@1 net@11 net@14 2.576
-Rres@2 b net@8 1.288
-Rres@3 net@8 net@11 2.576
-.ENDS wire-C_0_011f-222_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-222_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-222_9-R_34_667m
-.ENDS wire90-222_9-layer_1-width_3
-
-*** CELL: oneHotM:moveAnd{sch}
-.SUBCKT moveAnd again bit[Di] bit[Ti] do[Mv] done[D] done[M] done[T] fire[M]
-+ilc[ck] ilc[decLO] ilc[do] ilc[ho] ilc[mo] win[M]
-Xinv@0 ilc[do] net@20 inv-X_5
-Xinv@1 net@49 net@52 inv-X_10
-Xinv@2 net@75 ilc[decLO] inv-X_20
-XinvI@0 win[M] net@46 inv-X_5
-XinvI@1 win[M] ilc[ck] inv-X_10
-Xnand2@0 ilc[do] bit[Di] net@66 nand2-X_5
-Xnand2@1 ilc[do] bit[Ti] net@70 nand2-X_5
-Xnand2@2 do[Mv] net@53 again nand2-X_20
-Xnor2n@0 skip win[M] fire[M] nor2n-X_20
-Xnor2n@1 ilc[mo] win[M] done[M] nor2n-X_5
-Xnor2n@2 net@64 win[M] done[D] nor2n-X_5
-Xnor2n@3 net@68 win[M] done[T] nor2n-X_5
-Xnor2n@4 ilc[ho] win[M] net@76 nor2n-X_5
-Xwire90@0 net@20 skip wire90-495_9-layer_1-width_3
-Xwire90@1 net@49 net@46 wire90-142_6-layer_1-width_3
-Xwire90@2 net@52 net@53 wire90-224_6-layer_1-width_3
-Xwire90@4 net@66 net@64 wire90-222_9-layer_1-width_3
-Xwire90@5 net@70 net@68 wire90-222_9-layer_1-width_3
-Xwire90@6 net@76 net@75 wire90-224_6-layer_1-width_3
-.ENDS moveAnd
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-979-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-979-R_34_667m
+.ENDS wire90-979-layer_1-width_3
-*** CELL: driversL:predDri60wMC{sch}
-.SUBCKT driversL__predDri60wMC in mc pred
-XNMOSx@0 pred in gnd NMOSx-X_60
-XNMOSx@1 pred mc gnd NMOSx-X_10
-Xinv@0 pred net@145 inv-X_10
-Xpms3@0 pred mc in net@174 pms3-X_3_333
-Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3
-.ENDS driversL__predDri60wMC
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-704_9-R_34_667m a b
+Ccap@0 gnd net@14 2.585f
+Ccap@1 gnd net@8 2.585f
+Ccap@2 gnd net@11 2.585f
+Rres@0 net@14 a 4.073
+Rres@1 net@11 net@14 8.146
+Rres@2 b net@8 4.073
+Rres@3 net@8 net@11 8.146
+.ENDS wire-C_0_011f-704_9-R_34_667m
-*** CELL: redFive:nms1{sch}
-.SUBCKT nms1-X_10 d g
-XNMOS@1 d g gnd NMOSx-X_10
-.ENDS nms1-X_10
-
-*** CELL: oneHotM:predWaitB{sch}
-.SUBCKT predWaitB ign[1] ign[2] out pred[1] pred[2]
-XNMOSx@6 net@108 ign[1] out NMOSx-X_10
-XNMOSx@11 net@90 pred[1] out NMOSx-X_10
-Xnms1@1 net@108 pred[2] nms1-X_10
-Xnms1@4 net@90 ign[2] nms1-X_10
-Xpms2@0 out ign[2] pred[2] pms2-X_5
-Xpms2@1 out ign[1] pred[1] pms2-X_5
-Xwire90@0 net@108 net@90 wire90-218_6-layer_1-width_3
-.ENDS predWaitB
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-153_6-R_34_667m a b
-Ccap@0 gnd net@14 0.563f
-Ccap@1 gnd net@8 0.563f
-Ccap@2 gnd net@11 0.563f
-Rres@0 net@14 a 0.887
-Rres@1 net@11 net@14 1.775
-Rres@2 b net@8 0.887
-Rres@3 net@8 net@11 1.775
-.ENDS wire-C_0_011f-153_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-153_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-153_6-R_34_667m
-.ENDS wire90-153_6-layer_1-width_3
-
-*** CELL: oneHotM:movePreds{sch}
-.SUBCKT movePreds do[Mv] done[D] done[M] done[T] done[Tp] ign[D] ign[T] mc
-+pred[D] pred[T] s[1] s[2] s[3] wait
-Xinv@0 net@29 s[1] inv-X_10
-Xinv@1 net@33 s[2] inv-X_10
-Xinv@2 net@36 s[3] inv-X_10
-XinvI@0 do[Mv] net@28 inv-X_5
-XinvI@1 pred[T] net@32 inv-X_5
-XinvI@2 pred[D] net@35 inv-X_5
-XinvI@3 ign[T] net@69 inv-X_5
-XinvI@4 ign[D] net@74 inv-X_5
-XpredDri6@0 done[D] mc pred[D] driversL__predDri60wMC
-XpredDri6@1 done[T] mc pred[T] driversL__predDri60wMC
-XpredORdr@0 done[Tp] done[M] mc do[Mv] predORdri20wMC
-XpredWait@0 net@71 net@76 wait pred[T] pred[D] predWaitB
-Xwire90@0 net@29 net@28 wire90-142_6-layer_1-width_3
-Xwire90@1 net@33 net@32 wire90-142_6-layer_1-width_3
-Xwire90@2 net@36 net@35 wire90-142_6-layer_1-width_3
-Xwire90@3 net@69 net@71 wire90-153_6-layer_1-width_3
-Xwire90@4 net@76 net@74 wire90-153_6-layer_1-width_3
-.ENDS movePreds
-
-*** CELL: oneHotM:moveTorpPreds{sch}
-.SUBCKT moveTorpPreds TpBAR do[Tp] done[M] fire[T] mc s[4] s[5] torp torpBAR
-+win[T]
-Xinv@0 TpBAR s[4] inv-X_10
-Xinv@1 torpBAR s[5] inv-X_10
-XinvI@1 do[Tp] TpBAR inv-X_10
-XinvI@2 torp torpBAR inv-X_10
-XinvI@3 win[T] fire[T] inv-X_30
-XpredDri2@0 fire[T] mc torp predDri20wMC
-XpredORdr@0 fire[T] done[M] mc do[Tp] predORdri20wMC
-.ENDS moveTorpPreds
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-704_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-704_9-R_34_667m
+.ENDS wire90-704_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-617-R_34_667m a b
-Ccap@0 gnd net@14 2.262f
-Ccap@1 gnd net@8 2.262f
-Ccap@2 gnd net@11 2.262f
-Rres@0 net@14 a 3.565
-Rres@1 net@11 net@14 7.13
-Rres@2 b net@8 3.565
-Rres@3 net@8 net@11 7.13
-.ENDS wire-C_0_011f-617-R_34_667m
+.SUBCKT wire-C_0_011f-784_7-R_34_667m a b
+Ccap@0 gnd net@14 2.877f
+Ccap@1 gnd net@8 2.877f
+Ccap@2 gnd net@11 2.877f
+Rres@0 net@14 a 4.534
+Rres@1 net@11 net@14 9.068
+Rres@2 b net@8 4.534
+Rres@3 net@8 net@11 9.068
+.ENDS wire-C_0_011f-784_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-617-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-617-R_34_667m
-.ENDS wire90-617-layer_1-width_3
+.SUBCKT wire90-784_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-784_7-R_34_667m
+.ENDS wire90-784_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1348_3-R_34_667m a b
-Ccap@0 gnd net@14 4.944f
-Ccap@1 gnd net@8 4.944f
-Ccap@2 gnd net@11 4.944f
-Rres@0 net@14 a 7.79
-Rres@1 net@11 net@14 15.58
-Rres@2 b net@8 7.79
-Rres@3 net@8 net@11 15.58
-.ENDS wire-C_0_011f-1348_3-R_34_667m
+.SUBCKT wire-C_0_011f-631_7-R_34_667m a b
+Ccap@0 gnd net@14 2.316f
+Ccap@1 gnd net@8 2.316f
+Ccap@2 gnd net@11 2.316f
+Rres@0 net@14 a 3.65
+Rres@1 net@11 net@14 7.3
+Rres@2 b net@8 3.65
+Rres@3 net@8 net@11 7.3
+.ENDS wire-C_0_011f-631_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1348_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1348_3-R_34_667m
-.ENDS wire90-1348_3-layer_1-width_3
+.SUBCKT wire90-631_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-631_7-R_34_667m
+.ENDS wire90-631_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-865_4-R_34_667m a b
-Ccap@0 gnd net@14 3.173f
-Ccap@1 gnd net@8 3.173f
-Ccap@2 gnd net@11 3.173f
-Rres@0 net@14 a 5
-Rres@1 net@11 net@14 10
-Rres@2 b net@8 5
-Rres@3 net@8 net@11 10
-.ENDS wire-C_0_011f-865_4-R_34_667m
+.SUBCKT wire-C_0_011f-328_2-R_34_667m a b
+Ccap@0 gnd net@14 1.203f
+Ccap@1 gnd net@8 1.203f
+Ccap@2 gnd net@11 1.203f
+Rres@0 net@14 a 1.896
+Rres@1 net@11 net@14 3.793
+Rres@2 b net@8 1.896
+Rres@3 net@8 net@11 3.793
+.ENDS wire-C_0_011f-328_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-865_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-865_4-R_34_667m
-.ENDS wire90-865_4-layer_1-width_3
+.SUBCKT wire90-328_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-328_2-R_34_667m
+.ENDS wire90-328_2-layer_1-width_3
+
+*** CELL: loopCountM:calculate{sch}
+.SUBCKT calculate bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] do[2] do[3] do[4]
++do[5] do[6] zero zoo
+Xinv@0 net@257 do[2] inv-X_10
+Xinv@1 bit[2] net@128 inv-X_10
+Xinv@2 bit[1] net@257 inv-X_10
+Xnand2@0 bit[3] bit[1] net@145 nand2-X_10
+Xnand2@1 bit[4] bit[2] net@195 nand2-X_10
+Xnand2@2 bit[3] bit[5] net@315 nand2-X_10
+Xnand3@0 bit[5] bit[3] bit[1] net@264 nand3-X_6_667
+Xnand3@1 bit[6] bit[4] bit[2] net@198 nand3-X_6_667
+Xnor2n@1 net@128 net@257 do[3] nor2n-X_10
+Xnor2n@2 net@145 net@146 do[4] nor2n-X_10
+Xnor2n@3 net@195 net@58 do[5] nor2n-X_10
+Xnor2n@4 net@221 net@56 do[6] nor2n-X_10
+Xnor2n@5 net@289 net@267 zoo nor2n-X_10
+Xnor2n@6 net@198 net@264 zero nor2n-X_10
+Xwire90@0 net@264 net@221 wire90-979-layer_1-width_3
+Xwire90@1 net@58 net@145 wire90-704_9-layer_1-width_3
+Xwire90@3 net@56 net@195 wire90-704_3-layer_1-width_3
+Xwire90@5 net@198 net@289 wire90-784_7-layer_1-width_3
+Xwire90@6 net@146 net@128 wire90-631_7-layer_1-width_3
+Xwire90@8 net@267 net@315 wire90-328_2-layer_1-width_3
+.ENDS calculate
+
+*** CELL: redFive:pms2{sch}
+.SUBCKT pms2-X_1 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_2
+XPMOS@1 d g2 net@2 PMOSx-X_2
+.ENDS pms2-X_1
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1509_4-R_34_667m a b
-Ccap@0 gnd net@14 5.534f
-Ccap@1 gnd net@8 5.534f
-Ccap@2 gnd net@11 5.534f
-Rres@0 net@14 a 8.721
-Rres@1 net@11 net@14 17.442
-Rres@2 b net@8 8.721
-Rres@3 net@8 net@11 17.442
-.ENDS wire-C_0_011f-1509_4-R_34_667m
+.SUBCKT wire-C_0_011f-185-R_34_667m a b
+Ccap@0 gnd net@14 0.678f
+Ccap@1 gnd net@8 0.678f
+Ccap@2 gnd net@11 0.678f
+Rres@0 net@14 a 1.069
+Rres@1 net@11 net@14 2.138
+Rres@2 b net@8 1.069
+Rres@3 net@8 net@11 2.138
+.ENDS wire-C_0_011f-185-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1509_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1509_4-R_34_667m
-.ENDS wire90-1509_4-layer_1-width_3
+.SUBCKT wire90-185-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-185-R_34_667m
+.ENDS wire90-185-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-479_8-R_34_667m a b
-Ccap@0 gnd net@14 1.759f
-Ccap@1 gnd net@8 1.759f
-Ccap@2 gnd net@11 1.759f
-Rres@0 net@14 a 2.772
-Rres@1 net@11 net@14 5.544
-Rres@2 b net@8 2.772
-Rres@3 net@8 net@11 5.544
-.ENDS wire-C_0_011f-479_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-479_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-479_8-R_34_667m
-.ENDS wire90-479_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-930_7-R_34_667m a b
-Ccap@0 gnd net@14 3.413f
-Ccap@1 gnd net@8 3.413f
-Ccap@2 gnd net@11 3.413f
-Rres@0 net@14 a 5.377
-Rres@1 net@11 net@14 10.755
-Rres@2 b net@8 5.377
-Rres@3 net@8 net@11 10.755
-.ENDS wire-C_0_011f-930_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-930_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-930_7-R_34_667m
-.ENDS wire90-930_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-682_4-R_34_667m a b
-Ccap@0 gnd net@14 2.502f
-Ccap@1 gnd net@8 2.502f
-Ccap@2 gnd net@11 2.502f
-Rres@0 net@14 a 3.943
-Rres@1 net@11 net@14 7.886
-Rres@2 b net@8 3.943
-Rres@3 net@8 net@11 7.886
-.ENDS wire-C_0_011f-682_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-682_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-682_4-R_34_667m
-.ENDS wire90-682_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-897_3-R_34_667m a b
-Ccap@0 gnd net@14 3.29f
-Ccap@1 gnd net@8 3.29f
-Ccap@2 gnd net@11 3.29f
-Rres@0 net@14 a 5.184
-Rres@1 net@11 net@14 10.369
-Rres@2 b net@8 5.184
-Rres@3 net@8 net@11 10.369
-.ENDS wire-C_0_011f-897_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-897_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-897_3-R_34_667m
-.ENDS wire90-897_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1010_4-R_34_667m a b
-Ccap@0 gnd net@14 3.705f
-Ccap@1 gnd net@8 3.705f
-Ccap@2 gnd net@11 3.705f
-Rres@0 net@14 a 5.838
-Rres@1 net@11 net@14 11.676
-Rres@2 b net@8 5.838
-Rres@3 net@8 net@11 11.676
-.ENDS wire-C_0_011f-1010_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1010_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1010_4-R_34_667m
-.ENDS wire90-1010_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-918_3-R_34_667m a b
-Ccap@0 gnd net@14 3.367f
-Ccap@1 gnd net@8 3.367f
-Ccap@2 gnd net@11 3.367f
-Rres@0 net@14 a 5.306
-Rres@1 net@11 net@14 10.611
-Rres@2 b net@8 5.306
-Rres@3 net@8 net@11 10.611
-.ENDS wire-C_0_011f-918_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-918_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-918_3-R_34_667m
-.ENDS wire90-918_3-layer_1-width_3
-
-*** CELL: oneHotM:moveAll{sch}
-.SUBCKT moveAll bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] fire[M] flag[D][set]
-+ilc[ck] ilc[decLO] ilc[do] ilc[ho] ilc[mo] mc pred[D] pred[T] ready s[1] s[2]
-+s[3] s[4] s[5] torp
-XmeArbite@1 ready vdd net@535 net@508 net@391 net@739 net@500 net@738
-+meArbiter
-XmoveAnd@1 net@727 bit[Di] bit[Ti] do[Mv] done[D] do[reD] done[T] fire[M]
-+ilc[ck] ilc[decLO] ilc[do] ilc[ho] ilc[mo] win[M] moveAnd
-XmovePred@0 do[Mv] done[D] done[M] done[T] done[Tp] bit[5] bit[4] mc pred[D]
-+pred[T] s[1] s[2] s[3] wait movePreds
-XmoveTorp@1 net@695 do[Tp] done[M] net@751 mc s[4] s[5] torp net@703 win[T]
-+moveTorpPreds
-Xpms1@0 flag[D][set] win[T] pms1-X_20
-Xwire90@1 net@508 win[T] wire90-617-layer_1-width_3
-Xwire90@5 net@727 net@391 wire90-1348_3-layer_1-width_3
-Xwire90@6 wait net@739 wire90-865_4-layer_1-width_3
-Xwire90@28 net@535 win[M] wire90-1509_4-layer_1-width_3
-Xwire90@29 wire90@29_a done[D] wire90-479_8-layer_1-width_3
-Xwire90@30 done[M] do[reD] wire90-930_7-layer_1-width_3
-Xwire90@31 wire90@31_a done[T] wire90-682_4-layer_1-width_3
-Xwire90@33 net@695 net@500 wire90-897_3-layer_1-width_3
-Xwire90@34 net@703 net@738 wire90-1010_4-layer_1-width_3
-Xwire90@36 net@751 done[Tp] wire90-918_3-layer_1-width_3
-.ENDS moveAll
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4231-R_34_667m a b
-Ccap@0 gnd net@14 15.514f
-Ccap@1 gnd net@8 15.514f
-Ccap@2 gnd net@11 15.514f
-Rres@0 net@14 a 24.446
-Rres@1 net@11 net@14 48.892
-Rres@2 b net@8 24.446
-Rres@3 net@8 net@11 48.892
-.ENDS wire-C_0_011f-4231-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4231-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4231-R_34_667m
-.ENDS wire90-4231-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3133-R_34_667m a b
-Ccap@0 gnd net@14 11.488f
-Ccap@1 gnd net@8 11.488f
-Ccap@2 gnd net@11 11.488f
-Rres@0 net@14 a 18.102
-Rres@1 net@11 net@14 36.204
-Rres@2 b net@8 18.102
-Rres@3 net@8 net@11 36.204
-.ENDS wire-C_0_011f-3133-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3133-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3133-R_34_667m
-.ENDS wire90-3133-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1028-R_34_667m a b
-Ccap@0 gnd net@14 3.769f
-Ccap@1 gnd net@8 3.769f
-Ccap@2 gnd net@11 3.769f
-Rres@0 net@14 a 5.94
-Rres@1 net@11 net@14 11.879
-Rres@2 b net@8 5.94
-Rres@3 net@8 net@11 11.879
-.ENDS wire-C_0_011f-1028-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1028-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1028-R_34_667m
-.ENDS wire90-1028-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-852-R_34_667m a b
-Ccap@0 gnd net@14 3.124f
-Ccap@1 gnd net@8 3.124f
-Ccap@2 gnd net@11 3.124f
-Rres@0 net@14 a 4.923
-Rres@1 net@11 net@14 9.845
-Rres@2 b net@8 4.923
-Rres@3 net@8 net@11 9.845
-.ENDS wire-C_0_011f-852-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-852-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-852-R_34_667m
-.ENDS wire90-852-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1616-R_34_667m a b
-Ccap@0 gnd net@14 5.925f
-Ccap@1 gnd net@8 5.925f
-Ccap@2 gnd net@11 5.925f
-Rres@0 net@14 a 9.337
-Rres@1 net@11 net@14 18.674
-Rres@2 b net@8 9.337
-Rres@3 net@8 net@11 18.674
-.ENDS wire-C_0_011f-1616-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1616-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1616-R_34_667m
-.ENDS wire90-1616-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-809-R_34_667m a b
-Ccap@0 gnd net@14 2.966f
-Ccap@1 gnd net@8 2.966f
-Ccap@2 gnd net@11 2.966f
-Rres@0 net@14 a 4.674
-Rres@1 net@11 net@14 9.348
-Rres@2 b net@8 4.674
-Rres@3 net@8 net@11 9.348
-.ENDS wire-C_0_011f-809-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-809-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-809-R_34_667m
-.ENDS wire90-809-layer_1-width_3
+*** CELL: latchesK:mlat1in10{sch}
+.SUBCKT mlat1in10 cl[F] cl[T] in[1] out[1]
+Xinv@0 net@26 out[1] inv-X_10
+Xnms2@0 net@4 out[1] cl[F] nms2-X_2
+Xnms2@1 net@4 in[1] cl[T] nms2-X_2
+Xpms2@0 net@4 out[1] cl[T] pms2-X_1
+Xpms2@1 net@4 in[1] cl[F] pms2-X_2
+Xwire90@0 net@4 net@26 wire90-185-layer_1-width_3
+.ENDS mlat1in10
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_15 d g s
+MNMOSf@0 d g s gnd nch W='45*(1+ABN/sqrt(45*2))' L='2'
++DELVTO='AVT0N/sqrt(45*2)'
+.ENDS NMOSx-X_15
+
+*** CELL: redFive:pms2{sch}
+.SUBCKT pms2-X_15 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_30
+XPMOS@1 d g2 net@2 PMOSx-X_30
+.ENDS pms2-X_15
+
+*** CELL: redFive:nor2{sch}
+.SUBCKT nor2-X_15 ina inb out
+XNMOS@0 out ina gnd NMOSx-X_15
+XNMOS@1 out inb gnd NMOSx-X_15
+Xpms2@0 out ina inb pms2-X_15
+.ENDS nor2-X_15
+
+*** CELL: redFive:nor2n{sch}
+.SUBCKT nor2n-X_15 ina inb out
+Xnor2@0 ina inb out nor2-X_15
+.ENDS nor2n-X_15
+
+*** CELL: redFive:invLT{sch}
+.SUBCKT invLT-X_2 in out
+XNMOS@0 out in gnd NMOSx-X_4
+XPMOS@0 out in vdd PMOSx-X_2
+.ENDS invLT-X_2
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-678-R_34_667m a b
-Ccap@0 gnd net@14 2.486f
-Ccap@1 gnd net@8 2.486f
-Ccap@2 gnd net@11 2.486f
-Rres@0 net@14 a 3.917
-Rres@1 net@11 net@14 7.835
-Rres@2 b net@8 3.917
-Rres@3 net@8 net@11 7.835
-.ENDS wire-C_0_011f-678-R_34_667m
+.SUBCKT wire-C_0_011f-133_8-R_34_667m a b
+Ccap@0 gnd net@14 0.491f
+Ccap@1 gnd net@8 0.491f
+Ccap@2 gnd net@11 0.491f
+Rres@0 net@14 a 0.773
+Rres@1 net@11 net@14 1.546
+Rres@2 b net@8 0.773
+Rres@3 net@8 net@11 1.546
+.ENDS wire-C_0_011f-133_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-678-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-678-R_34_667m
-.ENDS wire90-678-layer_1-width_3
+.SUBCKT wire90-133_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-133_8-R_34_667m
+.ENDS wire90-133_8-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3855-R_34_667m a b
-Ccap@0 gnd net@14 14.135f
-Ccap@1 gnd net@8 14.135f
-Ccap@2 gnd net@11 14.135f
-Rres@0 net@14 a 22.273
-Rres@1 net@11 net@14 44.547
-Rres@2 b net@8 22.273
-Rres@3 net@8 net@11 44.547
-.ENDS wire-C_0_011f-3855-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3855-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3855-R_34_667m
-.ENDS wire90-3855-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3794-R_34_667m a b
-Ccap@0 gnd net@14 13.911f
-Ccap@1 gnd net@8 13.911f
-Ccap@2 gnd net@11 13.911f
-Rres@0 net@14 a 21.921
-Rres@1 net@11 net@14 43.842
-Rres@2 b net@8 21.921
-Rres@3 net@8 net@11 43.842
-.ENDS wire-C_0_011f-3794-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3794-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3794-R_34_667m
-.ENDS wire90-3794-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3514-R_34_667m a b
-Ccap@0 gnd net@14 12.885f
-Ccap@1 gnd net@8 12.885f
-Ccap@2 gnd net@11 12.885f
-Rres@0 net@14 a 20.303
-Rres@1 net@11 net@14 40.606
-Rres@2 b net@8 20.303
-Rres@3 net@8 net@11 40.606
-.ENDS wire-C_0_011f-3514-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3514-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3514-R_34_667m
-.ENDS wire90-3514-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3529-R_34_667m a b
-Ccap@0 gnd net@14 12.94f
-Ccap@1 gnd net@8 12.94f
-Ccap@2 gnd net@11 12.94f
-Rres@0 net@14 a 20.39
-Rres@1 net@11 net@14 40.78
-Rres@2 b net@8 20.39
-Rres@3 net@8 net@11 40.78
-.ENDS wire-C_0_011f-3529-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3529-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3529-R_34_667m
-.ENDS wire90-3529-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3203-R_34_667m a b
-Ccap@0 gnd net@14 11.744f
-Ccap@1 gnd net@8 11.744f
-Ccap@2 gnd net@11 11.744f
-Rres@0 net@14 a 18.506
-Rres@1 net@11 net@14 37.012
-Rres@2 b net@8 18.506
-Rres@3 net@8 net@11 37.012
-.ENDS wire-C_0_011f-3203-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3203-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3203-R_34_667m
-.ENDS wire90-3203-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3265-R_34_667m a b
-Ccap@0 gnd net@14 11.972f
-Ccap@1 gnd net@8 11.972f
-Ccap@2 gnd net@11 11.972f
-Rres@0 net@14 a 18.864
-Rres@1 net@11 net@14 37.729
-Rres@2 b net@8 18.864
-Rres@3 net@8 net@11 37.729
-.ENDS wire-C_0_011f-3265-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3265-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3265-R_34_667m
-.ENDS wire90-3265-layer_1-width_3
-
-*** CELL: dockPartsM:dockCenterTry2{sch}
-.SUBCKT dockCenterTry2 Dvoid bit[Di] bit[Ti] bitt[10] bitt[11] bitt[12]
-+bitt[13] bitt[14] bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7]
-+bitt[8] bitt[9] do[Co] do[Ld] fire[M] flag[A][clr] flag[A][set] flag[B][clr]
-+flag[B][set] flag[C][F] flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2]
-+inLO[3] inLO[4] inLO[5] inLO[6] inLO[7] m1[10] m1[11] m1[12] m1[1] m1[2]
-+m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc pred[D] pred[T] ready s[10] s[1]
-+s[2] s[3] s[4] s[5] s[6] s[7] s[8] s[9] torp
-Xflags@0 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
-+flags@0_flag[C][T] m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6]
-+m1[7] m1[8] m1[9] mc flags
-Xilc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8]
-+ilc[decLO] ilc@0_ilc[do] ilc[load] ilc@0_ilc[mo] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[7] ilc
-XmoveAll@0 bit[Di] bit[Ti] do[Mv] do[Tp] moveAll@0_do[reD] fire[M]
-+flag[D][set] net@89 net@93 ilc[do] ilc[ho] ilc[mo] mc pred[D] pred[T] ready
-+s[1] s[2] s[3] s[4] s[5] torp moveAll
-Xolc@0 bitt[9] bitt[10] bitt[11] bitt[12] bitt[13] bitt[14] inLO[1] inLO[2]
-+inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo] olc
-XolcContr@0 Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] net@81 mc
-+olc[dec] olc[load] olc[zero] olc[zoo] s[8] s[9] s[10] olcControl
-Xwire90@1 wire90@1_a olc[load] wire90-4231-layer_1-width_3
-Xwire90@2 wire90@2_a olc[dec] wire90-3133-layer_1-width_3
-Xwire90@3 wire90@3_a olc[zero] wire90-1028-layer_1-width_3
-Xwire90@4 wire90@4_a olc[zoo] wire90-852-layer_1-width_3
-Xwire90@5 wire90@5_a flag[A][set] wire90-3750-layer_1-width_3
-Xwire90@6 wire90@6_a flag[A][clr] wire90-3560-layer_1-width_3
-Xwire90@7 wire90@7_a flag[B][set] wire90-3750-layer_1-width_3
-Xwire90@8 wire90@8_a flag[B][clr] wire90-3611-layer_1-width_3
-Xwire90@9 wire90@9_a flag[D][set] wire90-1850-layer_1-width_3
-Xwire90@10 wire90@10_a flag[D][clr] wire90-1852-layer_1-width_3
-Xwire90@11 wire90@11_a ilc[mo] wire90-1616-layer_1-width_3
-Xwire90@12 wire90@12_a ilc[do] wire90-809-layer_1-width_3
-Xwire90@13 wire90@13_a ilc[ho] wire90-678-layer_1-width_3
-Xwire90@15 wire90@15_a inLO[1] wire90-3855-layer_1-width_3
-Xwire90@16 wire90@16_a inLO[2] wire90-3794-layer_1-width_3
-Xwire90@17 wire90@17_a inLO[3] wire90-3514-layer_1-width_3
-Xwire90@18 wire90@18_a inLO[4] wire90-3529-layer_1-width_3
-Xwire90@19 wire90@19_a inLO[5] wire90-3203-layer_1-width_3
-Xwire90@20 wire90@20_a inLO[6] wire90-3265-layer_1-width_3
-Xwire90@21 ilc[load] net@81 wire90-867_8-layer_1-width_3
-Xwire90@22 net@89 ilc[ck] wire90-867_8-layer_1-width_3
-Xwire90@23 net@93 ilc[decLO] wire90-867_8-layer_1-width_3
-.ENDS dockCenterTry2
+*** CELL: latchesK:mlat1in5i{sch}
+.SUBCKT mlat1in5i c[F] c[T] in out
+XinvLT@0 out net@119 invLT-X_2
+Xnms2@2 out in c[T] nms2-X_5
+Xnms2@3 out net@114 c[F] nms2-X_2
+Xpms2@0 out net@114 c[T] pms2-X_1
+Xpms2@1 out in c[F] pms2-X_5
+Xwire90@19 net@114 net@119 wire90-133_8-layer_1-width_3
+.ENDS mlat1in5i
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_2 d g s
-MNMOSf@0 d g s gnd nch W='6*(1+ABN/sqrt(6*2))' L='2' DELVTO='AVT0N/sqrt(6*2)'
-.ENDS NMOSx-X_2
+*** CELL: redFive:nms3{sch}
+.SUBCKT nms3-X_2 d g g2 g3
+XNMOS@0 d g3 net@6 NMOSx-X_6
+XNMOS@1 net@7 g gnd NMOSx-X_6
+XNMOS@2 net@6 g2 net@7 NMOSx-X_6
+.ENDS nms3-X_2
-*** CELL: redFive:pms2_sy{sch}
-.SUBCKT pms2_sy-X_4 d g g2
-Xpms2@0 d g g2 pms2-X_2
-Xpms2@1 d g2 g pms2-X_2
-.ENDS pms2_sy-X_4
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-200_9-R_34_667m a b
+Ccap@0 gnd net@14 0.737f
+Ccap@1 gnd net@8 0.737f
+Ccap@2 gnd net@11 0.737f
+Rres@0 net@14 a 1.161
+Rres@1 net@11 net@14 2.322
+Rres@2 b net@8 1.161
+Rres@3 net@8 net@11 2.322
+.ENDS wire-C_0_011f-200_9-R_34_667m
-*** CELL: redFive:nor2HT_sy{sch}
-.SUBCKT nor2HT_sy-X_4 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_2
-XNMOS@1 out ina gnd NMOSx-X_2
-Xpms2_sy@0 out ina inb pms2_sy-X_4
-.ENDS nor2HT_sy-X_4
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-200_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-200_9-R_34_667m
+.ENDS wire90-200_9-layer_1-width_3
+
+*** CELL: latchesK:mlat2in10i{sch}
+.SUBCKT mlat2in10i clA[F] clA[T] clB[F] clB[T] inA inB out[1]
+Xinv@0 out[1] net@33 inv-X_4
+Xnms2@0 out[1] inB clB[T] nms2-X_10
+Xnms2@1 out[1] inA clA[T] nms2-X_10
+Xnms3@0 out[1] clB[F] clA[F] net@33 nms3-X_2
+Xpms2@0 out[1] inB clB[F] pms2-X_10
+Xpms2@1 out[1] inA clA[F] pms2-X_10
+Xpms3@0 out[1] clA[T] clB[T] net@81 pms3-X_1
+Xwire90@1 net@81 net@33 wire90-200_9-layer_1-width_3
+.ENDS mlat2in10i
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-173_2-R_34_667m a b
+Ccap@0 gnd net@14 0.635f
+Ccap@1 gnd net@8 0.635f
+Ccap@2 gnd net@11 0.635f
+Rres@0 net@14 a 1.001
+Rres@1 net@11 net@14 2.001
+Rres@2 b net@8 1.001
+Rres@3 net@8 net@11 2.001
+.ENDS wire-C_0_011f-173_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-173_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-173_2-R_34_667m
+.ENDS wire90-173_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-238_2-R_34_667m a b
-Ccap@0 gnd net@14 0.873f
-Ccap@1 gnd net@8 0.873f
-Ccap@2 gnd net@11 0.873f
-Rres@0 net@14 a 1.376
-Rres@1 net@11 net@14 2.753
-Rres@2 b net@8 1.376
-Rres@3 net@8 net@11 2.753
-.ENDS wire-C_0_011f-238_2-R_34_667m
+.SUBCKT wire-C_0_011f-381_1-R_34_667m a b
+Ccap@0 gnd net@14 1.397f
+Ccap@1 gnd net@8 1.397f
+Ccap@2 gnd net@11 1.397f
+Rres@0 net@14 a 2.202
+Rres@1 net@11 net@14 4.404
+Rres@2 b net@8 2.202
+Rres@3 net@8 net@11 4.404
+.ENDS wire-C_0_011f-381_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-238_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-238_2-R_34_667m
-.ENDS wire90-238_2-layer_1-width_3
+.SUBCKT wire90-381_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-381_1-R_34_667m
+.ENDS wire90-381_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-520-R_34_667m a b
-Ccap@0 gnd net@14 1.907f
-Ccap@1 gnd net@8 1.907f
-Ccap@2 gnd net@11 1.907f
-Rres@0 net@14 a 3.004
-Rres@1 net@11 net@14 6.009
-Rres@2 b net@8 3.004
-Rres@3 net@8 net@11 6.009
-.ENDS wire-C_0_011f-520-R_34_667m
+.SUBCKT wire-C_0_011f-981_4-R_34_667m a b
+Ccap@0 gnd net@14 3.598f
+Ccap@1 gnd net@8 3.598f
+Ccap@2 gnd net@11 3.598f
+Rres@0 net@14 a 5.67
+Rres@1 net@11 net@14 11.341
+Rres@2 b net@8 5.67
+Rres@3 net@8 net@11 11.341
+.ENDS wire-C_0_011f-981_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-520-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-520-R_34_667m
-.ENDS wire90-520-layer_1-width_3
+.SUBCKT wire90-981_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-981_4-R_34_667m
+.ENDS wire90-981_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-222_3-R_34_667m a b
-Ccap@0 gnd net@14 0.815f
-Ccap@1 gnd net@8 0.815f
-Ccap@2 gnd net@11 0.815f
-Rres@0 net@14 a 1.284
-Rres@1 net@11 net@14 2.569
-Rres@2 b net@8 1.284
-Rres@3 net@8 net@11 2.569
-.ENDS wire-C_0_011f-222_3-R_34_667m
+.SUBCKT wire-C_0_011f-523_4-R_34_667m a b
+Ccap@0 gnd net@14 1.919f
+Ccap@1 gnd net@8 1.919f
+Ccap@2 gnd net@11 1.919f
+Rres@0 net@14 a 3.024
+Rres@1 net@11 net@14 6.048
+Rres@2 b net@8 3.024
+Rres@3 net@8 net@11 6.048
+.ENDS wire-C_0_011f-523_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-222_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-222_3-R_34_667m
-.ENDS wire90-222_3-layer_1-width_3
+.SUBCKT wire90-523_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-523_4-R_34_667m
+.ENDS wire90-523_4-layer_1-width_3
-*** CELL: centersJ:ctrAND4in30{sch}
-.SUBCKT ctrAND4in30 inA inB inC inD out
-Xinv@1 net@3 out inv-X_30
-Xnand2@1 net@43 net@58 net@67 nand2-X_10
-Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4
-Xnor2n@0 inD inC net@64 nor2n-X_5
-Xwire90@0 net@64 net@43 wire90-238_2-layer_1-width_3
-Xwire90@1 net@67 net@3 wire90-520-layer_1-width_3
-Xwire90@2 net@61 net@58 wire90-222_3-layer_1-width_3
-.ENDS ctrAND4in30
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-535_1-R_34_667m a b
+Ccap@0 gnd net@14 1.962f
+Ccap@1 gnd net@8 1.962f
+Ccap@2 gnd net@11 1.962f
+Rres@0 net@14 a 3.092
+Rres@1 net@11 net@14 6.183
+Rres@2 b net@8 3.092
+Rres@3 net@8 net@11 6.183
+.ENDS wire-C_0_011f-535_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-535_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-535_1-R_34_667m
+.ENDS wire90-535_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-162_4-R_34_667m a b
-Ccap@0 gnd net@14 0.595f
-Ccap@1 gnd net@8 0.595f
-Ccap@2 gnd net@11 0.595f
-Rres@0 net@14 a 0.938
-Rres@1 net@11 net@14 1.877
-Rres@2 b net@8 0.938
-Rres@3 net@8 net@11 1.877
-.ENDS wire-C_0_011f-162_4-R_34_667m
+.SUBCKT wire-C_0_011f-555_1-R_34_667m a b
+Ccap@0 gnd net@14 2.035f
+Ccap@1 gnd net@8 2.035f
+Ccap@2 gnd net@11 2.035f
+Rres@0 net@14 a 3.207
+Rres@1 net@11 net@14 6.414
+Rres@2 b net@8 3.207
+Rres@3 net@8 net@11 6.414
+.ENDS wire-C_0_011f-555_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-162_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-162_4-R_34_667m
-.ENDS wire90-162_4-layer_1-width_3
+.SUBCKT wire90-555_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-555_1-R_34_667m
+.ENDS wire90-555_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-228_5-R_34_667m a b
-Ccap@0 gnd net@14 0.838f
-Ccap@1 gnd net@8 0.838f
-Ccap@2 gnd net@11 0.838f
-Rres@0 net@14 a 1.32
-Rres@1 net@11 net@14 2.64
-Rres@2 b net@8 1.32
-Rres@3 net@8 net@11 2.64
-.ENDS wire-C_0_011f-228_5-R_34_667m
+.SUBCKT wire-C_0_011f-677_1-R_34_667m a b
+Ccap@0 gnd net@14 2.483f
+Ccap@1 gnd net@8 2.483f
+Ccap@2 gnd net@11 2.483f
+Rres@0 net@14 a 3.912
+Rres@1 net@11 net@14 7.824
+Rres@2 b net@8 3.912
+Rres@3 net@8 net@11 7.824
+.ENDS wire-C_0_011f-677_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-228_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-228_5-R_34_667m
-.ENDS wire90-228_5-layer_1-width_3
+.SUBCKT wire90-677_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-677_1-R_34_667m
+.ENDS wire90-677_1-layer_1-width_3
-*** CELL: latchesK:rsLatchA{sch}
-.SUBCKT rsLatchA mc out outBar reset set
-XNMOSx@0 net@193 reset gnd NMOSx-X_10
-XNMOSx@1 net@188 mc gnd NMOSx-X_4
-XPMOSx@3 net@188 net@177 vdd PMOSx-X_10
-Xinv@0 net@193 outBar inv-X_10
-Xinv@1 set net@213 inv-X_4
-Xinv@2 outBar out inv-X_10
-Xnms2@0 net@188 outBar net@177 nms2-X_2
-Xpms3@0 net@193 mc outBar reset pms3-X_1
-Xwire90@0 net@213 net@177 wire90-162_4-layer_1-width_3
-Xwire90@1 net@188 net@193 wire90-228_5-layer_1-width_3
-.ENDS rsLatchA
+*** CELL: loopCountM:ringB{sch}
+.SUBCKT ringB bit[1] count[F] count[T] do[1] inLO[1] load[F] load[T]
+Xinv@0 net@60 bit[1] inv-X_20
+Xinv@1 bit[1] net@67 inv-X_5
+Xinv@2 net@68 net@65 inv-X_10
+Xinv@3 xx[T] net@64 inv-X_10
+Xmlat1in5@0 xx[T] xx[F] net@66 net@9 mlat1in5i
+Xmlat1in5@1 count[T] count[F] do[1] net@77 mlat1in5i
+Xmlat2in1@0 load[F] load[T] xx[F] xx[T] inLO[1] net@63 net@61 mlat2in10i
+Xnor2n@0 net@78 count[F] net@84 nor2n-X_10
+Xwire90@1 net@67 net@68 wire90-173_2-layer_1-width_3
+Xwire90@2 net@65 net@66 wire90-381_1-layer_1-width_3
+Xwire90@3 net@60 net@61 wire90-981_4-layer_1-width_3
+Xwire90@5 net@63 net@9 wire90-523_4-layer_1-width_3
+Xwire90@6 net@64 xx[F] wire90-535_1-layer_1-width_3
+Xwire90@7 net@77 net@78 wire90-555_1-layer_1-width_3
+Xwire90@8 net@84 xx[T] wire90-677_1-layer_1-width_3
+.ENDS ringB
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-468-R_34_667m a b
-Ccap@0 gnd net@14 1.716f
-Ccap@1 gnd net@8 1.716f
-Ccap@2 gnd net@11 1.716f
-Rres@0 net@14 a 2.704
-Rres@1 net@11 net@14 5.408
-Rres@2 b net@8 2.704
-Rres@3 net@8 net@11 5.408
-.ENDS wire-C_0_011f-468-R_34_667m
+.SUBCKT wire-C_0_011f-1588-R_34_667m a b
+Ccap@0 gnd net@14 5.823f
+Ccap@1 gnd net@8 5.823f
+Ccap@2 gnd net@11 5.823f
+Rres@0 net@14 a 9.175
+Rres@1 net@11 net@14 18.35
+Rres@2 b net@8 9.175
+Rres@3 net@8 net@11 18.35
+.ENDS wire-C_0_011f-1588-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-468-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-468-R_34_667m
-.ENDS wire90-468-layer_1-width_3
+.SUBCKT wire90-1588-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1588-R_34_667m
+.ENDS wire90-1588-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-347_9-R_34_667m a b
-Ccap@0 gnd net@14 1.276f
-Ccap@1 gnd net@8 1.276f
-Ccap@2 gnd net@11 1.276f
-Rres@0 net@14 a 2.01
-Rres@1 net@11 net@14 4.02
-Rres@2 b net@8 2.01
-Rres@3 net@8 net@11 4.02
-.ENDS wire-C_0_011f-347_9-R_34_667m
+.SUBCKT wire-C_0_011f-1317_1-R_34_667m a b
+Ccap@0 gnd net@14 4.829f
+Ccap@1 gnd net@8 4.829f
+Ccap@2 gnd net@11 4.829f
+Rres@0 net@14 a 7.61
+Rres@1 net@11 net@14 15.22
+Rres@2 b net@8 7.61
+Rres@3 net@8 net@11 15.22
+.ENDS wire-C_0_011f-1317_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-347_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-347_9-R_34_667m
-.ENDS wire90-347_9-layer_1-width_3
+.SUBCKT wire90-1317_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1317_1-R_34_667m
+.ENDS wire90-1317_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1283_3-R_34_667m a b
+Ccap@0 gnd net@14 4.705f
+Ccap@1 gnd net@8 4.705f
+Ccap@2 gnd net@11 4.705f
+Rres@0 net@14 a 7.415
+Rres@1 net@11 net@14 14.829
+Rres@2 b net@8 7.415
+Rres@3 net@8 net@11 14.829
+.ENDS wire-C_0_011f-1283_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1283_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1283_3-R_34_667m
+.ENDS wire90-1283_3-layer_1-width_3
+
+*** CELL: loopCountM:ilcEven{sch}
+.SUBCKT ilcEven bit[2] bit[4] bit[6] bit[8] do[2] do[4] do[6] ilc[decLO]
++inLO[2] inLO[4] inLO[6] inLO[8] load[T] zero
+Xinv@7 count[T] net@273 inv-X_30
+Xinv@8 load[T] net@275 inv-X_30
+Xmlat1in1@1 load[F] load[T] inLO[8] bit[8] mlat1in10
+Xnor2n@0 zero ilc[decLO] net@365 nor2n-X_15
+XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
+XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
+XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
+Xwire90@8 net@273 count[F] wire90-1588-layer_1-width_3
+Xwire90@9 net@275 load[F] wire90-1317_1-layer_1-width_3
+Xwire90@10 net@365 count[T] wire90-1283_3-layer_1-width_3
+.ENDS ilcEven
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-450_6-R_34_667m a b
-Ccap@0 gnd net@14 1.652f
-Ccap@1 gnd net@8 1.652f
-Ccap@2 gnd net@11 1.652f
-Rres@0 net@14 a 2.603
-Rres@1 net@11 net@14 5.207
-Rres@2 b net@8 2.603
-Rres@3 net@8 net@11 5.207
-.ENDS wire-C_0_011f-450_6-R_34_667m
+.SUBCKT wire-C_0_011f-1458_1-R_34_667m a b
+Ccap@0 gnd net@14 5.346f
+Ccap@1 gnd net@8 5.346f
+Ccap@2 gnd net@11 5.346f
+Rres@0 net@14 a 8.425
+Rres@1 net@11 net@14 16.849
+Rres@2 b net@8 8.425
+Rres@3 net@8 net@11 16.849
+.ENDS wire-C_0_011f-1458_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-450_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-450_6-R_34_667m
-.ENDS wire90-450_6-layer_1-width_3
+.SUBCKT wire90-1458_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1458_1-R_34_667m
+.ENDS wire90-1458_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-603_6-R_34_667m a b
-Ccap@0 gnd net@14 2.213f
-Ccap@1 gnd net@8 2.213f
-Ccap@2 gnd net@11 2.213f
-Rres@0 net@14 a 3.487
-Rres@1 net@11 net@14 6.975
-Rres@2 b net@8 3.487
-Rres@3 net@8 net@11 6.975
-.ENDS wire-C_0_011f-603_6-R_34_667m
+.SUBCKT wire-C_0_011f-341_1-R_34_667m a b
+Ccap@0 gnd net@14 1.251f
+Ccap@1 gnd net@8 1.251f
+Ccap@2 gnd net@11 1.251f
+Rres@0 net@14 a 1.971
+Rres@1 net@11 net@14 3.942
+Rres@2 b net@8 1.971
+Rres@3 net@8 net@11 3.942
+.ENDS wire-C_0_011f-341_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-603_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-603_6-R_34_667m
-.ENDS wire90-603_6-layer_1-width_3
-
-*** CELL: gaspM:anAltEnd{sch}
-.SUBCKT anAltEnd fire[A] fire[B] mc predA predB s[1] s[2] s[3] succ
-XctrAND4i@2 net@1013 succ net@1133 fire[B] fire[A] ctrAND4in30
-XctrAND4i@3 net@1007 succ fire[A] net@1155 fire[B] ctrAND4in30
-Xinv@3 net@822 s[1] inv-X_10
-Xinv@4 net@824 s[3] inv-X_10
-Xinv@5 predA net@822 inv-X_5
-Xinv@6 predB net@824 inv-X_5
-Xinv@7 net@1133 s[2] inv-X_10
-XpredDri2@0 fire[A] mc predA predDri20wMC
-XpredDri2@1 fire[B] mc predB predDri20wMC
-XrsLatchA@1 mc net@1040 net@1082 fire[B] fire[A] rsLatchA
-XsucORdri@0 fire[A] fire[B] succ sucORdri20
-Xwire90@34 net@824 net@1007 wire90-468-layer_1-width_3
-Xwire90@35 net@822 net@1013 wire90-347_9-layer_1-width_3
-Xwire90@36 net@1155 net@1082 wire90-450_6-layer_1-width_3
-Xwire90@37 net@1133 net@1040 wire90-603_6-layer_1-width_3
-.ENDS anAltEnd
-
-*** CELL: scanM:scanEx3{sch}
-.SUBCKT scanEx3 dIn[1] dIn[2] dIn[3] mc sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sor[1]
-XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanM__scanCellE
-XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanM__scanCellE
-XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sor[1] scanM__scanCellE
-Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
-Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3
-.ENDS scanEx3
+.SUBCKT wire90-341_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-341_1-R_34_667m
+.ENDS wire90-341_1-layer_1-width_3
-*** CELL: stagesM:altEndDockStage{sch}
-.SUBCKT altEndDockStage inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
-+inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23]
-+inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31]
-+inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
-+inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33]
-+inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26]
-+out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34]
-+out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] predA predB
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ
-XanAltEnd@1 fire[A] fire[B] sir[9] predA predB s[1] s[2] s[3] succ anAltEnd
-Xins2in20@0 take[A] take[B] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
-+inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23]
-+inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31]
-+inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
-+inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33]
-+inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26]
-+out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34]
-+out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax36
-XlatchDri@0 net@3 net@27 latchDriver60
-XlatchDri@1 net@7 net@23 latchDriver60
-XscanEx3@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sor[1] scanEx3
-Xwire90@0 net@7 fire[B] wire90-1336_2-layer_1-width_3
-Xwire90@1 net@3 fire[A] wire90-1307-layer_1-width_3
-Xwire90@2 net@23 take[B] wire90-1336_2-layer_1-width_3
-Xwire90@3 net@27 take[A] wire90-1307-layer_1-width_3
-.ENDS altEndDockStage
+*** CELL: loopCountM:ilcOdd{sch}
+.SUBCKT ilcOdd bit[1] bit[3] bit[5] bit[7] do[3] do[5] do[7] ilc[decLO]
++inLO[1] inLO[3] inLO[5] load[T] zero
+Xinv@5 count[T] net@273 inv-X_30
+Xinv@6 load[T] net@275 inv-X_30
+Xinv@7 ilc[decLO] net@441 inv-X_5
+Xmlat2in1@1 load[F] load[T] ilc[decLO] check[T] gnd do[7] bit[7] mlat2in10i
+Xnor2n@0 zero ilc[decLO] net@454 nor2n-X_15
+XringB@3 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB
+XringB@4 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB
+XringB@5 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB
+Xwire90@4 net@273 count[F] wire90-1588-layer_1-width_3
+Xwire90@5 net@275 load[F] wire90-1458_1-layer_1-width_3
+Xwire90@6 net@441 check[T] wire90-341_1-layer_1-width_3
+Xwire90@7 net@454 count[T] wire90-1283_3-layer_1-width_3
+.ENDS ilcOdd
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-237_2-R_34_667m a b
-Ccap@0 gnd net@14 0.87f
-Ccap@1 gnd net@8 0.87f
-Ccap@2 gnd net@11 0.87f
-Rres@0 net@14 a 1.37
-Rres@1 net@11 net@14 2.741
-Rres@2 b net@8 1.37
-Rres@3 net@8 net@11 2.741
-.ENDS wire-C_0_011f-237_2-R_34_667m
+.SUBCKT wire-C_0_011f-349_2-R_34_667m a b
+Ccap@0 gnd net@14 1.28f
+Ccap@1 gnd net@8 1.28f
+Ccap@2 gnd net@11 1.28f
+Rres@0 net@14 a 2.018
+Rres@1 net@11 net@14 4.035
+Rres@2 b net@8 2.018
+Rres@3 net@8 net@11 4.035
+.ENDS wire-C_0_011f-349_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-237_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-237_2-R_34_667m
-.ENDS wire90-237_2-layer_1-width_3
+.SUBCKT wire90-349_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-349_2-R_34_667m
+.ENDS wire90-349_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-221_8-R_34_667m a b
-Ccap@0 gnd net@14 0.813f
-Ccap@1 gnd net@8 0.813f
-Ccap@2 gnd net@11 0.813f
-Rres@0 net@14 a 1.282
-Rres@1 net@11 net@14 2.563
-Rres@2 b net@8 1.282
-Rres@3 net@8 net@11 2.563
-.ENDS wire-C_0_011f-221_8-R_34_667m
+.SUBCKT wire-C_0_011f-475_3-R_34_667m a b
+Ccap@0 gnd net@14 1.743f
+Ccap@1 gnd net@8 1.743f
+Ccap@2 gnd net@11 1.743f
+Rres@0 net@14 a 2.746
+Rres@1 net@11 net@14 5.492
+Rres@2 b net@8 2.746
+Rres@3 net@8 net@11 5.492
+.ENDS wire-C_0_011f-475_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-221_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-221_8-R_34_667m
-.ENDS wire90-221_8-layer_1-width_3
-
-*** CELL: centersJ:ctrAND4in30M{sch}
-.SUBCKT ctrAND4in30M inA inB inC inD out outM
-Xinv@1 outM out inv-X_30
-Xnand2@1 net@43 net@58 outM nand2-X_10
-Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4
-Xnor2n@0 inD inC net@64 nor2n-X_5
-Xwire90@0 net@64 net@43 wire90-237_2-layer_1-width_3
-Xwire90@2 net@61 net@58 wire90-221_8-layer_1-width_3
-.ENDS ctrAND4in30M
-
-*** CELL: redFive:nand2n_sy{sch}
-.SUBCKT nand2n_sy-X_10 ina inb out
-Xnand2_sy@0 ina inb out nand2_sy-X_10
-.ENDS nand2n_sy-X_10
+.SUBCKT wire90-475_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-475_3-R_34_667m
+.ENDS wire90-475_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-700-R_34_667m a b
-Ccap@0 gnd net@14 2.567f
-Ccap@1 gnd net@8 2.567f
-Ccap@2 gnd net@11 2.567f
-Rres@0 net@14 a 4.044
-Rres@1 net@11 net@14 8.089
-Rres@2 b net@8 4.044
-Rres@3 net@8 net@11 8.089
-.ENDS wire-C_0_011f-700-R_34_667m
+.SUBCKT wire-C_0_011f-422_8-R_34_667m a b
+Ccap@0 gnd net@14 1.55f
+Ccap@1 gnd net@8 1.55f
+Ccap@2 gnd net@11 1.55f
+Rres@0 net@14 a 2.443
+Rres@1 net@11 net@14 4.886
+Rres@2 b net@8 2.443
+Rres@3 net@8 net@11 4.886
+.ENDS wire-C_0_011f-422_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-700-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-700-R_34_667m
-.ENDS wire90-700-layer_1-width_3
+.SUBCKT wire90-422_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-422_8-R_34_667m
+.ENDS wire90-422_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-839_6-R_34_667m a b
-Ccap@0 gnd net@14 3.079f
-Ccap@1 gnd net@8 3.079f
-Ccap@2 gnd net@11 3.079f
-Rres@0 net@14 a 4.851
-Rres@1 net@11 net@14 9.702
-Rres@2 b net@8 4.851
-Rres@3 net@8 net@11 9.702
-.ENDS wire-C_0_011f-839_6-R_34_667m
+.SUBCKT wire-C_0_011f-484_8-R_34_667m a b
+Ccap@0 gnd net@14 1.778f
+Ccap@1 gnd net@8 1.778f
+Ccap@2 gnd net@11 1.778f
+Rres@0 net@14 a 2.801
+Rres@1 net@11 net@14 5.602
+Rres@2 b net@8 2.801
+Rres@3 net@8 net@11 5.602
+.ENDS wire-C_0_011f-484_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-839_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-839_6-R_34_667m
-.ENDS wire90-839_6-layer_1-width_3
+.SUBCKT wire90-484_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-484_8-R_34_667m
+.ENDS wire90-484_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-438_2-R_34_667m a b
-Ccap@0 gnd net@14 1.607f
-Ccap@1 gnd net@8 1.607f
-Ccap@2 gnd net@11 1.607f
-Rres@0 net@14 a 2.532
-Rres@1 net@11 net@14 5.064
-Rres@2 b net@8 2.532
-Rres@3 net@8 net@11 5.064
-.ENDS wire-C_0_011f-438_2-R_34_667m
+.SUBCKT wire-C_0_011f-407_8-R_34_667m a b
+Ccap@0 gnd net@14 1.495f
+Ccap@1 gnd net@8 1.495f
+Ccap@2 gnd net@11 1.495f
+Rres@0 net@14 a 2.356
+Rres@1 net@11 net@14 4.712
+Rres@2 b net@8 2.356
+Rres@3 net@8 net@11 4.712
+.ENDS wire-C_0_011f-407_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-438_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-438_2-R_34_667m
-.ENDS wire90-438_2-layer_1-width_3
+.SUBCKT wire90-407_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-407_8-R_34_667m
+.ENDS wire90-407_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-257_4-R_34_667m a b
-Ccap@0 gnd net@14 0.944f
-Ccap@1 gnd net@8 0.944f
-Ccap@2 gnd net@11 0.944f
-Rres@0 net@14 a 1.487
-Rres@1 net@11 net@14 2.974
-Rres@2 b net@8 1.487
-Rres@3 net@8 net@11 2.974
-.ENDS wire-C_0_011f-257_4-R_34_667m
+.SUBCKT wire-C_0_011f-999_1-R_34_667m a b
+Ccap@0 gnd net@14 3.663f
+Ccap@1 gnd net@8 3.663f
+Ccap@2 gnd net@11 3.663f
+Rres@0 net@14 a 5.773
+Rres@1 net@11 net@14 11.545
+Rres@2 b net@8 5.773
+Rres@3 net@8 net@11 11.545
+.ENDS wire-C_0_011f-999_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-257_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-257_4-R_34_667m
-.ENDS wire90-257_4-layer_1-width_3
+.SUBCKT wire90-999_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-999_1-R_34_667m
+.ENDS wire90-999_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-458_8-R_34_667m a b
-Ccap@0 gnd net@14 1.682f
-Ccap@1 gnd net@8 1.682f
-Ccap@2 gnd net@11 1.682f
-Rres@0 net@14 a 2.651
-Rres@1 net@11 net@14 5.302
-Rres@2 b net@8 2.651
-Rres@3 net@8 net@11 5.302
-.ENDS wire-C_0_011f-458_8-R_34_667m
+.SUBCKT wire-C_0_011f-1276_9-R_34_667m a b
+Ccap@0 gnd net@14 4.682f
+Ccap@1 gnd net@8 4.682f
+Ccap@2 gnd net@11 4.682f
+Rres@0 net@14 a 7.378
+Rres@1 net@11 net@14 14.755
+Rres@2 b net@8 7.378
+Rres@3 net@8 net@11 14.755
+.ENDS wire-C_0_011f-1276_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-458_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-458_8-R_34_667m
-.ENDS wire90-458_8-layer_1-width_3
+.SUBCKT wire90-1276_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1276_9-R_34_667m
+.ENDS wire90-1276_9-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-744_5-R_34_667m a b
-Ccap@0 gnd net@14 2.73f
-Ccap@1 gnd net@8 2.73f
-Ccap@2 gnd net@11 2.73f
-Rres@0 net@14 a 4.302
-Rres@1 net@11 net@14 8.603
-Rres@2 b net@8 4.302
-Rres@3 net@8 net@11 8.603
-.ENDS wire-C_0_011f-744_5-R_34_667m
+*** CELL: loopCountM:ilc{sch}
+.SUBCKT ilc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8]
++ilc[decLO] ilc[do] ilc[load] ilc[mo] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
++inLO[6] inLO[8]
+Xcalculat@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4]
++do[5] do[6] net@422 do[7] calculate
+XilcEven@0 bitt[2] bitt[4] bitt[6] bitt[8] do[2] do[4] do[6] ilc[decLO]
++inLO[2] inLO[4] inLO[6] inLO[8] ilc[load] zero ilcEven
+XilcOdd@0 bitt[1] bitt[3] bitt[5] bitt[7] do[3] do[5] do[7] ilc[decLO]
++inLO[1] inLO[3] inLO[5] ilc[load] zero ilcOdd
+Xnand2@0 bitt[8] do[7] ilc[mo] nand2-X_10
+Xnand3@0 bitt[8] bitt[7] zero ilc[do] nand3-X_6_667
+Xwire90@1 wire90@1_a do[2] wire90-349_2-layer_1-width_3
+Xwire90@2 wire90@2_a do[3] wire90-475_3-layer_1-width_3
+Xwire90@3 wire90@3_a do[4] wire90-422_8-layer_1-width_3
+Xwire90@4 wire90@4_a do[5] wire90-484_8-layer_1-width_3
+Xwire90@5 wire90@5_a do[6] wire90-407_8-layer_1-width_3
+Xwire90@6 wire90@6_a do[7] wire90-999_1-layer_1-width_3
+Xwire90@41 zero net@422 wire90-1276_9-layer_1-width_3
+.ENDS ilc
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-744_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-744_5-R_34_667m
-.ENDS wire90-744_5-layer_1-width_3
+*** CELL: driversL:predORdri20wMC{sch}
+.SUBCKT predORdri20wMC inA inB mc pred
+XNMOSx@0 pred inA gnd NMOSx-X_20
+XNMOSx@1 pred mc gnd NMOSx-X_4
+XNMOSx@2 pred inB gnd NMOSx-X_20
+XPMOSx@1 pred net@217 net@203 PMOSx-X_4
+XPMOSx@2 net@203 inB net@204 PMOSx-X_4
+XPMOSx@3 net@204 inA net@205 PMOSx-X_4
+XPMOSx@4 net@205 mc vdd PMOSx-X_4
+Xinv@0 pred net@145 inv-X_4
+Xwire90@0 net@217 net@145 wire90-243_6-layer_1-width_3
+.ENDS predORdri20wMC
-*** CELL: gaspL:anAltStart{sch}
-.SUBCKT anAltStart fire[A] fire[B] mc pred s[1] s[2] succA succB
-XctrAND4i@1 net@634 succA fire[B] net@912 fire[A] net@866 ctrAND4in30M
-XctrAND4i@3 net@634 succB net@909 fire[A] fire[B] net@885 ctrAND4in30M
-Xinv@3 net@634 s[1] inv-X_10
-Xinv@4 pred net@787 inv-X_10
-Xinv@5 net@912 s[2] inv-X_10
-Xnand2n_s@0 net@143 net@410 net@422 nand2n_sy-X_10
-XpredDri2@0 net@815 mc pred predDri20wMC
-XrsLatchA@1 mc net@905 net@911 fire[B] fire[A] rsLatchA
-XsucDri20@0 fire[A] succA sucDri20
-XsucDri20@1 fire[B] succB sucDri20
-Xwire90@16 net@410 net@866 wire90-700-layer_1-width_3
-Xwire90@17 net@143 net@885 wire90-839_6-layer_1-width_3
-Xwire90@19 net@912 net@905 wire90-438_2-layer_1-width_3
-Xwire90@20 net@815 net@422 wire90-257_4-layer_1-width_3
-Xwire90@27 net@909 net@911 wire90-458_8-layer_1-width_3
-Xwire90@28 net@787 net@634 wire90-744_5-layer_1-width_3
-.ENDS anAltStart
+*** CELL: redFive:nand2n{sch}
+.SUBCKT nand2n-X_20 ina inb out
+Xnand2@0 ina inb out nand2-X_20
+.ENDS nand2n-X_20
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1300-R_34_667m a b
-Ccap@0 gnd net@14 4.767f
-Ccap@1 gnd net@8 4.767f
-Ccap@2 gnd net@11 4.767f
-Rres@0 net@14 a 7.511
-Rres@1 net@11 net@14 15.022
-Rres@2 b net@8 7.511
-Rres@3 net@8 net@11 15.022
-.ENDS wire-C_0_011f-1300-R_34_667m
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_22 d g s
+MPMOSf@0 d g s vdd pch W='132*(1+ABP/sqrt(132*2))' L='2'
++DELVTO='AVT0P/sqrt(132*2)'
+.ENDS PMOSx-X_22
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1300-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1300-R_34_667m
-.ENDS wire90-1300-layer_1-width_3
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_66 d g s
+MNMOSf@0 d g s gnd nch W='198*(1+ABN/sqrt(198*2))' L='2'
++DELVTO='AVT0N/sqrt(198*2)'
+.ENDS NMOSx-X_66
+
+*** CELL: redFive:nms3{sch}
+.SUBCKT nms3-X_22 d g g2 g3
+XNMOS@0 d g3 net@6 NMOSx-X_66
+XNMOS@1 net@7 g gnd NMOSx-X_66
+XNMOS@2 net@6 g2 net@7 NMOSx-X_66
+.ENDS nms3-X_22
+
+*** CELL: redFive:nand3{sch}
+.SUBCKT nand3-X_22 ina inb inc out
+XPMOS@0 out inc vdd PMOSx-X_22
+XPMOS@1 out inb vdd PMOSx-X_22
+XPMOS@2 out ina vdd PMOSx-X_22
+Xnms3@0 out ina inb inc nms3-X_22
+.ENDS nand3-X_22
+
+*** CELL: gates3inM:nand3in44s{sch}
+.SUBCKT nand3in44s inA inB inC out
+Xnand3@0 inA inB inC out nand3-X_22
+Xnand3@1 inB inA inC out nand3-X_22
+.ENDS nand3in44s
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1301_9-R_34_667m a b
-Ccap@0 gnd net@14 4.774f
-Ccap@1 gnd net@8 4.774f
-Ccap@2 gnd net@11 4.774f
-Rres@0 net@14 a 7.522
-Rres@1 net@11 net@14 15.044
-Rres@2 b net@8 7.522
-Rres@3 net@8 net@11 15.044
-.ENDS wire-C_0_011f-1301_9-R_34_667m
+.SUBCKT wire-C_0_011f-321_9-R_34_667m a b
+Ccap@0 gnd net@14 1.18f
+Ccap@1 gnd net@8 1.18f
+Ccap@2 gnd net@11 1.18f
+Rres@0 net@14 a 1.86
+Rres@1 net@11 net@14 3.72
+Rres@2 b net@8 1.86
+Rres@3 net@8 net@11 3.72
+.ENDS wire-C_0_011f-321_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1301_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1301_9-R_34_667m
-.ENDS wire90-1301_9-layer_1-width_3
-
-*** CELL: stagesM:altStartDockStage{sch}
-.SUBCKT altStartDockStage in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] outA[10] outA[11] outA[12] outA[13]
-+outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20]
-+outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28]
-+outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35]
-+outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] outB[10]
-+outB[11] outB[12] outB[13] outB[14] outB[15] outB[16] outB[17] outB[18]
-+outB[19] outB[1] outB[20] outB[21] outB[22] outB[23] outB[24] outB[25]
-+outB[26] outB[27] outB[28] outB[29] outB[2] outB[30] outB[31] outB[32]
-+outB[33] outB[34] outB[35] outB[36] outB[3] outB[4] outB[5] outB[6] outB[7]
-+outB[8] outB[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] sor[1] succA succB
-XanAltSta@0 fire[A] fire[B] sir[9] pred net@48[1] net@48[0] succA succB
-+anAltStart
-Xins1in20@0 net@23 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] outA[10] outA[11] outA[12] outA[13]
-+outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20]
-+outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28]
-+outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35]
-+outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] ins1in20Bx36
-Xins1in20@1 net@25 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] outB[10] outB[11] outB[12] outB[13]
-+outB[14] outB[15] outB[16] outB[17] outB[18] outB[19] outB[1] outB[20]
-+outB[21] outB[22] outB[23] outB[24] outB[25] outB[26] outB[27] outB[28]
-+outB[29] outB[2] outB[30] outB[31] outB[32] outB[33] outB[34] outB[35]
-+outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] outB[8] outB[9] ins1in20Bx36
-XlatchDri@0 net@5 net@20 latchDriver60
-XlatchDri@1 net@6 net@22 latchDriver60
-XscanEx2v@1 net@48[1] net@48[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sor[1] scanEx2
-Xwire90@0 fire[A] net@5 wire90-1300-layer_1-width_3
-Xwire90@1 fire[B] net@6 wire90-1301_9-layer_1-width_3
-Xwire90@2 net@20 net@23 wire90-1300-layer_1-width_3
-Xwire90@3 net@22 net@25 wire90-1300-layer_1-width_3
-.ENDS altStartDockStage
+.SUBCKT wire90-321_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-321_9-R_34_667m
+.ENDS wire90-321_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-249_5-R_34_667m a b
-Ccap@0 gnd net@14 0.915f
-Ccap@1 gnd net@8 0.915f
-Ccap@2 gnd net@11 0.915f
-Rres@0 net@14 a 1.442
-Rres@1 net@11 net@14 2.883
-Rres@2 b net@8 1.442
-Rres@3 net@8 net@11 2.883
-.ENDS wire-C_0_011f-249_5-R_34_667m
+.SUBCKT wire-C_0_011f-294-R_34_667m a b
+Ccap@0 gnd net@14 1.078f
+Ccap@1 gnd net@8 1.078f
+Ccap@2 gnd net@11 1.078f
+Rres@0 net@14 a 1.699
+Rres@1 net@11 net@14 3.397
+Rres@2 b net@8 1.699
+Rres@3 net@8 net@11 3.397
+.ENDS wire-C_0_011f-294-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-249_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-249_5-R_34_667m
-.ENDS wire90-249_5-layer_1-width_3
+.SUBCKT wire90-294-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-294-R_34_667m
+.ENDS wire90-294-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-355_8-R_34_667m a b
-Ccap@0 gnd net@14 1.305f
-Ccap@1 gnd net@8 1.305f
-Ccap@2 gnd net@11 1.305f
-Rres@0 net@14 a 2.056
-Rres@1 net@11 net@14 4.111
-Rres@2 b net@8 2.056
-Rres@3 net@8 net@11 4.111
-.ENDS wire-C_0_011f-355_8-R_34_667m
+.SUBCKT wire-C_0_011f-572_3-R_34_667m a b
+Ccap@0 gnd net@14 2.098f
+Ccap@1 gnd net@8 2.098f
+Ccap@2 gnd net@11 2.098f
+Rres@0 net@14 a 3.307
+Rres@1 net@11 net@14 6.613
+Rres@2 b net@8 3.307
+Rres@3 net@8 net@11 6.613
+.ENDS wire-C_0_011f-572_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-355_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-355_8-R_34_667m
-.ENDS wire90-355_8-layer_1-width_3
+.SUBCKT wire90-572_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-572_3-R_34_667m
+.ENDS wire90-572_3-layer_1-width_3
-*** CELL: centersJ:ctrAND2in30{sch}
-.SUBCKT ctrAND2in30 inA inB out
-Xinv@0 net@7 net@8 inv-X_10
-Xinv@1 net@9 out inv-X_30
-Xnor2HT_s@1 inA inB net@6 nor2HT_sy-X_4
-Xwire90@0 net@6 net@7 wire90-249_5-layer_1-width_3
-Xwire90@1 net@8 net@9 wire90-355_8-layer_1-width_3
-.ENDS ctrAND2in30
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-741_5-R_34_667m a b
+Ccap@0 gnd net@14 2.719f
+Ccap@1 gnd net@8 2.719f
+Ccap@2 gnd net@11 2.719f
+Rres@0 net@14 a 4.284
+Rres@1 net@11 net@14 8.568
+Rres@2 b net@8 4.284
+Rres@3 net@8 net@11 8.568
+.ENDS wire-C_0_011f-741_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-741_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-741_5-R_34_667m
+.ENDS wire90-741_5-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-291_8-R_34_667m a b
-Ccap@0 gnd net@14 1.07f
-Ccap@1 gnd net@8 1.07f
-Ccap@2 gnd net@11 1.07f
-Rres@0 net@14 a 1.686
-Rres@1 net@11 net@14 3.372
-Rres@2 b net@8 1.686
-Rres@3 net@8 net@11 3.372
-.ENDS wire-C_0_011f-291_8-R_34_667m
+.SUBCKT wire-C_0_011f-783-R_34_667m a b
+Ccap@0 gnd net@14 2.871f
+Ccap@1 gnd net@8 2.871f
+Ccap@2 gnd net@11 2.871f
+Rres@0 net@14 a 4.524
+Rres@1 net@11 net@14 9.048
+Rres@2 b net@8 4.524
+Rres@3 net@8 net@11 9.048
+.ENDS wire-C_0_011f-783-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-291_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-291_8-R_34_667m
-.ENDS wire90-291_8-layer_1-width_3
+.SUBCKT wire90-783-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-783-R_34_667m
+.ENDS wire90-783-layer_1-width_3
-*** CELL: gaspM:aStage{sch}
-.SUBCKT gaspM__aStage fire mc pred s[1] succ
-XctrAND2i@4 net@494 succ fire ctrAND2in30
-Xinv@4 net@987 s[1] inv-X_10
-Xinv@5 pred net@987 inv-X_5
-XpredDri2@1 fire mc pred predDri20wMC
-XsucDri20@1 fire succ sucDri20
-Xwire90@0 net@987 net@494 wire90-291_8-layer_1-width_3
-.ENDS gaspM__aStage
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1254_1-R_34_667m a b
+Ccap@0 gnd net@14 4.598f
+Ccap@1 gnd net@8 4.598f
+Ccap@2 gnd net@11 4.598f
+Rres@0 net@14 a 7.246
+Rres@1 net@11 net@14 14.492
+Rres@2 b net@8 7.246
+Rres@3 net@8 net@11 14.492
+.ENDS wire-C_0_011f-1254_1-R_34_667m
-*** CELL: stagesM:plainDockStage{sch}
-.SUBCKT plainDockStage in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] sor[1] succ take[1]
-XaStage@1 net@1 sir[9] pred net@41 succ gaspM__aStage
-Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
-+out[7] out[8] out[9] ins1in20Bx36
-XlatchDri@0 fire[1] take[1] latchDriver60
-XscanEx1v@0 net@41 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1vertA
-Xwire90@1 net@1 fire[1] wire90-791_7-layer_1-width_3
-.ENDS plainDockStage
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1254_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1254_1-R_34_667m
+.ENDS wire90-1254_1-layer_1-width_3
-*** CELL: stageGroupsM:dockWagNine{sch}
-.SUBCKT dockWagNine in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
-+out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] sor[1] succ take[1] take[2] take[3] take[4] take[5] take[6]
-XaltEndDo@0 net@16[26] net@16[25] net@16[24] net@16[23] net@16[22] net@16[21]
-+net@16[20] net@16[19] net@16[18] net@16[17] net@16[35] net@16[16] net@16[15]
-+net@16[14] net@16[13] net@16[12] net@16[11] net@16[10] net@16[9] net@16[8]
-+net@16[7] net@16[34] net@16[6] net@16[5] net@16[4] net@16[3] net@16[2]
-+net@16[1] net@16[0] net@16[33] net@16[32] net@16[31] net@16[30] net@16[29]
-+net@16[28] net@16[27] net@19[26] net@19[25] net@19[24] net@19[23] net@19[22]
-+net@19[21] net@19[20] net@19[19] net@19[18] net@19[17] net@19[35] net@19[16]
-+net@19[15] net@19[14] net@19[13] net@19[12] net@19[11] net@19[10] net@19[9]
-+net@19[8] net@19[7] net@19[34] net@19[6] net@19[5] net@19[4] net@19[3]
-+net@19[2] net@19[1] net@19[0] net@19[33] net@19[32] net@19[31] net@19[30]
-+net@19[29] net@19[28] net@19[27] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
-+out[7] out[8] out[9] net@69 net@58 net@134[8] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] sor[1] succ altEndDockStage
-XaltStart@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4]
-+in[5] in[6] in[7] in[8] in[9] net@21[26] net@21[25] net@21[24] net@21[23]
-+net@21[22] net@21[21] net@21[20] net@21[19] net@21[18] net@21[17] net@21[35]
-+net@21[16] net@21[15] net@21[14] net@21[13] net@21[12] net@21[11] net@21[10]
-+net@21[9] net@21[8] net@21[7] net@21[34] net@21[6] net@21[5] net@21[4]
-+net@21[3] net@21[2] net@21[1] net@21[0] net@21[33] net@21[32] net@21[31]
-+net@21[30] net@21[29] net@21[28] net@21[27] net@20[26] net@20[25] net@20[24]
-+net@20[23] net@20[22] net@20[21] net@20[20] net@20[19] net@20[18] net@20[17]
-+net@20[35] net@20[16] net@20[15] net@20[14] net@20[13] net@20[12] net@20[11]
-+net@20[10] net@20[9] net@20[8] net@20[7] net@20[34] net@20[6] net@20[5]
-+net@20[4] net@20[3] net@20[2] net@20[1] net@20[0] net@20[33] net@20[32]
-+net@20[31] net@20[30] net@20[29] net@20[28] net@20[27] pred sir[1] sir[2]
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@116[8] net@97 net@100
-+altStartDockStage
-XplainDoc@0 net@2[26] net@2[25] net@2[24] net@2[23] net@2[22] net@2[21]
-+net@2[20] net@2[19] net@2[18] net@2[17] net@2[35] net@2[16] net@2[15]
-+net@2[14] net@2[13] net@2[12] net@2[11] net@2[10] net@2[9] net@2[8] net@2[7]
-+net@2[34] net@2[6] net@2[5] net@2[4] net@2[3] net@2[2] net@2[1] net@2[0]
-+net@2[33] net@2[32] net@2[31] net@2[30] net@2[29] net@2[28] net@2[27]
-+net@3[26] net@3[25] net@3[24] net@3[23] net@3[22] net@3[21] net@3[20]
-+net@3[19] net@3[18] net@3[17] net@3[35] net@3[16] net@3[15] net@3[14]
-+net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7] net@3[34]
-+net@3[6] net@3[5] net@3[4] net@3[3] net@3[2] net@3[1] net@3[0] net@3[33]
-+net@3[32] net@3[31] net@3[30] net@3[29] net@3[28] net@3[27] net@107
-+net@131[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@130[8]
-+net@106 take[5] plainDockStage
-XplainDoc@1 net@20[26] net@20[25] net@20[24] net@20[23] net@20[22] net@20[21]
-+net@20[20] net@20[19] net@20[18] net@20[17] net@20[35] net@20[16] net@20[15]
-+net@20[14] net@20[13] net@20[12] net@20[11] net@20[10] net@20[9] net@20[8]
-+net@20[7] net@20[34] net@20[6] net@20[5] net@20[4] net@20[3] net@20[2]
-+net@20[1] net@20[0] net@20[33] net@20[32] net@20[31] net@20[30] net@20[29]
-+net@20[28] net@20[27] net@2[26] net@2[25] net@2[24] net@2[23] net@2[22]
-+net@2[21] net@2[20] net@2[19] net@2[18] net@2[17] net@2[35] net@2[16]
-+net@2[15] net@2[14] net@2[13] net@2[12] net@2[11] net@2[10] net@2[9] net@2[8]
-+net@2[7] net@2[34] net@2[6] net@2[5] net@2[4] net@2[3] net@2[2] net@2[1]
-+net@2[0] net@2[33] net@2[32] net@2[31] net@2[30] net@2[29] net@2[28]
-+net@2[27] net@60 net@125[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] net@131[8] net@108 take[4] plainDockStage
-XplainDoc@2 net@3[26] net@3[25] net@3[24] net@3[23] net@3[22] net@3[21]
-+net@3[20] net@3[19] net@3[18] net@3[17] net@3[35] net@3[16] net@3[15]
-+net@3[14] net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7]
-+net@3[34] net@3[6] net@3[5] net@3[4] net@3[3] net@3[2] net@3[1] net@3[0]
-+net@3[33] net@3[32] net@3[31] net@3[30] net@3[29] net@3[28] net@3[27]
-+net@19[26] net@19[25] net@19[24] net@19[23] net@19[22] net@19[21] net@19[20]
-+net@19[19] net@19[18] net@19[17] net@19[35] net@19[16] net@19[15] net@19[14]
-+net@19[13] net@19[12] net@19[11] net@19[10] net@19[9] net@19[8] net@19[7]
-+net@19[34] net@19[6] net@19[5] net@19[4] net@19[3] net@19[2] net@19[1]
-+net@19[0] net@19[33] net@19[32] net@19[31] net@19[30] net@19[29] net@19[28]
-+net@19[27] net@105 net@130[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@134[8] net@104 take[6] plainDockStage
-XplainDoc@3 net@0[26] net@0[25] net@0[24] net@0[23] net@0[22] net@0[21]
-+net@0[20] net@0[19] net@0[18] net@0[17] net@0[35] net@0[16] net@0[15]
-+net@0[14] net@0[13] net@0[12] net@0[11] net@0[10] net@0[9] net@0[8] net@0[7]
-+net@0[34] net@0[6] net@0[5] net@0[4] net@0[3] net@0[2] net@0[1] net@0[0]
-+net@0[33] net@0[32] net@0[31] net@0[30] net@0[29] net@0[28] net@0[27]
-+net@1[26] net@1[25] net@1[24] net@1[23] net@1[22] net@1[21] net@1[20]
-+net@1[19] net@1[18] net@1[17] net@1[35] net@1[16] net@1[15] net@1[14]
-+net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] net@1[7] net@1[34]
-+net@1[6] net@1[5] net@1[4] net@1[3] net@1[2] net@1[1] net@1[0] net@1[33]
-+net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] net@1[27] net@109
-+net@127[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@128[8]
-+net@111 take[2] plainDockStage
-XplainDoc@4 net@21[26] net@21[25] net@21[24] net@21[23] net@21[22] net@21[21]
-+net@21[20] net@21[19] net@21[18] net@21[17] net@21[35] net@21[16] net@21[15]
-+net@21[14] net@21[13] net@21[12] net@21[11] net@21[10] net@21[9] net@21[8]
-+net@21[7] net@21[34] net@21[6] net@21[5] net@21[4] net@21[3] net@21[2]
-+net@21[1] net@21[0] net@21[33] net@21[32] net@21[31] net@21[30] net@21[29]
-+net@21[28] net@21[27] net@0[26] net@0[25] net@0[24] net@0[23] net@0[22]
-+net@0[21] net@0[20] net@0[19] net@0[18] net@0[17] net@0[35] net@0[16]
-+net@0[15] net@0[14] net@0[13] net@0[12] net@0[11] net@0[10] net@0[9] net@0[8]
-+net@0[7] net@0[34] net@0[6] net@0[5] net@0[4] net@0[3] net@0[2] net@0[1]
-+net@0[0] net@0[33] net@0[32] net@0[31] net@0[30] net@0[29] net@0[28]
-+net@0[27] net@64 net@116[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] net@127[8] net@110 take[1] plainDockStage
-XplainDoc@5 net@1[26] net@1[25] net@1[24] net@1[23] net@1[22] net@1[21]
-+net@1[20] net@1[19] net@1[18] net@1[17] net@1[35] net@1[16] net@1[15]
-+net@1[14] net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] net@1[7]
-+net@1[34] net@1[6] net@1[5] net@1[4] net@1[3] net@1[2] net@1[1] net@1[0]
-+net@1[33] net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] net@1[27]
-+net@16[26] net@16[25] net@16[24] net@16[23] net@16[22] net@16[21] net@16[20]
-+net@16[19] net@16[18] net@16[17] net@16[35] net@16[16] net@16[15] net@16[14]
-+net@16[13] net@16[12] net@16[11] net@16[10] net@16[9] net@16[8] net@16[7]
-+net@16[34] net@16[6] net@16[5] net@16[4] net@16[3] net@16[2] net@16[1]
-+net@16[0] net@16[33] net@16[32] net@16[31] net@16[30] net@16[29] net@16[28]
-+net@16[27] net@112 net@128[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@125[8] net@102 take[3] plainDockStage
-Xwire90@0 net@97 net@64 wire90-414-layer_1-width_3
-Xwire90@1 net@100 net@60 wire90-414-layer_1-width_3
-Xwire90@2 net@110 net@109 wire90-414-layer_1-width_3
-Xwire90@3 net@106 net@105 wire90-414-layer_1-width_3
-Xwire90@4 net@111 net@112 wire90-414-layer_1-width_3
-Xwire90@5 net@104 net@58 wire90-414-layer_1-width_3
-Xwire90@6 net@108 net@107 wire90-414-layer_1-width_3
-Xwire90@7 net@102 net@69 wire90-414-layer_1-width_3
-.ENDS dockWagNine
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1300_1-R_34_667m a b
+Ccap@0 gnd net@14 4.767f
+Ccap@1 gnd net@8 4.767f
+Ccap@2 gnd net@11 4.767f
+Rres@0 net@14 a 7.512
+Rres@1 net@11 net@14 15.023
+Rres@2 b net@8 7.512
+Rres@3 net@8 net@11 15.023
+.ENDS wire-C_0_011f-1300_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1300_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1300_1-R_34_667m
+.ENDS wire90-1300_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-161_8-R_34_667m a b
-Ccap@0 gnd net@14 0.593f
-Ccap@1 gnd net@8 0.593f
-Ccap@2 gnd net@11 0.593f
-Rres@0 net@14 a 0.935
-Rres@1 net@11 net@14 1.87
-Rres@2 b net@8 0.935
-Rres@3 net@8 net@11 1.87
-.ENDS wire-C_0_011f-161_8-R_34_667m
+.SUBCKT wire-C_0_011f-392_9-R_34_667m a b
+Ccap@0 gnd net@14 1.441f
+Ccap@1 gnd net@8 1.441f
+Ccap@2 gnd net@11 1.441f
+Rres@0 net@14 a 2.27
+Rres@1 net@11 net@14 4.54
+Rres@2 b net@8 2.27
+Rres@3 net@8 net@11 4.54
+.ENDS wire-C_0_011f-392_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-161_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-161_8-R_34_667m
-.ENDS wire90-161_8-layer_1-width_3
+.SUBCKT wire90-392_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-392_9-R_34_667m
+.ENDS wire90-392_9-layer_1-width_3
-*** CELL: centersJ:ctrAND2in30A{sch}
-.SUBCKT ctrAND2in30A inA inB out
-Xinv@1 net@9 out inv-X_30
-Xinv@2 inA net@27 inv-X_5
-Xnand2LT_@0 net@32 inB net@24 nand2LT_sy-X_10
-Xwire90@0 net@27 net@32 wire90-161_8-layer_1-width_3
-Xwire90@1 net@24 net@9 wire90-372_8-layer_1-width_3
-.ENDS ctrAND2in30A
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-174_7-R_34_667m a b
+Ccap@0 gnd net@14 0.641f
+Ccap@1 gnd net@8 0.641f
+Ccap@2 gnd net@11 0.641f
+Rres@0 net@14 a 1.009
+Rres@1 net@11 net@14 2.019
+Rres@2 b net@8 1.009
+Rres@3 net@8 net@11 2.019
+.ENDS wire-C_0_011f-174_7-R_34_667m
-*** CELL: gaspM:gaspLit{sch}
-.SUBCKT gaspLit do[L] fire[L] mc ready s[1]
-XctrAND2i@0 net@189 ready fire[L] ctrAND2in30A
-Xinv@1 do[L] net@190 inv-X_5
-XinvI@0 net@189 s[1] inv-X_10
-XpredDri2@1 fire[L] mc do[L] predDri20wMC
-Xwire90@1 net@190 net@189 wire90-414-layer_1-width_3
-.ENDS gaspLit
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-174_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-174_7-R_34_667m
+.ENDS wire90-174_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-295_8-R_34_667m a b
-Ccap@0 gnd net@14 1.085f
-Ccap@1 gnd net@8 1.085f
-Ccap@2 gnd net@11 1.085f
-Rres@0 net@14 a 1.709
-Rres@1 net@11 net@14 3.418
-Rres@2 b net@8 1.709
-Rres@3 net@8 net@11 3.418
-.ENDS wire-C_0_011f-295_8-R_34_667m
+.SUBCKT wire-C_0_011f-1154_9-R_34_667m a b
+Ccap@0 gnd net@14 4.235f
+Ccap@1 gnd net@8 4.235f
+Ccap@2 gnd net@11 4.235f
+Rres@0 net@14 a 6.673
+Rres@1 net@11 net@14 13.346
+Rres@2 b net@8 6.673
+Rres@3 net@8 net@11 13.346
+.ENDS wire-C_0_011f-1154_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-295_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-295_8-R_34_667m
-.ENDS wire90-295_8-layer_1-width_3
+.SUBCKT wire90-1154_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1154_9-R_34_667m
+.ENDS wire90-1154_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-555_8-R_34_667m a b
-Ccap@0 gnd net@14 2.038f
-Ccap@1 gnd net@8 2.038f
-Ccap@2 gnd net@11 2.038f
-Rres@0 net@14 a 3.211
-Rres@1 net@11 net@14 6.423
-Rres@2 b net@8 3.211
-Rres@3 net@8 net@11 6.423
-.ENDS wire-C_0_011f-555_8-R_34_667m
+.SUBCKT wire-C_0_011f-590_5-R_34_667m a b
+Ccap@0 gnd net@14 2.165f
+Ccap@1 gnd net@8 2.165f
+Ccap@2 gnd net@11 2.165f
+Rres@0 net@14 a 3.412
+Rres@1 net@11 net@14 6.824
+Rres@2 b net@8 3.412
+Rres@3 net@8 net@11 6.824
+.ENDS wire-C_0_011f-590_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-555_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-555_8-R_34_667m
-.ENDS wire90-555_8-layer_1-width_3
+.SUBCKT wire90-590_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-590_5-R_34_667m
+.ENDS wire90-590_5-layer_1-width_3
-*** CELL: latchesK:latch2in60C{sch}
-.SUBCKT latch2in60C hcl[A] hcl[B] inA[1] inB[1] outS[1]
-Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@14 raw2inLatchF
-XinvLT@0 net@15 net@18 invLT-X_5
-XinvLT@1 net@16 net@19 inv-X_20
-XinvLT@2 net@17 outS[1] inv-X_60
-Xwire90@0 net@14 net@15 wire90-295_8-layer_1-width_3
-Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3
-Xwire90@2 net@19 net@17 wire90-555_8-layer_1-width_3
-.ENDS latch2in60C
+*** CELL: moveM:races{sch}
+.SUBCKT races bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] in[D] in[T] succ torp
++winHI[M] winLO[M]
+Xarbiter2@0 net@131 net@128 torp in[D] arbiter2
+Xarbiter2@1 net@130 net@129 torp in[T] arbiter2
+XinvI@0 net@150 fire[T] inv-X_20
+Xnand2@0 bit[Di] do[Tp] net@35 nand2-X_10
+Xnand2@1 bit[Ti] do[Tp] net@42 nand2-X_10
+Xnand2@2 net@94 do[Mv] net@86 nand2-X_5
+Xnand2@3 winLO[M] winLO[M] winHI[M] nand2-X_5
+Xnand2n@0 bit[Di] net@11 net@57 nand2n-X_20
+Xnand2n@1 bit[Ti] net@53 net@60 nand2n-X_20
+Xnand3in4@0 net@159 net@123 net@98 winLO[M] nand3in44s
+Xnor2_sy@0 net@48 net@45 net@151 nor2_sy-X_20
+Xnor2n@0 net@39 net@12 net@44 nor2n-X_20
+Xnor2n@1 net@36 net@32 net@43 nor2n-X_20
+Xnor2n@2 succ net@153 net@152 nor2n-X_20
+Xnor2n@3 net@171 net@171 net@176 nor2n-X_5
+Xwire90@0 net@131 net@12 wire90-321_9-layer_1-width_3
+Xwire90@1 net@130 net@32 wire90-321_9-layer_1-width_3
+Xwire90@2 net@129 net@53 wire90-294-layer_1-width_3
+Xwire90@3 net@128 net@11 wire90-294-layer_1-width_3
+Xwire90@4 net@35 net@39 wire90-572_3-layer_1-width_3
+Xwire90@5 net@42 net@36 wire90-572_3-layer_1-width_3
+Xwire90@6 net@44 net@45 wire90-741_5-layer_1-width_3
+Xwire90@7 net@43 net@48 wire90-783-layer_1-width_3
+Xwire90@8 net@60 net@123 wire90-1254_1-layer_1-width_3
+Xwire90@9 net@57 net@159 wire90-1300_1-layer_1-width_3
+Xwire90@11 net@86 net@153 wire90-392_9-layer_1-width_3
+Xwire90@12 net@94 net@176 wire90-174_7-layer_1-width_3
+Xwire90@13 net@152 net@98 wire90-1154_9-layer_1-width_3
+Xwire90@15 net@151 net@150 wire90-590_5-layer_1-width_3
+Xwire90@17 net@171 winHI[M] wire90-174_7-layer_1-width_3
+.ENDS races
-*** CELL: driversJ:latchAndDriver60{sch}
-.SUBCKT latchAndDriver60 inA inB out
-Xinv@0 net@8 out inv-X_60
-Xnand2@0 inA inB net@26 nand2-X_20
-Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3
-.ENDS latchAndDriver60
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-362_9-R_34_667m a b
+Ccap@0 gnd net@14 1.331f
+Ccap@1 gnd net@8 1.331f
+Ccap@2 gnd net@11 1.331f
+Rres@0 net@14 a 2.097
+Rres@1 net@11 net@14 4.194
+Rres@2 b net@8 2.097
+Rres@3 net@8 net@11 4.194
+.ENDS wire-C_0_011f-362_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-362_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-362_9-R_34_667m
+.ENDS wire90-362_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-602_7-R_34_667m a b
+Ccap@0 gnd net@14 2.21f
+Ccap@1 gnd net@8 2.21f
+Ccap@2 gnd net@11 2.21f
+Rres@0 net@14 a 3.482
+Rres@1 net@11 net@14 6.965
+Rres@2 b net@8 3.482
+Rres@3 net@8 net@11 6.965
+.ENDS wire-C_0_011f-602_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-602_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-602_7-R_34_667m
+.ENDS wire90-602_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-269_9-R_34_667m a b
+Ccap@0 gnd net@14 0.99f
+Ccap@1 gnd net@8 0.99f
+Ccap@2 gnd net@11 0.99f
+Rres@0 net@14 a 1.559
+Rres@1 net@11 net@14 3.119
+Rres@2 b net@8 1.559
+Rres@3 net@8 net@11 3.119
+.ENDS wire-C_0_011f-269_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-269_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-269_9-R_34_667m
+.ENDS wire90-269_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-709_6-R_34_667m a b
+Ccap@0 gnd net@14 2.602f
+Ccap@1 gnd net@8 2.602f
+Ccap@2 gnd net@11 2.602f
+Rres@0 net@14 a 4.1
+Rres@1 net@11 net@14 8.2
+Rres@2 b net@8 4.1
+Rres@3 net@8 net@11 8.2
+.ENDS wire-C_0_011f-709_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-709_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-709_6-R_34_667m
+.ENDS wire90-709_6-layer_1-width_3
+
+*** CELL: moveM:moveOut{sch}
+.SUBCKT moveOut bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp]
++fire[M] flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4]
++s[5] succ[sf] winLO[M]
+Xinv@0 net@28 s[4] inv-X_10
+Xinv@1 net@29 s[3] inv-X_10
+Xinv@2 net@50 s[5] inv-X_10
+Xinv@9 fire[T] net@186 inv-X_5
+Xinv@10 ilc[do] net@221 inv-X_5
+Xinv@11 net@227 s[2] inv-X_10
+Xinv@12 net@194 s[1] inv-X_10
+XinvI@0 do[Tp] net@28 inv-X_5
+XinvI@1 epi[torp] net@29 inv-X_5
+XinvI@2 do[Mv] net@50 inv-X_5
+XinvI@7 pred[D] net@227 inv-X_5
+XinvI@8 pred[T] net@194 inv-X_5
+Xnand2@2 ilc[do] bit[Di] net@208 nand2-X_5
+Xnand2@3 ilc[do] bit[Ti] net@207 nand2-X_5
+Xnor2n@1 ilc[mo] winLO[M] net@250 nor2n-X_10
+Xnor2n@5 net@206 winLO[M] net@203 nor2n-X_10
+Xnor2n@6 net@205 winLO[M] net@204 nor2n-X_10
+Xnor2n@7 net@220 winLO[M] fire[M] nor2n-X_20
+Xpms1@0 flag[D][set] net@186 pms1-X_20
+XpredDri2@0 fire[T] mc epi[torp] predDri20wMC
+XpredDri2@3 net@201 mc pred[D] predDri20wMC
+XpredDri2@4 net@200 mc pred[T] predDri20wMC
+XpredORdr@0 fire[T] done[M] mc do[Tp] predORdri20wMC
+XpredORdr@1 fire[T] done[M] mc do[Mv] predORdri20wMC
+Xraces@0 bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] pred[D] pred[T] succ[sf]
++epi[torp] races@0_winHI[M] winLO[M] races
+XsucDri20@0 done[M] do[reD] sucDri20
+Xwire90@9 net@206 net@208 wire90-362_9-layer_1-width_3
+Xwire90@10 net@220 net@221 wire90-602_7-layer_1-width_3
+Xwire90@11 net@200 net@204 wire90-269_9-layer_1-width_3
+Xwire90@12 net@201 net@203 wire90-269_9-layer_1-width_3
+Xwire90@13 net@205 net@207 wire90-362_9-layer_1-width_3
+Xwire90@15 done[M] net@250 wire90-709_6-layer_1-width_3
+.ENDS moveOut
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-387_3-R_34_667m a b
-Ccap@0 gnd net@14 1.42f
-Ccap@1 gnd net@8 1.42f
-Ccap@2 gnd net@11 1.42f
-Rres@0 net@14 a 2.238
-Rres@1 net@11 net@14 4.475
-Rres@2 b net@8 2.238
-Rres@3 net@8 net@11 4.475
-.ENDS wire-C_0_011f-387_3-R_34_667m
+.SUBCKT wire-C_0_011f-297_9-R_34_667m a b
+Ccap@0 gnd net@14 1.092f
+Ccap@1 gnd net@8 1.092f
+Ccap@2 gnd net@11 1.092f
+Rres@0 net@14 a 1.721
+Rres@1 net@11 net@14 3.442
+Rres@2 b net@8 1.721
+Rres@3 net@8 net@11 3.442
+.ENDS wire-C_0_011f-297_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-387_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-387_3-R_34_667m
-.ENDS wire90-387_3-layer_1-width_3
-
-*** CELL: driversJ:latchAndDriver30{sch}
-.SUBCKT latchAndDriver30 inA inB out
-Xinv@0 net@8 out inv-X_30
-Xnand2@0 inA inB net@26 nand2-X_10
-Xwire90@0 net@26 net@8 wire90-387_3-layer_1-width_3
-.ENDS latchAndDriver30
-
-*** CELL: loopCountM:muxForD{sch}
-.SUBCKT muxForD in[1] in[2] in[3] in[4] in[5] in[6] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] sel
-Xinv@0 sel net@0 inv-X_20
-Xinv@1 sF net@1 inv-X_20
-Xmux10/2x@0 in[1] in[2] in[3] in[4] in[5] in[6] gnd out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] sF sT mux10/2x7
-Xwire90@0 net@0 sF wire90-704_3-layer_1-width_3
-Xwire90@1 net@1 sT wire90-704_3-layer_1-width_3
-.ENDS muxForD
+.SUBCKT wire90-297_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-297_9-R_34_667m
+.ENDS wire90-297_9-layer_1-width_3
-*** CELL: registersM:data2in60Cx18{sch}
-.SUBCKT data2in60Cx18 dcl[A] dcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
-+inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6]
-+inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16]
-+inB[17] inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
-+inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
-+out[18] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-XhiL[1] dcl[A] dcl[B] inA[1] inB[1] out[1] latch2in60C
-XhiL[2] dcl[A] dcl[B] inA[2] inB[2] out[2] latch2in60C
-XhiL[3] dcl[A] dcl[B] inA[3] inB[3] out[3] latch2in60C
-XhiL[4] dcl[A] dcl[B] inA[4] inB[4] out[4] latch2in60C
-XhiL[5] dcl[A] dcl[B] inA[5] inB[5] out[5] latch2in60C
-XhiL[6] dcl[A] dcl[B] inA[6] inB[6] out[6] latch2in60C
-XhiL[7] dcl[A] dcl[B] inA[7] inB[7] out[7] latch2in60C
-XhiL[8] dcl[A] dcl[B] inA[8] inB[8] out[8] latch2in60C
-XhiL[9] dcl[A] dcl[B] inA[9] inB[9] out[9] latch2in60C
-XhiL[10] dcl[A] dcl[B] inA[10] inB[10] out[10] latch2in60C
-XhiL[11] dcl[A] dcl[B] inA[11] inB[11] out[11] latch2in60C
-XhiL[12] dcl[A] dcl[B] inA[12] inB[12] out[12] latch2in60C
-XhiL[13] dcl[A] dcl[B] inA[13] inB[13] out[13] latch2in60C
-XhiL[14] dcl[A] dcl[B] inA[14] inB[14] out[14] latch2in60C
-XhiL[15] dcl[A] dcl[B] inA[15] inB[15] out[15] latch2in60C
-XhiL[16] dcl[A] dcl[B] inA[16] inB[16] out[16] latch2in60C
-XhiL[17] dcl[A] dcl[B] inA[17] inB[17] out[17] latch2in60C
-XhiL[18] dcl[A] dcl[B] inA[18] inB[18] out[18] latch2in60C
-.ENDS data2in60Cx18
+*** CELL: scanM:scanEx2h{sch}
+.SUBCKT scanEx2h dIn[1] dIn[2] mc p1p p2p rd sin sout
+XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanM__scanCellE
+XscanCell@11 dIn[2] p1p p2p rd net@31 sout scanM__scanCellE
+Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
+.ENDS scanEx2h
-*** CELL: registersM:data2in60Cx37{sch}
-.SUBCKT data2in60Cx37 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] inA[16]
-+inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] inA[24]
-+inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] inA[32]
-+inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
-+inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33]
-+inB[34] inB[35] inB[36] inB[37] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8]
-+inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17]
-+out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25]
-+out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33]
-+out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8]
-+out[9] take[A] take[B]
-Xdata2in6@1 take[A2] take[B2] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15]
-+inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inA[7]
-+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17]
-+inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] data2in60Cx18
-Xdata2in6@2 take[A1] take[B1] inA[29] inA[30] inA[31] inA[32] inA[33] inA[34]
-+inA[35] inA[36] inA[37] inA[20] inA[21] inA[22] inA[23] inA[24] inA[25]
-+inA[26] inA[27] inA[28] inB[29] inB[30] inB[31] inB[32] inB[33] inB[34]
-+inB[35] inB[36] inB[37] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25]
-+inB[26] inB[27] inB[28] out[29] out[30] out[31] out[32] out[33] out[34]
-+out[35] out[36] out[37] out[20] out[21] out[22] out[23] out[24] out[25]
-+out[26] out[27] out[28] data2in60Cx18
-Xlatch2in@4 take[A] take[B] inA[19] inB[19] out[19] latch2in60C
-Xwire90@0 take[A] take[A2] wire90-2550-layer_1-width_3
-Xwire90@4 take[B] take[B2] wire90-2550-layer_1-width_3
-Xwire90@5 take[B] take[B1] wire90-2550-layer_1-width_3
-Xwire90@6 take[A] take[A1] wire90-2550-layer_1-width_3
-.ENDS data2in60Cx37
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-218_6-R_34_667m a b
+Ccap@0 gnd net@14 0.802f
+Ccap@1 gnd net@8 0.802f
+Ccap@2 gnd net@11 0.802f
+Rres@0 net@14 a 1.263
+Rres@1 net@11 net@14 2.526
+Rres@2 b net@8 1.263
+Rres@3 net@8 net@11 2.526
+.ENDS wire-C_0_011f-218_6-R_34_667m
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_9_6 d g s
-MNMOSf@0 d g s gnd nch W='28.8*(1+ABN/sqrt(28.8*2))' L='2'
-+DELVTO='AVT0N/sqrt(28.8*2)'
-.ENDS NMOSx-X_9_6
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-218_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-218_6-R_34_667m
+.ENDS wire90-218_6-layer_1-width_3
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_9_6 d g s
-MPMOSf@0 d g s vdd pch W='57.6*(1+ABP/sqrt(57.6*2))' L='2'
-+DELVTO='AVT0P/sqrt(57.6*2)'
-.ENDS PMOSx-X_9_6
+*** CELL: scanM:scanEx3h{sch}
+.SUBCKT scanEx3h dIn[1] dIn[2] dIn[3] mc p1p p2p rd sin sout
+XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanM__scanCellE
+XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanM__scanCellE
+XscanCell@12 dIn[3] p1p p2p rd net@32 sout scanM__scanCellE
+Xwire90@0 net@18 net@31 wire90-218_6-layer_1-width_3
+Xwire90@1 net@20 net@32 wire90-218_6-layer_1-width_3
+.ENDS scanEx3h
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_9_6 in out
-XNMOS@0 out in gnd NMOSx-X_9_6
-XPMOS@0 out in vdd PMOSx-X_9_6
-.ENDS inv-X_9_6
+*** CELL: scanM:scanEx4h{sch}
+.SUBCKT scanEx4h dIn[1] dIn[2] dIn[3] dIn[4] mc p1p p2p rd sin sout
+XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanM__scanCellE
+XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanM__scanCellE
+XscanCell@12 dIn[3] p1p p2p rd net@32 net@24 scanM__scanCellE
+XscanCell@13 dIn[4] p1p p2p rd net@33 sout scanM__scanCellE
+Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
+Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3
+Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3
+.ENDS scanEx4h
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-277_3-R_34_667m a b
-Ccap@0 gnd net@14 1.017f
-Ccap@1 gnd net@8 1.017f
-Ccap@2 gnd net@11 1.017f
-Rres@0 net@14 a 1.602
-Rres@1 net@11 net@14 3.204
-Rres@2 b net@8 1.602
-Rres@3 net@8 net@11 3.204
-.ENDS wire-C_0_011f-277_3-R_34_667m
+.SUBCKT wire-C_0_011f-4243_4-R_34_667m a b
+Ccap@0 gnd net@14 15.559f
+Ccap@1 gnd net@8 15.559f
+Ccap@2 gnd net@11 15.559f
+Rres@0 net@14 a 24.517
+Rres@1 net@11 net@14 49.035
+Rres@2 b net@8 24.517
+Rres@3 net@8 net@11 49.035
+.ENDS wire-C_0_011f-4243_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-277_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-277_3-R_34_667m
-.ENDS wire90-277_3-layer_1-width_3
+.SUBCKT wire90-4243_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4243_4-R_34_667m
+.ENDS wire90-4243_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-114_7-R_34_667m a b
-Ccap@0 gnd net@14 0.421f
-Ccap@1 gnd net@8 0.421f
-Ccap@2 gnd net@11 0.421f
-Rres@0 net@14 a 0.663
-Rres@1 net@11 net@14 1.325
-Rres@2 b net@8 0.663
-Rres@3 net@8 net@11 1.325
-.ENDS wire-C_0_011f-114_7-R_34_667m
+.SUBCKT wire-C_0_011f-467_9-R_34_667m a b
+Ccap@0 gnd net@14 1.716f
+Ccap@1 gnd net@8 1.716f
+Ccap@2 gnd net@11 1.716f
+Rres@0 net@14 a 2.703
+Rres@1 net@11 net@14 5.407
+Rres@2 b net@8 2.703
+Rres@3 net@8 net@11 5.407
+.ENDS wire-C_0_011f-467_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-114_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-114_7-R_34_667m
-.ENDS wire90-114_7-layer_1-width_3
-
-*** CELL: latchesK:latch1in09.6Bi{sch}
-.SUBCKT latch1in09_6Bi hcl in[1] out[1]
-Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF
-Xinv@0 net@23 out[1] inv-X_9_6
-XinvLT@0 net@18 net@25 inv-X_4
-Xwire90@0 net@19 net@18 wire90-277_3-layer_1-width_3
-Xwire90@1 net@25 net@23 wire90-114_7-layer_1-width_3
-.ENDS latch1in09_6Bi
-
-*** CELL: redFive:triInv{sch}
-.SUBCKT triInv-X_5 en enB in out
-Xnms2@0 out in en nms2-X_5
-Xpms2@0 out in enB pms2-X_5
-.ENDS triInv-X_5
-
-*** CELL: gates2inM:mux5{sch}
-.SUBCKT mux5 inA[1] inB[1] out[1] s[F] s[T]
-XtriInv@0 s[T] s[F] inA[1] out[1] triInv-X_5
-XtriInv@1 s[F] s[T] inB[1] out[1] triInv-X_5
-.ENDS mux5
-
-*** CELL: latchGroupsK:dataMux{sch}
-.SUBCKT dataMux hcl inB[1] in[1] out[1] s[F] s[T]
-Xlatch1in@1 hcl in[1] net@5 latch1in09_6Bi
-Xmux5@0 net@6 inB[1] out[1] s[F] s[T] mux5
-Xwire90@0 net@5 net@6 wire90-277_3-layer_1-width_3
-.ENDS dataMux
+.SUBCKT wire90-467_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-467_9-R_34_667m
+.ENDS wire90-467_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-251_8-R_34_667m a b
-Ccap@0 gnd net@14 0.923f
-Ccap@1 gnd net@8 0.923f
-Ccap@2 gnd net@11 0.923f
-Rres@0 net@14 a 1.455
-Rres@1 net@11 net@14 2.91
-Rres@2 b net@8 1.455
-Rres@3 net@8 net@11 2.91
-.ENDS wire-C_0_011f-251_8-R_34_667m
+.SUBCKT wire-C_0_011f-574_7-R_34_667m a b
+Ccap@0 gnd net@14 2.107f
+Ccap@1 gnd net@8 2.107f
+Ccap@2 gnd net@11 2.107f
+Rres@0 net@14 a 3.32
+Rres@1 net@11 net@14 6.641
+Rres@2 b net@8 3.32
+Rres@3 net@8 net@11 6.641
+.ENDS wire-C_0_011f-574_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-574_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-574_7-R_34_667m
+.ENDS wire90-574_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1674_7-R_34_667m a b
+Ccap@0 gnd net@14 6.141f
+Ccap@1 gnd net@8 6.141f
+Ccap@2 gnd net@11 6.141f
+Rres@0 net@14 a 9.676
+Rres@1 net@11 net@14 19.352
+Rres@2 b net@8 9.676
+Rres@3 net@8 net@11 19.352
+.ENDS wire-C_0_011f-1674_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-251_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-251_8-R_34_667m
-.ENDS wire90-251_8-layer_1-width_3
+.SUBCKT wire90-1674_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1674_7-R_34_667m
+.ENDS wire90-1674_7-layer_1-width_3
-*** CELL: registersM:shadowMux4{sch}
-.SUBCKT shadowMux4 in[1] in[2] in[3] in[4] out[1] out[2] out[3] out[4] s[F]
-+s[T] sign
-Xi[1] in[1] x[1] inv-X_10
-Xi[2] in[2] x[2] inv-X_10
-Xi[3] in[3] x[3] inv-X_10
-Xi[4] in[4] x[4] inv-X_10
-Xm[1] x[1] sign out[1] s[F] s[T] mux5
-Xm[2] x[2] sign out[2] s[F] s[T] mux5
-Xm[3] x[3] sign out[3] s[F] s[T] mux5
-Xm[4] x[4] sign out[4] s[F] s[T] mux5
-Xwire90@0 x[1] wire90@0_b wire90-251_8-layer_1-width_3
-Xwire90@1 x[2] wire90@1_b wire90-251_8-layer_1-width_3
-Xwire90@2 x[3] wire90@2_b wire90-251_8-layer_1-width_3
-Xwire90@3 x[4] wire90@3_b wire90-251_8-layer_1-width_3
-.ENDS shadowMux4
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1625_5-R_34_667m a b
+Ccap@0 gnd net@14 5.96f
+Ccap@1 gnd net@8 5.96f
+Ccap@2 gnd net@11 5.96f
+Rres@0 net@14 a 9.392
+Rres@1 net@11 net@14 18.784
+Rres@2 b net@8 9.392
+Rres@3 net@8 net@11 18.784
+.ENDS wire-C_0_011f-1625_5-R_34_667m
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_80 d g s
-MNMOSf@0 d g s gnd nch W='240*(1+ABN/sqrt(240*2))' L='2'
-+DELVTO='AVT0N/sqrt(240*2)'
-.ENDS NMOSx-X_80
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1625_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1625_5-R_34_667m
+.ENDS wire90-1625_5-layer_1-width_3
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_80 d g s
-MPMOSf@0 d g s vdd pch W='480*(1+ABP/sqrt(480*2))' L='2'
-+DELVTO='AVT0P/sqrt(480*2)'
-.ENDS PMOSx-X_80
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1899_2-R_34_667m a b
+Ccap@0 gnd net@14 6.964f
+Ccap@1 gnd net@8 6.964f
+Ccap@2 gnd net@11 6.964f
+Rres@0 net@14 a 10.973
+Rres@1 net@11 net@14 21.946
+Rres@2 b net@8 10.973
+Rres@3 net@8 net@11 21.946
+.ENDS wire-C_0_011f-1899_2-R_34_667m
-*** CELL: redFive:inv{sch}
-.SUBCKT inv-X_80 in out
-XNMOS@0 out in gnd NMOSx-X_80
-XPMOS@0 out in vdd PMOSx-X_80
-.ENDS inv-X_80
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1899_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1899_2-R_34_667m
+.ENDS wire90-1899_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-817_9-R_34_667m a b
-Ccap@0 gnd net@14 2.999f
-Ccap@1 gnd net@8 2.999f
-Ccap@2 gnd net@11 2.999f
-Rres@0 net@14 a 4.726
-Rres@1 net@11 net@14 9.451
-Rres@2 b net@8 4.726
-Rres@3 net@8 net@11 9.451
-.ENDS wire-C_0_011f-817_9-R_34_667m
+.SUBCKT wire-C_0_011f-1577_6-R_34_667m a b
+Ccap@0 gnd net@14 5.785f
+Ccap@1 gnd net@8 5.785f
+Ccap@2 gnd net@11 5.785f
+Rres@0 net@14 a 9.115
+Rres@1 net@11 net@14 18.23
+Rres@2 b net@8 9.115
+Rres@3 net@8 net@11 18.23
+.ENDS wire-C_0_011f-1577_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-817_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-817_9-R_34_667m
-.ENDS wire90-817_9-layer_1-width_3
+.SUBCKT wire90-1577_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1577_6-R_34_667m
+.ENDS wire90-1577_6-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1334_3-R_34_667m a b
-Ccap@0 gnd net@14 4.892f
-Ccap@1 gnd net@8 4.892f
-Ccap@2 gnd net@11 4.892f
-Rres@0 net@14 a 7.709
-Rres@1 net@11 net@14 15.419
-Rres@2 b net@8 7.709
-Rres@3 net@8 net@11 15.419
-.ENDS wire-C_0_011f-1334_3-R_34_667m
+.SUBCKT wire-C_0_011f-1661-R_34_667m a b
+Ccap@0 gnd net@14 6.09f
+Ccap@1 gnd net@8 6.09f
+Ccap@2 gnd net@11 6.09f
+Rres@0 net@14 a 9.597
+Rres@1 net@11 net@14 19.194
+Rres@2 b net@8 9.597
+Rres@3 net@8 net@11 19.194
+.ENDS wire-C_0_011f-1661-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1334_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1334_3-R_34_667m
-.ENDS wire90-1334_3-layer_1-width_3
+.SUBCKT wire90-1661-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1661-R_34_667m
+.ENDS wire90-1661-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-540-R_34_667m a b
-Ccap@0 gnd net@14 1.98f
-Ccap@1 gnd net@8 1.98f
-Ccap@2 gnd net@11 1.98f
-Rres@0 net@14 a 3.12
-Rres@1 net@11 net@14 6.24
-Rres@2 b net@8 3.12
-Rres@3 net@8 net@11 6.24
-.ENDS wire-C_0_011f-540-R_34_667m
+.SUBCKT wire-C_0_011f-1338_5-R_34_667m a b
+Ccap@0 gnd net@14 4.908f
+Ccap@1 gnd net@8 4.908f
+Ccap@2 gnd net@11 4.908f
+Rres@0 net@14 a 7.734
+Rres@1 net@11 net@14 15.467
+Rres@2 b net@8 7.734
+Rres@3 net@8 net@11 15.467
+.ENDS wire-C_0_011f-1338_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-540-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-540-R_34_667m
-.ENDS wire90-540-layer_1-width_3
-
-*** CELL: registersM:signLogic{sch}
-.SUBCKT signLogic inB[15] inB[20] s[F] s[T] sign
-Xinv@0 net@12 sign inv-X_80
-Xinv@2 inB[20] net@19 inv-X_30
-Xinv@3 net@7 s[T] inv-X_100
-Xinv@4 s[T] s[F] inv-X_80
-Xinv@5 net@14 net@13 inv-X_30
-Xnand2_sy@0 net@7 inB[15] net@21 nand2_sy-X_20
-Xwire90@2 net@13 net@12 wire90-817_9-layer_1-width_3
-Xwire90@4 net@19 net@7 wire90-1334_3-layer_1-width_3
-Xwire90@5 net@21 net@14 wire90-540-layer_1-width_3
-.ENDS signLogic
+.SUBCKT wire90-1338_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1338_5-R_34_667m
+.ENDS wire90-1338_5-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4861_7-R_34_667m a b
-Ccap@0 gnd net@14 17.826f
-Ccap@1 gnd net@8 17.826f
-Ccap@2 gnd net@11 17.826f
-Rres@0 net@14 a 28.09
-Rres@1 net@11 net@14 56.18
-Rres@2 b net@8 28.09
-Rres@3 net@8 net@11 56.18
-.ENDS wire-C_0_011f-4861_7-R_34_667m
+.SUBCKT wire-C_0_011f-1486_5-R_34_667m a b
+Ccap@0 gnd net@14 5.451f
+Ccap@1 gnd net@8 5.451f
+Ccap@2 gnd net@11 5.451f
+Rres@0 net@14 a 8.589
+Rres@1 net@11 net@14 17.177
+Rres@2 b net@8 8.589
+Rres@3 net@8 net@11 17.177
+.ENDS wire-C_0_011f-1486_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4861_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4861_7-R_34_667m
-.ENDS wire90-4861_7-layer_1-width_3
+.SUBCKT wire90-1486_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1486_5-R_34_667m
+.ENDS wire90-1486_5-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-5555_8-R_34_667m a b
-Ccap@0 gnd net@14 20.371f
-Ccap@1 gnd net@8 20.371f
-Ccap@2 gnd net@11 20.371f
-Rres@0 net@14 a 32.1
-Rres@1 net@11 net@14 64.2
-Rres@2 b net@8 32.1
-Rres@3 net@8 net@11 64.2
-.ENDS wire-C_0_011f-5555_8-R_34_667m
+.SUBCKT wire-C_0_011f-1831_6-R_34_667m a b
+Ccap@0 gnd net@14 6.716f
+Ccap@1 gnd net@8 6.716f
+Ccap@2 gnd net@11 6.716f
+Rres@0 net@14 a 10.583
+Rres@1 net@11 net@14 21.165
+Rres@2 b net@8 10.583
+Rres@3 net@8 net@11 21.165
+.ENDS wire-C_0_011f-1831_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-5555_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-5555_8-R_34_667m
-.ENDS wire90-5555_8-layer_1-width_3
+.SUBCKT wire90-1831_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1831_6-R_34_667m
+.ENDS wire90-1831_6-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-5262_9-R_34_667m a b
-Ccap@0 gnd net@14 19.297f
-Ccap@1 gnd net@8 19.297f
-Ccap@2 gnd net@11 19.297f
-Rres@0 net@14 a 30.408
-Rres@1 net@11 net@14 60.816
-Rres@2 b net@8 30.408
-Rres@3 net@8 net@11 60.816
-.ENDS wire-C_0_011f-5262_9-R_34_667m
+*** CELL: moveM:ilcMoveOut{sch}
+.SUBCKT ilcMoveOut bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp]
++fire[M] flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
++inLO[6] inLO[8] mc p1p p2p pred[D] pred[T] rd sin sout succ[sf]
+Xilc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8]
++ilc[decLO] ilc[do] ilc[load] ilc[mo] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
++inLO[6] inLO[8] ilc
+XoutDockM@0 bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M]
++flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4] s[5]
++succ[sf] net@72 moveOut
+XscanEx2h@0 s[1] s[5] mc p1p p2p rd net@51 net@58 scanEx2h
+XscanEx3h@0 s[4] s[3] s[2] mc p1p p2p rd net@58 sout scanEx3h
+XscanEx4h@0 bitt[1] bitt[3] bitt[5] bitt[7] mc p1p p2p rd sin net@50 scanEx4h
+XscanEx4h@1 bitt[2] bitt[4] bitt[6] bitt[8] mc p1p p2p rd net@50 net@51
++scanEx4h
+Xwire90@0 net@72 ilc[decLO] wire90-4243_4-layer_1-width_3
+Xwire90@1 wire90@1_a ilc[mo] wire90-467_9-layer_1-width_3
+Xwire90@2 wire90@2_a ilc[do] wire90-574_7-layer_1-width_3
+Xwire90@3 wire90@3_a bitt[8] wire90-1674_7-layer_1-width_3
+Xwire90@4 wire90@4_a bitt[1] wire90-1625_5-layer_1-width_3
+Xwire90@5 wire90@5_a bitt[2] wire90-1899_2-layer_1-width_3
+Xwire90@6 wire90@6_a bitt[3] wire90-1577_6-layer_1-width_3
+Xwire90@7 wire90@7_a bitt[4] wire90-1661-layer_1-width_3
+Xwire90@8 wire90@8_a bitt[5] wire90-1338_5-layer_1-width_3
+Xwire90@9 wire90@9_a bitt[6] wire90-1486_5-layer_1-width_3
+Xwire90@10 wire90@10_a bitt[7] wire90-1831_6-layer_1-width_3
+.ENDS ilcMoveOut
+
+*** CELL: wiresL:bitAssignments{sch}
+.SUBCKT bitAssignments
+.ENDS bitAssignments
+
+*** CELL: redFive:nand2_sy{sch}
+.SUBCKT nand2_sy-X_30 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_30
+XPMOS@1 out ina vdd PMOSx-X_30
+Xnms2_sy@0 out ina inb nms2_sy-X_30
+.ENDS nand2_sy-X_30
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-5262_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-5262_9-R_34_667m
-.ENDS wire90-5262_9-layer_1-width_3
+*** CELL: redFive:nand2n_sy{sch}
+.SUBCKT nand2n_sy-X_30 ina inb out
+Xnand2_sy@0 ina inb out nand2_sy-X_30
+.ENDS nand2n_sy-X_30
-*** CELL: registersM:shadow{sch}
-.SUBCKT shadow dd[1] dd[2] dd[3] dd[4] dd[5] dd[6] hcl inB[15] inB[16]
-+inB[17] inB[18] inB[19] inB[20] inn[10] inn[11] inn[12] inn[13] inn[14]
-+inn[15] inn[16] inn[17] inn[18] inn[7] inn[8] inn[9] outt[16] outt[17]
-+outt[18] outt[19] outt[20] outt[21] outt[22] outt[23] outt[24] outt[25]
-+outt[26] outt[27] outt[28] outt[29] outt[30] outt[31] outt[32] outt[33]
-+outt[34] outt[35] outt[36] outt[37]
-Xdl[1] hcl sign dd[1] outt[20] s[F] s[T] dataMux
-Xdl[2] hcl sign dd[2] outt[21] s[F] s[T] dataMux
-Xdl[3] hcl sign dd[3] outt[22] s[F] s[T] dataMux
-Xdl[4] hcl sign dd[4] outt[23] s[F] s[T] dataMux
-Xdl[5] hcl sign dd[5] outt[24] s[F] s[T] dataMux
-Xdl[6] hcl sign dd[6] outt[25] s[F] s[T] dataMux
-Xdl[7] hcl sign inn[7] outt[26] s[F] s[T] dataMux
-Xdl[8] hcl sign inn[8] outt[27] s[F] s[T] dataMux
-Xdl[9] hcl sign inn[9] outt[28] s[F] s[T] dataMux
-Xdr[1] hcl sign inn[18] outt[37] s[F] s[T] dataMux
-Xdr[2] hcl sign inn[17] outt[36] s[F] s[T] dataMux
-Xdr[3] hcl sign inn[16] outt[35] s[F] s[T] dataMux
-Xdr[4] hcl sign inn[15] outt[34] s[F] s[T] dataMux
-Xdr[5] hcl sign inn[14] outt[33] s[F] s[T] dataMux
-Xdr[6] hcl sign inn[13] outt[32] s[F] s[T] dataMux
-Xdr[7] hcl sign inn[12] outt[31] s[F] s[T] dataMux
-Xdr[8] hcl sign inn[11] outt[30] s[F] s[T] dataMux
-Xdr[9] hcl sign inn[10] outt[29] s[F] s[T] dataMux
-XshadowMu@1 inB[16] inB[17] inB[18] inB[19] outt[16] outt[17] outt[18]
-+outt[19] s[F] s[T] sign shadowMux4
-XsignLogi@0 inB[15] inB[20] s[F] s[T] sign signLogic
-Xwire90@1 s[F] wire90@1_b wire90-4861_7-layer_1-width_3
-Xwire90@2 s[T] wire90@2_b wire90-5555_8-layer_1-width_3
-Xwire90@3 sign wire90@3_b wire90-5262_9-layer_1-width_3
-.ENDS shadow
+*** CELL: redFive:nms3{sch}
+.SUBCKT nms3-X_20 d g g2 g3
+XNMOS@0 d g3 net@6 NMOSx-X_60
+XNMOS@1 net@7 g gnd NMOSx-X_60
+XNMOS@2 net@6 g2 net@7 NMOSx-X_60
+.ENDS nms3-X_20
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4175_4-R_34_667m a b
-Ccap@0 gnd net@14 15.31f
-Ccap@1 gnd net@8 15.31f
-Ccap@2 gnd net@11 15.31f
-Rres@0 net@14 a 24.125
-Rres@1 net@11 net@14 48.249
-Rres@2 b net@8 24.125
-Rres@3 net@8 net@11 48.249
-.ENDS wire-C_0_011f-4175_4-R_34_667m
+*** CELL: redFive:pms1{sch}
+.SUBCKT pms1-X_3 d g
+XPMOS@0 d g vdd PMOSx-X_3
+.ENDS pms1-X_3
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4175_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4175_4-R_34_667m
-.ENDS wire90-4175_4-layer_1-width_3
+*** CELL: predicateM:nand3in20sr{sch}
+.SUBCKT nand3in20sr inA inB inC out resetLO
+Xnms3a@0 out inA inB inC nms3-X_20
+Xpms1@0 out inC pms1-X_3
+Xpms1@1 out inB pms1-X_3
+Xpms1@2 out inA pms1-X_3
+Xpms1@3 out resetLO pms1-X_20
+.ENDS nand3in20sr
-*** CELL: registersM:newDregister{sch}
-.SUBCKT newDregister dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17]
-+dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27]
-+dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37]
-+dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4]
-+out[5] out[6] out[7] out[8] out[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
-+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7]
-+ps[8] ps[9] take[A] take[B]
-Xdata2in6@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
-+dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28]
-+dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3]
-+dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
-+ss[16] ss[17] ss[18] ss[19] ps[1] ss[20] ss[21] ss[22] ss[23] ss[24] ss[25]
-+ss[26] ss[27] ss[28] ss[29] ps[2] ss[30] ss[31] ss[32] ss[33] ss[34] ss[35]
-+ss[36] ss[37] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1]
-+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28]
-+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36]
-+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] take[A] take[B]
-+data2in60Cx37
-Xinv@0 take[B] net@66 inv-X_40
-Xshadow@0 out[1] out[2] out[3] out[4] out[5] out[6] net@66 ps[15] ps[16]
-+ps[17] ps[18] ps[19] ps[20] out[10] out[11] out[12] out[13] out[14] out[15]
-+out[16] out[17] out[18] out[7] out[8] out[9] ss[16] ss[17] ss[18] ss[19]
-+ss[20] ss[21] ss[22] ss[23] ss[24] ss[25] ss[26] ss[27] ss[28] ss[29] ss[30]
-+ss[31] ss[32] ss[33] ss[34] ss[35] ss[36] ss[37] shadow
-Xwire90@0 net@66 wire90@0_b wire90-4175_4-layer_1-width_3
-.ENDS newDregister
+*** CELL: driversL:sucDri20plain{sch}
+.SUBCKT sucDri20plain in succ
+XPMOSx@0 succ in vdd PMOSx-X_20
+Xinv@1 succ net@94 inv-X_4
+Xnms2@0 succ net@127 in nms2-X_2
+Xwire90@0 net@127 net@94 wire90-124_7-layer_1-width_3
+.ENDS sucDri20plain
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_16 d g s
-MNMOSf@0 d g s gnd nch W='48*(1+ABN/sqrt(48*2))' L='2'
-+DELVTO='AVT0N/sqrt(48*2)'
-.ENDS NMOSx-X_16
+*** CELL: predicateM:predSucDri{sch}
+.SUBCKT predSucDri do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] sel[Co]
++sel[Ld] sel[Lt] sel[Mv] sel[Tp]
+Xna[1] sel[Ld] fire[do] w[1] nand2-X_10
+Xna[2] sel[Co] fire[do] w[2] nand2-X_10
+Xna[3] sel[Mv] fire[do] w[3] nand2-X_10
+Xna[4] sel[Tp] fire[do] w[4] nand2-X_10
+Xna[5] sel[Lt] fire[do] w[5] nand2-X_10
+Xsd[1] w[1] do[Ld] sucDri20plain
+Xsd[2] w[2] do[Co] sucDri20plain
+Xsd[3] w[3] do[Mv] sucDri20plain
+Xsd[4] w[4] do[Tp] sucDri20plain
+Xsd[5] w[5] do[Lt] sucDri20plain
+Xwire90@0 w[1] wire90@0_b wire90-503_4-layer_1-width_3
+Xwire90@1 w[2] wire90@1_b wire90-503_4-layer_1-width_3
+Xwire90@2 w[3] wire90@2_b wire90-503_4-layer_1-width_3
+Xwire90@3 w[4] wire90@3_b wire90-503_4-layer_1-width_3
+Xwire90@4 w[5] wire90@4_b wire90-503_4-layer_1-width_3
+.ENDS predSucDri
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_8 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_16
-XNMOS@1 net@0 g gnd NMOSx-X_16
-.ENDS nms2-X_8
+*** CELL: orangeTSMC090nm:PMOS4x{sch}
+.SUBCKT PMOS4x-X_3 b d g s
+MPMOS4f@0 d g s b pch W='18*(1+ABP/sqrt(18*2))' L='2'
++DELVTO='AVT0P/sqrt(18*2)'
+.ENDS PMOS4x-X_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-627_9-R_34_667m a b
-Ccap@0 gnd net@14 2.302f
-Ccap@1 gnd net@8 2.302f
-Ccap@2 gnd net@11 2.302f
-Rres@0 net@14 a 3.628
-Rres@1 net@11 net@14 7.256
-Rres@2 b net@8 3.628
-Rres@3 net@8 net@11 7.256
-.ENDS wire-C_0_011f-627_9-R_34_667m
+*** CELL: redFive:pms2{sch}
+.SUBCKT pms2-X_1_5 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_3
+XPMOS@1 d g2 net@2 PMOSx-X_3
+.ENDS pms2-X_1_5
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-627_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-627_9-R_34_667m
-.ENDS wire90-627_9-layer_1-width_3
+*** CELL: driversL:predCond20wMC{sch}
+.SUBCKT predCond20wMC cond in mc pred
+XNMOSx@1 pred mc gnd NMOSx-X_10
+XPMOS4x@0 PMOS4x@0_b pred in net@217 PMOS4x-X_3
+XPMOS4x@1 PMOS4x@1_b pred cond net@210 PMOS4x-X_3
+Xinv@0 pred net@145 inv-X_10
+Xnms2@0 pred cond in nms2-X_20
+Xpms2a@0 net@217 mc net@200 pms2-X_1_5
+Xwire90@0 net@200 net@145 wire90-243_6-layer_1-width_3
+Xwire90@1 net@217 net@210 wire90-243_6-layer_1-width_3
+.ENDS predCond20wMC
-*** CELL: driversL:sucANDdri60{sch}
-.SUBCKT sucANDdri60 inA inB succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_60
-Xinv@0 succ net@71 inv-X_5
-Xnand2@0 inA inB net@67 nand2-X_10
-Xnms2@0 succ net@51 net@72 nms2-X_8
-Xwire90@0 net@67 net@51 wire90-627_9-layer_1-width_3
-Xwire90@1 net@72 net@71 wire90-124_7-layer_1-width_3
-.ENDS sucANDdri60
+*** CELL: driversL:predCond20wMS{sch}
+.SUBCKT predCond20wMS cond in mc pred
+XPMOSx@0 pred cond net@210 PMOSx-X_3
+XPMOSx@1 pred in net@217 PMOSx-X_3
+Xinv@0 pred net@145 inv-X_10
+XinvLT@0 mc net@240 invLT-X_5
+Xnms2@0 pred cond in nms2-X_20
+Xpms1@0 pred net@240 pms1-X_3
+Xpms2a@0 net@217 mc net@200 pms2-X_1_5
+Xwire90@0 net@200 net@145 wire90-243_6-layer_1-width_3
+Xwire90@1 net@217 net@210 wire90-243_6-layer_1-width_3
+.ENDS predCond20wMS
-*** CELL: stagesM:litDockStage{sch}
-.SUBCKT litDockStage do[L] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16]
-+dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26]
-+dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36]
-+dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] fire[M] flag[C]
-+outLO[1] outLO[2] outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ps[10]
-+ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20]
-+ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ready
-+signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] sor[1] succ[D] succ[T]
-XgaspLit@0 do[L] net@10 sir[9] ready net@27 gaspLit
-Xinv@0 ps[17] net@77 inv-X_10
-Xlatch2in@0 take[A] net@81 dp[B] signalBitFromInboundSwitchFabric flag[C]
-+latch2in60C
-XlatchAnd@1 ps[17] fire[M] take[A] latchAndDriver60
-XlatchAnd@2 net@77 fire[M] net@81 latchAndDriver30
-XlatchDri@0 net@13 take[B] latchDriver60
-XmuxForD@0 out[1] out[2] out[3] out[4] out[5] out[6] outLO[1] outLO[2]
-+outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForD
-XnewDregi@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
-+dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28]
-+dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3]
-+dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16]
-+ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8]
-+ps[9] take[A] take[B] newDregister
-Xnor2n_sy@0 succ[T] succ[D] ready nor2n_sy-X_10
-XscanEx1v@0 net@27 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1vertA
-XsucANDdr@0 ps[16] fire[M] succ[D] sucANDdri60
-XsucANDdr@1 ps[15] fire[M] succ[T] sucANDdri60
-Xwire90@0 net@10 net@13 wire90-4175_4-layer_1-width_3
-.ENDS litDockStage
+*** CELL: predicateM:predFlagDri{sch}
+.SUBCKT predFlagDri fire[do] flag[A][clr] flag[A][set] flag[B][clr]
++flag[B][set] flag[D][clr] flag[D][set] mc sel[Fl] sel[rD]
+XbitAssig@0 bitAssignments
+Xpc[1] sel[Fl] fire[do] mc flag[A][set] predCond20wMC
+Xpc[2] sel[Fl] fire[do] mc flag[A][clr] predCond20wMC
+Xpc[3] sel[Fl] fire[do] mc flag[B][set] predCond20wMC
+Xpc[4] sel[Fl] fire[do] mc flag[B][clr] predCond20wMC
+XpredCond@0 sel[rD] fire[do] mc flag[D][clr] predCond20wMC
+XpredCond@1 sel[rD] fire[do] mc flag[D][set] predCond20wMS
+.ENDS predFlagDri
+
+*** CELL: predicateM:ohPredDo{sch}
+.SUBCKT ohPredDo do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] fire[skip]
++flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set]
++mc ps[do] ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD]
+XbitAssig@0 bitAssignments
+XohPredDo@3 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] sel[Co] sel[Ld]
++sel[Lt] sel[Mv] sel[Tp] predSucDri
+XpredFlag@1 fire[do] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
++flag[D][clr] flag[D][set] mc sel[Fl] sel[rD] predFlagDri
+XsucDri20@0 net@55 ps[skip] sucDri20
+XsucDri20@1 fire[do] ps[do] sucDri20
+Xwire90@2 fire[skip] net@55 wire90-309-layer_1-width_3
+.ENDS ohPredDo
+
+*** CELL: redFive:pms1{sch}
+.SUBCKT pms1-X_5 d g
+XPMOS@0 d g vdd PMOSx-X_5
+.ENDS pms1-X_5
-*** CELL: registersM:addr2in60Cx7{sch}
-.SUBCKT addr2in60Cx7 ainA[1] ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7]
-+ainB[1] ainB[2] ainB[3] ainB[4] ainB[5] ainB[6] ainB[7] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] fire[A] fire[B]
-XhiL[1] fire[A] fire[B] ainA[1] ainB[1] aout[1] latch2in60C
-XhiL[2] fire[A] fire[B] ainA[2] ainB[2] aout[2] latch2in60C
-XhiL[3] fire[A] fire[B] ainA[3] ainB[3] aout[3] latch2in60C
-XhiL[4] fire[A] fire[B] ainA[4] ainB[4] aout[4] latch2in60C
-XhiL[5] fire[A] fire[B] ainA[5] ainB[5] aout[5] latch2in60C
-XhiL[6] fire[A] fire[B] ainA[6] ainB[6] aout[6] latch2in60C
-XhiL[7] fire[A] fire[B] ainA[7] ainB[7] aout[7] latch2in60C
-.ENDS addr2in60Cx7
+*** CELL: predicateM:ohSRxor{sch}
+.SUBCKT ohSRxor flag[F] flag[T] out resetLO sel[1] sel[2]
+Xnms2b@4 out flag[T] sel[1] nms2-X_5
+Xnms2b@5 out flag[F] sel[2] nms2-X_5
+Xpms1@0 out resetLO pms1-X_5
+Xpms2@0 out flag[T] sel[2] pms2-X_1
+Xpms2@1 out flag[F] sel[1] pms2-X_1
+.ENDS ohSRxor
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2330-R_34_667m a b
-Ccap@0 gnd net@14 8.543f
-Ccap@1 gnd net@8 8.543f
-Ccap@2 gnd net@11 8.543f
-Rres@0 net@14 a 13.462
-Rres@1 net@11 net@14 26.924
-Rres@2 b net@8 13.462
-Rres@3 net@8 net@11 26.924
-.ENDS wire-C_0_011f-2330-R_34_667m
+.SUBCKT wire-C_0_011f-395_6-R_34_667m a b
+Ccap@0 gnd net@14 1.451f
+Ccap@1 gnd net@8 1.451f
+Ccap@2 gnd net@11 1.451f
+Rres@0 net@14 a 2.286
+Rres@1 net@11 net@14 4.571
+Rres@2 b net@8 2.286
+Rres@3 net@8 net@11 4.571
+.ENDS wire-C_0_011f-395_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2330-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2330-R_34_667m
-.ENDS wire90-2330-layer_1-width_3
-
-*** CELL: registersM:addr2in60Cx15{sch}
-.SUBCKT addr2in60Cx15 ainA[10] ainA[11] ainA[12] ainA[13] ainA[14] ainA[1]
-+ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ainA[8] ainA[9] ainA[TT]
-+ainB[10] ainB[11] ainB[12] ainB[13] ainB[14] ainB[1] ainB[2] ainB[3] ainB[4]
-+ainB[5] ainB[6] ainB[7] ainB[8] ainB[9] ainB[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] fire[A] fire[B]
-Xaddr2in6@1 ainA[1] ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ainB[1]
-+ainB[2] ainB[3] ainB[4] ainB[5] ainB[6] ainB[7] aout[1] aout[2] aout[3]
-+aout[4] aout[5] aout[6] aout[7] fire[A2] fire[B2] addr2in60Cx7
-Xaddr2in6@2 ainA[8] ainA[9] ainA[10] ainA[11] ainA[12] ainA[13] ainA[14]
-+ainB[8] ainB[9] ainB[10] ainB[11] ainB[12] ainB[13] ainB[14] aout[8] aout[9]
-+aout[10] aout[11] aout[12] aout[13] aout[14] fire[A1] fire[B1] addr2in60Cx7
-Xlatch2in@4 fire[A2] fire[B2] ainA[TT] ainB[TT] aout[TT] latch2in60C
-Xwire90@3 fire[A] fire[A1] wire90-2330-layer_1-width_3
-Xwire90@4 fire[B] fire[B1] wire90-2330-layer_1-width_3
-Xwire90@5 fire[B] fire[B2] wire90-2330-layer_1-width_3
-Xwire90@6 fire[A] fire[A2] wire90-2330-layer_1-width_3
-.ENDS addr2in60Cx15
-
-*** CELL: gates3inM:nand3in6.6{sch}
-.SUBCKT nand3in6_6 inA inB inC out
-Xnand3@0 inA inB inC out nand3-X_6_667
-.ENDS nand3in6_6
+.SUBCKT wire90-395_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-395_6-R_34_667m
+.ENDS wire90-395_6-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3616_3-R_34_667m a b
-Ccap@0 gnd net@14 13.26f
-Ccap@1 gnd net@8 13.26f
-Ccap@2 gnd net@11 13.26f
-Rres@0 net@14 a 20.894
-Rres@1 net@11 net@14 41.788
-Rres@2 b net@8 20.894
-Rres@3 net@8 net@11 41.788
-.ENDS wire-C_0_011f-3616_3-R_34_667m
+.SUBCKT wire-C_0_011f-313_6-R_34_667m a b
+Ccap@0 gnd net@14 1.15f
+Ccap@1 gnd net@8 1.15f
+Ccap@2 gnd net@11 1.15f
+Rres@0 net@14 a 1.812
+Rres@1 net@11 net@14 3.624
+Rres@2 b net@8 1.812
+Rres@3 net@8 net@11 3.624
+.ENDS wire-C_0_011f-313_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3616_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3616_3-R_34_667m
-.ENDS wire90-3616_3-layer_1-width_3
+.SUBCKT wire90-313_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-313_6-R_34_667m
+.ENDS wire90-313_6-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3495_7-R_34_667m a b
-Ccap@0 gnd net@14 12.818f
-Ccap@1 gnd net@8 12.818f
-Ccap@2 gnd net@11 12.818f
-Rres@0 net@14 a 20.197
-Rres@1 net@11 net@14 40.395
-Rres@2 b net@8 20.197
-Rres@3 net@8 net@11 40.395
-.ENDS wire-C_0_011f-3495_7-R_34_667m
+.SUBCKT wire-C_0_011f-339-R_34_667m a b
+Ccap@0 gnd net@14 1.243f
+Ccap@1 gnd net@8 1.243f
+Ccap@2 gnd net@11 1.243f
+Rres@0 net@14 a 1.959
+Rres@1 net@11 net@14 3.917
+Rres@2 b net@8 1.959
+Rres@3 net@8 net@11 3.917
+.ENDS wire-C_0_011f-339-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3495_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3495_7-R_34_667m
-.ENDS wire90-3495_7-layer_1-width_3
+.SUBCKT wire90-339-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-339-R_34_667m
+.ENDS wire90-339-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-270-R_34_667m a b
-Ccap@0 gnd net@14 0.99f
-Ccap@1 gnd net@8 0.99f
-Ccap@2 gnd net@11 0.99f
-Rres@0 net@14 a 1.56
-Rres@1 net@11 net@14 3.12
-Rres@2 b net@8 1.56
-Rres@3 net@8 net@11 3.12
-.ENDS wire-C_0_011f-270-R_34_667m
+.SUBCKT wire-C_0_011f-286_1-R_34_667m a b
+Ccap@0 gnd net@14 1.049f
+Ccap@1 gnd net@8 1.049f
+Ccap@2 gnd net@11 1.049f
+Rres@0 net@14 a 1.653
+Rres@1 net@11 net@14 3.306
+Rres@2 b net@8 1.653
+Rres@3 net@8 net@11 3.306
+.ENDS wire-C_0_011f-286_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-270-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-270-R_34_667m
-.ENDS wire90-270-layer_1-width_3
+.SUBCKT wire90-286_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-286_1-R_34_667m
+.ENDS wire90-286_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-358-R_34_667m a b
+.SUBCKT wire-C_0_011f-358_1-R_34_667m a b
Ccap@0 gnd net@14 1.313f
Ccap@1 gnd net@8 1.313f
Ccap@2 gnd net@11 1.313f
-Rres@0 net@14 a 2.068
-Rres@1 net@11 net@14 4.137
-Rres@2 b net@8 2.068
-Rres@3 net@8 net@11 4.137
-.ENDS wire-C_0_011f-358-R_34_667m
+Rres@0 net@14 a 2.069
+Rres@1 net@11 net@14 4.138
+Rres@2 b net@8 2.069
+Rres@3 net@8 net@11 4.138
+.ENDS wire-C_0_011f-358_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-358-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-358-R_34_667m
-.ENDS wire90-358-layer_1-width_3
+.SUBCKT wire90-358_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-358_1-R_34_667m
+.ENDS wire90-358_1-layer_1-width_3
-*** CELL: registersM:newPathReg{sch}
-.SUBCKT newPathReg aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
-+dp[10] dp[11] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9]
-+fire[M] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4]
-+ps[5] ps[6] ps[7] ps[8] ps[9]
-Xaddr2in6@0 dp[10] dp[11] dp[12] dp[12] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5]
-+dp[6] dp[7] dp[8] dp[9] ps[15] ps[10] ps[11] ps[12] ps[13] ps[13] ps[1] ps[2]
-+ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[15] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] take[dp] take[ps] addr2in60Cx15
-Xinv@1 ps[13] net@46 inv-X_10
-Xinv@2 ps[14] net@47 inv-X_10
-XinvI@0 net@19 net@40 inv-X_30
-XlatchAnd@0 ps[14] fire[M] net@43 latchAndDriver30
-Xnand3in6@1 net@25 net@28 fire[M] net@19 nand3in6_6
-Xwire90@0 net@43 take[dp] wire90-3616_3-layer_1-width_3
-Xwire90@1 net@40 take[ps] wire90-3495_7-layer_1-width_3
-Xwire90@3 net@46 net@28 wire90-270-layer_1-width_3
-Xwire90@4 net@47 net@25 wire90-358-layer_1-width_3
-.ENDS newPathReg
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-415_1-R_34_667m a b
+Ccap@0 gnd net@14 1.522f
+Ccap@1 gnd net@8 1.522f
+Ccap@2 gnd net@11 1.522f
+Rres@0 net@14 a 2.398
+Rres@1 net@11 net@14 4.797
+Rres@2 b net@8 2.398
+Rres@3 net@8 net@11 4.797
+.ENDS wire-C_0_011f-415_1-R_34_667m
-*** CELL: dockM:inputDock{sch}
-.SUBCKT inputDock aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
-+freqOut inP[10] inP[11] inP[12] inP[13] inP[14] inP[15] inP[16] inP[17]
-+inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23] inP[24] inP[25]
-+inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31] inP[32] inP[33]
-+inP[34] inP[35] inP[36] inP[37] inP[3] inP[4] inP[5] inP[6] inP[7] inP[8]
-+inP[9] inP[B] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4]
-+in[5] in[6] in[7] in[8] in[9] in[T] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] pred pred[D] pred[T]
-+signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] sor[1] succ[D] succ[T]
-XbitAssig@0 bitAssignments
-XcenterFi@0 centerFi@0_do[Lt] pred centerFi@0_fire[M] centerFi@0_flag[C][F]
-+centerFi@0_flag[C][T] centerFi@0_inLO[1] centerFi@0_inLO[2]
-+centerFi@0_inLO[3] centerFi@0_inLO[4] centerFi@0_inLO[5] centerFi@0_inLO[6]
-+centerFi@0_inLO[8] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] in[T] centerFi@0_pred[D] net@2
-+centerFi@0_pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17]
-+ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27]
-+ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3]
-+ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] net@8[26] net@8[25] net@8[24] net@8[23]
-+net@8[22] net@8[21] net@8[20] net@8[19] net@8[18] net@8[17] net@8[35]
-+net@8[16] net@8[15] net@8[14] net@8[13] net@8[12] net@8[11] net@8[10]
-+net@8[9] net@8[8] net@8[7] net@8[34] net@8[6] net@8[5] net@8[4] net@8[3]
-+net@8[2] net@8[1] net@8[0] net@8[33] net@8[32] net@8[31] net@8[30] net@8[29]
-+net@8[28] net@8[27] net@13[26] net@13[25] net@13[24] net@13[23] net@13[22]
-+net@13[21] net@13[20] net@13[19] net@13[18] net@13[17] net@13[35] net@13[16]
-+net@13[15] net@13[14] net@13[13] net@13[12] net@13[11] net@13[10] net@13[9]
-+net@13[8] net@13[7] net@13[34] net@13[6] net@13[5] net@13[4] net@13[3]
-+net@13[2] net@13[1] net@13[0] net@13[33] net@13[32] net@13[31] net@13[30]
-+net@13[29] net@13[28] net@13[27] net@61 centerFi@0_sf[succ] net@26[8] sir[2]
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@122[8] centerFive
-XdockCent@1 ps[21] ps[18] ps[19] dockCent@1_bitt[10] dockCent@1_bitt[11]
-+dockCent@1_bitt[12] dockCent@1_bitt[13] dockCent@1_bitt[14]
-+dockCent@1_bitt[1] dockCent@1_bitt[2] dockCent@1_bitt[3] dockCent@1_bitt[4]
-+dockCent@1_bitt[5] dockCent@1_bitt[6] dockCent@1_bitt[7] dockCent@1_bitt[8]
-+dockCent@1_bitt[9] do[Co] do[Ld] fire[M] flag[A][clr] flag[A][set]
-+flag[B][clr] flag[B][set] flag[C][F] flag[C][T] flag[D][clr] flag[D][set]
-+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[7] m1[10] m1[11] m1[12]
-+m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] sir[9] pred[D] pred[T]
-+net@107 dockCent@1_s[10] dockCent@1_s[1] dockCent@1_s[2] dockCent@1_s[3]
-+dockCent@1_s[4] dockCent@1_s[5] dockCent@1_s[6] dockCent@1_s[7]
-+dockCent@1_s[8] dockCent@1_s[9] epi[TORP] dockCenterTry2
-XdockWagN@0 net@13[26] net@13[25] net@13[24] net@13[23] net@13[22] net@13[21]
-+net@13[20] net@13[19] net@13[18] net@13[17] net@13[35] net@13[16] net@13[15]
-+net@13[14] net@13[13] net@13[12] net@13[11] net@13[10] net@13[9] net@13[8]
-+net@13[7] net@13[34] net@13[6] net@13[5] net@13[4] net@13[3] net@13[2]
-+net@13[1] net@13[0] net@13[33] net@13[32] net@13[31] net@13[30] net@13[29]
-+net@13[28] net@13[27] net@8[26] net@8[25] net@8[24] net@8[23] net@8[22]
-+net@8[21] net@8[20] net@8[19] net@8[18] net@8[17] net@8[35] net@8[16]
-+net@8[15] net@8[14] net@8[13] net@8[12] net@8[11] net@8[10] net@8[9] net@8[8]
-+net@8[7] net@8[34] net@8[6] net@8[5] net@8[4] net@8[3] net@8[2] net@8[1]
-+net@8[0] net@8[33] net@8[32] net@8[31] net@8[30] net@8[29] net@8[28]
-+net@8[27] net@20 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] net@26[8] net@60 take[1] take[2] take[3] freqOut take[5] take[6]
-+dockWagNine
-Xinv@0 flag[C][T] flag[C][F] inv-X_10
-XlitDockS@1 do[Lt] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15] inP[16]
-+inP[17] inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23] inP[24]
-+inP[25] inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31] inP[32]
-+inP[33] inP[34] inP[35] inP[36] inP[37] inP[3] inP[4] inP[5] inP[6] inP[7]
-+inP[8] inP[9] inP[B] fire[M] flag[C][T] inLO[1] inLO[2] inLO[3] inLO[4]
-+inLO[5] inLO[6] inLO[7] out[10] out[11] out[12] out[13] out[14] out[15]
-+out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23]
-+out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31]
-+out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6]
-+out[7] out[8] out[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17]
-+ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9]
-+net@107 signalBitFromInboundSwitchFabric net@122[8] sir[2] sir[3] sir[4]
-+sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] litDockStage
-XnewPathR@0 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] in[10]
-+in[11] in[12] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] fire[M]
-+ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] ps[5] ps[6]
-+ps[7] ps[8] ps[9] newPathReg
-Xwire90@0 net@60 net@2 wire90-414-layer_1-width_3
-Xwire90@1 net@61 net@20 wire90-414-layer_1-width_3
-.ENDS inputDock
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-415_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-415_1-R_34_667m
+.ENDS wire90-415_1-layer_1-width_3
+
+*** CELL: predicateM:ohSRxor6x12{sch}
+.SUBCKT ohSRxor6x12 all any flag[A][clr] flag[A][set] flag[B][clr]
++flag[B][set] flag[D][clr] flag[D][set] in[1][F] in[1][T] in[2][F] in[2][T]
++in[3][F] in[3][T] in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T]
++resetLO
+Xnand3in6@3 match[12T] match[34T] match[56T] any nand3in6_6sym
+Xnor3in3_@2 match[12F] match[34F] match[56F] all nor3in6_6sym
+XohSRxor@6 flag[A][clr] flag[A][set] net@106 resetLO in[1][T] in[2][T]
++ohSRxor
+XohSRxor@7 flag[A][clr] flag[A][set] net@107 resetLO in[1][F] in[2][F]
++ohSRxor
+XohSRxor@8 flag[B][clr] flag[B][set] net@125 resetLO in[3][F] in[4][F]
++ohSRxor
+XohSRxor@9 flag[B][clr] flag[B][set] net@122 resetLO in[3][T] in[4][T]
++ohSRxor
+XohSRxor@10 flag[D][clr] flag[D][set] net@177 resetLO in[5][F] in[6][F]
++ohSRxor
+XohSRxor@11 flag[D][clr] flag[D][set] net@178 resetLO in[5][T] in[6][T]
++ohSRxor
+Xwire90@1 match[34T] net@122 wire90-395_6-layer_1-width_3
+Xwire90@3 match[56T] net@178 wire90-313_6-layer_1-width_3
+Xwire90@4 net@107 match[12F] wire90-339-layer_1-width_3
+Xwire90@5 match[12T] net@106 wire90-286_1-layer_1-width_3
+Xwire90@6 match[34F] net@125 wire90-358_1-layer_1-width_3
+Xwire90@7 net@177 match[56F] wire90-415_1-layer_1-width_3
+.ENDS ohSRxor6x12
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-506_4-R_34_667m a b
-Ccap@0 gnd net@14 1.857f
-Ccap@1 gnd net@8 1.857f
-Ccap@2 gnd net@11 1.857f
-Rres@0 net@14 a 2.926
-Rres@1 net@11 net@14 5.852
-Rres@2 b net@8 2.926
-Rres@3 net@8 net@11 5.852
-.ENDS wire-C_0_011f-506_4-R_34_667m
+.SUBCKT wire-C_0_011f-625_1-R_34_667m a b
+Ccap@0 gnd net@14 2.292f
+Ccap@1 gnd net@8 2.292f
+Ccap@2 gnd net@11 2.292f
+Rres@0 net@14 a 3.612
+Rres@1 net@11 net@14 7.223
+Rres@2 b net@8 3.612
+Rres@3 net@8 net@11 7.223
+.ENDS wire-C_0_011f-625_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-506_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-506_4-R_34_667m
-.ENDS wire90-506_4-layer_1-width_3
+.SUBCKT wire90-625_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-625_1-R_34_667m
+.ENDS wire90-625_1-layer_1-width_3
-*** CELL: countersL:cntShift{sch}
-.SUBCKT cntShift ctgLO myp1p myp2p sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
-+sid[7] sid[8] sid[9] sin
-Xinv@3 net@98 myp1p inv-X_40
-Xinv@4 net@100 myp2p inv-X_40
-Xnand2@4 ctgLO sid[2] net@99 nand2-X_10
-Xnand2@5 ctgLO sid[3] net@97 nand2-X_10
-Xwire90@9 net@98 net@97 wire90-506_4-layer_1-width_3
-Xwire90@10 net@100 net@99 wire90-506_4-layer_1-width_3
-.ENDS cntShift
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-215_4-R_34_667m a b
+Ccap@0 gnd net@14 0.79f
+Ccap@1 gnd net@8 0.79f
+Ccap@2 gnd net@11 0.79f
+Rres@0 net@14 a 1.245
+Rres@1 net@11 net@14 2.489
+Rres@2 b net@8 1.245
+Rres@3 net@8 net@11 2.489
+.ENDS wire-C_0_011f-215_4-R_34_667m
-*** CELL: countersL:cntFreq{sch}
-.SUBCKT cntFreq count ctgLO fin fout myFin
-Xinv@0 ctgLO net@17 inv-X_10
-Xinv@1 count ctgLO inv-X_40
-Xnand2@0 net@18 myFin net@72 nand2-X_5
-Xnand2@1 ctgLO fin net@33 nand2-X_5
-Xnand2_sy@0 net@34 net@39 fout nand2_sy-X_20
-Xwire90@2 net@17 net@18 wire90-506_4-layer_1-width_3
-Xwire90@4 net@34 net@33 wire90-506_4-layer_1-width_3
-Xwire90@5 net@39 net@72 wire90-506_4-layer_1-width_3
-.ENDS cntFreq
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-215_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-215_4-R_34_667m
+.ENDS wire90-215_4-layer_1-width_3
-*** CELL: latchesK:latch2in10A{sch}
-.SUBCKT latch2in10A hcl[A] hcl[B] inA[1] inB[1] out[1]
-Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF
-XinvLT@1 net@16 out[1] inv-X_10
-Xwire90@1 dataBar net@16 wire90-242_1-layer_1-width_3
-.ENDS latch2in10A
+*** CELL: predicateM:ohPredPred{sch}
+.SUBCKT ohPredPred any do fire[both] flag[A][clr] flag[A][set] flag[B][clr]
++flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F]
++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
++m1cate[5][T] m1cate[6][F] m1cate[6][T] mc resetLO s[1] s[2]
+Xinv@0 net@51 resetLO inv-X_10
+Xinv@2 fire[both] net@54 inv-X_10
+XinvI@0 net@18 net@49 inv-X_5
+XinvI@1 net@66 s[1] inv-X_10
+XinvI@2 net@71 s[2] inv-X_10
+Xnor2_sy@2 m1cate[1][F] m1cate[1][T] net@62 nor2_sy-X_5
+Xnor2_sy@3 flag[A][clr] flag[A][set] net@67 nor2_sy-X_5
+XohSRxor6@1 do any flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
++flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T]
++m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T]
++m1cate[6][F] m1cate[6][T] net@18 ohSRxor6x12
+Xpp[1] fire[both] mc m1cate[1][T] predDri20wMC
+Xpp[2] fire[both] mc m1cate[1][F] predDri20wMC
+Xpp[3] fire[both] mc m1cate[2][T] predDri20wMC
+Xpp[4] fire[both] mc m1cate[2][F] predDri20wMC
+Xpp[5] fire[both] mc m1cate[3][T] predDri20wMC
+Xpp[6] fire[both] mc m1cate[3][F] predDri20wMC
+Xpp[7] fire[both] mc m1cate[4][T] predDri20wMC
+Xpp[8] fire[both] mc m1cate[4][F] predDri20wMC
+Xpp[9] fire[both] mc m1cate[5][T] predDri20wMC
+Xpp[10] fire[both] mc m1cate[5][F] predDri20wMC
+Xpp[11] fire[both] mc m1cate[6][T] predDri20wMC
+Xpp[12] fire[both] mc m1cate[6][F] predDri20wMC
+Xwire90@1 net@54 net@18 wire90-625_1-layer_1-width_3
+Xwire90@3 net@49 net@51 wire90-142_6-layer_1-width_3
+Xwire90@4 net@62 net@66 wire90-215_4-layer_1-width_3
+Xwire90@5 net@67 net@71 wire90-215_4-layer_1-width_3
+.ENDS ohPredPred
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-214_2-R_34_667m a b
-Ccap@0 gnd net@14 0.785f
-Ccap@1 gnd net@8 0.785f
-Ccap@2 gnd net@11 0.785f
-Rres@0 net@14 a 1.238
-Rres@1 net@11 net@14 2.475
-Rres@2 b net@8 1.238
-Rres@3 net@8 net@11 2.475
-.ENDS wire-C_0_011f-214_2-R_34_667m
+.SUBCKT wire-C_0_011f-556_1-R_34_667m a b
+Ccap@0 gnd net@14 2.039f
+Ccap@1 gnd net@8 2.039f
+Ccap@2 gnd net@11 2.039f
+Rres@0 net@14 a 3.213
+Rres@1 net@11 net@14 6.426
+Rres@2 b net@8 3.213
+Rres@3 net@8 net@11 6.426
+.ENDS wire-C_0_011f-556_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-214_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-214_2-R_34_667m
-.ENDS wire90-214_2-layer_1-width_3
+.SUBCKT wire90-556_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-556_1-R_34_667m
+.ENDS wire90-556_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-413_4-R_34_667m a b
-Ccap@0 gnd net@14 1.516f
-Ccap@1 gnd net@8 1.516f
-Ccap@2 gnd net@11 1.516f
-Rres@0 net@14 a 2.389
-Rres@1 net@11 net@14 4.777
-Rres@2 b net@8 2.389
-Rres@3 net@8 net@11 4.777
-.ENDS wire-C_0_011f-413_4-R_34_667m
+.SUBCKT wire-C_0_011f-557-R_34_667m a b
+Ccap@0 gnd net@14 2.042f
+Ccap@1 gnd net@8 2.042f
+Ccap@2 gnd net@11 2.042f
+Rres@0 net@14 a 3.218
+Rres@1 net@11 net@14 6.436
+Rres@2 b net@8 3.218
+Rres@3 net@8 net@11 6.436
+.ENDS wire-C_0_011f-557-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-413_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-413_4-R_34_667m
-.ENDS wire90-413_4-layer_1-width_3
+.SUBCKT wire90-557-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-557-R_34_667m
+.ENDS wire90-557-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-231_2-R_34_667m a b
-Ccap@0 gnd net@14 0.848f
-Ccap@1 gnd net@8 0.848f
-Ccap@2 gnd net@11 0.848f
-Rres@0 net@14 a 1.336
-Rres@1 net@11 net@14 2.672
-Rres@2 b net@8 1.336
-Rres@3 net@8 net@11 2.672
-.ENDS wire-C_0_011f-231_2-R_34_667m
+.SUBCKT wire-C_0_011f-318_8-R_34_667m a b
+Ccap@0 gnd net@14 1.169f
+Ccap@1 gnd net@8 1.169f
+Ccap@2 gnd net@11 1.169f
+Rres@0 net@14 a 1.842
+Rres@1 net@11 net@14 3.684
+Rres@2 b net@8 1.842
+Rres@3 net@8 net@11 3.684
+.ENDS wire-C_0_011f-318_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-231_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-231_2-R_34_667m
-.ENDS wire90-231_2-layer_1-width_3
-
-*** CELL: countersL:cntScnOne{sch}
-.SUBCKT cntScnOne cin ctgLO out p1p p2p sin
-Xinv@0 out net@14 inv-X_5
-Xlatch2in@0 cB p1p net@3 net@3 out latch2in10A
-Xlatch2in@1 cA p2p net@15 sin net@6 latch2in10A
-Xnor2n_sy@0 ctgLO cB net@20 nor2n_sy-X_5
-Xnor2n_sy@2 ctgLO cin net@25 nor2n_sy-X_5
-Xwire90@0 net@15 net@14 wire90-214_2-layer_1-width_3
-Xwire90@1 net@6 net@3 wire90-506_4-layer_1-width_3
-Xwire90@2 net@20 cA wire90-413_4-layer_1-width_3
-Xwire90@3 net@25 cB wire90-231_2-layer_1-width_3
-.ENDS cntScnOne
+.SUBCKT wire90-318_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-318_8-R_34_667m
+.ENDS wire90-318_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-668_5-R_34_667m a b
-Ccap@0 gnd net@14 2.451f
-Ccap@1 gnd net@8 2.451f
-Ccap@2 gnd net@11 2.451f
-Rres@0 net@14 a 3.862
-Rres@1 net@11 net@14 7.725
-Rres@2 b net@8 3.862
-Rres@3 net@8 net@11 7.725
-.ENDS wire-C_0_011f-668_5-R_34_667m
+.SUBCKT wire-C_0_011f-1035_5-R_34_667m a b
+Ccap@0 gnd net@14 3.797f
+Ccap@1 gnd net@8 3.797f
+Ccap@2 gnd net@11 3.797f
+Rres@0 net@14 a 5.983
+Rres@1 net@11 net@14 11.966
+Rres@2 b net@8 5.983
+Rres@3 net@8 net@11 11.966
+.ENDS wire-C_0_011f-1035_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-668_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-668_5-R_34_667m
-.ENDS wire90-668_5-layer_1-width_3
+.SUBCKT wire90-1035_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1035_5-R_34_667m
+.ENDS wire90-1035_5-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-680_5-R_34_667m a b
-Ccap@0 gnd net@14 2.495f
-Ccap@1 gnd net@8 2.495f
-Ccap@2 gnd net@11 2.495f
-Rres@0 net@14 a 3.932
-Rres@1 net@11 net@14 7.864
-Rres@2 b net@8 3.932
-Rres@3 net@8 net@11 7.864
-.ENDS wire-C_0_011f-680_5-R_34_667m
+.SUBCKT wire-C_0_011f-945_6-R_34_667m a b
+Ccap@0 gnd net@14 3.467f
+Ccap@1 gnd net@8 3.467f
+Ccap@2 gnd net@11 3.467f
+Rres@0 net@14 a 5.463
+Rres@1 net@11 net@14 10.927
+Rres@2 b net@8 5.463
+Rres@3 net@8 net@11 10.927
+.ENDS wire-C_0_011f-945_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-680_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-680_5-R_34_667m
-.ENDS wire90-680_5-layer_1-width_3
-
-*** CELL: countersL:cntScnFour{sch}
-.SUBCKT cntScnFour cin ctgLO out p1p p2p sin
-XcntScnOn@0 net@88 ctgLO net@40 p1p p2p net@88 cntScnOne
-XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne
-XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne
-XcntScnOn@3 net@94 ctgLO out p1p p2p net@94 cntScnOne
-Xwire90@4 net@40 net@94 wire90-668_5-layer_1-width_3
-Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3
-Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3
-.ENDS cntScnFour
-
-*** CELL: countersL:cntScnThree{sch}
-.SUBCKT cntScnThree cin ctgLO out p1p p2p sin
-XcntScnOn@0 net@88 ctgLO out p1p p2p net@88 cntScnOne
-XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne
-XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne
-Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3
-Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3
-.ENDS cntScnThree
+.SUBCKT wire90-945_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-945_6-R_34_667m
+.ENDS wire90-945_6-layer_1-width_3
-*** CELL: countersL:cntScnTwelve{sch}
-.SUBCKT cntScnTwelve cin ctgLO out p1p p2p sin
-XcntScnFo@0 net@60 ctgLO out p1p p2p net@60 cntScnFour
-XcntScnFo@1 cin ctgLO net@43 p1p p2p sin cntScnFour
-XcntScnFo@2 net@61 ctgLO net@46 p1p p2p net@61 cntScnFour
-Xwire90@5 net@43 net@61 wire90-668_5-layer_1-width_3
-Xwire90@6 net@46 net@60 wire90-668_5-layer_1-width_3
-.ENDS cntScnTwelve
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1126_1-R_34_667m a b
+Ccap@0 gnd net@14 4.129f
+Ccap@1 gnd net@8 4.129f
+Ccap@2 gnd net@11 4.129f
+Rres@0 net@14 a 6.506
+Rres@1 net@11 net@14 13.013
+Rres@2 b net@8 6.506
+Rres@3 net@8 net@11 13.013
+.ENDS wire-C_0_011f-1126_1-R_34_667m
-*** CELL: countersL:instructionCount{sch}
-.SUBCKT instructionCount cin count fin fout sid[1] sid[2] sid[3] sid[4]
-+sid[5] sid[6] sid[7] sid[8] sid[9] sod[1]
-XcntContr@0 ctgLO myp1p myp2p sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
-+sid[7] sid[8] sid[9] sod[1] cntShift
-XcntFreq@0 count ctgLO fin fout net@77 cntFreq
-XcntScnFo@1 cin ctgLO net@1 myp1p myp2p sid[1] cntScnFour
-XcntScnTh@0 net@77 ctgLO net@78 myp1p myp2p net@77 cntScnThree
-XcntScnTw@3 net@2 ctgLO net@124 myp1p myp2p net@2 cntScnTwelve
-XcntScnTw@5 net@136 ctgLO net@144 myp1p myp2p net@136 cntScnTwelve
-Xwire90@0 net@1 net@2 wire90-506_4-layer_1-width_3
-Xwire90@1 net@124 net@77 wire90-506_4-layer_1-width_3
-Xwire90@2 net@78 net@136 wire90-506_4-layer_1-width_3
-Xwire90@3 net@144 sod[1] wire90-506_4-layer_1-width_3
-.ENDS instructionCount
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1126_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1126_1-R_34_667m
+.ENDS wire90-1126_1-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-546_2-R_34_667m a b
-Ccap@0 gnd net@14 2.003f
-Ccap@1 gnd net@8 2.003f
-Ccap@2 gnd net@11 2.003f
-Rres@0 net@14 a 3.156
-Rres@1 net@11 net@14 6.312
-Rres@2 b net@8 3.156
-Rres@3 net@8 net@11 6.312
-.ENDS wire-C_0_011f-546_2-R_34_667m
+.SUBCKT wire-C_0_011f-361_6-R_34_667m a b
+Ccap@0 gnd net@14 1.326f
+Ccap@1 gnd net@8 1.326f
+Ccap@2 gnd net@11 1.326f
+Rres@0 net@14 a 2.089
+Rres@1 net@11 net@14 4.178
+Rres@2 b net@8 2.089
+Rres@3 net@8 net@11 4.178
+.ENDS wire-C_0_011f-361_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-546_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-546_2-R_34_667m
-.ENDS wire90-546_2-layer_1-width_3
+.SUBCKT wire90-361_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-361_6-R_34_667m
+.ENDS wire90-361_6-layer_1-width_3
-*** CELL: latchesK:latch1in60C{sch}
-.SUBCKT latch1in60C hcl inS[1] outS[1]
-Xhi2inLat@0 hcl inS[1] net@14 raw1inLatchF
-XinvLT@0 net@15 net@18 invLT-X_5
-XinvLT@1 net@16 net@19 inv-X_20
-XinvLT@2 net@17 outS[1] inv-X_60
-Xwire90@0 net@14 net@15 wire90-294_8-layer_1-width_3
-Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3
-Xwire90@2 net@19 net@17 wire90-546_2-layer_1-width_3
-.ENDS latch1in60C
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2526_6-R_34_667m a b
+Ccap@0 gnd net@14 9.264f
+Ccap@1 gnd net@8 9.264f
+Ccap@2 gnd net@11 9.264f
+Rres@0 net@14 a 14.598
+Rres@1 net@11 net@14 29.196
+Rres@2 b net@8 14.598
+Rres@3 net@8 net@11 29.196
+.ENDS wire-C_0_011f-2526_6-R_34_667m
-*** CELL: registersM:addr1in60Cx7{sch}
-.SUBCKT addr1in60Cx7 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire
-Xlat[1] fire ain[1] aout[1] latch1in60C
-Xlat[2] fire ain[2] aout[2] latch1in60C
-Xlat[3] fire ain[3] aout[3] latch1in60C
-Xlat[4] fire ain[4] aout[4] latch1in60C
-Xlat[5] fire ain[5] aout[5] latch1in60C
-Xlat[6] fire ain[6] aout[6] latch1in60C
-Xlat[7] fire ain[7] aout[7] latch1in60C
-.ENDS addr1in60Cx7
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2526_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2526_6-R_34_667m
+.ENDS wire90-2526_6-layer_1-width_3
-*** CELL: registersM:addr1in60Cx15{sch}
-.SUBCKT addr1in60Cx15 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] fire
-Xaddr1in6@0 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8]
-+aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@17 addr1in60Cx7
-Xaddr1in6@1 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] net@19 addr1in60Cx7
-Xlatch1in@0 fire ain[TT] aout[TT] latch1in60C
-Xwire90@0 net@19 fire wire90-2330-layer_1-width_3
-Xwire90@1 fire net@17 wire90-2330-layer_1-width_3
-.ENDS addr1in60Cx15
+*** CELL: predicateM:ohPredAll{sch}
+.SUBCKT ohPredAll do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr]
++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F]
++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p
++ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD]
++sin sout
+XbitAssig@0 bitAssignments
+XinvI@0 net@82 fire[do] inv-X_40
+XinvI@1 net@63 fire[skip] inv-X_10
+Xnand2_sy@0 net@94 net@11 net@63 nand2_sy-X_10
+Xnand2n_s@0 net@147 net@84 fire[both] nand2n_sy-X_30
+Xnand3in2@1 net@46 net@41 net@11 net@82 net@21 nand3in20sr
+Xnor2n_sy@0 ps[skip] ps[do] net@39 nor2n_sy-X_5
+Xnor2n_sy@2 do[Lt] do[Mv] net@38 nor2n_sy-X_5
+XohPredDo@1 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] net@149 flag[A][clr]
++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] mc ps[do]
++ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] ohPredDo
+XohPredPr@1 net@92 net@139 net@160 flag[A][clr] flag[A][set] flag[B][clr]
++flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F]
++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
++m1cate[5][T] m1cate[6][F] m1cate[6][T] mc net@19 s[1] s[2] ohPredPred
+XscanEx2h@0 s[1] s[2] mc p1p p2p rd sin sout scanEx2h
+Xwire90@0 net@39 net@11 wire90-556_1-layer_1-width_3
+Xwire90@1 net@38 net@41 wire90-557-layer_1-width_3
+Xwire90@2 net@46 net@139 wire90-775_9-layer_1-width_3
+Xwire90@3 net@21 net@19 wire90-318_8-layer_1-width_3
+Xwire90@4 net@82 net@84 wire90-1035_5-layer_1-width_3
+Xwire90@5 net@147 net@63 wire90-945_6-layer_1-width_3
+Xwire90@6 net@92 net@94 wire90-1126_1-layer_1-width_3
+Xwire90@7 net@149 fire[skip] wire90-361_6-layer_1-width_3
+Xwire90@9 fire[both] net@160 wire90-2526_6-layer_1-width_3
+.ENDS ohPredAll
-*** CELL: registersM:data1in60Cx18{sch}
-.SUBCKT data1in60Cx18 dcl in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2]
-+out[3] out[4] out[5] out[6] out[7] out[8] out[9]
-Xlat[1] dcl in[1] out[1] latch1in60C
-Xlat[2] dcl in[2] out[2] latch1in60C
-Xlat[3] dcl in[3] out[3] latch1in60C
-Xlat[4] dcl in[4] out[4] latch1in60C
-Xlat[5] dcl in[5] out[5] latch1in60C
-Xlat[6] dcl in[6] out[6] latch1in60C
-Xlat[7] dcl in[7] out[7] latch1in60C
-Xlat[8] dcl in[8] out[8] latch1in60C
-Xlat[9] dcl in[9] out[9] latch1in60C
-Xlat[10] dcl in[10] out[10] latch1in60C
-Xlat[11] dcl in[11] out[11] latch1in60C
-Xlat[12] dcl in[12] out[12] latch1in60C
-Xlat[13] dcl in[13] out[13] latch1in60C
-Xlat[14] dcl in[14] out[14] latch1in60C
-Xlat[15] dcl in[15] out[15] latch1in60C
-Xlat[16] dcl in[16] out[16] latch1in60C
-Xlat[17] dcl in[17] out[17] latch1in60C
-Xlat[18] dcl in[18] out[18] latch1in60C
-.ENDS data1in60Cx18
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b
+Ccap@0 gnd net@14 6.469f
+Ccap@1 gnd net@8 6.469f
+Ccap@2 gnd net@11 6.469f
+Rres@0 net@14 a 10.194
+Rres@1 net@11 net@14 20.389
+Rres@2 b net@8 10.194
+Rres@3 net@8 net@11 20.389
+.ENDS wire-C_0_011f-1764_4-R_34_667m
-*** CELL: registersM:data1in60Cx37{sch}
-.SUBCKT data1in60Cx37 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4]
-+out[5] out[6] out[7] out[8] out[9] take
-Xdata1in6@1 net@19 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] data1in60Cx18
-Xdata1in6@2 net@17 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20]
-+out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] data1in60Cx18
-Xlatch1in@0 take in[19] out[19] latch1in60C
-Xwire90@2 take net@17 wire90-2550-layer_1-width_3
-Xwire90@3 net@19 take wire90-2550-layer_1-width_3
-.ENDS data1in60Cx37
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1764_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m
+.ENDS wire90-1764_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-698_4-R_34_667m a b
-Ccap@0 gnd net@14 2.561f
-Ccap@1 gnd net@8 2.561f
-Ccap@2 gnd net@11 2.561f
-Rres@0 net@14 a 4.035
-Rres@1 net@11 net@14 8.07
-Rres@2 b net@8 4.035
-Rres@3 net@8 net@11 8.07
-.ENDS wire-C_0_011f-698_4-R_34_667m
+.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b
+Ccap@0 gnd net@14 5.036f
+Ccap@1 gnd net@8 5.036f
+Ccap@2 gnd net@11 5.036f
+Rres@0 net@14 a 7.935
+Rres@1 net@11 net@14 15.87
+Rres@2 b net@8 7.935
+Rres@3 net@8 net@11 15.87
+.ENDS wire-C_0_011f-1373_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-698_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-698_4-R_34_667m
-.ENDS wire90-698_4-layer_1-width_3
+.SUBCKT wire90-1373_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m
+.ENDS wire90-1373_4-layer_1-width_3
-*** CELL: driversL:dataDriver60{sch}
-.SUBCKT dataDriver60 inA inB out
-Xinv@0 net@8 out inv-X_60
-Xnand2@1 inA inB net@7 nand2-X_20
-Xwire90@0 net@7 net@8 wire90-698_4-layer_1-width_3
-.ENDS dataDriver60
+*** CELL: loopCountM:olcEven{sch}
+.SUBCKT olcEven bit[2] bit[4] bit[6] count[T] do[2] do[4] do[6] inLO[2]
++inLO[4] inLO[6] load[T]
+Xinv@2 count[T] net@210 inv-X_30
+Xinv@3 load[T] net@211 inv-X_30
+XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
+XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
+XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
+Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3
+Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3
+.ENDS olcEven
-*** CELL: driversJ:predDri60wMC{sch}
-.SUBCKT driversJ__predDri60wMC in mc pred
-XNMOSx@0 pred in gnd NMOSx-X_60
-XNMOSx@1 pred mc gnd NMOSx-X_10
-Xinv@0 pred net@145 inv-X_10
-Xpms3@0 pred mc in net@174 pms3-X_3_333
-Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3
-.ENDS driversJ__predDri60wMC
+*** CELL: loopCountM:olcOdd{sch}
+.SUBCKT olcOdd bit[1] bit[3] bit[5] count[T] do[3] do[5] inLO[1] inLO[3]
++inLO[5] load[T]
+Xinv@2 load[T] net@307 inv-X_30
+Xinv@3 count[T] net@310 inv-X_30
+XringB@3 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB
+XringB@4 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB
+XringB@5 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB
+Xwire90@2 net@307 load[F] wire90-1373_4-layer_1-width_3
+Xwire90@3 net@310 count[F] wire90-1764_4-layer_1-width_3
+.ENDS olcOdd
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-175-R_34_667m a b
-Ccap@0 gnd net@14 0.642f
-Ccap@1 gnd net@8 0.642f
-Ccap@2 gnd net@11 0.642f
-Rres@0 net@14 a 1.011
-Rres@1 net@11 net@14 2.022
-Rres@2 b net@8 1.011
-Rres@3 net@8 net@11 2.022
-.ENDS wire-C_0_011f-175-R_34_667m
+.SUBCKT wire-C_0_011f-380_7-R_34_667m a b
+Ccap@0 gnd net@14 1.396f
+Ccap@1 gnd net@8 1.396f
+Ccap@2 gnd net@11 1.396f
+Rres@0 net@14 a 2.2
+Rres@1 net@11 net@14 4.399
+Rres@2 b net@8 2.2
+Rres@3 net@8 net@11 4.399
+.ENDS wire-C_0_011f-380_7-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-175-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-175-R_34_667m
-.ENDS wire90-175-layer_1-width_3
+.SUBCKT wire90-380_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-380_7-R_34_667m
+.ENDS wire90-380_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-516_9-R_34_667m a b
-Ccap@0 gnd net@14 1.895f
-Ccap@1 gnd net@8 1.895f
-Ccap@2 gnd net@11 1.895f
-Rres@0 net@14 a 2.987
-Rres@1 net@11 net@14 5.973
-Rres@2 b net@8 2.987
-Rres@3 net@8 net@11 5.973
-.ENDS wire-C_0_011f-516_9-R_34_667m
+.SUBCKT wire-C_0_011f-544_8-R_34_667m a b
+Ccap@0 gnd net@14 1.998f
+Ccap@1 gnd net@8 1.998f
+Ccap@2 gnd net@11 1.998f
+Rres@0 net@14 a 3.148
+Rres@1 net@11 net@14 6.295
+Rres@2 b net@8 3.148
+Rres@3 net@8 net@11 6.295
+.ENDS wire-C_0_011f-544_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-516_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-516_9-R_34_667m
-.ENDS wire90-516_9-layer_1-width_3
+.SUBCKT wire90-544_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-544_8-R_34_667m
+.ENDS wire90-544_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-160_4-R_34_667m a b
-Ccap@0 gnd net@14 0.588f
-Ccap@1 gnd net@8 0.588f
-Ccap@2 gnd net@11 0.588f
-Rres@0 net@14 a 0.927
-Rres@1 net@11 net@14 1.854
-Rres@2 b net@8 0.927
-Rres@3 net@8 net@11 1.854
-.ENDS wire-C_0_011f-160_4-R_34_667m
+.SUBCKT wire-C_0_011f-478_3-R_34_667m a b
+Ccap@0 gnd net@14 1.754f
+Ccap@1 gnd net@8 1.754f
+Ccap@2 gnd net@11 1.754f
+Rres@0 net@14 a 2.764
+Rres@1 net@11 net@14 5.527
+Rres@2 b net@8 2.764
+Rres@3 net@8 net@11 5.527
+.ENDS wire-C_0_011f-478_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-160_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-160_4-R_34_667m
-.ENDS wire90-160_4-layer_1-width_3
+.SUBCKT wire90-478_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-478_3-R_34_667m
+.ENDS wire90-478_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-130_1-R_34_667m a b
-Ccap@0 gnd net@14 0.477f
-Ccap@1 gnd net@8 0.477f
-Ccap@2 gnd net@11 0.477f
-Rres@0 net@14 a 0.752
-Rres@1 net@11 net@14 1.503
-Rres@2 b net@8 0.752
-Rres@3 net@8 net@11 1.503
-.ENDS wire-C_0_011f-130_1-R_34_667m
+.SUBCKT wire-C_0_011f-554_3-R_34_667m a b
+Ccap@0 gnd net@14 2.032f
+Ccap@1 gnd net@8 2.032f
+Ccap@2 gnd net@11 2.032f
+Rres@0 net@14 a 3.203
+Rres@1 net@11 net@14 6.405
+Rres@2 b net@8 3.203
+Rres@3 net@8 net@11 6.405
+.ENDS wire-C_0_011f-554_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-130_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-130_1-R_34_667m
-.ENDS wire90-130_1-layer_1-width_3
+.SUBCKT wire90-554_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-554_3-R_34_667m
+.ENDS wire90-554_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-350_6-R_34_667m a b
-Ccap@0 gnd net@14 1.286f
-Ccap@1 gnd net@8 1.286f
-Ccap@2 gnd net@11 1.286f
-Rres@0 net@14 a 2.026
-Rres@1 net@11 net@14 4.051
-Rres@2 b net@8 2.026
-Rres@3 net@8 net@11 4.051
-.ENDS wire-C_0_011f-350_6-R_34_667m
+.SUBCKT wire-C_0_011f-463_3-R_34_667m a b
+Ccap@0 gnd net@14 1.699f
+Ccap@1 gnd net@8 1.699f
+Ccap@2 gnd net@11 1.699f
+Rres@0 net@14 a 2.677
+Rres@1 net@11 net@14 5.354
+Rres@2 b net@8 2.677
+Rres@3 net@8 net@11 5.354
+.ENDS wire-C_0_011f-463_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-350_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-350_6-R_34_667m
-.ENDS wire90-350_6-layer_1-width_3
+.SUBCKT wire90-463_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-463_3-R_34_667m
+.ENDS wire90-463_3-layer_1-width_3
-*** CELL: gaspM:gaspDrain{sch}
-.SUBCKT gaspDrain clear fire go pred s[1] s[2] silent succ take tok
-Xarbiter2@0 net@374 net@353 pred net@375 arbiter2
-XctrAND2i@5 net@241 succ fire ctrAND2in100LT
-XdataDriv@0 tok fire take dataDriver60
-Xinv@1 go net@360 inv-X_10
-Xinv@4 pred net@472 inv-X_5
-Xinv@5 silent net@463 inv-X_10
-XinvI@0 net@357 net@409 inv-X_10
-XinvI@1 net@475 s[1] inv-X_10
-XpredDri6@0 fire clear pred driversJ__predDri60wMC
-XsucANDdr@4 net@499 fire succ sucANDdri60
-Xwire90@1 net@374 net@241 wire90-175-layer_1-width_3
-Xwire90@7 net@375 net@360 wire90-516_9-layer_1-width_3
-Xwire90@10 net@357 net@353 wire90-160_4-layer_1-width_3
-Xwire90@11 s[2] net@409 wire90-130_1-layer_1-width_3
-Xwire90@15 net@472 net@475 wire90-142_6-layer_1-width_3
-Xwire90@16 net@463 net@499 wire90-350_6-layer_1-width_3
-.ENDS gaspDrain
+*** CELL: loopCountM:olc{sch}
+.SUBCKT olc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2]
++inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo]
+XcountLog@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4]
++do[5] do[6] olc[zero] olc[zoo] calculate
+XolcEven@1 bitt[2] bitt[4] bitt[6] olc[dec] do[2] do[4] do[6] inLO[2] inLO[4]
++inLO[6] olc[load] olcEven
+XolcOdd@2 bitt[1] bitt[3] bitt[5] olc[dec] do[3] do[5] inLO[1] inLO[3]
++inLO[5] olc[load] olcOdd
+Xwire90@1 wire90@1_a do[2] wire90-380_7-layer_1-width_3
+Xwire90@2 wire90@2_a do[3] wire90-544_8-layer_1-width_3
+Xwire90@3 wire90@3_a do[4] wire90-478_3-layer_1-width_3
+Xwire90@4 wire90@4_a do[5] wire90-554_3-layer_1-width_3
+Xwire90@5 wire90@5_a do[6] wire90-463_3-layer_1-width_3
+.ENDS olc
-*** CELL: latchPartsK:latchPointFmcHI{sch}
-.SUBCKT latchPointFmcHI mc x[F] x[T]
-XPMOSx@0 gnd mc x[T] NMOSx-X_3
-XPMOSx@1 vdd mc x[F] NMOSx-X_6
-.ENDS latchPointFmcHI
+*** CELL: centersJ:ctrAND1in100{sch}
+.SUBCKT ctrAND1in100 in out
+Xinv@11 net@125 net@120 inv-X_30
+XinvI@3 in net@101 inv-X_10
+XinvI@4 net@82 out inv-X_100
+Xwire90@1 net@101 net@125 wire90-414-layer_1-width_3
+Xwire90@2 net@120 net@82 wire90-927-layer_1-width_3
+.ENDS ctrAND1in100
-*** CELL: latchesK:raw2inLatchFmc{sch}
-.SUBCKT raw2inLatchFmc hcl inA[1] mc out[F]
-XlatchKee@0 out[F] net@63 latchKeep
-XlatchPoi@0 hcl inA[1] out[F] net@45 latchPointF
-XlatchPoi@1 mc out[F] net@45 latchPointFmcHI
-Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3
-.ENDS raw2inLatchFmc
+*** CELL: centersJ:ctrAND2in100{sch}
+.SUBCKT ctrAND2in100 inA inB out
+Xinv@9 net@163 net@161 inv-X_30
+XinvI@1 net@162 out inv-X_100
+Xnor2n_sy@0 inA inB net@158 nor2n_sy-X_10
+Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3
+Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3
+.ENDS ctrAND2in100
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_3_999 d g s
+MNMOSf@0 d g s gnd nch W='11.997*(1+ABN/sqrt(11.997*2))' L='2'
++DELVTO='AVT0N/sqrt(11.997*2)'
+.ENDS NMOSx-X_3_999
+
+*** CELL: redFive:nms3{sch}
+.SUBCKT nms3-X_1_333 d g g2 g3
+XNMOS@0 d g3 net@6 NMOSx-X_3_999
+XNMOS@1 net@7 g gnd NMOSx-X_3_999
+XNMOS@2 net@6 g2 net@7 NMOSx-X_3_999
+.ENDS nms3-X_1_333
+
+*** CELL: driversL:sucDri20or{sch}
+.SUBCKT sucDri20or inA inB succ
+Xinv@1 succ net@94 inv-X_4
+Xnms3b@0 succ net@142 inB inA nms3-X_1_333
+Xpms1@0 succ inA pms1-X_20
+Xpms1@1 succ inB pms1-X_20
+Xwire90@0 net@142 net@94 wire90-124_7-layer_1-width_3
+.ENDS sucDri20or
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-283-R_34_667m a b
-Ccap@0 gnd net@14 1.038f
-Ccap@1 gnd net@8 1.038f
-Ccap@2 gnd net@11 1.038f
-Rres@0 net@14 a 1.635
-Rres@1 net@11 net@14 3.27
-Rres@2 b net@8 1.635
-Rres@3 net@8 net@11 3.27
-.ENDS wire-C_0_011f-283-R_34_667m
+.SUBCKT wire-C_0_011f-802-R_34_667m a b
+Ccap@0 gnd net@14 2.941f
+Ccap@1 gnd net@8 2.941f
+Ccap@2 gnd net@11 2.941f
+Rres@0 net@14 a 4.634
+Rres@1 net@11 net@14 9.268
+Rres@2 b net@8 4.634
+Rres@3 net@8 net@11 9.268
+.ENDS wire-C_0_011f-802-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-283-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-283-R_34_667m
-.ENDS wire90-283-layer_1-width_3
+.SUBCKT wire90-802-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-802-R_34_667m
+.ENDS wire90-802-layer_1-width_3
-*** CELL: latchesK:latch2in10Alomc{sch}
-.SUBCKT latch2in10Alomc hcl inA[1] mc out[1]
-Xhi2inLat@0 hcl inA[1] mc dataBar raw2inLatchFmc
-XinvLT@0 net@20 out[1] invLT-X_10
-Xwire90@0 dataBar net@20 wire90-283-layer_1-width_3
-.ENDS latch2in10Alomc
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-911_4-R_34_667m a b
+Ccap@0 gnd net@14 3.342f
+Ccap@1 gnd net@8 3.342f
+Ccap@2 gnd net@11 3.342f
+Rres@0 net@14 a 5.266
+Rres@1 net@11 net@14 10.532
+Rres@2 b net@8 5.266
+Rres@3 net@8 net@11 10.532
+.ENDS wire-C_0_011f-911_4-R_34_667m
-*** CELL: scanM:scanCellF{sch}
-.SUBCKT scanCellF dout[1] mc p1p p2p rd sin sout wr
-Xlatch1in@0 p2p sin net@2 latch1in10A
-Xlatch2in@0 p1p rd net@10 dout[1] sout latch2in10Alo
-Xlatch2in@1 wr sout mc dout[1] latch2in10Alomc
-Xwire90@0 net@2 net@10 wire90-297_6-layer_1-width_3
-.ENDS scanCellF
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-911_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-911_4-R_34_667m
+.ENDS wire90-911_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-405-R_34_667m a b
+Ccap@0 gnd net@14 1.485f
+Ccap@1 gnd net@8 1.485f
+Ccap@2 gnd net@11 1.485f
+Rres@0 net@14 a 2.34
+Rres@1 net@11 net@14 4.68
+Rres@2 b net@8 2.34
+Rres@3 net@8 net@11 4.68
+.ENDS wire-C_0_011f-405-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-405-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-405-R_34_667m
+.ENDS wire90-405-layer_1-width_3
-*** CELL: scanM:scanFx3{sch}
-.SUBCKT scanFx3 dout[1] dout[2] dout[3] sic[1] sic[2] sic[3] sic[4] sic[5]
-+sic[6] sic[7] sic[8] sic[9] soc[1]
-XscanCell@4 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4]
-+scanCellF
-XscanCell@5 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 net@31 sic[4]
-+scanCellF
-XscanCell@6 dout[3] sic[9] sic[3] sic[2] sic[5] net@33 soc[1] sic[4]
-+scanCellF
-Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3
-Xwire90@1 net@31 net@33 wire90-297_6-layer_1-width_3
-.ENDS scanFx3
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-472_9-R_34_667m a b
+Ccap@0 gnd net@14 1.734f
+Ccap@1 gnd net@8 1.734f
+Ccap@2 gnd net@11 1.734f
+Rres@0 net@14 a 2.732
+Rres@1 net@11 net@14 5.465
+Rres@2 b net@8 2.732
+Rres@3 net@8 net@11 5.465
+.ENDS wire-C_0_011f-472_9-R_34_667m
-*** CELL: stagesM:drainStage{sch}
-.SUBCKT drainStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15]
-+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25]
-+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35]
-+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1]
-+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28]
-+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36]
-+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] sic[2]
-+sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4]
-+sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ
-Xaddr1in6@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] net@4 addr1in60Cx15
-Xdata1in6@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] net@5 data1in60Cx37
-XgaspDrai@0 clear net@4 go pred net@17[1] net@17[0] silent succ net@5 ain[TT]
-+gaspDrain
-XscanEx2v@1 net@17[1] net@17[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sor[1] scanEx2
-XscanFx3@0 go clear silent sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
-+sic[8] sic[9] soc[1] scanFx3
-.ENDS drainStage
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-472_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-472_9-R_34_667m
+.ENDS wire90-472_9-layer_1-width_3
-*** CELL: latchGroupsK:latchWscM2{sch}
-.SUBCKT latchWscM2 hcl in[1] out[1] p1p p2p rd sin sout wr
-Xhi2inLat@1 hcl wr in[1] sout out[1] latch2in60C
-XscanCell@2 out[1] p1p p2p rd sin sout scanJ__scanCellE
-.ENDS latchWscM2
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-346_7-R_34_667m a b
+Ccap@0 gnd net@14 1.271f
+Ccap@1 gnd net@8 1.271f
+Ccap@2 gnd net@11 1.271f
+Rres@0 net@14 a 2.003
+Rres@1 net@11 net@14 4.006
+Rres@2 b net@8 2.003
+Rres@3 net@8 net@11 4.006
+.ENDS wire-C_0_011f-346_7-R_34_667m
-*** CELL: registersM:addr1in60Cx7scan{sch}
-.SUBCKT addr1in60Cx7scan ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7]
-+aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire p1p p2p rd sin
-+sout wr[A]
-Xla[1] fire ain[1] aout[1] p1p p2p rd sin xin[2] wr[A] latchWscM2
-Xla[2] fire ain[2] aout[2] p1p p2p rd xin[2] xin[3] wr[A] latchWscM2
-Xla[3] fire ain[3] aout[3] p1p p2p rd xin[3] xin[4] wr[A] latchWscM2
-Xla[4] fire ain[4] aout[4] p1p p2p rd xin[4] xin[5] wr[A] latchWscM2
-Xla[5] fire ain[5] aout[5] p1p p2p rd xin[5] xin[6] wr[A] latchWscM2
-Xla[6] fire ain[6] aout[6] p1p p2p rd xin[6] xin[7] wr[A] latchWscM2
-Xla[7] fire ain[7] aout[7] p1p p2p rd xin[7] sout wr[A] latchWscM2
-.ENDS addr1in60Cx7scan
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-346_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-346_7-R_34_667m
+.ENDS wire90-346_7-layer_1-width_3
-*** CELL: registersM:data1in60Cx18scan{sch}
-.SUBCKT data1in60Cx18scan dcl in[10] in[11] in[12] in[13] in[14] in[15]
-+in[16] in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9]
-+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18]
-+out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] p1p p2p rd sin
-+sout wr[D]
-Xla[1] dcl in[1] out[1] p1p p2p rd sin xin[2] wr[D] latchWscM2
-Xla[2] dcl in[2] out[2] p1p p2p rd xin[2] xin[3] wr[D] latchWscM2
-Xla[3] dcl in[3] out[3] p1p p2p rd xin[3] xin[4] wr[D] latchWscM2
-Xla[4] dcl in[4] out[4] p1p p2p rd xin[4] xin[5] wr[D] latchWscM2
-Xla[5] dcl in[5] out[5] p1p p2p rd xin[5] xin[6] wr[D] latchWscM2
-Xla[6] dcl in[6] out[6] p1p p2p rd xin[6] xin[7] wr[D] latchWscM2
-Xla[7] dcl in[7] out[7] p1p p2p rd xin[7] xin[8] wr[D] latchWscM2
-Xla[8] dcl in[8] out[8] p1p p2p rd xin[8] xin[9] wr[D] latchWscM2
-Xla[9] dcl in[9] out[9] p1p p2p rd xin[9] xin[10] wr[D] latchWscM2
-Xla[10] dcl in[10] out[10] p1p p2p rd xin[10] xin[11] wr[D] latchWscM2
-Xla[11] dcl in[11] out[11] p1p p2p rd xin[11] xin[12] wr[D] latchWscM2
-Xla[12] dcl in[12] out[12] p1p p2p rd xin[12] xin[13] wr[D] latchWscM2
-Xla[13] dcl in[13] out[13] p1p p2p rd xin[13] xin[14] wr[D] latchWscM2
-Xla[14] dcl in[14] out[14] p1p p2p rd xin[14] xin[15] wr[D] latchWscM2
-Xla[15] dcl in[15] out[15] p1p p2p rd xin[15] xin[16] wr[D] latchWscM2
-Xla[16] dcl in[16] out[16] p1p p2p rd xin[16] xin[17] wr[D] latchWscM2
-Xla[17] dcl in[17] out[17] p1p p2p rd xin[17] xin[18] wr[D] latchWscM2
-Xla[18] dcl in[18] out[18] p1p p2p rd xin[18] sout wr[D] latchWscM2
-.ENDS data1in60Cx18scan
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-438_9-R_34_667m a b
+Ccap@0 gnd net@14 1.609f
+Ccap@1 gnd net@8 1.609f
+Ccap@2 gnd net@11 1.609f
+Rres@0 net@14 a 2.536
+Rres@1 net@11 net@14 5.072
+Rres@2 b net@8 2.536
+Rres@3 net@8 net@11 5.072
+.ENDS wire-C_0_011f-438_9-R_34_667m
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_30 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_60
-XNMOS@1 net@0 g gnd NMOSx-X_60
-.ENDS nms2-X_30
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-438_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-438_9-R_34_667m
+.ENDS wire90-438_9-layer_1-width_3
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_30 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_30
-XPMOS@1 out inb vdd PMOSx-X_30
-Xnms2@0 out ina inb nms2-X_30
-.ENDS nand2-X_30
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-143_2-R_34_667m a b
+Ccap@0 gnd net@14 0.525f
+Ccap@1 gnd net@8 0.525f
+Ccap@2 gnd net@11 0.525f
+Rres@0 net@14 a 0.827
+Rres@1 net@11 net@14 1.655
+Rres@2 b net@8 0.827
+Rres@3 net@8 net@11 1.655
+.ENDS wire-C_0_011f-143_2-R_34_667m
-*** CELL: redFive:nor2HT_sy{sch}
-.SUBCKT nor2HT_sy-X_10 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_5
-XNMOS@1 out ina gnd NMOSx-X_5
-Xpms2_sy@0 out ina inb pms2_sy-X_10
-.ENDS nor2HT_sy-X_10
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-143_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-143_2-R_34_667m
+.ENDS wire90-143_2-layer_1-width_3
-*** CELL: centersJ:ctrAND3in100A{sch}
-.SUBCKT ctrAND3in100A inA inB inC out
-Xinv@4 inC net@30 inv-X_10
-Xinv@5 net@9 out inv-X_100
-Xnand2@0 net@19 net@15 net@27 nand2-X_30
-Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_10
-Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
-Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
-Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
-.ENDS ctrAND3in100A
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-144_3-R_34_667m a b
+Ccap@0 gnd net@14 0.529f
+Ccap@1 gnd net@8 0.529f
+Ccap@2 gnd net@11 0.529f
+Rres@0 net@14 a 0.834
+Rres@1 net@11 net@14 1.667
+Rres@2 b net@8 0.834
+Rres@3 net@8 net@11 1.667
+.ENDS wire-C_0_011f-144_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-144_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-144_3-R_34_667m
+.ENDS wire90-144_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-918_6-R_34_667m a b
-Ccap@0 gnd net@14 3.368f
-Ccap@1 gnd net@8 3.368f
-Ccap@2 gnd net@11 3.368f
-Rres@0 net@14 a 5.307
-Rres@1 net@11 net@14 10.615
-Rres@2 b net@8 5.307
-Rres@3 net@8 net@11 10.615
-.ENDS wire-C_0_011f-918_6-R_34_667m
+.SUBCKT wire-C_0_011f-431_3-R_34_667m a b
+Ccap@0 gnd net@14 1.581f
+Ccap@1 gnd net@8 1.581f
+Ccap@2 gnd net@11 1.581f
+Rres@0 net@14 a 2.492
+Rres@1 net@11 net@14 4.984
+Rres@2 b net@8 2.492
+Rres@3 net@8 net@11 4.984
+.ENDS wire-C_0_011f-431_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-918_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-918_6-R_34_667m
-.ENDS wire90-918_6-layer_1-width_3
+.SUBCKT wire90-431_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-431_3-R_34_667m
+.ENDS wire90-431_3-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1177-R_34_667m a b
-Ccap@0 gnd net@14 4.316f
-Ccap@1 gnd net@8 4.316f
-Ccap@2 gnd net@11 4.316f
-Rres@0 net@14 a 6.8
-Rres@1 net@11 net@14 13.601
-Rres@2 b net@8 6.8
-Rres@3 net@8 net@11 13.601
-.ENDS wire-C_0_011f-1177-R_34_667m
+.SUBCKT wire-C_0_011f-485_9-R_34_667m a b
+Ccap@0 gnd net@14 1.782f
+Ccap@1 gnd net@8 1.782f
+Ccap@2 gnd net@11 1.782f
+Rres@0 net@14 a 2.807
+Rres@1 net@11 net@14 5.615
+Rres@2 b net@8 2.807
+Rres@3 net@8 net@11 5.615
+.ENDS wire-C_0_011f-485_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1177-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1177-R_34_667m
-.ENDS wire90-1177-layer_1-width_3
+.SUBCKT wire90-485_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-485_9-R_34_667m
+.ENDS wire90-485_9-layer_1-width_3
-*** CELL: gaspM:fillScanControl{sch}
-.SUBCKT fillScanControl si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9]
-+so[1] wr[A] wr[D]
-XdataDriv@2 so[1] si[4] wr[D] dataDriver60
-XdataDriv@3 net@4 net@21 wr[A] dataDriver60
-XscanCell@2 scanCell@2_dIn[1] si[3] si[2] si[5] si[1] net@7 scanM__scanCellE
-XscanCell@3 scanCell@3_dIn[1] si[3] si[2] si[5] net@4 so[1] scanM__scanCellE
-Xwire90@0 net@7 net@4 wire90-918_6-layer_1-width_3
-Xwire90@1 net@21 si[4] wire90-1177-layer_1-width_3
-.ENDS fillScanControl
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-208_9-R_34_667m a b
+Ccap@0 gnd net@14 0.766f
+Ccap@1 gnd net@8 0.766f
+Ccap@2 gnd net@11 0.766f
+Rres@0 net@14 a 1.207
+Rres@1 net@11 net@14 2.414
+Rres@2 b net@8 1.207
+Rres@3 net@8 net@11 2.414
+.ENDS wire-C_0_011f-208_9-R_34_667m
-*** CELL: driversJ:sucORdri60{sch}
-.SUBCKT sucORdri60 inA inB succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_60
-Xinv@0 succ net@71 inv-X_5
-Xnms2@0 succ net@51 net@72 nms2-X_8
-Xnor2_sy@0 inA inB net@67 nor2_sy-X_20
-Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3
-Xwire90@1 net@72 net@71 wire90-209-layer_1-width_3
-.ENDS sucORdri60
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-208_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-208_9-R_34_667m
+.ENDS wire90-208_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-602_3-R_34_667m a b
-Ccap@0 gnd net@14 2.208f
-Ccap@1 gnd net@8 2.208f
-Ccap@2 gnd net@11 2.208f
-Rres@0 net@14 a 3.48
-Rres@1 net@11 net@14 6.96
-Rres@2 b net@8 3.48
-Rres@3 net@8 net@11 6.96
-.ENDS wire-C_0_011f-602_3-R_34_667m
+.SUBCKT wire-C_0_011f-127_4-R_34_667m a b
+Ccap@0 gnd net@14 0.467f
+Ccap@1 gnd net@8 0.467f
+Ccap@2 gnd net@11 0.467f
+Rres@0 net@14 a 0.736
+Rres@1 net@11 net@14 1.472
+Rres@2 b net@8 0.736
+Rres@3 net@8 net@11 1.472
+.ENDS wire-C_0_011f-127_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-602_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-602_3-R_34_667m
-.ENDS wire90-602_3-layer_1-width_3
-
-*** CELL: gaspM:gaspFill{sch}
-.SUBCKT gaspFill block fill fire pred s[1] s[2] si[1] si[2] si[3] si[4] si[5]
-+si[6] si[7] si[8] si[9] so[1] succ take wr[A] wr[D]
-XctrAND3i@1 net@602 succ fire fire[B] ctrAND3in30
-XctrAND3i@3 net@454 succ block fire ctrAND3in100A
-XfillScan@1 si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1] wr[A]
-+wr[D] fillScanControl
-Xinv@0 pred net@533 inv-X_5
-Xinv@1 fill net@537 inv-X_5
-XinvI@0 net@454 s[1] inv-X_10
-XinvI@1 net@602 s[2] inv-X_10
-XlatchDri@0 fire take latchDriver60
-XpredDri6@2 fire si[9] pred driversL__predDri60wMC
-XsucORdri@1 fire net@320 succ sucORdri60
-Xwire90@1 net@537 net@602 wire90-602_3-layer_1-width_3
-Xwire90@12 net@533 net@454 wire90-602_3-layer_1-width_3
-Xwire90@15 fire[B] net@320 wire90-602_3-layer_1-width_3
-.ENDS gaspFill
+.SUBCKT wire90-127_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-127_4-R_34_667m
+.ENDS wire90-127_4-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-70-R_34_667m a b
-Ccap@0 gnd net@14 0.257f
-Ccap@1 gnd net@8 0.257f
-Ccap@2 gnd net@11 0.257f
-Rres@0 net@14 a 0.404
-Rres@1 net@11 net@14 0.809
-Rres@2 b net@8 0.404
-Rres@3 net@8 net@11 0.809
-.ENDS wire-C_0_011f-70-R_34_667m
+.SUBCKT wire-C_0_011f-215_9-R_34_667m a b
+Ccap@0 gnd net@14 0.792f
+Ccap@1 gnd net@8 0.792f
+Ccap@2 gnd net@11 0.792f
+Rres@0 net@14 a 1.247
+Rres@1 net@11 net@14 2.495
+Rres@2 b net@8 1.247
+Rres@3 net@8 net@11 2.495
+.ENDS wire-C_0_011f-215_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-70-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-70-R_34_667m
-.ENDS wire90-70-layer_1-width_3
+.SUBCKT wire90-215_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-215_9-R_34_667m
+.ENDS wire90-215_9-layer_1-width_3
-*** CELL: scanJ:scanAmp{sch}
-.SUBCKT scanAmp in[1] out[1]
-Xinv@0 in[1] net@1 inv-X_10
-Xinv@1 net@2 out[1] inv-X_20
-Xwire90@0 net@1 net@2 wire90-70-layer_1-width_3
-.ENDS scanAmp
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-140_6-R_34_667m a b
+Ccap@0 gnd net@14 0.516f
+Ccap@1 gnd net@8 0.516f
+Ccap@2 gnd net@11 0.516f
+Rres@0 net@14 a 0.812
+Rres@1 net@11 net@14 1.625
+Rres@2 b net@8 0.812
+Rres@3 net@8 net@11 1.625
+.ENDS wire-C_0_011f-140_6-R_34_667m
-*** CELL: gaspM:scanAMPx5{sch}
-.SUBCKT scanAMPx5 si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1]
-+so[2] so[3] so[4] so[5]
-Xsa[1] si[1] so[1] scanAmp
-Xsa[2] si[2] so[2] scanAmp
-Xsa[3] si[3] so[3] scanAmp
-Xsa[4] si[4] so[4] scanAmp
-Xsa[5] si[5] so[5] scanAmp
-.ENDS scanAMPx5
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-140_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-140_6-R_34_667m
+.ENDS wire90-140_6-layer_1-width_3
+
+*** CELL: loopCountM:olcControl{sch}
+.SUBCKT olcControl Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set]
++ilc[load] mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3]
+XctrAND1i@0 net@527 net@165 ctrAND1in30
+XctrAND1i@3 net@519 ilc[load] ctrAND1in100
+XctrAND1i@4 net@547 net@162 ctrAND1in30
+XctrAND2i@3 do[2] net@339 olc[load] ctrAND2in100LT
+XctrAND2i@5 olc[zero] net@547 olc[dec] ctrAND2in100
+Xinv@6 olc[zoo] net@180 inv-X_5
+Xinv@7 olc[zero] net@184 inv-X_5
+Xinv@14 do[Co] net@386 inv-X_10
+Xinv@16 Dvoid net@451 inv-X_5
+Xinv@18 flag[D][set] net@535 inv-X_5
+Xinv@19 flag[D][clr] net@539 inv-X_5
+Xinv@20 do[Ld] net@576 inv-X_5
+XinvI@2 net@538 s[3] inv-X_10
+XinvI@3 net@534 s[2] inv-X_10
+XinvI@4 net@575 s[1] inv-X_10
+Xnand2@0 net@288 net@162 net@286 nand2-X_5
+Xnand2@1 net@289 net@165 net@284 nand2-X_5
+Xnand2@2 olc[zoo] net@162 net@279 nand2-X_5
+Xnand2@3 olc[zero] net@165 net@281 nand2-X_5
+Xnand2@4 Dvoid do[Ld] net@471 nand2-X_5
+Xnand2@5 net@455 do[Ld] net@438 nand2-X_5
+Xnor2_sy@1 do[reD] do[2] net@556 nor2_sy-X_5
+XpredDri2@0 net@358 mc do[2] predDri20wMC
+XpredDri2@2 net@162 mc do[Co] predDri20wMC
+XpredDri2@3 net@165 mc do[reD] predDri20wMC
+XpredORdr@0 ilc[load] olc[load] mc do[Ld] predORdri20wMC
+XsucDri20@0 olc[load] net@278 sucDri20
+XsucDri20@3 net@428 net@424 flag[D][clr] sucDri20or
+XsucDri20@4 net@426 net@422 flag[D][set] sucDri20or
+Xwire90@6 net@358 net@165 wire90-802-layer_1-width_3
+Xwire90@8 net@278 do[2] wire90-911_4-layer_1-width_3
+Xwire90@9 net@281 net@422 wire90-405-layer_1-width_3
+Xwire90@10 net@279 net@426 wire90-472_9-layer_1-width_3
+Xwire90@11 net@286 net@428 wire90-346_7-layer_1-width_3
+Xwire90@12 net@284 net@424 wire90-438_9-layer_1-width_3
+Xwire90@13 net@180 net@288 wire90-143_2-layer_1-width_3
+Xwire90@14 net@184 net@289 wire90-144_3-layer_1-width_3
+Xwire90@17 net@471 net@339 wire90-431_3-layer_1-width_3
+Xwire90@19 net@386 net@547 wire90-485_9-layer_1-width_3
+Xwire90@20 net@438 net@519 wire90-208_9-layer_1-width_3
+Xwire90@21 net@455 net@451 wire90-127_4-layer_1-width_3
+Xwire90@22 net@556 net@527 wire90-215_9-layer_1-width_3
+Xwire90@23 net@535 net@534 wire90-140_6-layer_1-width_3
+Xwire90@24 net@539 net@538 wire90-140_6-layer_1-width_3
+Xwire90@25 net@576 net@575 wire90-140_6-layer_1-width_3
+.ENDS olcControl
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2500-R_34_667m a b
-Ccap@0 gnd net@14 9.167f
-Ccap@1 gnd net@8 9.167f
-Ccap@2 gnd net@11 9.167f
-Rres@0 net@14 a 14.444
-Rres@1 net@11 net@14 28.889
-Rres@2 b net@8 14.444
-Rres@3 net@8 net@11 28.889
-.ENDS wire-C_0_011f-2500-R_34_667m
+.SUBCKT wire-C_0_011f-1022_9-R_34_667m a b
+Ccap@0 gnd net@14 3.751f
+Ccap@1 gnd net@8 3.751f
+Ccap@2 gnd net@11 3.751f
+Rres@0 net@14 a 5.91
+Rres@1 net@11 net@14 11.82
+Rres@2 b net@8 5.91
+Rres@3 net@8 net@11 11.82
+.ENDS wire-C_0_011f-1022_9-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2500-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2500-R_34_667m
-.ENDS wire90-2500-layer_1-width_3
-
-*** CELL: stagesM:fillStage{sch}
-.SUBCKT fillStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] extra fire in[10] in[11] in[12] in[13]
-+in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
-+in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
-+in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
-+succ
-Xaddr1in6@0 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] net@13 sx[3] sx[2] sx[5] net@61
-+net@62 sx[A] addr1in60Cx7scan
-Xaddr1in6@1 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8]
-+aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@16 sx[3] sx[2] sx[5]
-+net@62 net@66 sx[A] addr1in60Cx7scan
-Xdata1in6@0 net@3 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] sx[3] sx[2] sx[5] net@66 net@65
-+sx[D] data1in60Cx18scan
-Xdata1in6@1 net@0 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20]
-+out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] sx[3] sx[2]
-+sx[5] net@64 sz[1] sx[D] data1in60Cx18scan
-XgaspFill@0 block fill fire pred s[1] s[2] sx[1] sx[2] sx[3] sx[4] sx[5]
-+sid[6] sid[7] sid[8] sid[9] sy[1] succ net@8 sx[A] sx[D] gaspFill
-XlatchWsc@0 net@0 in[19] out[19] sx[3] sx[2] sx[5] net@65 net@64 sx[D]
-+latchWscM2
-XlatchWsc@1 net@13 ain[TT] aout[TT] sx[3] sx[2] sx[5] sy[1] net@61 sx[A]
-+latchWscM2
-XscanAMPx@0 sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9]
-+sx[1] sx[2] sx[3] sx[4] sx[5] scanAMPx5
-XscanAMPx@1 sz[1] sx[2] sx[3] sx[4] sx[5] sid[6] sid[7] sid[8] sid[9] sod[1]
-+sod[2] sod[3] sod[4] sod[5] scanAMPx5
-XscanEx2@0 s[1] s[2] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx2
-XscanFx3@0 block extra fill sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
-+sic[8] sic[9] soc[1] scanFx3
-Xwire90@1 net@8 net@0 wire90-2550-layer_1-width_3
-Xwire90@3 fire net@16 wire90-2500-layer_1-width_3
-Xwire90@4 net@3 net@8 wire90-2550-layer_1-width_3
-Xwire90@5 net@13 fire wire90-2500-layer_1-width_3
-.ENDS fillStage
+.SUBCKT wire90-1022_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1022_9-R_34_667m
+.ENDS wire90-1022_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2080_4-R_34_667m a b
-Ccap@0 gnd net@14 7.628f
-Ccap@1 gnd net@8 7.628f
-Ccap@2 gnd net@11 7.628f
-Rres@0 net@14 a 12.02
-Rres@1 net@11 net@14 24.04
-Rres@2 b net@8 12.02
-Rres@3 net@8 net@11 24.04
-.ENDS wire-C_0_011f-2080_4-R_34_667m
+.SUBCKT wire-C_0_011f-810_8-R_34_667m a b
+Ccap@0 gnd net@14 2.973f
+Ccap@1 gnd net@8 2.973f
+Ccap@2 gnd net@11 2.973f
+Rres@0 net@14 a 4.685
+Rres@1 net@11 net@14 9.369
+Rres@2 b net@8 4.685
+Rres@3 net@8 net@11 9.369
+.ENDS wire-C_0_011f-810_8-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2080_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2080_4-R_34_667m
-.ENDS wire90-2080_4-layer_1-width_3
+.SUBCKT wire90-810_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-810_8-R_34_667m
+.ENDS wire90-810_8-layer_1-width_3
-*** CELL: stageGroupsM:properStopper{sch}
-.SUBCKT properStopper ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] extra fire in[10] in[11] in[12] in[13]
-+in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23]
-+in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33]
-+in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
-+succ
-XdrainSta@1 net@65[41] net@65[40] net@65[39] net@65[38] net@65[37] net@65[50]
-+net@65[49] net@65[48] net@65[47] net@65[46] net@65[45] net@65[44] net@65[43]
-+net@65[42] net@65[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
-+net@65[27] net@65[26] net@65[25] net@65[24] net@65[23] net@65[22] net@65[21]
-+net@65[20] net@65[19] net@65[18] net@65[36] net@65[17] net@65[16] net@65[15]
-+net@65[14] net@65[13] net@65[12] net@65[11] net@65[10] net@65[9] net@65[8]
-+net@65[35] net@65[7] net@65[6] net@65[5] net@65[4] net@65[3] net@65[2]
-+net@65[1] net@65[0] net@65[34] net@65[33] net@65[32] net@65[31] net@65[30]
-+net@65[29] net@65[28] out[10] out[11] out[12] out[13] out[14] out[15] out[16]
-+out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24]
-+out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32]
-+out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7]
-+out[8] out[9] net@42 net@3[8] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
-+sic[8] sic[9] net@2[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
-+sir[9] soc[1] sor[1] succ drainStage
-XfillStag@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] net@65[41] net@65[40]
-+net@65[39] net@65[38] net@65[37] net@65[50] net@65[49] net@65[48] net@65[47]
-+net@65[46] net@65[45] net@65[44] net@65[43] net@65[42] net@65[51] extra fire
-+in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1]
-+in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2]
-+in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3] in[4] in[5]
-+in[6] in[7] in[8] in[9] net@65[27] net@65[26] net@65[25] net@65[24]
-+net@65[23] net@65[22] net@65[21] net@65[20] net@65[19] net@65[18] net@65[36]
-+net@65[17] net@65[16] net@65[15] net@65[14] net@65[13] net@65[12] net@65[11]
-+net@65[10] net@65[9] net@65[8] net@65[35] net@65[7] net@65[6] net@65[5]
-+net@65[4] net@65[3] net@65[2] net@65[1] net@65[0] net@65[34] net@65[33]
-+net@65[32] net@65[31] net@65[30] net@65[29] net@65[28] pred sic[1] sic[2]
-+sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4]
-+sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] net@3[8] sod[1] sod[2] sod[3] sod[4] sod[5] net@2[8]
-+net@41 fillStage
-Xwire90@0 net@41 net@42 wire90-2080_4-layer_1-width_3
-.ENDS properStopper
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4437_9-R_34_667m a b
+Ccap@0 gnd net@14 16.272f
+Ccap@1 gnd net@8 16.272f
+Ccap@2 gnd net@11 16.272f
+Rres@0 net@14 a 25.641
+Rres@1 net@11 net@14 51.282
+Rres@2 b net@8 25.641
+Rres@3 net@8 net@11 51.282
+.ENDS wire-C_0_011f-4437_9-R_34_667m
-*** CELL: stageGroupsM:fillDrainCount{sch}
-.SUBCKT fillDrainCount ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] fin fout in[10] in[11] in[12] in[13] in[14]
-+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24]
-+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34]
-+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
-+succ
-Xinstruct@0 net@53 net@48 fin fout net@61[8] sod[2] sod[3] sod[4] sod[5]
-+sid[6] sid[7] sid[8] sid[9] sod[1] instructionCount
-XproperSt@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] net@86 net@53 in[10] in[11] in[12] in[13] in[14]
-+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24]
-+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34]
-+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
-+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] net@61[8] sod[2] sod[3] sod[4] sod[5]
-+sor[1] succ properStopper
-Xwire90@1 net@86 net@48 wire90-2080_4-layer_1-width_3
-.ENDS fillDrainCount
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4437_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4437_9-R_34_667m
+.ENDS wire90-4437_9-layer_1-width_3
-*** CELL: scanM:scanCap{sch}
-.SUBCKT scanCap si[1] si[2] si[3] si[4] si[5] si[9]
-.ENDS scanCap
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3501_1-R_34_667m a b
+Ccap@0 gnd net@14 12.837f
+Ccap@1 gnd net@8 12.837f
+Ccap@2 gnd net@11 12.837f
+Rres@0 net@14 a 20.229
+Rres@1 net@11 net@14 40.457
+Rres@2 b net@8 20.229
+Rres@3 net@8 net@11 40.457
+.ENDS wire-C_0_011f-3501_1-R_34_667m
-*** CELL: registersM:addr1in20Bx7{sch}
-.SUBCKT addr1in20Bx7 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1]
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire
-Xlat[1] fire ain[1] aout[1] latch1in20B
-Xlat[2] fire ain[2] aout[2] latch1in20B
-Xlat[3] fire ain[3] aout[3] latch1in20B
-Xlat[4] fire ain[4] aout[4] latch1in20B
-Xlat[5] fire ain[5] aout[5] latch1in20B
-Xlat[6] fire ain[6] aout[6] latch1in20B
-Xlat[7] fire ain[7] aout[7] latch1in20B
-.ENDS addr1in20Bx7
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3501_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3501_1-R_34_667m
+.ENDS wire90-3501_1-layer_1-width_3
-*** CELL: registersM:addr1in20Bx15{sch}
-.SUBCKT addr1in20Bx15 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] fire
-Xaddr1in2@1 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8]
-+aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@17 addr1in20Bx7
-Xaddr1in2@2 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] net@19 addr1in20Bx7
-Xlatch1in@1 fire ain[TT] aout[TT] latch1in20B
-Xwire90@0 net@19 fire wire90-2330-layer_1-width_3
-Xwire90@1 fire net@17 wire90-2330-layer_1-width_3
-.ENDS addr1in20Bx15
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1686-R_34_667m a b
+Ccap@0 gnd net@14 6.182f
+Ccap@1 gnd net@8 6.182f
+Ccap@2 gnd net@11 6.182f
+Rres@0 net@14 a 9.741
+Rres@1 net@11 net@14 19.483
+Rres@2 b net@8 9.741
+Rres@3 net@8 net@11 19.483
+.ENDS wire-C_0_011f-1686-R_34_667m
-*** CELL: registersM:data1in20Bx37{sch}
-.SUBCKT data1in20Bx37 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
-+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37]
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13]
-+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21]
-+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4]
-+out[5] out[6] out[7] out[8] out[9] take
-Xins1in20@0 net@17 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29]
-+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20]
-+out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] ins1in20Bx18
-Xins1in20@1 net@19 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
-+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] ins1in20Bx18
-Xlatch1in@1 take in[19] out[19] latch1in20B
-Xwire90@2 take net@17 wire90-2550-layer_1-width_3
-Xwire90@3 net@19 take wire90-2550-layer_1-width_3
-.ENDS data1in20Bx37
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1686-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1686-R_34_667m
+.ENDS wire90-1686-layer_1-width_3
-*** CELL: gaspM:gaspWeak{sch}
-.SUBCKT gaspWeak fire mc pred s[1] succ take tok
-XctrAND2i@0 net@10 succ fire ctrAND2in100LT
-XdataDriv@0 tok fire take dataDriver60
-Xinv@0 pred net@8 inv-X_5
-XinvI@0 net@10 s[1] inv-X_10
-XpredDri2@0 net@30 mc pred predDri20wMC
-XsucDri20@0 fire succ sucDri20
-Xwire90@0 net@8 net@10 wire90-602_3-layer_1-width_3
-Xwire90@1 net@30 fire wire90-602_3-layer_1-width_3
-.ENDS gaspWeak
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1399-R_34_667m a b
+Ccap@0 gnd net@14 5.13f
+Ccap@1 gnd net@8 5.13f
+Ccap@2 gnd net@11 5.13f
+Rres@0 net@14 a 8.083
+Rres@1 net@11 net@14 16.166
+Rres@2 b net@8 8.083
+Rres@3 net@8 net@11 16.166
+.ENDS wire-C_0_011f-1399-R_34_667m
-*** CELL: stagesM:weakStage{sch}
-.SUBCKT weakStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15]
-+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25]
-+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35]
-+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11]
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1]
-+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28]
-+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36]
-+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sir[1] sir[2]
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ
-Xaddr1in2@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12]
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7]
-+aout[8] aout[9] aout[TT] net@59 addr1in20Bx15
-Xdata1in2@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
-+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
-+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3]
-+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14]
-+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22]
-+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
-+out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5]
-+out[6] out[7] out[8] out[9] net@47 data1in20Bx37
-XgaspWeak@0 net@59 sir[9] pred net@39 succ net@47 ain[TT] gaspWeak
-XscanEx1v@0 net@39 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1vertA
-.ENDS weakStage
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1399-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1399-R_34_667m
+.ENDS wire90-1399-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1243_9-R_34_667m a b
-Ccap@0 gnd net@14 4.561f
-Ccap@1 gnd net@8 4.561f
-Ccap@2 gnd net@11 4.561f
-Rres@0 net@14 a 7.187
-Rres@1 net@11 net@14 14.374
-Rres@2 b net@8 7.187
-Rres@3 net@8 net@11 14.374
-.ENDS wire-C_0_011f-1243_9-R_34_667m
+.SUBCKT wire-C_0_011f-1408_5-R_34_667m a b
+Ccap@0 gnd net@14 5.164f
+Ccap@1 gnd net@8 5.164f
+Ccap@2 gnd net@11 5.164f
+Rres@0 net@14 a 8.138
+Rres@1 net@11 net@14 16.276
+Rres@2 b net@8 8.138
+Rres@3 net@8 net@11 16.276
+.ENDS wire-C_0_011f-1408_5-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1243_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1243_9-R_34_667m
-.ENDS wire90-1243_9-layer_1-width_3
+.SUBCKT wire90-1408_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1408_5-R_34_667m
+.ENDS wire90-1408_5-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1185_9-R_34_667m a b
-Ccap@0 gnd net@14 4.348f
-Ccap@1 gnd net@8 4.348f
-Ccap@2 gnd net@11 4.348f
-Rres@0 net@14 a 6.852
-Rres@1 net@11 net@14 13.704
-Rres@2 b net@8 6.852
-Rres@3 net@8 net@11 13.704
-.ENDS wire-C_0_011f-1185_9-R_34_667m
+.SUBCKT wire-C_0_011f-1925_2-R_34_667m a b
+Ccap@0 gnd net@14 7.059f
+Ccap@1 gnd net@8 7.059f
+Ccap@2 gnd net@11 7.059f
+Rres@0 net@14 a 11.123
+Rres@1 net@11 net@14 22.247
+Rres@2 b net@8 11.123
+Rres@3 net@8 net@11 22.247
+.ENDS wire-C_0_011f-1925_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1185_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1185_9-R_34_667m
-.ENDS wire90-1185_9-layer_1-width_3
+.SUBCKT wire90-1925_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1925_2-R_34_667m
+.ENDS wire90-1925_2-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1249_9-R_34_667m a b
-Ccap@0 gnd net@14 4.583f
-Ccap@1 gnd net@8 4.583f
-Ccap@2 gnd net@11 4.583f
-Rres@0 net@14 a 7.222
-Rres@1 net@11 net@14 14.443
-Rres@2 b net@8 7.222
-Rres@3 net@8 net@11 14.443
-.ENDS wire-C_0_011f-1249_9-R_34_667m
+.SUBCKT wire-C_0_011f-1638_1-R_34_667m a b
+Ccap@0 gnd net@14 6.006f
+Ccap@1 gnd net@8 6.006f
+Ccap@2 gnd net@11 6.006f
+Rres@0 net@14 a 9.465
+Rres@1 net@11 net@14 18.929
+Rres@2 b net@8 9.465
+Rres@3 net@8 net@11 18.929
+.ENDS wire-C_0_011f-1638_1-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1249_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1249_9-R_34_667m
-.ENDS wire90-1249_9-layer_1-width_3
+.SUBCKT wire90-1638_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1638_1-R_34_667m
+.ENDS wire90-1638_1-layer_1-width_3
-*** CELL: stageGroupsM:upDown8weak{sch}
-.SUBCKT upDown8weak ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1]
-+ainD[2] ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[TT]
-+ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] ainU[3] ainU[4]
-+ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[TT] aoutD[10] aoutD[11]
-+aoutD[12] aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5]
-+aoutD[6] aoutD[7] aoutD[8] aoutD[9] aoutD[TT] aoutU[10] aoutU[11] aoutU[12]
-+aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6]
-+aoutU[7] aoutU[8] aoutU[9] aoutU[TT] inD[10] inD[11] inD[12] inD[13] inD[14]
-+inD[15] inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22]
-+inD[23] inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30]
-+inD[31] inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5]
-+inD[6] inD[7] inD[8] inD[9] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15]
-+inU[16] inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23]
-+inU[24] inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31]
-+inU[32] inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6]
-+inU[7] inU[8] inU[9] outD[10] outD[11] outD[12] outD[13] outD[14] outD[15]
-+outD[16] outD[17] outD[18] outD[19] outD[1] outD[20] outD[21] outD[22]
-+outD[23] outD[24] outD[25] outD[26] outD[27] outD[28] outD[29] outD[2]
-+outD[30] outD[31] outD[32] outD[33] outD[34] outD[35] outD[36] outD[37]
-+outD[3] outD[4] outD[5] outD[6] outD[7] outD[8] outD[9] outU[10] outU[11]
-+outU[12] outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19]
-+outU[1] outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26]
-+outU[27] outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33]
-+outU[34] outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7]
-+outU[8] outU[9] predD predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] sor[1] succD succU
-XweakStag@18 ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2]
-+ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[TT] net@189[41]
-+net@189[40] net@189[39] net@189[38] net@189[37] net@189[50] net@189[49]
-+net@189[48] net@189[47] net@189[46] net@189[45] net@189[44] net@189[43]
-+net@189[42] net@189[51] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15]
-+inU[16] inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23]
-+inU[24] inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31]
-+inU[32] inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6]
-+inU[7] inU[8] inU[9] net@189[27] net@189[26] net@189[25] net@189[24]
-+net@189[23] net@189[22] net@189[21] net@189[20] net@189[19] net@189[18]
-+net@189[36] net@189[17] net@189[16] net@189[15] net@189[14] net@189[13]
-+net@189[12] net@189[11] net@189[10] net@189[9] net@189[8] net@189[35]
-+net@189[7] net@189[6] net@189[5] net@189[4] net@189[3] net@189[2] net@189[1]
-+net@189[0] net@189[34] net@189[33] net@189[32] net@189[31] net@189[30]
-+net@189[29] net@189[28] predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] net@117[8] net@28 weakStage
-XweakStag@19 net@189[41] net@189[40] net@189[39] net@189[38] net@189[37]
-+net@189[50] net@189[49] net@189[48] net@189[47] net@189[46] net@189[45]
-+net@189[44] net@189[43] net@189[42] net@189[51] net@190[41] net@190[40]
-+net@190[39] net@190[38] net@190[37] net@190[50] net@190[49] net@190[48]
-+net@190[47] net@190[46] net@190[45] net@190[44] net@190[43] net@190[42]
-+net@190[51] net@189[27] net@189[26] net@189[25] net@189[24] net@189[23]
-+net@189[22] net@189[21] net@189[20] net@189[19] net@189[18] net@189[36]
-+net@189[17] net@189[16] net@189[15] net@189[14] net@189[13] net@189[12]
-+net@189[11] net@189[10] net@189[9] net@189[8] net@189[35] net@189[7]
-+net@189[6] net@189[5] net@189[4] net@189[3] net@189[2] net@189[1] net@189[0]
-+net@189[34] net@189[33] net@189[32] net@189[31] net@189[30] net@189[29]
-+net@189[28] net@190[27] net@190[26] net@190[25] net@190[24] net@190[23]
-+net@190[22] net@190[21] net@190[20] net@190[19] net@190[18] net@190[36]
-+net@190[17] net@190[16] net@190[15] net@190[14] net@190[13] net@190[12]
-+net@190[11] net@190[10] net@190[9] net@190[8] net@190[35] net@190[7]
-+net@190[6] net@190[5] net@190[4] net@190[3] net@190[2] net@190[1] net@190[0]
-+net@190[34] net@190[33] net@190[32] net@190[31] net@190[30] net@190[29]
-+net@190[28] net@46 net@120[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@123[8] net@62 weakStage
-XweakStag@20 net@190[41] net@190[40] net@190[39] net@190[38] net@190[37]
-+net@190[50] net@190[49] net@190[48] net@190[47] net@190[46] net@190[45]
-+net@190[44] net@190[43] net@190[42] net@190[51] net@191[41] net@191[40]
-+net@191[39] net@191[38] net@191[37] net@191[50] net@191[49] net@191[48]
-+net@191[47] net@191[46] net@191[45] net@191[44] net@191[43] net@191[42]
-+net@191[51] net@190[27] net@190[26] net@190[25] net@190[24] net@190[23]
-+net@190[22] net@190[21] net@190[20] net@190[19] net@190[18] net@190[36]
-+net@190[17] net@190[16] net@190[15] net@190[14] net@190[13] net@190[12]
-+net@190[11] net@190[10] net@190[9] net@190[8] net@190[35] net@190[7]
-+net@190[6] net@190[5] net@190[4] net@190[3] net@190[2] net@190[1] net@190[0]
-+net@190[34] net@190[33] net@190[32] net@190[31] net@190[30] net@190[29]
-+net@190[28] net@191[27] net@191[26] net@191[25] net@191[24] net@191[23]
-+net@191[22] net@191[21] net@191[20] net@191[19] net@191[18] net@191[36]
-+net@191[17] net@191[16] net@191[15] net@191[14] net@191[13] net@191[12]
-+net@191[11] net@191[10] net@191[9] net@191[8] net@191[35] net@191[7]
-+net@191[6] net@191[5] net@191[4] net@191[3] net@191[2] net@191[1] net@191[0]
-+net@191[34] net@191[33] net@191[32] net@191[31] net@191[30] net@191[29]
-+net@191[28] net@63 net@126[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@129[8] net@64 weakStage
-XweakStag@21 net@191[41] net@191[40] net@191[39] net@191[38] net@191[37]
-+net@191[50] net@191[49] net@191[48] net@191[47] net@191[46] net@191[45]
-+net@191[44] net@191[43] net@191[42] net@191[51] aoutU[10] aoutU[11] aoutU[12]
-+aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6]
-+aoutU[7] aoutU[8] aoutU[9] aoutU[TT] net@191[27] net@191[26] net@191[25]
-+net@191[24] net@191[23] net@191[22] net@191[21] net@191[20] net@191[19]
-+net@191[18] net@191[36] net@191[17] net@191[16] net@191[15] net@191[14]
-+net@191[13] net@191[12] net@191[11] net@191[10] net@191[9] net@191[8]
-+net@191[35] net@191[7] net@191[6] net@191[5] net@191[4] net@191[3] net@191[2]
-+net@191[1] net@191[0] net@191[34] net@191[33] net@191[32] net@191[31]
-+net@191[30] net@191[29] net@191[28] outU[10] outU[11] outU[12] outU[13]
-+outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] outU[1] outU[20]
-+outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] outU[27] outU[28]
-+outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] outU[34] outU[35]
-+outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] outU[8] outU[9]
-+net@65 net@132[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+net@135[8] succU weakStage
-XweakStag@22 net@192[41] net@192[40] net@192[39] net@192[38] net@192[37]
-+net@192[50] net@192[49] net@192[48] net@192[47] net@192[46] net@192[45]
-+net@192[44] net@192[43] net@192[42] net@192[51] aoutD[10] aoutD[11] aoutD[12]
-+aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5] aoutD[6]
-+aoutD[7] aoutD[8] aoutD[9] aoutD[TT] net@192[27] net@192[26] net@192[25]
-+net@192[24] net@192[23] net@192[22] net@192[21] net@192[20] net@192[19]
-+net@192[18] net@192[36] net@192[17] net@192[16] net@192[15] net@192[14]
-+net@192[13] net@192[12] net@192[11] net@192[10] net@192[9] net@192[8]
-+net@192[35] net@192[7] net@192[6] net@192[5] net@192[4] net@192[3] net@192[2]
-+net@192[1] net@192[0] net@192[34] net@192[33] net@192[32] net@192[31]
-+net@192[30] net@192[29] net@192[28] outD[10] outD[11] outD[12] outD[13]
-+outD[14] outD[15] outD[16] outD[17] outD[18] outD[19] outD[1] outD[20]
-+outD[21] outD[22] outD[23] outD[24] outD[25] outD[26] outD[27] outD[28]
-+outD[29] outD[2] outD[30] outD[31] outD[32] outD[33] outD[34] outD[35]
-+outD[36] outD[37] outD[3] outD[4] outD[5] outD[6] outD[7] outD[8] outD[9]
-+net@50 net@117[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+net@120[8] succD weakStage
-XweakStag@23 net@193[41] net@193[40] net@193[39] net@193[38] net@193[37]
-+net@193[50] net@193[49] net@193[48] net@193[47] net@193[46] net@193[45]
-+net@193[44] net@193[43] net@193[42] net@193[51] net@192[41] net@192[40]
-+net@192[39] net@192[38] net@192[37] net@192[50] net@192[49] net@192[48]
-+net@192[47] net@192[46] net@192[45] net@192[44] net@192[43] net@192[42]
-+net@192[51] net@193[27] net@193[26] net@193[25] net@193[24] net@193[23]
-+net@193[22] net@193[21] net@193[20] net@193[19] net@193[18] net@193[36]
-+net@193[17] net@193[16] net@193[15] net@193[14] net@193[13] net@193[12]
-+net@193[11] net@193[10] net@193[9] net@193[8] net@193[35] net@193[7]
-+net@193[6] net@193[5] net@193[4] net@193[3] net@193[2] net@193[1] net@193[0]
-+net@193[34] net@193[33] net@193[32] net@193[31] net@193[30] net@193[29]
-+net@193[28] net@192[27] net@192[26] net@192[25] net@192[24] net@192[23]
-+net@192[22] net@192[21] net@192[20] net@192[19] net@192[18] net@192[36]
-+net@192[17] net@192[16] net@192[15] net@192[14] net@192[13] net@192[12]
-+net@192[11] net@192[10] net@192[9] net@192[8] net@192[35] net@192[7]
-+net@192[6] net@192[5] net@192[4] net@192[3] net@192[2] net@192[1] net@192[0]
-+net@192[34] net@192[33] net@192[32] net@192[31] net@192[30] net@192[29]
-+net@192[28] net@44 net@123[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@126[8] net@51 weakStage
-XweakStag@24 net@194[41] net@194[40] net@194[39] net@194[38] net@194[37]
-+net@194[50] net@194[49] net@194[48] net@194[47] net@194[46] net@194[45]
-+net@194[44] net@194[43] net@194[42] net@194[51] net@193[41] net@193[40]
-+net@193[39] net@193[38] net@193[37] net@193[50] net@193[49] net@193[48]
-+net@193[47] net@193[46] net@193[45] net@193[44] net@193[43] net@193[42]
-+net@193[51] net@194[27] net@194[26] net@194[25] net@194[24] net@194[23]
-+net@194[22] net@194[21] net@194[20] net@194[19] net@194[18] net@194[36]
-+net@194[17] net@194[16] net@194[15] net@194[14] net@194[13] net@194[12]
-+net@194[11] net@194[10] net@194[9] net@194[8] net@194[35] net@194[7]
-+net@194[6] net@194[5] net@194[4] net@194[3] net@194[2] net@194[1] net@194[0]
-+net@194[34] net@194[33] net@194[32] net@194[31] net@194[30] net@194[29]
-+net@194[28] net@193[27] net@193[26] net@193[25] net@193[24] net@193[23]
-+net@193[22] net@193[21] net@193[20] net@193[19] net@193[18] net@193[36]
-+net@193[17] net@193[16] net@193[15] net@193[14] net@193[13] net@193[12]
-+net@193[11] net@193[10] net@193[9] net@193[8] net@193[35] net@193[7]
-+net@193[6] net@193[5] net@193[4] net@193[3] net@193[2] net@193[1] net@193[0]
-+net@193[34] net@193[33] net@193[32] net@193[31] net@193[30] net@193[29]
-+net@193[28] net@52 net@129[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@132[8] net@43 weakStage
-XweakStag@25 ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] ainD[2]
-+ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[TT] net@194[41]
-+net@194[40] net@194[39] net@194[38] net@194[37] net@194[50] net@194[49]
-+net@194[48] net@194[47] net@194[46] net@194[45] net@194[44] net@194[43]
-+net@194[42] net@194[51] inD[10] inD[11] inD[12] inD[13] inD[14] inD[15]
-+inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] inD[23]
-+inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] inD[31]
-+inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] inD[6]
-+inD[7] inD[8] inD[9] net@194[27] net@194[26] net@194[25] net@194[24]
-+net@194[23] net@194[22] net@194[21] net@194[20] net@194[19] net@194[18]
-+net@194[36] net@194[17] net@194[16] net@194[15] net@194[14] net@194[13]
-+net@194[12] net@194[11] net@194[10] net@194[9] net@194[8] net@194[35]
-+net@194[7] net@194[6] net@194[5] net@194[4] net@194[3] net@194[2] net@194[1]
-+net@194[0] net@194[34] net@194[33] net@194[32] net@194[31] net@194[30]
-+net@194[29] net@194[28] predD net@135[8] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] sor[1] net@53 weakStage
-Xwire90@1 net@44 net@43 wire90-1243_9-layer_1-width_3
-Xwire90@2 net@28 net@46 wire90-1185_9-layer_1-width_3
-Xwire90@3 net@62 net@63 wire90-1185_9-layer_1-width_3
-Xwire90@4 net@64 net@65 wire90-1185_9-layer_1-width_3
-Xwire90@5 net@50 net@51 wire90-1249_9-layer_1-width_3
-Xwire90@6 net@52 net@53 wire90-1249_9-layer_1-width_3
-.ENDS upDown8weak
+*** CELL: loopCountM:olcWcont{sch}
+.SUBCKT olcWcont Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set]
++ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sin
++sout
+Xolc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2]
++inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo] olc
+XolcContr@0 Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] ilc[load]
++mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3] olcControl
+XscanEx3h@1 bitt[1] bitt[3] bitt[5] mc p1p p2p rd sin net@46 scanEx3h
+XscanEx3h@2 bitt[2] bitt[4] bitt[6] mc p1p p2p rd net@46 net@48 scanEx3h
+XscanEx3h@3 s[3] s[2] s[1] mc p1p p2p rd net@48 sout scanEx3h
+Xwire90@1 olc[zero] wire90@1_b wire90-1022_9-layer_1-width_3
+Xwire90@2 olc[zoo] wire90@2_b wire90-810_8-layer_1-width_3
+Xwire90@3 olc[load] wire90@3_b wire90-4437_9-layer_1-width_3
+Xwire90@4 olc[dec] wire90@4_b wire90-3501_1-layer_1-width_3
+Xwire90@5 wire90@5_a bitt[4] wire90-1686-layer_1-width_3
+Xwire90@6 wire90@6_a bitt[5] wire90-1399-layer_1-width_3
+Xwire90@7 wire90@7_a bitt[6] wire90-1408_5-layer_1-width_3
+Xwire90@8 wire90@8_a bitt[1] wire90-1686-layer_1-width_3
+Xwire90@9 wire90@9_a bitt[2] wire90-1925_2-layer_1-width_3
+Xwire90@10 wire90@10_a bitt[3] wire90-1638_1-layer_1-width_3
+.ENDS olcWcont
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3750-R_34_667m a b
+Ccap@0 gnd net@14 13.75f
+Ccap@1 gnd net@8 13.75f
+Ccap@2 gnd net@11 13.75f
+Rres@0 net@14 a 21.667
+Rres@1 net@11 net@14 43.333
+Rres@2 b net@8 21.667
+Rres@3 net@8 net@11 43.333
+.ENDS wire-C_0_011f-3750-R_34_667m
-*** CELL: stageGroupsM:northFifo{sch}
-.SUBCKT northFifo ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2]
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11]
-+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6]
-+aout[7] aout[8] aout[9] aout[TT] fin fout in[10] in[11] in[12] in[13] in[14]
-+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24]
-+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34]
-+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10]
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19]
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27]
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35]
-+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
-+sic[2] sic[3] sic[4] sic[5] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5]
-+sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[8] sir[9]
-+succ
-XfillDrai@1 net@256[41] net@256[40] net@256[39] net@256[38] net@256[37]
-+net@256[50] net@256[49] net@256[48] net@256[47] net@256[46] net@256[45]
-+net@256[44] net@256[43] net@256[42] net@256[51] net@259[41] net@259[40]
-+net@259[39] net@259[38] net@259[37] net@259[50] net@259[49] net@259[48]
-+net@259[47] net@259[46] net@259[45] net@259[44] net@259[43] net@259[42]
-+net@259[51] fin fout net@256[27] net@256[26] net@256[25] net@256[24]
-+net@256[23] net@256[22] net@256[21] net@256[20] net@256[19] net@256[18]
-+net@256[36] net@256[17] net@256[16] net@256[15] net@256[14] net@256[13]
-+net@256[12] net@256[11] net@256[10] net@256[9] net@256[8] net@256[35]
-+net@256[7] net@256[6] net@256[5] net@256[4] net@256[3] net@256[2] net@256[1]
-+net@256[0] net@256[34] net@256[33] net@256[32] net@256[31] net@256[30]
-+net@256[29] net@256[28] net@259[27] net@259[26] net@259[25] net@259[24]
-+net@259[23] net@259[22] net@259[21] net@259[20] net@259[19] net@259[18]
-+net@259[36] net@259[17] net@259[16] net@259[15] net@259[14] net@259[13]
-+net@259[12] net@259[11] net@259[10] net@259[9] net@259[8] net@259[35]
-+net@259[7] net@259[6] net@259[5] net@259[4] net@259[3] net@259[2] net@259[1]
-+net@259[0] net@259[34] net@259[33] net@259[32] net@259[31] net@259[30]
-+net@259[29] net@259[28] net@263 sic[1] sic[2] sic[3] sic[4] sic[5] sic[3]
-+sic[2] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8]
-+sid[9] net@254[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] sir[9]
-+sic[8] sid[8] sid[7] sid[6] net@235[5] net@235[4] sir[8] net@267
-+fillDrainCount
-XscanCap@5 sid[8] sid[7] sid[6] net@235[5] net@235[4] sid[9] scanCap
-XscanCap@6 sic[8] sic[2] sic[3] sic[4] sic[5] sic[9] scanCap
-XscanCap@7 sir[8] sir[2] sir[3] sir[4] sir[5] sir[9] scanCap
-XupDown8w@2 net@259[41] net@259[40] net@259[39] net@259[38] net@259[37]
-+net@259[50] net@259[49] net@259[48] net@259[47] net@259[46] net@259[45]
-+net@259[44] net@259[43] net@259[42] net@259[51] ain[10] ain[11] ain[12]
-+ain[13] ain[14] ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] ain[8]
-+ain[9] ain[TT] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] net@256[41]
-+net@256[40] net@256[39] net@256[38] net@256[37] net@256[50] net@256[49]
-+net@256[48] net@256[47] net@256[46] net@256[45] net@256[44] net@256[43]
-+net@256[42] net@256[51] net@259[27] net@259[26] net@259[25] net@259[24]
-+net@259[23] net@259[22] net@259[21] net@259[20] net@259[19] net@259[18]
-+net@259[36] net@259[17] net@259[16] net@259[15] net@259[14] net@259[13]
-+net@259[12] net@259[11] net@259[10] net@259[9] net@259[8] net@259[35]
-+net@259[7] net@259[6] net@259[5] net@259[4] net@259[3] net@259[2] net@259[1]
-+net@259[0] net@259[34] net@259[33] net@259[32] net@259[31] net@259[30]
-+net@259[29] net@259[28] in[10] in[11] in[12] in[13] in[14] in[15] in[16]
-+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26]
-+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36]
-+in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12]
-+out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20]
-+out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29]
-+out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3]
-+out[4] out[5] out[6] out[7] out[8] out[9] net@256[27] net@256[26] net@256[25]
-+net@256[24] net@256[23] net@256[22] net@256[21] net@256[20] net@256[19]
-+net@256[18] net@256[36] net@256[17] net@256[16] net@256[15] net@256[14]
-+net@256[13] net@256[12] net@256[11] net@256[10] net@256[9] net@256[8]
-+net@256[35] net@256[7] net@256[6] net@256[5] net@256[4] net@256[3] net@256[2]
-+net@256[1] net@256[0] net@256[34] net@256[33] net@256[32] net@256[31]
-+net@256[30] net@256[29] net@256[28] net@229 pred sir[1] sir[2] sir[3] sir[4]
-+sir[5] sir[3] sir[2] sir[8] sir[9] net@254[8] succ net@264 upDown8weak
-Xwire90@6 net@229 net@267 wire90-1185_9-layer_1-width_3
-Xwire90@18 net@264 net@263 wire90-1185_9-layer_1-width_3
-.ENDS northFifo
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3750-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3750-R_34_667m
+.ENDS wire90-3750-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3560-R_34_667m a b
+Ccap@0 gnd net@14 13.053f
+Ccap@1 gnd net@8 13.053f
+Ccap@2 gnd net@11 13.053f
+Rres@0 net@14 a 20.569
+Rres@1 net@11 net@14 41.138
+Rres@2 b net@8 20.569
+Rres@3 net@8 net@11 41.138
+.ENDS wire-C_0_011f-3560-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3560-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3560-R_34_667m
+.ENDS wire90-3560-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3611-R_34_667m a b
+Ccap@0 gnd net@14 13.24f
+Ccap@1 gnd net@8 13.24f
+Ccap@2 gnd net@11 13.24f
+Rres@0 net@14 a 20.864
+Rres@1 net@11 net@14 41.727
+Rres@2 b net@8 20.864
+Rres@3 net@8 net@11 41.727
+.ENDS wire-C_0_011f-3611-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3611-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3611-R_34_667m
+.ENDS wire90-3611-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1850-R_34_667m a b
+Ccap@0 gnd net@14 6.783f
+Ccap@1 gnd net@8 6.783f
+Ccap@2 gnd net@11 6.783f
+Rres@0 net@14 a 10.689
+Rres@1 net@11 net@14 21.378
+Rres@2 b net@8 10.689
+Rres@3 net@8 net@11 21.378
+.ENDS wire-C_0_011f-1850-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1850-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1850-R_34_667m
+.ENDS wire90-1850-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1852-R_34_667m a b
+Ccap@0 gnd net@14 6.791f
+Ccap@1 gnd net@8 6.791f
+Ccap@2 gnd net@11 6.791f
+Rres@0 net@14 a 10.7
+Rres@1 net@11 net@14 21.401
+Rres@2 b net@8 10.7
+Rres@3 net@8 net@11 21.401
+.ENDS wire-C_0_011f-1852-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1852-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1852-R_34_667m
+.ENDS wire90-1852-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-867_8-R_34_667m a b
+Ccap@0 gnd net@14 3.182f
+Ccap@1 gnd net@8 3.182f
+Ccap@2 gnd net@11 3.182f
+Rres@0 net@14 a 5.014
+Rres@1 net@11 net@14 10.028
+Rres@2 b net@8 5.014
+Rres@3 net@8 net@11 10.028
+.ENDS wire-C_0_011f-867_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-867_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-867_8-R_34_667m
+.ENDS wire90-867_8-layer_1-width_3
+
+*** CELL: stagesM:outDockCenter{sch}
+.SUBCKT outDockCenter bit[Di] bit[Do] bit[Ti] do[Lt] epi[torp] fire[M]
++fire[do] flag[A][clr] flag[A][set] flag[C][T] flag[D][clr] flag[D][set]
++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] m1[10] m1[11] m1[12]
++m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F]
++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p
++pred[D] pred[T] ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv]
++sel[Tp] sel[rD] sin sout succ[sf]
+Xflags@0 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T]
++m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc
++flags
+XilcMoveO@0 bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M]
++flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6]
++inLO[8] mc p1p p2p pred[D] pred[T] rd net@249 sout succ[sf] ilcMoveOut
+XohPredAl@0 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr]
++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F]
++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p
++ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD]
++net@244 net@249 ohPredAll
+XolcWcont@0 sel[rD] do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] net@165
++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sin net@244
++olcWcont
+Xwire90@5 wire90@5_a flag[A][set] wire90-3750-layer_1-width_3
+Xwire90@6 wire90@6_a flag[A][clr] wire90-3560-layer_1-width_3
+Xwire90@7 wire90@7_a flag[B][set] wire90-3750-layer_1-width_3
+Xwire90@8 wire90@8_a flag[B][clr] wire90-3611-layer_1-width_3
+Xwire90@9 wire90@9_a flag[D][set] wire90-1850-layer_1-width_3
+Xwire90@10 wire90@10_a flag[D][clr] wire90-1852-layer_1-width_3
+Xwire90@24 net@165 ilc[load] wire90-867_8-layer_1-width_3
+.ENDS outDockCenter
+
+*** CELL: stagesM:outDockPredStage{sch}
+.SUBCKT outDockPredStage do[Lt] epi[torp] fire[M] flag[A][clr] flag[A][set]
++flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
++inLO[6] inLO[8] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
++m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
++m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
++m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
++m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12]
++ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22]
++ps[23] ps[24] ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32]
++ps[33] ps[34] ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do]
++ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
++sor[1] succ[sf] take[ps]
+XdockPSre@0 net@39 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
++m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
++m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
++m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
++inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17]
++ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27]
++ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3]
++ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[ps] dockPSreg
+XoutDockC@0 ps[18] ps[16] ps[19] do[Lt] epi[torp] fire[M] net@6 flag[A][clr]
++flag[A][set] flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3]
++inLO[4] inLO[5] inLO[6] inLO[8] m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4]
++m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
++m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] sir[3] sir[2] pred[D] pred[T]
++ps[do] ps[skip] sir[5] m1[24] m1[22] m1[23] m1[27] m1[25] m1[26] m1[21]
++sir[1] sor[1] succ[sf] outDockCenter
+Xwire90@0 net@6 net@39 wire90-791_7-layer_1-width_3
+.ENDS outDockPredStage
+
+*** CELL: stageGroupsM:outM1PredLit{sch}
+.SUBCKT outM1PredLit dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17]
++dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27]
++dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37]
++dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11] dsA[12]
++dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7] dsA[8]
++dsA[9] dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16]
++dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24]
++dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32]
++dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7]
++dsD[8] dsD[9] epi[torp] flag[A][clr] flag[A][set] flag[C][T] flag[D][clr]
++flag[D][set] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18]
++m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28]
++m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4]
++m1[5] m1[6] m1[7] m1[8] m1[9] pred[D] pred[R] pred[T] ps[do] ps[skip]
++ring[10] ring[11] ring[12] ring[13] ring[14] ring[15] ring[16] ring[17]
++ring[18] ring[19] ring[1] ring[20] ring[21] ring[22] ring[23] ring[24]
++ring[25] ring[26] ring[27] ring[28] ring[29] ring[2] ring[30] ring[31]
++ring[32] ring[33] ring[34] ring[35] ring[36] ring[3] ring[4] ring[5] ring[6]
++ring[7] ring[8] ring[9] signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3]
++sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] succ[m1]
+XlitDockS@0 dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3]
++dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9] dsA[TT] net@45 dp[10] dp[11] dp[12]
++dp[13] dp[14] dp[15] dp[16] dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22]
++dp[23] dp[24] dp[25] dp[26] dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32]
++dp[33] dp[34] dp[35] dp[36] dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9]
++dp[B] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16] dsD[17] dsD[18]
++dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] dsD[25] dsD[26]
++dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] dsD[33] dsD[34]
++dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] dsD[8] dsD[9]
++net@44 sourceOfFlagC inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[7]
++ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1]
++ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ready
++signalBitFromInboundSwitchFabric net@48[8] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] litDockStage
+XmOneDock@0 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18]
++m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28]
++m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4]
++m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
++m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[R] ring[10] ring[11] ring[12]
++ring[13] ring[14] ring[15] ring[16] ring[17] ring[18] ring[19] ring[1]
++ring[20] ring[21] ring[22] ring[23] ring[24] ring[25] ring[26] ring[27]
++ring[28] ring[29] ring[2] ring[30] ring[31] ring[32] ring[33] ring[34]
++ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9]
++sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@47[8]
++succ[m1] take[m1] mOneDockStage
+XoutDockP@0 net@45 epi[torp] net@44 flag[A][clr] flag[A][set] flag[C][T]
++flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6]
++inLO[7] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19]
++m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29]
++m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5]
++m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T]
++m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T]
++m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14]
++ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24]
++ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34]
++ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip]
++net@47[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@48[8]
++succ[D] take[ps] outDockPredStage
+.ENDS outM1PredLit
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-10-R_34_667m a b
+Ccap@0 gnd net@14 0.0367f
+Ccap@1 gnd net@8 0.0367f
+Ccap@2 gnd net@11 0.0367f
+Rres@0 net@14 a 57.778m
+Rres@1 net@11 net@14 0.116
+Rres@2 b net@8 57.778m
+Rres@3 net@8 net@11 0.116
+.ENDS wire-C_0_011f-10-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-10-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-10-R_34_667m
+.ENDS wire90-10-layer_1-width_3
+
+*** CELL: dockM:outputDock{sch}
+.SUBCKT outputDock do[epi] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16]
++dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26]
++dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36]
++dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11]
++dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7]
++dsA[8] dsA[9] dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16]
++dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24]
++dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32]
++dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7]
++dsD[8] dsD[9] fout in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27]
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3]
++in[4] in[5] in[6] in[7] in[8] in[9] in[T] pred[D] pred[T]
++signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
++sir[7] sir[8] sir[9] sor[1] succ[D] succ[T]
+XdockWagN@0 net@26[26] net@26[25] net@26[24] net@26[23] net@26[22] net@26[21]
++net@26[20] net@26[19] net@26[18] net@26[17] net@26[35] net@26[16] net@26[15]
++net@26[14] net@26[13] net@26[12] net@26[11] net@26[10] net@26[9] net@26[8]
++net@26[7] net@26[34] net@26[6] net@26[5] net@26[4] net@26[3] net@26[2]
++net@26[1] net@26[0] net@26[33] net@26[32] net@26[31] net@26[30] net@26[29]
++net@26[28] net@26[27] net@57[26] net@57[25] net@57[24] net@57[23] net@57[22]
++net@57[21] net@57[20] net@57[19] net@57[18] net@57[17] net@57[35] net@57[16]
++net@57[15] net@57[14] net@57[13] net@57[12] net@57[11] net@57[10] net@57[9]
++net@57[8] net@57[7] net@57[34] net@57[6] net@57[5] net@57[4] net@57[3]
++net@57[2] net@57[1] net@57[0] net@57[33] net@57[32] net@57[31] net@57[30]
++net@57[29] net@57[28] net@57[27] net@15 net@75[8] sir[2] sir[3] sir[4] sir[5]
++sir[6] sir[7] sir[8] sir[9] net@76[8] net@85 take[1] take[2] take[3] fout
++take[5] take[6] dockWagNine
+XepiRQod@1 do[epi] net@89 net@82 flag[A][clr] flag[A][set] flag[D][clr]
++flag[D][set] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28]
++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4]
++in[5] in[6] in[7] in[8] in[9] in[T] net@68[26] net@68[25] net@68[24]
++net@68[23] net@68[22] net@68[21] net@68[20] net@68[19] net@68[18] net@68[17]
++net@68[35] net@68[16] net@68[15] net@68[14] net@68[13] net@68[12] net@68[11]
++net@68[10] net@68[9] net@68[8] net@68[7] net@68[34] net@68[6] net@68[5]
++net@68[4] net@68[3] net@68[2] net@68[1] net@68[0] net@68[33] net@68[32]
++net@68[31] net@68[30] net@68[29] net@68[28] net@68[27] ps[do] ps[skip]
++net@26[26] net@26[25] net@26[24] net@26[23] net@26[22] net@26[21] net@26[20]
++net@26[19] net@26[18] net@26[17] net@26[35] net@26[16] net@26[15] net@26[14]
++net@26[13] net@26[12] net@26[11] net@26[10] net@26[9] net@26[8] net@26[7]
++net@26[34] net@26[6] net@26[5] net@26[4] net@26[3] net@26[2] net@26[1]
++net@26[0] net@26[33] net@26[32] net@26[31] net@26[30] net@26[29] net@26[28]
++net@26[27] net@90 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
++sir[9] net@75[8] epiRQod
+XoutM1Pre@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
++dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28]
++dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3]
++dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11] dsA[12] dsA[13]
++dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9]
++dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16] dsD[17]
++dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] dsD[25]
++dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] dsD[33]
++dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] dsD[8]
++dsD[9] torp flag[A][clr] flag[A][set] outM1Pre@0_flag[C][T] flag[D][clr]
++flag[D][set] net@68[26] net@68[25] net@68[24] net@68[23] net@68[22]
++net@68[21] net@68[20] net@68[19] net@68[18] net@68[17] net@68[35] net@68[16]
++net@68[15] net@68[14] net@68[13] net@68[12] net@68[11] net@68[10] net@68[9]
++net@68[8] net@68[7] net@68[34] net@68[6] net@68[5] net@68[4] net@68[3]
++net@68[2] net@68[1] net@68[0] net@68[33] net@68[32] net@68[31] net@68[30]
++net@68[29] net@68[28] net@68[27] pred[D] net@84 pred[T] ps[do] ps[skip]
++net@57[26] net@57[25] net@57[24] net@57[23] net@57[22] net@57[21] net@57[20]
++net@57[19] net@57[18] net@57[17] net@57[35] net@57[16] net@57[15] net@57[14]
++net@57[13] net@57[12] net@57[11] net@57[10] net@57[9] net@57[8] net@57[7]
++net@57[34] net@57[6] net@57[5] net@57[4] net@57[3] net@57[2] net@57[1]
++net@57[0] net@57[33] net@57[32] net@57[31] net@57[30] net@57[29] net@57[28]
++net@57[27] signalBitFromInboundSwitchFabric net@76[8] sir[2] sir[3] sir[4]
++sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] net@88 outM1PredLit
+Xwire90@1 net@84 net@85 wire90-10-layer_1-width_3
+Xwire90@2 torp net@82 wire90-10-layer_1-width_3
+Xwire90@3 net@89 net@88 wire90-10-layer_1-width_3
+Xwire90@4 net@15 net@90 wire90-10-layer_1-width_3
+.ENDS outputDock
*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-476_7-R_34_667m a b
.global gnd vdd
-*** TOP LEVEL CELL: marina{sch}
-XinputDoc@1 doutA[10] doutA[11] doutA[12] doutA[13] doutA[14] doutA[1]
-+doutA[2] doutA[3] doutA[4] doutA[5] doutA[6] doutA[7] doutA[8] doutA[9]
-+doutA[TT] net@43 din[10] din[11] din[12] din[13] din[14] din[15] din[16]
+*** TOP LEVEL CELL: marinaOut{sch}
+XnorthFif@1 dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3]
++dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9] dsA[TT] ain[10] ain[11] ain[12]
++ain[13] ain[14] ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] ain[8]
++ain[9] ain[T] net@38 fout dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15]
++dsD[16] dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23]
++dsD[24] dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31]
++dsD[32] dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6]
++dsD[7] dsD[8] dsD[9] din[10] din[11] din[12] din[13] din[14] din[15] din[16]
++din[17] din[18] din[19] din[1] din[20] din[21] din[22] din[23] din[24]
++din[25] din[26] din[27] din[28] din[29] din[2] din[30] din[31] din[32]
++din[33] din[34] din[35] din[36] din[37] din[3] din[4] din[5] din[6] din[7]
++din[8] din[9] ddo[D] net@116[8] sic[2] sic[3] sic[4] sic[5] sic[8] sic[9]
++net@117[8] net@117[7] net@117[6] net@117[5] net@117[4] sid[6] sid[7] sid[8]
++sid[9] net@109[8] sir[2] sir[3] sir[4] sir[5] sir[8] sir[9] doo[D] northFifo
+XoutputDo@0 net@14 din[10] din[11] din[12] din[13] din[14] din[15] din[16]
+din[17] din[18] din[19] din[1] din[20] din[21] din[22] din[23] din[24]
+din[25] din[26] din[27] din[28] din[29] din[2] din[30] din[31] din[32]
+din[33] din[34] din[35] din[36] din[37] din[3] din[4] din[5] din[6] din[7]
-+din[8] din[9] ain[6] iout[10] iout[11] iout[12] iout[13] iout[14] iout[15]
-+iout[16] iout[17] iout[18] iout[19] iout[1] iout[20] iout[21] iout[22]
-+iout[23] iout[24] iout[25] iout[26] iout[27] iout[28] iout[29] iout[2]
-+iout[30] iout[31] iout[32] iout[33] iout[34] iout[35] iout[36] iout[3]
-+iout[4] iout[5] iout[6] iout[7] iout[8] iout[9] aout[T] doutD[10] doutD[11]
-+doutD[12] doutD[13] doutD[14] doutD[15] doutD[16] doutD[17] doutD[18]
-+doutD[19] doutD[1] doutD[20] doutD[21] doutD[22] doutD[23] doutD[24]
-+doutD[25] doutD[26] doutD[27] doutD[28] doutD[29] doutD[2] doutD[30]
-+doutD[31] doutD[32] doutD[33] doutD[34] doutD[35] doutD[36] doutD[37]
-+doutD[3] doutD[4] doutD[5] doutD[6] doutD[7] doutD[8] doutD[9] net@14 doo[T]
-+doo[D] ain[14] net@107[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8]
-+sir[9] net@108[8] ddo[T] ddo[D] inputDock
-XnorthFif@1 doutA[10] doutA[11] doutA[12] doutA[13] doutA[14] doutA[1]
-+doutA[2] doutA[3] doutA[4] doutA[5] doutA[6] doutA[7] doutA[8] doutA[9]
-+doutA[TT] ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] ain[4]
-+ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] net@38 fout doutD[10] doutD[11]
-+doutD[12] doutD[13] doutD[14] doutD[15] doutD[16] doutD[17] doutD[18]
-+doutD[19] doutD[1] doutD[20] doutD[21] doutD[22] doutD[23] doutD[24]
-+doutD[25] doutD[26] doutD[27] doutD[28] doutD[29] doutD[2] doutD[30]
-+doutD[31] doutD[32] doutD[33] doutD[34] doutD[35] doutD[36] doutD[37]
-+doutD[3] doutD[4] doutD[5] doutD[6] doutD[7] doutD[8] doutD[9] din[10]
-+din[11] din[12] din[13] din[14] din[15] din[16] din[17] din[18] din[19]
-+din[1] din[20] din[21] din[22] din[23] din[24] din[25] din[26] din[27]
-+din[28] din[29] din[2] din[30] din[31] din[32] din[33] din[34] din[35]
-+din[36] din[37] din[3] din[4] din[5] din[6] din[7] din[8] din[9] ddo[D]
-+net@116[8] sic[2] sic[3] sic[4] sic[5] sic[8] sic[9] net@117[8] net@117[7]
-+net@117[6] net@117[5] net@117[4] sid[6] sid[7] sid[8] sid[9] net@109[8]
-+sir[2] sir[3] sir[4] sir[5] sir[8] sir[9] doo[D] northFifo
++din[8] din[9] ain[6] dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2]
++dsA[3] dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9] dsA[TT] dsD[10] dsD[11]
++dsD[12] dsD[13] dsD[14] dsD[15] dsD[16] dsD[17] dsD[18] dsD[19] dsD[1]
++dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] dsD[25] dsD[26] dsD[27] dsD[28]
++dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] dsD[33] dsD[34] dsD[35] dsD[36]
++dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] dsD[8] dsD[9] net@44 iout[10]
++iout[11] iout[12] iout[13] iout[14] iout[15] iout[16] iout[17] iout[18]
++iout[19] iout[1] iout[20] iout[21] iout[22] iout[23] iout[24] iout[25]
++iout[26] iout[27] iout[28] iout[29] iout[2] iout[30] iout[31] iout[32]
++iout[33] iout[34] iout[35] iout[36] iout[3] iout[4] iout[5] iout[6] iout[7]
++iout[8] iout[9] aout[T] doo[T] doo[D] ain[14] net@119[8] sir[2] sir[3] sir[4]
++sir[5] sir[3] sir[2] sir[8] sir[9] net@120[8] ddo[T] ddo[D] outputDock
XsouthFif@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
-+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@43 fin
++aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@44 fin
+net@38 iout[10] iout[11] iout[12] iout[13] iout[14] iout[15] iout[16]
+iout[17] iout[18] iout[19] iout[1] iout[20] iout[21] iout[22] iout[23]
+iout[24] iout[25] iout[26] iout[27] iout[28] iout[29] iout[2] iout[30]
+sic[5] sic[3] sic[2] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
+sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8]
+sir[9] net@116[8] net@117[8] net@117[7] net@117[6] net@117[5] net@117[4]
-+net@107[8] net@14 southFifo
-XtokenFIF@0 ddo[T] net@108[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2]
++net@119[8] net@14 southFifo
+XtokenFIF@0 ddo[T] net@120[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2]
+sir[8] sir[9] net@109[8] doo[T] tokenFIFO
.END
projects / fleet.git / commitdiff