== FleetSim ==============================================================
== FPGA ==============================================================
- reg have_in1;
- reg [(`DATAWIDTH-1):0] reg_in1;
- reg have_in2;
- reg [(`DATAWIDTH-1):0] reg_in2;
- reg have_in3;
- reg [(`DATAWIDTH-1):0] reg_in3;
- reg have_inLut;
- reg [(`DATAWIDTH-1):0] reg_inLut;
+ wire [7:0] lut;
- wire [(`DATAWIDTH-1):0] out;
genvar i;
generate
for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
- assign out[i] = reg_inLut[{reg_in3[i], reg_in2[i], reg_in1[i]}];
+ assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}];
end
endgenerate
+ assign lut = inLut_d[7:0];
+
always @(posedge clk) begin
if (!rst) begin
- have_in1 = 0;
- have_in2 = 0;
- have_in3 = 0;
- have_inLut = 0;
`reset
end else begin
- if (!have_in1) begin
- `onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
- end else
- if (!have_in2) begin
- `onread(in2_r, in2_a) have_in2 = 1; reg_in2 = in2_d; end
- end else
- if (!have_in3) begin
- `onread(in3_r, in3_a) have_in3 = 1; reg_in3 = in3_d; end
- end else
- if (!have_inLut) begin
- `onread(inLut_r, inLut_a) have_inLut = 1; reg_inLut = inLut_d; end
- end else
-
- if (have_in1 && have_in2 && have_in3 && have_inLut) begin
- out_d = out;
- `onwrite(out_r, out_a)
- have_in1 = 0;
- have_in2 = 0;
- have_in3 = 0;
- have_inLut = 0;
+ if (!in1_r && in1_a) in1_a <= 0;
+ if (!in2_r && in2_a) in2_a <= 0;
+ if (!in3_r && in3_a) in3_a <= 0;
+ if (!inLut_r && inLut_a) inLut_a <= 0;
+ if (out_r && out_a) begin
+ in1_a <= 1;
+ in2_a <= 1;
+ in3_a <= 1;
+ inLut_a <= 1;
+ out_r <= 0;
+ end
+ if (in1_r && !in1_a && in2_r && !in2_a && in3_r && !in3_a && inLut_r && !inLut_a && !out_r && !out_a) begin
+ out_r <= 1;
end
- end
end
end
[*] deliver;
alu.inOp:
literal Alu2.inOp[ADD];
- load repeat counter with 63;
- deliver;
- load repeat counter with 63;
- deliver;
- load repeat counter with 63;
- deliver;
- load repeat counter with 63;
- deliver;
- load repeat counter with 3;
- deliver;
+ [*] deliver;
alu.in1:
literal 0;
deliver;
[L] sendto alu.in1;
tail;
-// acks from debug ship trigger new truth tables
-debug.in:
- [*] take, deliver, notify alu.out;
-
lut.inLut:
literal 0;
deliver;
[*] take, deliver;
+// acks from debug ship trigger new truth tables
+debug.in:
+ load repeat counter with 63;
+ take, deliver, notify alu.out;
+ load repeat counter with 63;
+ take, deliver, notify alu.out;
+ load repeat counter with 63;
+ take, deliver, notify alu.out;
+ load repeat counter with 63;
+ take, deliver, notify alu.out;
+ load repeat counter with 4;
+ take, deliver, notify alu.out;