tweak Verilog logic

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index 9ad420d..0cbe193 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -464,7 +464,7 @@ public class Verilog {
                 if (driver != null) {
                     sb.append("assign " + name +"_r = " + driver.name + "_r;\n");
                     sb.append("assign " + driver.name +"_a = " + name + "_a;\n");
-                    if (width>0 && !noDriveLatches)
+                    if (width>0 && !noDriveLatches && latchDriver==null)
                         sb.append("assign " + name +"   = " + driver.name + ";\n");
                 }
                 if (latchDriver != null) {