orange library for ESD pads ONLY

diff --git a/electric/orangeTSMC090nm_pads.jelib b/electric/orangeTSMC090nm_pads.jelib
new file mode 100644 (file)
index 0000000..c644278
--- /dev/null
+++ b/electric/orangeTSMC090nm_pads.jelib
@@ -0,0 +1,5761 @@
+# header information:
+HorangeTSMC090nm_pads|8.09i|USER_electrical_units()I70464
+
+# Views:
+Vicon|ic
+Vlayout|lay
+Vschematic|sch
+
+# Tools:
+Ouser|DefaultTechnology()Scmos90|SchematicTechnology()Scmos90
+Oio|GDSOutputConvertsBracketsInExports()BF|GDSWritesExportPins()BT
+OGateLayoutGenerator|enableNCC()SPurpleFour
+OSTA|GlobalSDCCommands()S"\n### clock setup\ncreate_clock -period 0.400 -name clk -waveform \"0 0.200\" clk\nset_clock_uncertainty -setup 0.015 clk\nset_clock_uncertainty -hold 0.015 clk\nset_propagated_clock clk\nset_clock_transition -rise 0.025 clk\nset_clock_transition -fall 0.025 clk\n#set_driving_cell -lib_cell inv_X008_0 clk\n"
+
+# Technologies:
+Tartwork|SelectedFoundryForartwork()S""
+Tcmos90|MininumCapacitanceINcmos90()D0.0|MininumResistanceINcmos90()D0.0
+Tmocmosold|CapacitanceParasiticForD-ActiveINmocmosold()D0.10000000149011612|CapacitanceParasiticForMetal-1INmocmosold()D0.029999999329447746|CapacitanceParasiticForMetal-2INmocmosold()D0.029999999329447746|CapacitanceParasiticForPolysiliconINmocmosold()D0.03999999910593033|CapacitanceParasiticForS-ActiveINmocmosold()D0.10000000149011612|ResistanceParasiticForMetal-1INmocmosold()D0.029999999329447746|ResistanceParasiticForMetal-2INmocmosold()D0.029999999329447746
+Tmocmossub|CapacitanceParasiticForMetal-1INmocmossub()D0.07000000029802322|CapacitanceParasiticForMetal-2INmocmossub()D0.03999999910593033|CapacitanceParasiticForMetal-3INmocmossub()D0.03999999910593033|CapacitanceParasiticForMetal-4INmocmossub()D0.03999999910593033|CapacitanceParasiticForMetal-5INmocmossub()D0.03999999910593033|CapacitanceParasiticForMetal-6INmocmossub()D0.03999999910593033|CapacitanceParasiticForN-ActiveINmocmossub()D0.8999999761581421|CapacitanceParasiticForP-ActiveINmocmossub()D0.8999999761581421|CapacitanceParasiticForPolysilicon-1INmocmossub()D0.09000000357627869|ResistanceParasiticForMetal-1INmocmossub()D0.05999999865889549|ResistanceParasiticForMetal-2INmocmossub()D0.05999999865889549|ResistanceParasiticForMetal-3INmocmossub()D0.05999999865889549|ResistanceParasiticForMetal-4INmocmossub()D0.029999999329447746|ResistanceParasiticForMetal-5INmocmossub()D0.029999999329447746|ResistanceParasiticForMetal-6INmocmossub()D0.029999999329447746|ResistanceParasiticForPoly-CutINmocmossub()D2.200000047683716|ResistanceParasiticForVia2INmocmossub()D0.8999999761581421|ResistanceParasiticForVia3INmocmossub()D0.800000011920929|ResistanceParasiticForVia4INmocmossub()D0.800000011920929|ResistanceParasiticForVia5INmocmossub()D0.800000011920929
+Tnmos|CapacitanceParasiticForDiffusionINnmos()D0.10000000149011612|CapacitanceParasiticForMetalINnmos()D0.029999999329447746|CapacitanceParasiticForPolysiliconINnmos()D0.03999999910593033|ResistanceParasiticForMetalINnmos()D0.029999999329447746
+Ttft|CIFLayerForPentINtft()SCEL|CIFLayerForVia1INtft()SCAA|CIFLayerForlay1INtft()SCPI|CIFLayerForlay2INtft()SCNI|CIFLayerForlay3INtft()SCDP|CIFLayerForlay4INtft()SCDN|MininumResistanceINtft()D10.0|SelectedFoundryFortft()SMOSIS
+
+# Cell LEload;1{ic}
+CLEload;1{ic}||artwork|1083966364000|1204183998562|E|ATTR_L(D5G1;HOLPUDX0.5;)S100|ATTR_LEWIRE(D5G1;HPT)I1|ATTR_layer(D5G1;HNOLPY-1;)S1|ATTR_width(D5G1;HNOLPY-2;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||-2|1|1|1||
+NPin|pin@1||2|1|1|1||
+NPin|pin@2||2|-1|1|1||
+NPin|pin@3||-2|-1|1|1||
+Nschematic:Bus_Pin|pin@5||-3|0|-1|-1||
+NPin|pin@6||-2|0|1|1||
+NPin|pin@7||-3|0|1|1||
+AThicker|net@0|||FS0|pin@1||2|1|pin@0||-2|1|ART_color()I74
+AThicker|net@1|||FS0|pin@2||2|-1|pin@3||-2|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@0||-2|1|pin@3||-2|-1|ART_color()I74
+AThicker|net@4|||FS900|pin@1||2|1|pin@2||2|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@6||-2|0|pin@7||-3|0|ART_color()I74
+Ea||D5G2;|pin@5||B
+X
+
+# Cell LEload;1{sch}
+CLEload;1{sch}||schematic|1083965121000|1176245140811||ATTR_L(D5FLeave alone;G1;HNOLPUDX-20.5;Y-6.5;)S100|ATTR_LEWIRE(D5G1;HNPTX-20.5;Y-9.5;)I1|ATTR_layer(D5FLeave alone;G1;HNOLPX-20.5;Y-7.5;)S1|ATTR_width(D5FLeave alone;G1;HNOLPX-20.5;Y-8.5;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-23|-1||||
+Ngeneric:Invisible-Pin|pin@0||-4|6|||||ART_message(BD5G2;)SLEload
+Ngeneric:Invisible-Pin|pin@3||-9|2|||||ART_message(D6G1;)S["wire in layer 'layer', 'L' lambda long,","'width' lambda wide, for the 180nm tech"]
+ILEload;1{ic}|wire180@0||12|6.63|||D0G4;|ATTR_L(D5G1;OLPUDX0.5;)S100|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NOLPY-1;)S1|ATTR_width(D5G1;NOLPY-2;)S3
+ILEload_sub;1{ic}|wire@0||-10.5|-1|||D0G4;|ATTR_LEWIRECAP(D5G1;NOJTUDX0.5;Y-1.5;)S((@layer==0?15:@layer<6?25:30)+(@width-3))*1e-18*@L
+Awire|net@0|||0|wire@0|a|-14.5|-1|conn@0|y|-21|-1
+Ea||D4G2;|conn@0|a|B
+X
+
+# Cell LEload_sub;1{ic}
+CLEload_sub;1{ic}||artwork|1083964052000|1176245054736|E|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@2||2|0|1.5|1.5|||ART_color()I74
+NPin|pin@0||-2.75|0|1|1||
+NPin|pin@1||-4|0||||
+NPin|pin@4||-2|0.75|1|1||
+NPin|pin@5||2|0.75|1|1||
+NPin|pin@6||2|-0.75|1|1||
+NPin|pin@7||-2|-0.75|1|1||
+Nschematic:Bus_Pin|pin@9||-4|0|-2|-2||
+Ngeneric:Invisible-Pin|pin@10||0|0|||||ART_message(D5G1;)SLEload_sub
+AThicker|net@0|||IJS0|pin@0||-2.75|0|pin@1||-4|0|ART_color()I74
+AThicker|net@2|||IJS0|pin@5||2|0.75|pin@4||-2|0.75|ART_color()I74
+AThicker|net@3|||IJS0|pin@6||2|-0.75|pin@7||-2|-0.75|ART_color()I74
+Ea||D5G2;|pin@9||U
+X
+
+# Cell LEload_sub;1{sch}
+CLEload_sub;1{sch}||schematic|1083961993000|1176245054736||prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@1||-7.5|3||||
+Ngeneric:Invisible-Pin|pin@5||-1|22|||||ART_message(D5G6;)SLEload_sub
+NWire_Pin|pin@12||8|3||||
+ILEload_sub;1{ic}|wire@0||22.5|23.5|||D0G4;
+Awire|a|D5G1.5;||1800|conn@1|y|-5.5|3|pin@12||8|3|ART_color()I0
+Ea||D4G2;|conn@1|a|U
+X
+
+# Cell NMOS4f;1{ic}
+CNMOS4f;1{ic}||artwork|1021415734000|1217455595839|E|ATTR_Delay(D5G1;HNPX3.25;Y-2.25;)I100|ATTR_L(D5G1;HNOLPX3.25;Y-0.25;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX1.75;Y0.75;)S3|ATTR_goop(D5G1;HNOLPX2.75;Y-3.25;)S1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||-0.25|-0.75||||
+NPin|pin@1||-0.25|-0.25||||
+NPin|pin@2||-0.75|-0.5|1|1|RR|
+NPin|pin@3||0|-0.5|||RR|
+Ngeneric:Invisible-Pin|pin@4||0|-0.5||||
+Ngeneric:Invisible-Pin|pin@5||0|-2||||
+NPin|pin@6||-1.5|0|1|1|RR|
+NPin|pin@7||-3|0|||RR|
+Nschematic:Bus_Pin|pin@8||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||0|2|-2|-2||
+NPin|pin@10||0|-2||||
+NPin|pin@11||-1.5|1|1|1||
+NPin|pin@12||-1.5|-1|1|1||
+NPin|pin@13||0|-1||||
+NPin|pin@14||-0.75|-1|1|1||
+NPin|pin@15||-0.75|1|1|1||
+NPin|pin@16||0|1||||
+NPin|pin@17||0|2||||
+AThicker|net@0|||FS2250|pin@0||-0.25|-0.75|pin@3||0|-0.5|ART_color()I74
+AThicker|net@1|||FS1350|pin@1||-0.25|-0.25|pin@3||0|-0.5|ART_color()I74
+AThicker|net@2|||FS1800|pin@2||-0.75|-0.5|pin@3||0|-0.5|ART_color()I74
+AThicker|net@3|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
+AThicker|net@4|||FS1800|pin@7||-3|0|pin@6||-1.5|0|ART_color()I74
+AThicker|net@5|||FS900|pin@11||-1.5|1|pin@12||-1.5|-1|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
+AThicker|net@7|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
+AThicker|net@8|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
+Eb||D5G1;|pin@4||B
+Ed||D5G1;|pin@9||B
+Eg||D5G1;|pin@8||I
+Es||D5G1;|pin@5||B
+X
+
+# Cell NMOS4f;1{sch}
+CNMOS4f;1{sch}||schematic|1021415734000|1217455606316||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-18;Y-11.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-18;Y-10.5;)S3|ATTR_goop(D5G1;HNOLPX-18;Y-14.5;)S1|ATTR_CDL_template(D5G1;NTX-3.5;Y-24;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*0.05u' L='$(L)*0.05u' M='$(goop)'|ATTR_SPICE_template(D5G1;NTX2.5;Y-19.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))' M='$(goop)'|ATTR_SPICE_template_calibre(D5G1;NTY-26;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*0.05u' L='$(L)*0.05u' M='$(goop)'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)' L='$(L)' M='$(goop)'|ATTR_verilog_template(D5G1;NTX-6;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f;1{ic}|NMOS4f@0||18.5|1|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NOLPX3.25;Y-0.25;)S2|ATTR_W(D6FLeave alone;G1;NOLPX1.75;Y0.75;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||4.5|-7.5||||
+NOff-Page|conn@1||4.5|-12.5||||
+NOff-Page|conn@2||4.5|0||||
+NOff-Page|conn@3||-18.5|-6.5||||
+N4-Port-Transistor|nmos4p@0||-2|-6.5|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch
+Ngeneric:Invisible-Pin|pin@0||-2|7.5|||||ART_message(D5G3;)S4-terminal standard-threshold NMOS device
+NWire_Pin|pin@1||0|-12.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||-1.5|13|||||ART_message(D5G6;)S[NMOS4f]
+Awire|net@0|||0|nmos4p@0|g|-3|-6.5|conn@3|y|-16.5|-6.5
+Awire|net@1|||1800|nmos4p@0|b|0|-7.5|conn@0|a|2.5|-7.5
+Awire|net@2|||900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
+Awire|net@3|||1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
+Awire|net@4|||1800|pin@2||0|0|conn@2|a|2.5|0
+Awire|net@5|||900|pin@2||0|0|nmos4p@0|d|0|-4.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@3|a|I
+Es||D5G2;|conn@1|y|B
+X
+
+# Cell NMOS4f_high;1{ic}
+CNMOS4f_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.25;Y-0.25;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX1.75;Y0.75;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||-0.25|-0.75||||
+NPin|pin@1||-0.25|-0.25||||
+NPin|pin@2||-0.75|-0.5|1|1|RR|
+NPin|pin@3||0|-0.5|||RR|
+Ngeneric:Invisible-Pin|pin@4||0|-0.5||||
+Ngeneric:Invisible-Pin|pin@5||0|-2||||
+NPin|pin@6||-2|0|1|1|RR|
+NPin|pin@7||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@8||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||0|2|-2|-2||
+NPin|pin@10||0|-2||||
+NPin|pin@11||-2|1|1|1||
+NPin|pin@12||-2|-1|1|1||
+NPin|pin@13||0|-1||||
+NPin|pin@14||-0.75|-1|1|1||
+NPin|pin@15||-0.75|1|1|1||
+NPin|pin@16||0|1||||
+NPin|pin@17||0|2||||
+AThicker|net@0|||FS2250|pin@0||-0.25|-0.75|pin@3||0|-0.5|ART_color()I74
+AThicker|net@1|||FS1350|pin@1||-0.25|-0.25|pin@3||0|-0.5|ART_color()I74
+AThicker|net@2|||FS1800|pin@2||-0.75|-0.5|pin@3||0|-0.5|ART_color()I74
+AThicker|net@3|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
+AThicker|net@4|||FS1800|pin@7||-3.5|0|pin@6||-2|0|ART_color()I74
+AThicker|net@5|||FS900|pin@11||-2|1|pin@12||-2|-1|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
+AThicker|net@7|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
+AThicker|net@8|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
+Eb||D5G1;|pin@4||B
+Ed||D5G1;|pin@9||B
+Eg||D5G1;|pin@8||I
+Es||D5G1;|pin@5||B
+X
+
+# Cell NMOS4f_high;1{sch}
+CNMOS4f_high;1{sch}||schematic|1021415734000|1159313234499||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-18;Y-11.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-18;Y-10.5;)S3|ATTR_CDL_template(D5G1;NTX-6.5;Y-26;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-5.5;Y-23.75;)StransistorType VTH-N-Transistor|ATTR_SPICE_template(D5G1;NTX-4.5;Y-19.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-6;Y-28;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-6;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_high;1{ic}|NMOS4f@0||18.5|1|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.25;Y-0.25;)S2|ATTR_W(D6FLeave alone;G1;NOLPX1.75;Y0.75;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||4.5|-7.5||||
+NOff-Page|conn@1||4.5|-12.5||||
+NOff-Page|conn@2||4.5|0||||
+NOff-Page|conn@3||-18.5|-6.5||||
+N4-Port-Transistor|nmos4p@0||-2|-6.5|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_hvt
+Ngeneric:Invisible-Pin|pin@0||-2|7.5|||||ART_message(D5G3;)S4-terminal high-threshold NMOS device
+NWire_Pin|pin@1||0|-12.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||-1.5|13|||||ART_message(D5G6;)SNMOS4f_high
+Awire|net@0|||0|nmos4p@0|g|-3|-6.5|conn@3|y|-16.5|-6.5
+Awire|net@1|||1800|nmos4p@0|b|0|-7.5|conn@0|a|2.5|-7.5
+Awire|net@2|||900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
+Awire|net@3|||1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
+Awire|net@4|||1800|pin@2||0|0|conn@2|a|2.5|0
+Awire|net@5|||900|pin@2||0|0|nmos4p@0|d|0|-4.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@3|a|I
+Es||D5G2;|conn@1|y|B
+X
+
+# Cell NMOS4f_io18;1{ic}
+CNMOS4f_io18;1{ic}||artwork|1021415734000|1204528157020|E|ATTR_Delay(D5G1;HNPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;HNPX3.25;Y-0.25;)S4|ATTR_W(D6FLeave alone;G1;HNPX1.75;Y0.75;)I3|ATTR_goop(D5G1;HNPX2.75;Y-3.25;)I1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||-0.25|-0.75||||
+NPin|pin@1||-0.25|-0.25||||
+NPin|pin@2||-0.75|-0.5|1|1|RR|
+NPin|pin@3||0|-0.5|||RR|
+Ngeneric:Invisible-Pin|pin@4||0|-0.5||||
+Ngeneric:Invisible-Pin|pin@5||0|-2||||
+NPin|pin@6||-2|0|1|1|RR|
+NPin|pin@7||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@8||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||0|2|-2|-2||
+NPin|pin@10||0|-2||||
+NPin|pin@11||-2|1|1|1||
+NPin|pin@12||-2|-1|1|1||
+NPin|pin@13||0|-1||||
+NPin|pin@14||-0.75|-1|1|1||
+NPin|pin@15||-0.75|1|1|1||
+NPin|pin@16||0|1||||
+NPin|pin@17||0|2||||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+AThicker|net@0|||FS2250|pin@0||-0.25|-0.75|pin@3||0|-0.5|ART_color()I74
+AThicker|net@1|||FS1350|pin@1||-0.25|-0.25|pin@3||0|-0.5|ART_color()I74
+AThicker|net@2|||FS1800|pin@2||-0.75|-0.5|pin@3||0|-0.5|ART_color()I74
+AThicker|net@3|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
+AThicker|net@4|||FS1800|pin@7||-3.5|0|pin@6||-2|0|ART_color()I74
+AThicker|net@5|||FS900|pin@11||-2|1|pin@12||-2|-1|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
+AThicker|net@7|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
+AThicker|net@8|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
+Eb||D5G1;|pin@4||B
+Ed||D5G1;|pin@9||B
+Eg||D5G1;|pin@8||I
+Es||D5G1;|pin@5||B
+X
+
+# Cell NMOS4f_io18;1{sch}
+CNMOS4f_io18;1{sch}||schematic|1021415734000|1217450409910||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5FLeave alone;G1;HNPX-18;Y-11.5;)S4|ATTR_W(D5FLeave alone;G1;HNPX-18;Y-10.5;)I3|ATTR_goop(D5G1;HNPX-18.25;Y-13.5;)I1|ATTR_CDL_template(D5G1;NTX-1.5;Y-25.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_18 W='$(W)*0.05u' L='$(L)*0.05u' M='$(goop)'|ATTR_NCC(D5G1;NTX-2.5;Y-23.5;)StransistorType  OD18-N-Transistor|ATTR_SPICE_template(D5G1;NTY-19.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_18 W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))' M='$(goop)'|ATTR_SPICE_template_calibre(D5G1;NTX-1;Y-27.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_18 W='$(W)*0.05u' L='$(L)*0.05u' M='$(goop)'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_18 W='$(W)' L='$(L)' M='$(goop)'|ATTR_verilog_template(D5G1;NTX-4;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_io18;1{ic}|NMOS4f@0||18.5|1|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;NPX3.25;Y-0.25;)S4|ATTR_W(D6FLeave alone;G1;NPX1.75;Y0.75;)I3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||4.5|-7.5||||
+NOff-Page|conn@1||4.5|-12.5||||
+NOff-Page|conn@2||4.5|0||||
+NOff-Page|conn@3||-18.5|-6.5||||
+N4-Port-Transistor|nmos4p@0||-2|-6.5|||R||ATTR_length(D5FLeave alone;G1;OJX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OJX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3.5;)Snch_18
+Ngeneric:Invisible-Pin|pin@0||-2|13.5|||||ART_message(D5G2;)S4-terminal NMOS device for 1.8V I/O pads
+NWire_Pin|pin@1||0|-12.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||-1.5|19|||||ART_message(D5G6;)SNMOS4f_io18
+Ngeneric:Invisible-Pin|pin@5||-2.25|8.5|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 4
+Awire|net@0|||0|nmos4p@0|g|-3|-6.5|conn@3|y|-16.5|-6.5
+Awire|net@1|||1800|nmos4p@0|b|0|-7.5|conn@0|a|2.5|-7.5
+Awire|net@2|||900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
+Awire|net@3|||1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
+Awire|net@4|||1800|pin@2||0|0|conn@2|a|2.5|0
+Awire|net@5|||900|pin@2||0|0|nmos4p@0|d|0|-4.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@3|a|I
+Es||D5G2;|conn@1|y|B
+X
+
+# Cell NMOS4f_io25;1{ic}
+CNMOS4f_io25;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.25;Y-0.25;)S5.6|ATTR_W(D6FLeave alone;G1;HNOLPX1.75;Y0.75;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||-0.25|-0.75||||
+NPin|pin@1||-0.25|-0.25||||
+NPin|pin@2||-0.75|-0.5|1|1|RR|
+NPin|pin@3||0|-0.5|||RR|
+Ngeneric:Invisible-Pin|pin@4||0|-0.5||||
+Ngeneric:Invisible-Pin|pin@5||0|-2||||
+NPin|pin@6||-2|0|1|1|RR|
+NPin|pin@7||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@8||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||0|2|-2|-2||
+NPin|pin@10||0|-2||||
+NPin|pin@11||-2|1|1|1||
+NPin|pin@12||-2|-1|1|1||
+NPin|pin@13||0|-1||||
+NPin|pin@14||-0.75|-1|1|1||
+NPin|pin@15||-0.75|1|1|1||
+NPin|pin@16||0|1||||
+NPin|pin@17||0|2||||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S2.5V
+AThicker|net@0|||FS2250|pin@0||-0.25|-0.75|pin@3||0|-0.5|ART_color()I74
+AThicker|net@1|||FS1350|pin@1||-0.25|-0.25|pin@3||0|-0.5|ART_color()I74
+AThicker|net@2|||FS1800|pin@2||-0.75|-0.5|pin@3||0|-0.5|ART_color()I74
+AThicker|net@3|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
+AThicker|net@4|||FS1800|pin@7||-3.5|0|pin@6||-2|0|ART_color()I74
+AThicker|net@5|||FS900|pin@11||-2|1|pin@12||-2|-1|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
+AThicker|net@7|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
+AThicker|net@8|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
+Eb||D5G1;|pin@4||B
+Ed||D5G1;|pin@9||B
+Eg||D5G1;|pin@8||I
+Es||D5G1;|pin@5||B
+X
+
+# Cell NMOS4f_io25;1{sch}
+CNMOS4f_io25;1{sch}||schematic|1021415734000|1159313192055||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-18;Y-11.5;)S5.6|ATTR_W(D5FLeave alone;G1;HNOLPX-18;Y-10.5;)S3|ATTR_CDL_template(D5G1;NTX-1;Y-26;)SM$(node_name) $(d) $(g) $(s) $(b) nch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-1.5;Y-23.5;)StransistorType  OD25-N-Transistor|ATTR_SPICE_template(D5G1;NTX2.5;Y-19.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_25 W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-0.5;Y-28;)SM$(node_name) $(d) $(g) $(s) $(b) nch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_25 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-6;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_io25;1{ic}|NMOS4f_i@1||18.5|1|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.25;Y-0.25;)S5.6|ATTR_W(D6FLeave alone;G1;NOLPX1.75;Y0.75;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||4.5|-7.5||||
+NOff-Page|conn@1||4.5|-12.5||||
+NOff-Page|conn@2||4.5|0||||
+NOff-Page|conn@3||-18.5|-6.5||||
+N4-Port-Transistor|nmos4p@0||-2|-6.5|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3.5;)Snch_25
+Ngeneric:Invisible-Pin|pin@0||-2|13.5|||||ART_message(D5G2;)S4-terminal NMOS device for 2.5V I/O pads
+NWire_Pin|pin@1||0|-12.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||-1.5|19|||||ART_message(D5G6;)SNMOS4f_io25
+Ngeneric:Invisible-Pin|pin@4||-2|8.5|||||ART_message(D5G2;)Sminimum length for 2.5V thick-oxide devices is 5.6
+Awire|net@0|||0|nmos4p@0|g|-3|-6.5|conn@3|y|-16.5|-6.5
+Awire|net@1|||1800|nmos4p@0|b|0|-7.5|conn@0|a|2.5|-7.5
+Awire|net@2|||900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
+Awire|net@3|||1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
+Awire|net@4|||1800|pin@2||0|0|conn@2|a|2.5|0
+Awire|net@5|||900|pin@2||0|0|nmos4p@0|d|0|-4.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@3|a|I
+Es||D5G2;|conn@1|y|B
+X
+
+# Cell NMOS4f_io33;1{ic}
+CNMOS4f_io33;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.25;Y-0.25;)S7.6|ATTR_W(D6FLeave alone;G1;HNOLPX1.75;Y0.75;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||-0.25|-0.75||||
+NPin|pin@1||-0.25|-0.25||||
+NPin|pin@2||-0.75|-0.5|1|1|RR|
+NPin|pin@3||0|-0.5|||RR|
+Ngeneric:Invisible-Pin|pin@4||0|-0.5||||
+Ngeneric:Invisible-Pin|pin@5||0|-2||||
+NPin|pin@6||-2|0|1|1|RR|
+NPin|pin@7||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@8||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||0|2|-2|-2||
+NPin|pin@10||0|-2||||
+NPin|pin@11||-2|1|1|1||
+NPin|pin@12||-2|-1|1|1||
+NPin|pin@13||0|-1||||
+NPin|pin@14||-0.75|-1|1|1||
+NPin|pin@15||-0.75|1|1|1||
+NPin|pin@16||0|1||||
+NPin|pin@17||0|2||||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S3.3V
+AThicker|net@0|||FS2250|pin@0||-0.25|-0.75|pin@3||0|-0.5|ART_color()I74
+AThicker|net@1|||FS1350|pin@1||-0.25|-0.25|pin@3||0|-0.5|ART_color()I74
+AThicker|net@2|||FS1800|pin@2||-0.75|-0.5|pin@3||0|-0.5|ART_color()I74
+AThicker|net@3|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
+AThicker|net@4|||FS1800|pin@7||-3.5|0|pin@6||-2|0|ART_color()I74
+AThicker|net@5|||FS900|pin@11||-2|1|pin@12||-2|-1|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
+AThicker|net@7|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
+AThicker|net@8|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
+Eb||D5G1;|pin@4||B
+Ed||D5G1;|pin@9||B
+Eg||D5G1;|pin@8||I
+Es||D5G1;|pin@5||B
+X
+
+# Cell NMOS4f_io33;1{sch}
+CNMOS4f_io33;1{sch}||schematic|1021415734000|1159313151805||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-18;Y-11.5;)S7.6|ATTR_W(D5FLeave alone;G1;HNOLPX-18;Y-10.5;)S3|ATTR_CDL_template(D5G1;NTX-3.5;Y-26;)SM$(node_name) $(d) $(g) $(s) $(b) nch_33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-5;Y-24;)StransistorType  OD33-N-Transistor|ATTR_SPICE_template(D5G1;NTX-1.5;Y-19.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_33 W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-3;Y-28;)SM$(node_name) $(d) $(g) $(s) $(b) nch_33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_33 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-6;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_io33;1{ic}|NMOS4f_i@3||18.5|1|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.25;Y-0.25;)S7.6|ATTR_W(D6FLeave alone;G1;NOLPX1.75;Y0.75;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||4.5|-7.5||||
+NOff-Page|conn@1||4.5|-12.5||||
+NOff-Page|conn@2||4.5|0||||
+NOff-Page|conn@3||-18.5|-6.5||||
+N4-Port-Transistor|nmos4p@0||-2|-6.5|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-4;)Snch_33
+Ngeneric:Invisible-Pin|pin@0||-2|13.5|||||ART_message(D5G2;)S4-terminal NMOS device for 3.3V I/O pads
+NWire_Pin|pin@1||0|-12.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||-1.5|19|||||ART_message(D5G6;)SNMOS4f_io33
+Ngeneric:Invisible-Pin|pin@4||-2|8.5|||||ART_message(D5G2;)Sminimum length for 3.3V thick-oxide devices is 7.6
+Awire|net@0|||0|nmos4p@0|g|-3|-6.5|conn@3|y|-16.5|-6.5
+Awire|net@1|||1800|nmos4p@0|b|0|-7.5|conn@0|a|2.5|-7.5
+Awire|net@2|||900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
+Awire|net@3|||1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
+Awire|net@4|||1800|pin@2||0|0|conn@2|a|2.5|0
+Awire|net@5|||900|pin@2||0|0|nmos4p@0|d|0|-4.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@3|a|I
+Es||D5G2;|conn@1|y|B
+X
+
+# Cell NMOS4f_low;1{ic}
+CNMOS4f_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.25;Y-0.25;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX1.75;Y0.75;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||-0.25|-0.75||||
+NPin|pin@1||-0.25|-0.25||||
+NPin|pin@2||-0.75|-0.5|1|1|RR|
+NPin|pin@3||0|-0.5|||RR|
+Ngeneric:Invisible-Pin|pin@4||0|-0.5||||
+Ngeneric:Invisible-Pin|pin@5||0|-2||||
+NPin|pin@6||-1|0|1|1|RR|
+NPin|pin@7||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@8||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||0|2|-2|-2||
+NPin|pin@10||0|-2||||
+NPin|pin@11||-1|1|1|1||
+NPin|pin@12||-1|-1|1|1||
+NPin|pin@13||0|-1||||
+NPin|pin@14||-0.75|-1|1|1||
+NPin|pin@15||-0.75|1|1|1||
+NPin|pin@16||0|1||||
+NPin|pin@17||0|2||||
+AThicker|net@0|||FS2250|pin@0||-0.25|-0.75|pin@3||0|-0.5|ART_color()I74
+AThicker|net@1|||FS1350|pin@1||-0.25|-0.25|pin@3||0|-0.5|ART_color()I74
+AThicker|net@2|||FS1800|pin@2||-0.75|-0.5|pin@3||0|-0.5|ART_color()I74
+AThicker|net@3|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
+AThicker|net@4|||FS1800|pin@7||-2.5|0|pin@6||-1|0|ART_color()I74
+AThicker|net@5|||FS900|pin@11||-1|1|pin@12||-1|-1|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
+AThicker|net@7|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
+AThicker|net@8|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
+Eb||D5G1;|pin@4||B
+Ed||D5G1;|pin@9||B
+Eg||D5G1;|pin@8||I
+Es||D5G1;|pin@5||B
+X
+
+# Cell NMOS4f_low;1{sch}
+CNMOS4f_low;1{sch}||schematic|1021415734000|1159313276571||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-18;Y-11.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-18;Y-10.5;)S3|ATTR_CDL_template(D5G1;NTX-4;Y-25.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-3.75;Y-23.5;)StransistorType VTL-N-Transistor|ATTR_SPICE_template(D5G1;NTX-3.5;Y-19.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-3.5;Y-27.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-6;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_low;1{ic}|NMOS4f@0||18.5|1|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.25;Y-0.25;)S2|ATTR_W(D6FLeave alone;G1;NOLPX1.75;Y0.75;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||4.5|-7.5||||
+NOff-Page|conn@1||4.5|-12.5||||
+NOff-Page|conn@2||4.5|0||||
+NOff-Page|conn@3||-18.5|-6.5||||
+N4-Port-Transistor|nmos4p@0||-2|-6.5|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_lvt
+Ngeneric:Invisible-Pin|pin@0||-2|8.5|||||ART_message(D5G3;)S4-terminal low-threshold NMOS device
+NWire_Pin|pin@1||0|-12.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||-1.5|14|||||ART_message(D5G6;)SNMOS4f_low
+Awire|net@0|||0|nmos4p@0|g|-3|-6.5|conn@3|y|-16.5|-6.5
+Awire|net@1|||1800|nmos4p@0|b|0|-7.5|conn@0|a|2.5|-7.5
+Awire|net@2|||900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
+Awire|net@3|||1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
+Awire|net@4|||1800|pin@2||0|0|conn@2|a|2.5|0
+Awire|net@5|||900|pin@2||0|0|nmos4p@0|d|0|-4.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@3|a|I
+Es||D5G2;|conn@1|y|B
+X
+
+# Cell NMOS4f_native;1{ic}
+CNMOS4f_native;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.25;Y-0.25;)S4|ATTR_W(D6FLeave alone;G1;HNOLPX1.75;Y0.75;)S10|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||-0.25|-0.75||||
+NPin|pin@1||-0.25|-0.25||||
+NPin|pin@2||-0.75|-0.5|1|1|RR|
+NPin|pin@3||0|-0.5|||RR|
+Ngeneric:Invisible-Pin|pin@4||0|-0.5||||
+Ngeneric:Invisible-Pin|pin@5||0|-2||||
+NPin|pin@6||-0.75|0|1|1|RR|
+NPin|pin@7||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@8||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||0|2|-2|-2||
+NPin|pin@10||0|-2||||
+NPin|pin@13||0|-1||||
+NPin|pin@14||-0.75|-1|1|1||
+NPin|pin@15||-0.75|1|1|1||
+NPin|pin@16||0|1||||
+NPin|pin@17||0|2||||
+AThicker|net@0|||FS2250|pin@0||-0.25|-0.75|pin@3||0|-0.5|ART_color()I74
+AThicker|net@1|||FS1350|pin@1||-0.25|-0.25|pin@3||0|-0.5|ART_color()I74
+AThicker|net@2|||FS1800|pin@2||-0.75|-0.5|pin@3||0|-0.5|ART_color()I74
+AThicker|net@3|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
+AThicker|net@4|||FS1800|pin@7||-2.5|0|pin@6||-0.75|0|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
+AThicker|net@7|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
+AThicker|net@8|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
+Eb||D5G1;|pin@4||B
+Ed||D5G1;|pin@9||B
+Eg||D5G1;|pin@8||I
+Es||D5G1;|pin@5||B
+X
+
+# Cell NMOS4f_native;1{sch}
+CNMOS4f_native;1{sch}||schematic|1021415734000|1158099366852||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-18;Y-11.5;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX-18;Y-10.5;)S10|ATTR_CDL_template(D5G1;NTX-6;Y-25.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-5;Y-23.5;)StransistorType  NT-N-Transistor|ATTR_SPICE_template(D5G1;NTX-3.5;Y-19.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-5.5;Y-27.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-6;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4f_native;1{ic}|NMOS4f@0||18.5|1|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.25;Y-0.25;)S4|ATTR_W(D6FLeave alone;G1;NOLPX1.75;Y0.75;)S10
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||4.5|-7.5||||
+NOff-Page|conn@1||4.5|-12.5||||
+NOff-Page|conn@2||4.5|0||||
+NOff-Page|conn@3||-12.5|-6.5||||
+N4-Port-Transistor|nmos4p@0||-2|-6.5|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-4;)Snch_na
+Ngeneric:Invisible-Pin|pin@0||-2|15.5|||||ART_message(D5G2;)S4-terminal native-threshold NMOS device
+NWire_Pin|pin@1||0|-12.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||-1.5|22|||||ART_message(D5G6;)SNMOS4f_native
+Ngeneric:Invisible-Pin|pin@4||-2.5|9|||||ART_message(D5G2;)S[note that the minimum allowed native,"device dimensions are W=10, L=4"]
+Awire|net@0|||0|nmos4p@0|g|-3|-6.5|conn@3|y|-10.5|-6.5
+Awire|net@1|||1800|nmos4p@0|b|0|-7.5|conn@0|a|2.5|-7.5
+Awire|net@2|||900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
+Awire|net@3|||1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
+Awire|net@4|||1800|pin@2||0|0|conn@2|a|2.5|0
+Awire|net@5|||900|pin@2||0|0|nmos4p@0|d|0|-4.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@3|a|I
+Es||D5G2;|conn@1|y|B
+X
+
+# Cell NMOS4fwk;1{ic}
+CNMOS4fwk;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||0|2||||
+NPin|pin@1||0|0.75||||
+NPin|pin@2||-0.75|0.75|1|1||
+NPin|pin@3||-0.75|-0.75|1|1||
+NPin|pin@4||0|-0.75||||
+NPin|pin@5||-1.25|-0.75|1|1||
+NPin|pin@6||-1.25|0.75|1|1||
+NPin|pin@7||0|-2||||
+Nschematic:Bus_Pin|pin@8||0|2|-2|-2||
+Nschematic:Bus_Pin|pin@9||-3|0|-2|-2||
+NPin|pin@10||-3|0|||RR|
+NPin|pin@11||-1.25|0|1|1|RR|
+Ngeneric:Invisible-Pin|pin@12||0|-2||||
+Ngeneric:Invisible-Pin|pin@13||-0.5|0|||||ART_message(D5G1;)S[wk]
+NPin|pin@14||0|-0.5||||
+NPin|pin@15||-0.75|-0.5|1|1||
+NPin|pin@16||-0.5|-0.75|1|1|YRR|
+NPin|pin@17||-0.75|-0.5|1|1|Y|
+NPin|pin@18||-0.75|-0.5|1|1||
+NPin|pin@19||-0.5|-0.25|1|1|RR|
+Nschematic:Bus_Pin|pin@20||0|-0.5||||
+AThicker|net@0|||FS900|pin@0||0|2|pin@1||0|0.75|ART_color()I74
+AThicker|net@1|||FS0|pin@1||0|0.75|pin@2||-0.75|0.75|ART_color()I74
+AThicker|net@2|||FS1800|pin@3||-0.75|-0.75|pin@4||0|-0.75|ART_color()I74
+AThicker|net@3|||FS900|pin@4||0|-0.75|pin@7||0|-2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||-1.25|0.75|pin@5||-1.25|-0.75|ART_color()I74
+AThicker|net@5|||FS1800|pin@10||-3|0|pin@11||-1.25|0|ART_color()I74
+AThicker|net@6|||FS900|pin@2||-0.75|0.75|pin@3||-0.75|-0.75|ART_color()I74
+AThicker|net@7|||FS1800|pin@15||-0.75|-0.5|pin@14||0|-0.5|ART_color()I74
+AThicker|net@8|||FS3150|pin@16||-0.5|-0.75|pin@17||-0.75|-0.5|ART_color()I74
+AThicker|net@9|||FS450|pin@19||-0.5|-0.25|pin@18||-0.75|-0.5|ART_color()I74
+Eb||D5G1;|pin@20||B
+Ed||D5G1;|pin@8||B
+Eg||D5G1;|pin@9||I
+Es||D5G1;|pin@12||B
+X
+
+# Cell NMOS4fwk;1{sch}
+CNMOS4fwk;1{sch}||schematic|1021415734000|1159313367315||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX-1;Y-29;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-0.5;Y-31;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-21.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4fwk;1{ic}|NMOS4fwk@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-10|-8||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||6|-16.5||||
+NOff-Page|conn@3||6|-9|||YRR|
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-2.5;)Snch
+Ngeneric:Invisible-Pin|pin@0||0|11.5|||||ART_message(D5G6;)S[NMOS4fwk]
+NWire_Pin|pin@1||0|0||||
+NWire_Pin|pin@2||0|-16.5||||
+Ngeneric:Invisible-Pin|pin@3||1|5.5|||||ART_message(D5G2;)S4-terminal standard threshold weak NMOS device
+Awire|net@0|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@1|||1800|conn@0|y|-8|-8|nmos4p@0|g|-3|-8
+Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
+Awire|net@3|||1800|pin@2||0|-16.5|conn@2|a|4|-16.5
+Awire|net@4|||900|nmos4p@0|s|0|-10|pin@2||0|-16.5
+Awire|net@5|||1800|nmos4p@0|b|0|-9|conn@3|y|4|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@0|a|I
+Es||D5G2;|conn@2|y|B
+X
+
+# Cell NMOS4fwk_high;1{ic}
+CNMOS4fwk_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||0|2||||
+NPin|pin@1||0|0.75||||
+NPin|pin@2||-0.75|0.75|1|1||
+NPin|pin@3||-0.75|-0.75|1|1||
+NPin|pin@4||0|-0.75||||
+NPin|pin@5||-1.75|-0.75|1|1||
+NPin|pin@6||-1.75|0.75|1|1||
+NPin|pin@7||0|-2||||
+Nschematic:Bus_Pin|pin@8||0|2|-2|-2||
+Nschematic:Bus_Pin|pin@9||-3|0|-2|-2||
+NPin|pin@10||-3|0|||RR|
+NPin|pin@11||-1.75|0|1|1|RR|
+Ngeneric:Invisible-Pin|pin@12||0|-2||||
+Ngeneric:Invisible-Pin|pin@13||-0.5|0|||||ART_message(D5G1;)S[wk]
+NPin|pin@14||0|-0.5||||
+NPin|pin@15||-0.75|-0.5|1|1||
+NPin|pin@16||-0.5|-0.75|1|1|YRR|
+NPin|pin@17||-0.75|-0.5|1|1|Y|
+NPin|pin@18||-0.75|-0.5|1|1||
+NPin|pin@19||-0.5|-0.25|1|1|RR|
+Nschematic:Bus_Pin|pin@20||0|-0.5||||
+AThicker|net@0|||FS900|pin@0||0|2|pin@1||0|0.75|ART_color()I74
+AThicker|net@1|||FS0|pin@1||0|0.75|pin@2||-0.75|0.75|ART_color()I74
+AThicker|net@2|||FS1800|pin@3||-0.75|-0.75|pin@4||0|-0.75|ART_color()I74
+AThicker|net@3|||FS900|pin@4||0|-0.75|pin@7||0|-2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||-1.75|0.75|pin@5||-1.75|-0.75|ART_color()I74
+AThicker|net@5|||FS1800|pin@10||-3|0|pin@11||-1.75|0|ART_color()I74
+AThicker|net@6|||FS900|pin@2||-0.75|0.75|pin@3||-0.75|-0.75|ART_color()I74
+AThicker|net@7|||FS1800|pin@15||-0.75|-0.5|pin@14||0|-0.5|ART_color()I74
+AThicker|net@8|||FS3150|pin@16||-0.5|-0.75|pin@17||-0.75|-0.5|ART_color()I74
+AThicker|net@9|||FS450|pin@19||-0.5|-0.25|pin@18||-0.75|-0.5|ART_color()I74
+Eb||D5G1;|pin@20||B
+Ed||D5G1;|pin@8||B
+Eg||D5G1;|pin@9||I
+Es||D5G1;|pin@12||B
+X
+
+# Cell NMOS4fwk_high;1{sch}
+CNMOS4fwk_high;1{sch}||schematic|1021415734000|1159313323976||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX1;Y-31.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX0.5;Y-28.75;)StransistorType VTH-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX0.5;Y-34;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-21.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_hvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4fwk_high;1{ic}|NMOS4fwk@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-10|-8||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||6|-16.5||||
+NOff-Page|conn@3||6|-9|||YRR|
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_hvt
+Ngeneric:Invisible-Pin|pin@0||0|11.5|||||ART_message(D5G6;)SNMOS4fwk_high
+NWire_Pin|pin@1||0|0||||
+NWire_Pin|pin@2||0|-16.5||||
+Ngeneric:Invisible-Pin|pin@3||1|5.5|||||ART_message(D5G2;)S4-terminal high-threshold weak NMOS device
+Awire|net@0|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@1|||1800|conn@0|y|-8|-8|nmos4p@0|g|-3|-8
+Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
+Awire|net@3|||1800|pin@2||0|-16.5|conn@2|a|4|-16.5
+Awire|net@4|||900|nmos4p@0|s|0|-10|pin@2||0|-16.5
+Awire|net@5|||1800|nmos4p@0|b|0|-9|conn@3|y|4|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@0|a|I
+Es||D5G2;|conn@2|y|B
+X
+
+# Cell NMOS4fwk_low;1{ic}
+CNMOS4fwk_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||0|2||||
+NPin|pin@1||0|0.75||||
+NPin|pin@2||-0.75|0.75|1|1||
+NPin|pin@3||-0.75|-0.75|1|1||
+NPin|pin@4||0|-0.75||||
+NPin|pin@5||-1|-0.75|1|1||
+NPin|pin@6||-1|0.75|1|1||
+NPin|pin@7||0|-2||||
+Nschematic:Bus_Pin|pin@8||0|2|-2|-2||
+Nschematic:Bus_Pin|pin@9||-2.5|0|-2|-2||
+NPin|pin@10||-2.5|0|||RR|
+NPin|pin@11||-1|0|1|1|RR|
+Ngeneric:Invisible-Pin|pin@12||0|-2||||
+Ngeneric:Invisible-Pin|pin@13||-0.5|0|||||ART_message(D5G1;)S[wk]
+NPin|pin@14||0|-0.5||||
+NPin|pin@15||-0.75|-0.5|1|1||
+NPin|pin@16||-0.5|-0.75|1|1|YRR|
+NPin|pin@17||-0.75|-0.5|1|1|Y|
+NPin|pin@18||-0.75|-0.5|1|1||
+NPin|pin@19||-0.5|-0.25|1|1|RR|
+Nschematic:Bus_Pin|pin@20||0|-0.5||||
+AThicker|net@0|||FS900|pin@0||0|2|pin@1||0|0.75|ART_color()I74
+AThicker|net@1|||FS0|pin@1||0|0.75|pin@2||-0.75|0.75|ART_color()I74
+AThicker|net@2|||FS1800|pin@3||-0.75|-0.75|pin@4||0|-0.75|ART_color()I74
+AThicker|net@3|||FS900|pin@4||0|-0.75|pin@7||0|-2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||-1|0.75|pin@5||-1|-0.75|ART_color()I74
+AThicker|net@5|||FS1800|pin@10||-2.5|0|pin@11||-1|0|ART_color()I74
+AThicker|net@6|||FS900|pin@2||-0.75|0.75|pin@3||-0.75|-0.75|ART_color()I74
+AThicker|net@7|||FS1800|pin@15||-0.75|-0.5|pin@14||0|-0.5|ART_color()I74
+AThicker|net@8|||FS3150|pin@16||-0.5|-0.75|pin@17||-0.75|-0.5|ART_color()I74
+AThicker|net@9|||FS450|pin@19||-0.5|-0.25|pin@18||-0.75|-0.5|ART_color()I74
+Eb||D5G1;|pin@20||B
+Ed||D5G1;|pin@8||B
+Eg||D5G1;|pin@9||I
+Es||D5G1;|pin@12||B
+X
+
+# Cell NMOS4fwk_low;1{sch}
+CNMOS4fwk_low;1{sch}||schematic|1021415734000|1159313388630||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX-1.5;Y-31.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX0.5;Y-29;)StransistorType VTL-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-1;Y-33.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-21.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_lvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4fwk_low;1{ic}|NMOS4fwk@0||20|0|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-10|-8||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||6|-16.5||||
+NOff-Page|conn@3||6|-9|||YRR|
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_lvt
+Ngeneric:Invisible-Pin|pin@0||1|12.5|||||ART_message(D5G6;)SNMOS4fwk_low
+NWire_Pin|pin@1||0|0||||
+NWire_Pin|pin@2||0|-16.5||||
+Ngeneric:Invisible-Pin|pin@3||-0.5|6.5|||||ART_message(D5G2;)S4-terminal low-threshold weak NMOS device
+Awire|net@0|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@1|||1800|conn@0|y|-8|-8|nmos4p@0|g|-3|-8
+Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
+Awire|net@3|||1800|pin@2||0|-16.5|conn@2|a|4|-16.5
+Awire|net@4|||900|nmos4p@0|s|0|-10|pin@2||0|-16.5
+Awire|net@5|||1800|nmos4p@0|b|0|-9|conn@3|y|4|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@0|a|I
+Es||D5G2;|conn@2|y|B
+X
+
+# Cell NMOS4fwk_native;1{ic}
+CNMOS4fwk_native;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNPX3.5;)S4|ATTR_W(D6FLeave alone;G1;HNPX2;Y1;)S10|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||0|2||||
+NPin|pin@1||0|0.75||||
+NPin|pin@2||-0.75|0.75|1|1||
+NPin|pin@3||-0.75|-0.75|1|1||
+NPin|pin@4||0|-0.75||||
+NPin|pin@7||0|-2||||
+Nschematic:Bus_Pin|pin@8||0|2|-2|-2||
+Nschematic:Bus_Pin|pin@9||-2.5|0|-2|-2||
+NPin|pin@10||-2.5|0|||RR|
+NPin|pin@11||-0.75|0|1|1|RR|
+Ngeneric:Invisible-Pin|pin@12||0|-2||||
+Ngeneric:Invisible-Pin|pin@13||-0.5|0|||||ART_message(D5G1;)S[wk]
+NPin|pin@14||0|-0.5||||
+NPin|pin@15||-0.75|-0.5|1|1||
+NPin|pin@16||-0.5|-0.75|1|1|YRR|
+NPin|pin@17||-0.75|-0.5|1|1|Y|
+NPin|pin@18||-0.75|-0.5|1|1||
+NPin|pin@19||-0.5|-0.25|1|1|RR|
+Nschematic:Bus_Pin|pin@20||0|-0.5||||
+AThicker|net@0|||FS900|pin@0||0|2|pin@1||0|0.75|ART_color()I74
+AThicker|net@1|||FS0|pin@1||0|0.75|pin@2||-0.75|0.75|ART_color()I74
+AThicker|net@2|||FS1800|pin@3||-0.75|-0.75|pin@4||0|-0.75|ART_color()I74
+AThicker|net@3|||FS900|pin@4||0|-0.75|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS1800|pin@10||-2.5|0|pin@11||-0.75|0|ART_color()I74
+AThicker|net@6|||FS900|pin@2||-0.75|0.75|pin@3||-0.75|-0.75|ART_color()I74
+AThicker|net@7|||FS1800|pin@15||-0.75|-0.5|pin@14||0|-0.5|ART_color()I74
+AThicker|net@8|||FS3150|pin@16||-0.5|-0.75|pin@17||-0.75|-0.5|ART_color()I74
+AThicker|net@9|||FS450|pin@19||-0.5|-0.25|pin@18||-0.75|-0.5|ART_color()I74
+Eb||D5G1;|pin@20||B
+Ed||D5G1;|pin@8||B
+Eg||D5G1;|pin@9||I
+Es||D5G1;|pin@12||B
+X
+
+# Cell NMOS4fwk_native;1{sch}
+CNMOS4fwk_native;1{sch}||schematic|1021415734000|1159313406251||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNPX-9;Y-13.5;)S4|ATTR_W(D5FLeave alone;G1;HNPX-8.5;Y-12.5;)S10|ATTR_CDL_template(D5G1;NTX-0.5;Y-31;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-1;Y-28.5;)StransistorType  NT-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTY-33;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-21.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch_na W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOS4fwk_native;1{ic}|NMOS4fwk@0||20|0|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NPX3.5;)S4|ATTR_W(D6FLeave alone;G1;NPX2;Y1;)S10|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-10|-8||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||6|-16.5||||
+NOff-Page|conn@3||6|-9|||YRR|
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OJX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OJX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-4;)Snch_na
+Ngeneric:Invisible-Pin|pin@0||1|17.5|||||ART_message(D5G6;)SNMOS4fwk_native
+NWire_Pin|pin@1||0|0||||
+NWire_Pin|pin@2||0|-16.5||||
+Ngeneric:Invisible-Pin|pin@3||-0.5|11.5|||||ART_message(D5G2;)S4-terminal native weak NMOS device
+Ngeneric:Invisible-Pin|pin@4||-0.5|6|||||ART_message(D5G2;)S[note that the minimum allowed native,"device dimensions are W=10, L=4"]
+Awire|net@0|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@1|||1800|conn@0|y|-8|-8|nmos4p@0|g|-3|-8
+Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
+Awire|net@3|||1800|pin@2||0|-16.5|conn@2|a|4|-16.5
+Awire|net@4|||900|nmos4p@0|s|0|-10|pin@2||0|-16.5
+Awire|net@5|||1800|nmos4p@0|b|0|-9|conn@3|y|4|-9
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@0|a|I
+Es||D5G2;|conn@2|y|B
+X
+
+# Cell NMOS4x;1{ic}
+CNMOS4x;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.5|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1.5|1|1|1||
+NPin|pin@7||-1.5|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Universal-Pin|pin@13||0|-0.5|-1|-1||
+NPin|pin@15||-0.75|-0.5|||X|
+NPin|pin@16||0|-0.5|1|1|XY|
+NPin|pin@17||0|-0.5|1|1|XY|
+NPin|pin@18||-0.25|-0.75|1|1|XYRR|
+NPin|pin@19||0|-0.5|1|1|XY|
+NPin|pin@20||-0.25|-0.25|1|1|XYRR|
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I10
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1.5|0|ART_color()I10
+AThicker|net@2|||FS900|pin@6||-1.5|1|pin@7||-1.5|-1|ART_color()I10
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I10
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
+AThicker|net@8|||FS2250|pin@18||-0.25|-0.75|pin@17||0|-0.5|ART_color()I10
+AThicker|net@9|||FS1350|pin@20||-0.25|-0.25|pin@19||0|-0.5|ART_color()I10
+AThicker|net@10|||FS1800|pin@15||-0.75|-0.5|pin@16||0|-0.5|ART_color()I10
+Eb||D5G1;|pin@13||U
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4x;1{sch}
+CNMOS4x;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOS4x;1{ic}|NMOS@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOLPX3.5;Y0.5;)S1
+INMOS4f;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (2-0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 3.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+NOff-Page|conn@3||11.5|-8.5|||YRR|
+Ngeneric:Invisible-Pin|pin@0||-13|-2|||||ART_message(D5G1;)S[Note: Gate Resistor removed for,NCC in miniheater chip]
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOS4x
+Ngeneric:Invisible-Pin|pin@4||-8.5|-4.5|||||ART_message(D5G1;)S[model,gate,resistance]
+Ngeneric:Invisible-Pin|pin@5||-0.5|6|||||ART_message(D5G2;)S4 terminal strength-based NMOS device
+Awire|net@0|||0|NMOSf@0|g|-3|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||1800|pin@1||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@2||0|0|conn@1|a|3.5|0
+Awire|net@8|||0|conn@3|y|9.5|-8.5|NMOSf@0|b|0|-8.5
+Eb||D4G2;|conn@3|a|P
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOS4x_io18;1{ic}
+CNMOS4x_io18;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+Ngeneric:Invisible-Pin|pin@14||0|-0.5||||
+NPin|pin@22||-0.75|-0.5|1|1|RR|
+NPin|pin@23||0|-0.5|||RR|
+NPin|pin@24||-0.25|-0.25||||
+NPin|pin@25||0|-0.5|||RR|
+NPin|pin@26||-0.25|-0.75||||
+NPin|pin@27||0|-0.5|||RR|
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I10
+AThicker|net@1|||FS1800|pin@2||-3.5|0|pin@1||-2|0|ART_color()I10
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I10
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I10
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
+AThicker|net@19|||FS1800|pin@22||-0.75|-0.5|pin@23||0|-0.5|ART_color()I10
+AThicker|net@20|||FS1350|pin@24||-0.25|-0.25|pin@25||0|-0.5|ART_color()I10
+AThicker|net@21|||FS2250|pin@26||-0.25|-0.75|pin@27||0|-0.5|ART_color()I10
+Eb||D5G1;|pin@14||B
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4x_io18;1{sch}
+CNMOS4x_io18;1{sch}||schematic|1021415734000|1158100927976||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOS4x_io18;1{ic}|NMOS@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+INMOS4f_io18;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (4-0.4) / @X + 0.4) : 4|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 3.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+NOff-Page|conn@3||8.5|-8.5||||
+Ngeneric:Invisible-Pin|pin@0||-13|-2|||||ART_message(D5G1;)S[Note: Gate Resistor removed for,NCC in miniheater chip]
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOS4x_io25
+Ngeneric:Invisible-Pin|pin@4||-8.5|-4.5|||||ART_message(D5G1;)S[model,gate,resistance]
+Ngeneric:Invisible-Pin|pin@5||-0.5|6|||||ART_message(D5G2;)S4-terminal strength-based NMOS device for 1.8V I/O pads
+Awire|net@0|||0|NMOSf@0|g|-3.5|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||1800|pin@1||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@2||0|0|conn@1|a|3.5|0
+Awire|net@8|||0|conn@3|a|6.5|-8.5|NMOSf@0|b|0|-8.5
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOS4x_io25;1{ic}
+CNMOS4x_io25;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S2.5V
+Ngeneric:Invisible-Pin|pin@14||0|-0.5||||
+NPin|pin@22||-0.75|-0.5|1|1|RR|
+NPin|pin@23||0|-0.5|||RR|
+NPin|pin@24||-0.25|-0.25||||
+NPin|pin@25||0|-0.5|||RR|
+NPin|pin@26||-0.25|-0.75||||
+NPin|pin@27||0|-0.5|||RR|
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I10
+AThicker|net@1|||FS1800|pin@2||-3.5|0|pin@1||-2|0|ART_color()I10
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I10
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I10
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
+AThicker|net@19|||FS1800|pin@22||-0.75|-0.5|pin@23||0|-0.5|ART_color()I10
+AThicker|net@20|||FS1350|pin@24||-0.25|-0.25|pin@25||0|-0.5|ART_color()I10
+AThicker|net@21|||FS2250|pin@26||-0.25|-0.75|pin@27||0|-0.5|ART_color()I10
+Eb||D5G1;|pin@14||B
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4x_io25;1{sch}
+CNMOS4x_io25;1{sch}||schematic|1021415734000|1158100925062||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOS4x_io25;1{ic}|NMOS4_io@1||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+INMOS4f_io25;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (5.6-0.4) / @X + 0.4) : 5.6|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 3.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+NOff-Page|conn@3||8.5|-8.5||||
+Ngeneric:Invisible-Pin|pin@0||-13|-2|||||ART_message(D5G1;)S[Note: Gate Resistor removed for,NCC in miniheater chip]
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOS4x_io33
+Ngeneric:Invisible-Pin|pin@4||-8.5|-4.5|||||ART_message(D5G1;)S[model,gate,resistance]
+Ngeneric:Invisible-Pin|pin@5||-0.5|6|||||ART_message(D5G2;)S4-terminal strength-based NMOS device for 2.5V I/O pads
+Awire|net@0|||0|NMOSf@0|g|-3.5|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||1800|pin@1||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@2||0|0|conn@1|a|3.5|0
+Awire|net@8|||0|conn@3|a|6.5|-8.5|NMOSf@0|b|0|-8.5
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOS4x_io33;1{ic}
+CNMOS4x_io33;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S3.3V
+Ngeneric:Invisible-Pin|pin@14||0|-0.5||||
+NPin|pin@22||-0.75|-0.5|1|1|RR|
+NPin|pin@23||0|-0.5|||RR|
+NPin|pin@24||-0.25|-0.25||||
+NPin|pin@25||0|-0.5|||RR|
+NPin|pin@26||-0.25|-0.75||||
+NPin|pin@27||0|-0.5|||RR|
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I10
+AThicker|net@1|||FS1800|pin@2||-3.5|0|pin@1||-2|0|ART_color()I10
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I10
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I10
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
+AThicker|net@19|||FS1800|pin@22||-0.75|-0.5|pin@23||0|-0.5|ART_color()I10
+AThicker|net@20|||FS1350|pin@24||-0.25|-0.25|pin@25||0|-0.5|ART_color()I10
+AThicker|net@21|||FS2250|pin@26||-0.25|-0.75|pin@27||0|-0.5|ART_color()I10
+Eb||D5G1;|pin@14||B
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOS4x_io33;1{sch}
+CNMOS4x_io33;1{sch}||schematic|1021415734000|1158100921910||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOS4x_io33;1{ic}|NMOS4_io@3||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+INMOS4f_io33;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (7.6-0.4) / @X + 0.4) : 7.6|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 3.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+NOff-Page|conn@3||8.5|-8.5||||
+Ngeneric:Invisible-Pin|pin@0||-13|-2|||||ART_message(D5G1;)S[Note: Gate Resistor removed for,NCC in miniheater chip]
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOS4x_io33
+Ngeneric:Invisible-Pin|pin@4||-8.5|-4.5|||||ART_message(D5G1;)S[model,gate,resistance]
+Ngeneric:Invisible-Pin|pin@5||-0.5|6|||||ART_message(D5G2;)S4-terminal strength-based NMOS device for 3.3V I/O pads
+Awire|net@0|||0|NMOSf@0|g|-3.5|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||1800|pin@1||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@2||0|0|conn@1|a|3.5|0
+Awire|net@8|||0|conn@3|a|6.5|-8.5|NMOSf@0|b|0|-8.5
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf;1{ic}
+CNMOSf;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.5|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1.5|1|1|1||
+NPin|pin@7||-1.5|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1.5|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-1.5|1|pin@7||-1.5|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf;1{sch}
+CNMOSf;1{sch}||schematic|1021415734000|1159313246486||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) $(b) nch W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf;1{ic}|NMOSf@0||28|0.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)S[NMOSf]
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S3-terminal standard threshold NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_high;1{ic}
+CNMOSf_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3.5|0|pin@1||-2|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_high;1{sch}
+CNMOSf_high;1{sch}||schematic|1021415734000|1159313222266||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX4;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX4.5;Y-28.5;)StransistorType VTH-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX4.5;Y-33;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2.5;Y-22;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX2.5;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_high;1{ic}|NMOSf@0||28|0.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1;Y-3;)Snch_hvt
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)SNMOSf_high
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S3-terminal high-threshold NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_io18;1{ic}
+CNMOSf_io18;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.25;Y-0.25;)S4|ATTR_W(D6FLeave alone;G1;HNOLPX1.75;Y0.75;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@5||0|-2||||
+NPin|pin@6||-2|0|1|1|RR|
+NPin|pin@7||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@8||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||0|2|-2|-2||
+NPin|pin@10||0|-2||||
+NPin|pin@11||-2|1|1|1||
+NPin|pin@12||-2|-1|1|1||
+NPin|pin@13||0|-1||||
+NPin|pin@14||-0.75|-1|1|1||
+NPin|pin@15||-0.75|1|1|1||
+NPin|pin@16||0|1||||
+NPin|pin@17||0|2||||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+AThicker|net@3|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I74
+AThicker|net@4|||FS1800|pin@7||-3.5|0|pin@6||-2|0|ART_color()I74
+AThicker|net@5|||FS900|pin@11||-2|1|pin@12||-2|-1|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|-1|pin@10||0|-2|ART_color()I74
+AThicker|net@7|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I74
+AThicker|net@8|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||0|2|pin@16||0|1|ART_color()I74
+Ed||D5G1;|pin@9||B
+Eg||D5G1;|pin@8||I
+Es||D5G1;|pin@5||B
+X
+
+# Cell NMOSf_io18;1{sch}
+CNMOSf_io18;1{sch}||schematic|1021415734000|1159313203077||ATTR_Delay(D5G1;HNPX-18.25;Y-12.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-18;Y-11.5;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX-18;Y-10.5;)S3|ATTR_CDL_template(D5G1;NTY-26;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-1.5;Y-23.75;)StransistorType OD18-N-Transistor|ATTR_SPICE_template(D5G1;NTX-3;Y-19.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX0.5;Y-28;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-17.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-21.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_io18;1{ic}|NMOSf_io@1||18.5|1|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.25;Y-0.25;)S4|ATTR_W(D6FLeave alone;G1;NOLPX1.75;Y0.75;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@1||4.5|-12.5||||
+NOff-Page|conn@2||4.5|0||||
+NOff-Page|conn@3||-18.5|-6.5||||
+NGround|gnd@0||7|-7.5|||R|
+N4-Port-Transistor|nmos4p@0||-2|-6.5|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-4;)Snch_18
+Ngeneric:Invisible-Pin|pin@0||-2|13.5|||||ART_message(D5G2;)S3-terminal NMOS device for 1.8V I/O pads
+NWire_Pin|pin@1||0|-12.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||-1.5|19|||||ART_message(D5G6;)SNMOSf_io18
+Ngeneric:Invisible-Pin|pin@4||-2|8.5|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 4
+Awire|net@0|||0|nmos4p@0|g|-3|-6.5|conn@3|y|-16.5|-6.5
+Awire|net@2|||900|nmos4p@0|s|0|-8.5|pin@1||0|-12.5
+Awire|net@3|||1800|pin@1||0|-12.5|conn@1|a|2.5|-12.5
+Awire|net@4|||1800|pin@2||0|0|conn@2|a|2.5|0
+Awire|net@5|||900|pin@2||0|0|nmos4p@0|d|0|-4.5
+Awire|net@6|||0|gnd@0||5|-7.5|nmos4p@0|b|0|-7.5
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@3|a|I
+Es||D5G2;|conn@1|y|B
+X
+
+# Cell NMOSf_io25;1{ic}
+CNMOSf_io25;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HPT)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S5.6|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.5|1.5|||||ART_message(D5G1;)S2.5V
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3.5|0|pin@1||-2|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_io25;1{sch}
+CNMOSf_io25;1{sch}||schematic|1021415734000|1159313179436||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S5.6|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX0.5;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX0.5;Y-29;)StransistorType  OD25-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_25 W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-33;)SM$(node_name) $(d) $(g) $(s) gnd nch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2.5;Y-22;)SM$(node_name) $(d) $(g) $(s) gnd nch_25 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_io25;1{ic}|NMOSf_25@1||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S5.6|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1;Y-4;)Snch_25
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|21|||||ART_message(D5G6;)SNMOSf_25
+Ngeneric:Invisible-Pin|pin@4||0|13.5|||||ART_message(D5G2;)S3-terminal NMOS device for 2.5V I/O pads
+Ngeneric:Invisible-Pin|pin@5||0|8.5|||||ART_message(D5G2;)Sminimum length for 2.5V thick-oxide devices is 5.6
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_io33;1{ic}
+CNMOSf_io33;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HPT)I100|ATTR_L(D5G1;HNOLPX3.5;)S7.6|ATTR_W(D6G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.5|1.5|||||ART_message(D5G1;)S3.3V
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3.5|0|pin@1||-2|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_io33;1{sch}
+CNMOSf_io33;1{sch}||schematic|1021415734000|1159313127323||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S7.6|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX2;Y-31.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1.5;Y-29;)StransistorType  OD33-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_33 W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX2.5;Y-33.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2.5;Y-22;)SM$(node_name) $(d) $(g) $(s) gnd nch_33 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_io33;1{ic}|NMOSf_33@1||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5G1;NOLPX3.5;)S7.6|ATTR_W(D6G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;NOLX-1.5;Y2;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;NOLX2.5;Y-6;)S"P(\"W\")"|SIM_spice_model(D5G1;X0.5;Y-3;)Snch_33
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|20|||||ART_message(D5G6;)SNMOSf_33
+Ngeneric:Invisible-Pin|pin@4||-1|12.5|||||ART_message(D5G2;)S3-terminal NMOS device for 3.3V I/O pads
+Ngeneric:Invisible-Pin|pin@5||-1|7.5|||||ART_message(D5G2;)Sminimum length for 3.3V thick-oxide devices is 7.6
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_low;1{ic}
+CNMOSf_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1|0|1|1|RR|
+NPin|pin@2||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1|1|1|1||
+NPin|pin@7||-1|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-2.5|0|pin@1||-1|0|ART_color()I74
+AThicker|net@2|||FS900|pin@6||-1|1|pin@7||-1|-1|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_low;1{sch}
+CNMOSf_low;1{sch}||schematic|1021415734000|1159313266395||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX1.5;Y-30.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX2;Y-28.5;)StransistorType VTL-N-Transistor|ATTR_SPICE_template(D5G1;NTX2;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-32.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2.5;Y-22;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_low;1{ic}|NMOSf@0||28|0.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_lvt
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|14|||||ART_message(D5G6;)SNMOSf_low
+Ngeneric:Invisible-Pin|pin@3||1.5|7.5|||||ART_message(D5G2;)S3-terminal low threshold NMOS device
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_native;1{ic}
+CNMOSf_native;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S4|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S10|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-0.75|0|1|1|RR|
+NPin|pin@2||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-2.5|0|pin@1||-0.75|0|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_native;1{sch}
+CNMOSf_native;1{sch}||schematic|1021415734000|1158099348261||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S10|ATTR_CDL_template(D5G1;NTX-1;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-0.5;Y-28.5;)StransistorType  NT-N-Transistor|ATTR_SPICE_template(D5G1;NTY-24.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-1.5;Y-33.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2.5;Y-22;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_native;1{ic}|NMOSf@0||27|7.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S4|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S10
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-4;)Snch_na
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-3.5|20|||||ART_message(D5G6;)SNMOSf_native
+Ngeneric:Invisible-Pin|pin@3||-3.5|13|||||ART_message(D5G2;)S3-terminal native NMOS device
+Ngeneric:Invisible-Pin|pin@4||-3.5|8|||||ART_message(D5G2;)S[note that the minimum allowed native,"device dimensions are W=10, L=4"]
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_native_od18;1{ic}
+CNMOSf_native_od18;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S24|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S10|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.75|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-1.75|-1|1|1||
+NPin|pin@10||-1.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+AThicker|net@0|||FS2700|pin@9||-1.75|-1|pin@10||-1.75|1|ART_color()I74
+AThicker|net@1|||FS0|pin@1||-1.75|0|pin@2||-3|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@5||0|-2|pin@8||0|-1|ART_color()I74
+AThicker|net@4|||FS0|pin@8||0|-1|pin@9||-1.75|-1|ART_color()I74
+AThicker|net@5|||FS1800|pin@10||-1.75|1|pin@11||0|1|ART_color()I74
+AThicker|net@6|||FS2700|pin@11||0|1|pin@12||0|2|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_native_od18;1{sch}
+CNMOSf_native_od18;1{sch}||schematic|1021415734000|1158082635019||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S24|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S10|ATTR_CDL_template(D5G1;NTX2.5;Y-31.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na18 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX2;Y-29;)StransistorType  NT-OD18-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na18 W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-34;)SM$(node_name) $(d) $(g) $(s) gnd nch_na18 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2.5;Y-22;)SM$(node_name) $(d) $(g) $(s) gnd nch_na18 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX3;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_native_od18;1{ic}|NMOSf@0||27|7.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S24|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S10
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-4;)Snch_na18
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-3.5|20|||||ART_message(D5G6;)SNMOSf_native_od18
+Ngeneric:Invisible-Pin|pin@3||-3.5|13|||||ART_message(D5G2;)S3-terminal 1.8V native NMOS device
+Ngeneric:Invisible-Pin|pin@4||-3.5|8|||||ART_message(D5G2;)S[note that the minimum allowed native,"device dimensions are W=10, L=24"]
+Awire|net@0|||1800|pin@1||0|0|conn@1|a|4.5|0
+Awire|net@1|||1800|conn@2|y|-14.5|-8|nmos4p@0|g|-3|-8
+Awire|net@2|||2700|pin@0||0|-16.5|nmos4p@0|s|0|-10
+Awire|net@3|||0|conn@0|a|4|-16.5|pin@0||0|-16.5
+Awire|net@4|||2700|nmos4p@0|d|0|-6|pin@1||0|0
+Awire|net@5|||0|gnd@0||5|-9|nmos4p@0|b|0|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_native_od25;1{ic}
+CNMOSf_native_od25;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNOLPX3.5;)S24|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S10|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.75|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-1.75|-1|1|1||
+NPin|pin@10||-1.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S2.5V
+AThicker|net@0|||FS900|pin@10||-1.75|1|pin@9||-1.75|-1|ART_color()I74
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1.75|0|ART_color()I74
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@9||-1.75|-1|pin@8||0|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-1.75|1|ART_color()I74
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_native_od25;1{sch}
+CNMOSf_native_od25;1{sch}||schematic|1021415734000|1158082583609||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNOLPX-9;Y-13.5;)S24|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S10|ATTR_CDL_template(D5G1;NTX4;Y-31.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX2.5;Y-29;)StransistorType  NT-OD25-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na25 W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX3.5;Y-34;)SM$(node_name) $(d) $(g) $(s) gnd nch_na25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2.5;Y-22;)SM$(node_name) $(d) $(g) $(s) gnd nch_na25 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1.5;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_native_od25;1{ic}|NMOSf@0||27|7.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NOLPX3.5;)S24|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S10
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-4;)Snch_na25
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-3.5|20|||||ART_message(D5G6;)SNMOSf_native_od25
+Ngeneric:Invisible-Pin|pin@3||-3.5|13|||||ART_message(D5G2;)S3-terminal 2.5V native NMOS device
+Ngeneric:Invisible-Pin|pin@4||-3.5|8|||||ART_message(D5G2;)S[note that the minimum allowed native,"device dimensions are W=10, L=24"]
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSf_native_od33;1{ic}
+CNMOSf_native_od33;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNOLPX3.5;)S24|ATTR_W(D6G1;HNOLPX2;Y1;)S10|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.75|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-1.75|-1|1|1||
+NPin|pin@10||-1.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S3.3V
+AThicker|net@0|||FS2700|pin@9||-1.75|-1|pin@10||-1.75|1|ART_color()I74
+AThicker|net@1|||FS0|pin@1||-1.75|0|pin@2||-3|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@5||0|-2|pin@8||0|-1|ART_color()I74
+AThicker|net@4|||FS0|pin@8||0|-1|pin@9||-1.75|-1|ART_color()I74
+AThicker|net@5|||FS1800|pin@10||-1.75|1|pin@11||0|1|ART_color()I74
+AThicker|net@6|||FS2700|pin@11||0|1|pin@12||0|2|ART_color()I74
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSf_native_od33;1{sch}
+CNMOSf_native_od33;1{sch}||schematic|1021415734000|1158082542097||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNOLPX-9;Y-13.5;)S24|ATTR_W(D5G1;HNOLPX-8.5;Y-12.5;)S10|ATTR_CDL_template(D5G1;NTX3;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_na33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-28.5;)StransistorType  NT-OD33-N-Transistor|ATTR_SPICE_template(D5G1;NTX2;Y-24.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na33 W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX2.5;Y-33.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2.5;Y-22;)SM$(node_name) $(d) $(g) $(s) gnd nch_na33 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1.5;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_native_od33;1{ic}|NMOSf@0||27|7.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NOLPX3.5;)S24|ATTR_W(D6G1;NOLPX2;Y1;)S10
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-4.5;)Snch_na33
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-3.5|20|||||ART_message(D5G6;)SNMOSf_native_od33
+Ngeneric:Invisible-Pin|pin@3||-3.5|13|||||ART_message(D5G2;)S3-terminal 3.3V native NMOS device
+Ngeneric:Invisible-Pin|pin@4||-3.5|8|||||ART_message(D5G2;)S[note that the minimum allowed native,"device dimensions are W=10, L=24"]
+Awire|net@0|||1800|pin@1||0|0|conn@1|a|4.5|0
+Awire|net@1|||1800|conn@2|y|-14.5|-8|nmos4p@0|g|-3|-8
+Awire|net@2|||2700|pin@0||0|-16.5|nmos4p@0|s|0|-10
+Awire|net@3|||0|conn@0|a|4|-16.5|pin@0||0|-16.5
+Awire|net@4|||2700|nmos4p@0|d|0|-6|pin@1||0|0
+Awire|net@5|||0|gnd@0||5|-9|nmos4p@0|b|0|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSfwk;1{ic}
+CNMOSfwk;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|-2||||
+NPin|pin@2||-1.25|0|1|1|RR|
+NPin|pin@3||-3|0|||RR|
+Nschematic:Bus_Pin|pin@4||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@5||0|2|-2|-2||
+NPin|pin@6||0|-2||||
+NPin|pin@7||-1.25|0.75|1|1||
+NPin|pin@8||-1.25|-0.75|1|1||
+NPin|pin@9||0|-0.75||||
+NPin|pin@10||-0.75|-0.75|1|1||
+NPin|pin@11||-0.75|0.75|1|1||
+NPin|pin@12||0|0.75||||
+NPin|pin@13||0|2||||
+AThicker|net@0|||FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I74
+AThicker|net@1|||FS1800|pin@3||-3|0|pin@2||-1.25|0|ART_color()I74
+AThicker|net@2|||FS900|pin@7||-1.25|0.75|pin@8||-1.25|-0.75|ART_color()I74
+AThicker|net@3|||FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I74
+AThicker|net@5|||FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I74
+Ed||D5G1;|pin@5||B
+Eg||D5G1;|pin@4||I
+Es||D5G1;|pin@1||B
+X
+
+# Cell NMOSfwk;1{sch}
+CNMOSfwk;1{sch}||schematic|1021415734000|1159313356852||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTX-1;Y-29;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)'  DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-0.5;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-21.5;)SM$(node_name) $(d) $(g) $(s) gnd nch W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSfwk;1{ic}|NMOSfwk@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||-10|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-2.5;)Snch
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||0|13.5|||||ART_message(D5G6;)S[NMOSfwk]
+Ngeneric:Invisible-Pin|pin@3||2|7|||||ART_message(D5G2;)S3-terminal standard threshold weak NMOS device
+Awire|net@0|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@1|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
+Awire|net@3|||1800|conn@2|y|-8|-8|nmos4p@0|g|-3|-8
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSfwk_high;1{ic}
+CNMOSfwk_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNOLPX3.5;)S2|ATTR_W(D6G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|-2||||
+NPin|pin@2||-1.75|0|1|1|RR|
+NPin|pin@3||-3|0|||RR|
+Nschematic:Bus_Pin|pin@4||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@5||0|2|-2|-2||
+NPin|pin@6||0|-2||||
+NPin|pin@7||-1.75|0.75|1|1||
+NPin|pin@8||-1.75|-0.75|1|1||
+NPin|pin@9||0|-0.75||||
+NPin|pin@10||-0.75|-0.75|1|1||
+NPin|pin@11||-0.75|0.75|1|1||
+NPin|pin@12||0|0.75||||
+NPin|pin@13||0|2||||
+AThicker|net@0|||FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I74
+AThicker|net@1|||FS1800|pin@3||-3|0|pin@2||-1.75|0|ART_color()I74
+AThicker|net@2|||FS900|pin@7||-1.75|0.75|pin@8||-1.75|-0.75|ART_color()I74
+AThicker|net@3|||FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I74
+AThicker|net@5|||FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I74
+Ed||D5G1;|pin@5||B
+Eg||D5G1;|pin@4||I
+Es||D5G1;|pin@1||B
+X
+
+# Cell NMOSfwk_high;1{sch}
+CNMOSfwk_high;1{sch}||schematic|1021415734000|1159313313027||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTY-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTY-28.75;)StransistorType VTH-N-Transistor|ATTR_SPICE_template(D5G1;NTX1.5;Y-24;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)'  DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX0.5;Y-33;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-21.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_hvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSfwk_high;1{ic}|NMOSfwk@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NOLPX3.5;)S2|ATTR_W(D6G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||-10|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1;Y-3.5;)Snch_hvt
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||0|13.5|||||ART_message(D5G6;)SNMOSfwk_high
+Ngeneric:Invisible-Pin|pin@3||2|7|||||ART_message(D5G2;)S3-terminal high-threshold weak NMOS device
+Awire|net@0|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@1|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
+Awire|net@3|||1800|conn@2|y|-8|-8|nmos4p@0|g|-3|-8
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSfwk_low;1{ic}
+CNMOSfwk_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|-2||||
+NPin|pin@2||-1|0|1|1|RR|
+NPin|pin@3||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@4||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@5||0|2|-2|-2||
+NPin|pin@6||0|-2||||
+NPin|pin@7||-1|0.75|1|1||
+NPin|pin@8||-1|-0.75|1|1||
+NPin|pin@9||0|-0.75||||
+NPin|pin@10||-0.75|-0.75|1|1||
+NPin|pin@11||-0.75|0.75|1|1||
+NPin|pin@12||0|0.75||||
+NPin|pin@13||0|2||||
+AThicker|net@0|||FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I74
+AThicker|net@1|||FS1800|pin@3||-2.5|0|pin@2||-1|0|ART_color()I74
+AThicker|net@2|||FS900|pin@7||-1|0.75|pin@8||-1|-0.75|ART_color()I74
+AThicker|net@3|||FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I74
+AThicker|net@5|||FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I74
+Ed||D5G1;|pin@5||B
+Eg||D5G1;|pin@4||I
+Es||D5G1;|pin@1||B
+X
+
+# Cell NMOSfwk_low;1{sch}
+CNMOSfwk_low;1{sch}||schematic|1021415734000|1159313378128||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S3|ATTR_CDL_template(D5G1;NTY-31.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-29;)StransistorType VTL-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)'  DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX0.5;Y-33.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-21.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_lvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSfwk_low;1{ic}|NMOSfwk@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||-10|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1;Y-3.5;)Snch_lvt
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||0|13.5|||||ART_message(D5G6;)SNMOSfwk_low
+Ngeneric:Invisible-Pin|pin@3||2|7|||||ART_message(D5G2;)S3-terminal low-threshold weak NMOS device
+Awire|net@0|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@1|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
+Awire|net@3|||1800|conn@2|y|-8|-8|nmos4p@0|g|-3|-8
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSfwk_native;1{ic}
+CNMOSfwk_native;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S4|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S10|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|-2||||
+NPin|pin@2||-0.75|0|1|1|RR|
+NPin|pin@3||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@4||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@5||0|2|-2|-2||
+NPin|pin@6||0|-2||||
+NPin|pin@9||0|-0.75||||
+NPin|pin@10||-0.75|-0.75|1|1||
+NPin|pin@11||-0.75|0.75|1|1||
+NPin|pin@12||0|0.75||||
+NPin|pin@13||0|2||||
+AThicker|net@0|||FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I74
+AThicker|net@1|||FS1800|pin@3||-2.5|0|pin@2||-0.75|0|ART_color()I74
+AThicker|net@3|||FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I74
+AThicker|net@5|||FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I74
+AThicker|net@6|||FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I74
+Ed||D5G1;|pin@5||B
+Eg||D5G1;|pin@4||I
+Es||D5G1;|pin@1||B
+X
+
+# Cell NMOSfwk_native;1{sch}
+CNMOSfwk_native;1{sch}||schematic|1021415734000|1158099882605||ATTR_Delay(D5G1;HNPX-8.5;Y-14.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-13.5;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX-8.5;Y-12.5;)S10|ATTR_CDL_template(D5G1;NTX1.5;Y-31.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-1;Y-29;)StransistorType  NT-N-Transistor|ATTR_SPICE_template(D5G1;NTX4;Y-24;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)*(1+ABN/sqrt($(W)*$(L)))' L='$(L)'  DELVTO='AVT0N/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-34;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-21.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_na W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Srtranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSfwk_native;1{ic}|NMOSfwk@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S4|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S10|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||-10|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3.5;)Snch_na
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||0|19.5|||||ART_message(D5G6;)SNMOSfwk_native
+Ngeneric:Invisible-Pin|pin@3||2|13|||||ART_message(D5G2;)S3-terminal native weak NMOS device
+Ngeneric:Invisible-Pin|pin@4||2.5|7|||||ART_message(D5G2;)S[note that the minimum allowed native,"device dimensions are W=10, L=4"]
+Awire|net@0|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@1|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@2|||1800|pin@1||0|0|conn@1|a|2.5|0
+Awire|net@3|||1800|conn@2|y|-8|-8|nmos4p@0|g|-3|-8
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSx;1{ic}
+CNMOSx;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.5|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1.5|1|1|1||
+NPin|pin@7||-1.5|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I10
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1.5|0|ART_color()I10
+AThicker|net@2|||FS900|pin@6||-1.5|1|pin@7||-1.5|-1|ART_color()I10
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I10
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSx;1{sch}
+CNMOSx;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOSx;1{ic}|NMOS@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOLPX3.5;Y0.5;)S1
+INMOSf;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (2-0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 3.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+Ngeneric:Invisible-Pin|pin@0||-13|-2|||||ART_message(D5G1;)S[Note: Gate Resistor removed for,NCC in miniheater chip]
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOSx
+Ngeneric:Invisible-Pin|pin@4||-8.5|-4.5|||||ART_message(D5G1;)S[model,gate,resistance]
+Ngeneric:Invisible-Pin|pin@5||-0.5|6|||||ART_message(D5G2;)Sstandard-threshold strength-based NMOS device
+Awire|net@0|||0|NMOSf@0|g|-3|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||1800|pin@1||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@2||0|0|conn@1|a|3.5|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSx_high;1{ic}
+CNMOSx_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-2|0|1|1|RR|
+NPin|pin@2||-3.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-2|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I10
+AThicker|net@1|||FS1800|pin@2||-3.5|0|pin@1||-2|0|ART_color()I10
+AThicker|net@2|||FS900|pin@6||-2|1|pin@7||-2|-1|ART_color()I10
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I10
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSx_high;1{sch}
+CNMOSx_high;1{sch}||schematic|1021415734000|1158100931062||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOSx_high;1{ic}|NMOS@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+INMOSf_high;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (2-0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 3.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+Ngeneric:Invisible-Pin|pin@0||-13|-2|||||ART_message(D5G1;)S[Note: Gate Resistor removed for,NCC in miniheater chip]
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOSx_high
+Ngeneric:Invisible-Pin|pin@4||-8.5|-4.5|||||ART_message(D5G1;)S[model,gate,resistance]
+Ngeneric:Invisible-Pin|pin@5||-0.5|6|||||ART_message(D5G2;)Shigh-threshold strength-based NMOS device
+Awire|net@0|||0|NMOSf@0|g|-3.5|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||1800|pin@1||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@2||0|0|conn@1|a|3.5|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSx_low;1{ic}
+CNMOSx_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1|0|1|1|RR|
+NPin|pin@2||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@6||-1|1|1|1||
+NPin|pin@7||-1|-1|1|1||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I10
+AThicker|net@1|||FS1800|pin@2||-2.5|0|pin@1||-1|0|ART_color()I10
+AThicker|net@2|||FS900|pin@6||-1|1|pin@7||-1|-1|ART_color()I10
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I10
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSx_low;1{sch}
+CNMOSx_low;1{sch}||schematic|1021415734000|1158100938709||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOSx_low;1{ic}|NMOS@0||17|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+INMOSf_low;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (2-0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 3.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+Ngeneric:Invisible-Pin|pin@0||-13|-2|||||ART_message(D5G1;)S[Note: Gate Resistor removed for,NCC in miniheater chip]
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOSx_low
+Ngeneric:Invisible-Pin|pin@4||-8.5|-4.5|||||ART_message(D5G1;)S[model,gate,resistance]
+Ngeneric:Invisible-Pin|pin@5||-0.5|6|||||ART_message(D5G2;)Slow-threshold strength-based NMOS device
+Awire|net@0|||0|NMOSf@0|g|-2.5|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||1800|pin@1||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@2||0|0|conn@1|a|3.5|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSx_native;1{ic}
+CNMOSx_native;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-0.75|0|1|1|RR|
+NPin|pin@2||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@3||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-0.75|-1|1|1||
+NPin|pin@10||-0.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+AThicker|net@0|||FS900|pin@10||-0.75|1|pin@9||-0.75|-1|ART_color()I10
+AThicker|net@1|||FS1800|pin@2||-2.5|0|pin@1||-0.75|0|ART_color()I10
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@9||-0.75|-1|pin@8||0|-1|ART_color()I10
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-0.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSx_native;1{sch}
+CNMOSx_native;1{sch}||schematic|1021415734000|1158100942644||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOSx_native;1{ic}|NMOS@0||20|0|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+INMOSf_native;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (4-0.4) / @X + 0.4) : 4|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 10.0*@X : 10.0
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+Ngeneric:Invisible-Pin|pin@0||-13|-2|||||ART_message(D5G1;)S[Note: Gate Resistor removed for,NCC in miniheater chip]
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOSx_native
+Ngeneric:Invisible-Pin|pin@4||-8.5|-4.5|||||ART_message(D5G1;)S[model,gate,resistance]
+Ngeneric:Invisible-Pin|pin@5||0|6|||||ART_message(D5G2;)S3 terminal native strength-based NMOS device
+Awire|net@0|||0|NMOSf@0|g|-2.5|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||1800|pin@1||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@2||0|0|conn@1|a|3.5|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSx_native_od18;1{ic}
+CNMOSx_native_od18;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.75|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-1.75|-1|1|1||
+NPin|pin@10||-1.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+AThicker|net@0|||FS2700|pin@9||-1.75|-1|pin@10||-1.75|1|ART_color()I10
+AThicker|net@1|||FS0|pin@1||-1.75|0|pin@2||-3|0|ART_color()I10
+AThicker|net@3|||FS2700|pin@5||0|-2|pin@8||0|-1|ART_color()I10
+AThicker|net@4|||FS0|pin@8||0|-1|pin@9||-1.75|-1|ART_color()I10
+AThicker|net@5|||FS1800|pin@10||-1.75|1|pin@11||0|1|ART_color()I10
+AThicker|net@6|||FS2700|pin@11||0|1|pin@12||0|2|ART_color()I10
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSx_native_od18;1{sch}
+CNMOSx_native_od18;1{sch}||schematic|1021415734000|1158100918384||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOSx_native_od18;1{ic}|NMOS@0||20|0|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+INMOSf_native_od18;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (24-0.4) / @X + 0.4) : 24|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 10.0*@X : 10.0
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOSx_native_od18
+Ngeneric:Invisible-Pin|pin@5||0|6|||||ART_message(D5G2;)S3 terminal 1.8V native strength-based NMOS device
+Awire|net@0|||0|NMOSf@0|g|-3|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||0|conn@0|a|4|-16.5|pin@1||0|-16.5
+Awire|net@4|||0|conn@1|a|3.5|0|pin@2||0|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSx_native_od25;1{ic}
+CNMOSx_native_od25;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.75|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-1.75|-1|1|1||
+NPin|pin@10||-1.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S2.5V
+AThicker|net@0|||FS900|pin@10||-1.75|1|pin@9||-1.75|-1|ART_color()I10
+AThicker|net@1|||FS1800|pin@2||-3|0|pin@1||-1.75|0|ART_color()I10
+AThicker|net@3|||FS900|pin@8||0|-1|pin@5||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@9||-1.75|-1|pin@8||0|-1|ART_color()I10
+AThicker|net@5|||FS0|pin@11||0|1|pin@10||-1.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@12||0|2|pin@11||0|1|ART_color()I10
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSx_native_od25;1{sch}
+CNMOSx_native_od25;1{sch}||schematic|1021415734000|1158100915657||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOSx_native_od25;1{ic}|NMOS@0||20|0|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+INMOSf_native_od25;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (24-0.4) / @X + 0.4) : 24|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 10.0*@X : 10.0
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOSx_native_od25
+Ngeneric:Invisible-Pin|pin@5||0|6|||||ART_message(D5G2;)S3 terminal 2.5V native strength-based NMOS device
+Awire|net@0|||0|NMOSf@0|g|-3|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||1800|pin@1||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@2||0|0|conn@1|a|3.5|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSx_native_od33;1{ic}
+CNMOSx_native_od33;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||0|-2||||
+NPin|pin@1||-1.75|0|1|1|RR|
+NPin|pin@2||-3|0|||RR|
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@4||0|2|-2|-2||
+NPin|pin@5||0|-2||||
+NPin|pin@8||0|-1||||
+NPin|pin@9||-1.75|-1|1|1||
+NPin|pin@10||-1.75|1|1|1||
+NPin|pin@11||0|1||||
+NPin|pin@12||0|2||||
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S3.3V
+AThicker|net@0|||FS2700|pin@9||-1.75|-1|pin@10||-1.75|1|ART_color()I10
+AThicker|net@1|||FS0|pin@1||-1.75|0|pin@2||-3|0|ART_color()I10
+AThicker|net@3|||FS2700|pin@5||0|-2|pin@8||0|-1|ART_color()I10
+AThicker|net@4|||FS0|pin@8||0|-1|pin@9||-1.75|-1|ART_color()I10
+AThicker|net@5|||FS1800|pin@10||-1.75|1|pin@11||0|1|ART_color()I10
+AThicker|net@6|||FS2700|pin@11||0|1|pin@12||0|2|ART_color()I10
+Ed||D5G1;|pin@4||B
+Eg||D5G1;|pin@3||I
+Es||D5G1;|pin@0||B
+X
+
+# Cell NMOSx_native_od33;1{sch}
+CNMOSx_native_od33;1{sch}||schematic|1021415734000|1158100912091||ATTR_Delay(D5G1;HNPX-8.5;Y-12.75;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-11.25;)S1|prototype_center()I[0,0]
+INMOSx_native_od33;1{ic}|NMOS@0||20|0|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOLPX3.5;Y0.5;)S1
+INMOSf_native_od33;1{ic}|NMOSf@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : (@X<1) ? (1.0 * (24-0.4) / @X + 0.4) : 24|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 1 ? 10.0*@X : 10.0
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||5.5|0||||
+NOff-Page|conn@2||-18.5|-8||||
+NWire_Pin|pin@1||0|-16.5||||
+NWire_Pin|pin@2||0|0||||
+Ngeneric:Invisible-Pin|pin@3||0|11.5|||||ART_message(D5G6;)SNMOSx_native_od33
+Ngeneric:Invisible-Pin|pin@5||0|6|||||ART_message(D5G2;)S3 terminal 3.3V native strength-based NMOS device
+Awire|net@0|||0|NMOSf@0|g|-3|-8|conn@2|y|-16.5|-8
+Awire|net@1|||2700|pin@1||0|-16.5|NMOSf@0|s|0|-10
+Awire|net@2|||900|pin@2||0|0|NMOSf@0|d|0|-6
+Awire|net@3|||0|conn@0|a|4|-16.5|pin@1||0|-16.5
+Awire|net@4|||0|conn@1|a|3.5|0|pin@2||0|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSxwk;1{ic}
+CNMOSxwk;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|-2||||
+NPin|pin@2||-1.25|0|1|1|RR|
+NPin|pin@3||-3|0|||RR|
+Nschematic:Bus_Pin|pin@4||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@5||0|2|-2|-2||
+NPin|pin@6||0|-2||||
+NPin|pin@7||-1.25|0.75|1|1||
+NPin|pin@8||-1.25|-0.75|1|1||
+NPin|pin@9||0|-0.75||||
+NPin|pin@10||-0.75|-0.75|1|1||
+NPin|pin@11||-0.75|0.75|1|1||
+NPin|pin@12||0|0.75||||
+NPin|pin@13||0|2||||
+AThicker|net@0|||FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I10
+AThicker|net@1|||FS1800|pin@3||-3|0|pin@2||-1.25|0|ART_color()I10
+AThicker|net@2|||FS900|pin@7||-1.25|0.75|pin@8||-1.25|-0.75|ART_color()I10
+AThicker|net@3|||FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I10
+AThicker|net@5|||FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I10
+AThicker|net@6|||FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I10
+Ed||D5G1;|pin@5||B
+Eg||D5G1;|pin@4||I
+Es||D5G1;|pin@1||B
+X
+
+# Cell NMOSxwk;1{sch}
+CNMOSxwk;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-13.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-12.25;)S1|prototype_center()I[0,0]
+INMOSfwk;1{ic}|NMOSfwk@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X==0 ? 0 : (@X<1) ? (1*(2-0.4)/@X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X>1 ? 3.0*@X : 3|ATTR_GEO()I0
+INMOSxwk;1{ic}|NMOSwk@0||23|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||-10|-8||||
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||2|11.5|||||ART_message(D5G6;)SNMOSxwk
+Ngeneric:Invisible-Pin|pin@3||1|5.5|||||ART_message(D5G2;)S3-terminal standard threshold weak strength based NMOS device
+Awire|net@0|||2700|pin@0||0|-16.5|NMOSfwk@0|s|0|-10
+Awire|net@1|||900|pin@1||0|0|NMOSfwk@0|d|0|-6
+Awire|net@2|||1800|conn@2|y|-8|-8|NMOSfwk@0|g|-3|-8
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@1||0|0|conn@1|a|2.5|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSxwk_high;1{ic}
+CNMOSxwk_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|-2||||
+NPin|pin@2||-1.75|0|1|1|RR|
+NPin|pin@3||-3|0|||RR|
+Nschematic:Bus_Pin|pin@4||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@5||0|2|-2|-2||
+NPin|pin@6||0|-2||||
+NPin|pin@7||-1.75|0.75|1|1||
+NPin|pin@8||-1.75|-0.75|1|1||
+NPin|pin@9||0|-0.75||||
+NPin|pin@10||-0.75|-0.75|1|1||
+NPin|pin@11||-0.75|0.75|1|1||
+NPin|pin@12||0|0.75||||
+NPin|pin@13||0|2||||
+AThicker|net@0|||FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I10
+AThicker|net@1|||FS1800|pin@3||-3|0|pin@2||-1.75|0|ART_color()I10
+AThicker|net@2|||FS900|pin@7||-1.75|0.75|pin@8||-1.75|-0.75|ART_color()I10
+AThicker|net@3|||FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I10
+AThicker|net@5|||FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I10
+AThicker|net@6|||FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I10
+Ed||D5G1;|pin@5||B
+Eg||D5G1;|pin@4||I
+Es||D5G1;|pin@1||B
+X
+
+# Cell NMOSxwk_high;1{sch}
+CNMOSxwk_high;1{sch}||schematic|1021415734000|1158100946251||ATTR_Delay(D5G1;HNPX-8.5;Y-13.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-12.25;)S1|prototype_center()I[0,0]
+INMOSfwk_high;1{ic}|NMOSfwk@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X==0 ? 0 : (@X<1) ? (1*(2-0.4)/@X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X>1 ? 3.0*@X : 3|ATTR_GEO()I0
+INMOSxwk_high;1{ic}|NMOSwk@0||23|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||-10|-8||||
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||2|11.5|||||ART_message(D5G6;)SNMOSxwk_high
+Ngeneric:Invisible-Pin|pin@3||1|5.5|||||ART_message(D5G2;)S3-terminal high-threshold weak strength based NMOS device
+Awire|net@0|||2700|pin@0||0|-16.5|NMOSfwk@0|s|0|-10
+Awire|net@1|||900|pin@1||0|0|NMOSfwk@0|d|0|-6
+Awire|net@2|||1800|conn@2|y|-8|-8|NMOSfwk@0|g|-3|-8
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@1||0|0|conn@1|a|2.5|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSxwk_low;1{ic}
+CNMOSxwk_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|-2||||
+NPin|pin@2||-1|0|1|1|RR|
+NPin|pin@3||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@4||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@5||0|2|-2|-2||
+NPin|pin@6||0|-2||||
+NPin|pin@9||0|-0.75||||
+NPin|pin@10||-0.75|-0.75|1|1||
+NPin|pin@11||-0.75|0.75|1|1||
+NPin|pin@12||0|0.75||||
+NPin|pin@13||0|2||||
+NPin|pin@14||-1|-0.75|1|1||
+NPin|pin@15||-1|0.75|1|1||
+AThicker|net@0|||FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I10
+AThicker|net@1|||FS1800|pin@3||-2.5|0|pin@2||-1|0|ART_color()I10
+AThicker|net@3|||FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I10
+AThicker|net@5|||FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I10
+AThicker|net@6|||FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I10
+AThicker|net@7|||FS900|pin@15||-1|0.75|pin@14||-1|-0.75|ART_color()I10
+Ed||D5G1;|pin@5||B
+Eg||D5G1;|pin@4||I
+Es||D5G1;|pin@1||B
+X
+
+# Cell NMOSxwk_low;1{sch}
+CNMOSxwk_low;1{sch}||schematic|1021415734000|1158100950827||ATTR_Delay(D5G1;HNPX-8.5;Y-13.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-12.25;)S1|prototype_center()I[0,0]
+INMOSfwk_low;1{ic}|NMOSfwk@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X==0 ? 0 : (@X<1) ? (1*(2-0.4)/@X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X>1 ? 3.0*@X : 3|ATTR_GEO()I0
+INMOSxwk_low;1{ic}|NMOSwk@0||23|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||-10|-8||||
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||2|11.5|||||ART_message(D5G6;)SNMOSxwk_low
+Ngeneric:Invisible-Pin|pin@3||1|5.5|||||ART_message(D5G2;)S3-terminal low-threshold weak strength based NMOS device
+Awire|net@0|||2700|pin@0||0|-16.5|NMOSfwk@0|s|0|-10
+Awire|net@1|||900|pin@1||0|0|NMOSfwk@0|d|0|-6
+Awire|net@2|||1800|conn@2|y|-8|-8|NMOSfwk@0|g|-2.5|-8
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@1||0|0|conn@1|a|2.5|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell NMOSxwk_native;1{ic}
+CNMOSxwk_native;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[0,-8000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|-2||||
+NPin|pin@2||-0.75|0|1|1|RR|
+NPin|pin@3||-2.5|0|||RR|
+Nschematic:Bus_Pin|pin@4||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@5||0|2|-2|-2||
+NPin|pin@6||0|-2||||
+NPin|pin@9||0|-0.75||||
+NPin|pin@10||-0.75|-0.75|1|1||
+NPin|pin@11||-0.75|0.75|1|1||
+NPin|pin@12||0|0.75||||
+NPin|pin@13||0|2||||
+AThicker|net@0|||FS900|pin@11||-0.75|0.75|pin@10||-0.75|-0.75|ART_color()I10
+AThicker|net@1|||FS1800|pin@3||-2.5|0|pin@2||-0.75|0|ART_color()I10
+AThicker|net@3|||FS900|pin@9||0|-0.75|pin@6||0|-2|ART_color()I10
+AThicker|net@4|||FS1800|pin@10||-0.75|-0.75|pin@9||0|-0.75|ART_color()I10
+AThicker|net@5|||FS0|pin@12||0|0.75|pin@11||-0.75|0.75|ART_color()I10
+AThicker|net@6|||FS900|pin@13||0|2|pin@12||0|0.75|ART_color()I10
+Ed||D5G1;|pin@5||B
+Eg||D5G1;|pin@4||I
+Es||D5G1;|pin@1||B
+X
+
+# Cell NMOSxwk_native;2{sch}
+CNMOSxwk_native;2{sch}||schematic|1021415734000|1158100953810||ATTR_Delay(D5G1;HNPX-8.5;Y-13.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y-12.25;)S1|prototype_center()I[0,0]
+INMOSfwk_native;1{ic}|NMOSfwk@0||0|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X==0 ? 0 : (@X<1) ? (1*(4-0.4)/@X + 0.4) : 4|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X>1 ? 10.0*@X : 10.0|ATTR_GEO()I0
+INMOSxwk_native;1{ic}|NMOSwk@0||23|-1|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||4.5|0||||
+NOff-Page|conn@2||-10|-8||||
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||2|11.5|||||ART_message(D5G6;)SNMOSxwk_native
+Ngeneric:Invisible-Pin|pin@3||1|5.5|||||ART_message(D5G2;)S3-terminal native weak strength based NMOS device
+Awire|net@0|||2700|pin@0||0|-16.5|NMOSfwk@0|s|0|-10
+Awire|net@1|||900|pin@1||0|0|NMOSfwk@0|d|0|-6
+Awire|net@2|||1800|conn@2|y|-8|-8|NMOSfwk@0|g|-2.5|-8
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||1800|pin@1||0|0|conn@1|a|2.5|0
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f;1{ic}
+CPMOS4f;1{ic}||artwork|1021415734000|1204327262057|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|ATTR_goop(D5G1;HNOLPX3.5;Y-3;)S1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|1|1|||ART_color()I74
+NPin|pin@0||-0.5|0.25|1|1|YRR|
+NPin|pin@1||-0.5|0.75|1|1|YRR|
+NPin|pin@2||-0.75|0.5|1|1|Y|
+NPin|pin@3||0|0.5||||
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Ngeneric:Invisible-Pin|pin@5||0|0.5||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-3|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-3|0|||RR|
+NPin|pin@14||-2.5|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-1.5|-1|1|1||
+NPin|pin@17||-1.5|1|1|1||
+AThicker|net@0|||FS3150|pin@0||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@1|||FS450|pin@1||-0.5|0.75|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@2|||FS0|pin@3||0|0.5|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@3|||FS0|pin@8||0|1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-1|pin@11||0|-1|ART_color()I74
+AThicker|net@5|||FS1800|pin@13||-3|0|pin@14||-2.5|0|ART_color()I74
+AThicker|net@6|||FS2700|pin@8||0|1|pin@15||0|2|ART_color()I74
+AThicker|net@7|||FS900|pin@11||0|-1|pin@12||0|-2|ART_color()I74
+AThicker|net@8|||FS900|pin@9||-0.75|1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||-1.5|1|pin@16||-1.5|-1|ART_color()I74
+Eb||D5G1;|pin@5||B
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOS4f;1{sch}
+CPMOS4f;1{sch}||schematic|1021415734000|1217451702506||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_goop(D5G1;HNOLPX-2;Y-17;)S1|ATTR_CDL_template(D5G1;NTX2;Y-13;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)*0.05u' L='$(L)*0.05u' M='$(goop)'|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))' M='$(goop)'|ATTR_SPICE_template_calibre(D5G1;NTX2.5;Y-15;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)*0.05u' L='$(L)*0.05u' M='$(goop)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)' L='$(L)' M='$(goop)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f;1{ic}|PMOS4f@0||17.25|10.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||5|8||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|24|||||ART_message(D5G6;)SPMOS4f
+Ngeneric:Invisible-Pin|pin@3||-1.5|18.5|||||ART_message(D5G2;)S4-terminal standard-threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Spch
+Awire|net@0|||0|pmos4p@0|g|-3|7|conn@2|y|-10|7
+Awire|net@1|||1800|pin@0||0|11.5|conn@0|a|3|11.5
+Awire|net@2|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
+Awire|net@3|||1800|pmos4p@0|b|0|8|conn@1|a|3|8
+Awire|net@4|||0|conn@3|a|3|1|pin@1||0|1
+Awire|net@5|||2700|pin@1||0|1|pmos4p@0|d|0|5
+Eb||D5G2;|conn@1|y|B
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f_high;1{ic}
+CPMOS4f_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.75;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.25;Y-0.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX3;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|||ART_color()I74
+NPin|pin@0||-0.5|0.25|1|1|YRR|
+NPin|pin@1||-0.5|0.75|1|1|YRR|
+NPin|pin@2||-0.75|0.5|1|1|Y|
+NPin|pin@3||0|0.5||||
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Ngeneric:Invisible-Pin|pin@5||0|0.5||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-3.5|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-3.5|0|||RR|
+NPin|pin@14||-3|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-2|-1|1|1||
+NPin|pin@17||-2|1|1|1||
+AThicker|net@0|||FS3150|pin@0||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@1|||FS450|pin@1||-0.5|0.75|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@2|||FS0|pin@3||0|0.5|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@3|||FS0|pin@8||0|1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-1|pin@11||0|-1|ART_color()I74
+AThicker|net@5|||FS1800|pin@13||-3.5|0|pin@14||-3|0|ART_color()I74
+AThicker|net@6|||FS2700|pin@8||0|1|pin@15||0|2|ART_color()I74
+AThicker|net@7|||FS900|pin@11||0|-1|pin@12||0|-2|ART_color()I74
+AThicker|net@8|||FS900|pin@9||-0.75|1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||-2|1|pin@16||-2|-1|ART_color()I74
+Eb||D5G1;|pin@5||B
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOS4f_high;1{sch}
+CPMOS4f_high;1{sch}||schematic|1021415734000|1159313486964||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_CDL_template(D5G1;NTX0.5;Y-15;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  VTH-P-Transistor|ATTR_SPICE_template(D5G1;NTX0.5;Y-9;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-17;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f_high;1{ic}|PMOS4f@0||17.25|10.5|||D0G4;|ATTR_Delay(D5G1;NPX3.75;Y-2.25;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.25;Y-0.25;)S2|ATTR_W(D5FLeave alone;G1;NOLPX3;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||5|8||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|24|||||ART_message(D5G6;)SPMOS4f_high
+Ngeneric:Invisible-Pin|pin@3||-1.5|18.5|||||ART_message(D5G2;)S4-terminal high-threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3.5;)Spch_hvt
+Awire|net@0|||0|pmos4p@0|g|-3|7|conn@2|y|-10|7
+Awire|net@1|||1800|pin@0||0|11.5|conn@0|a|3|11.5
+Awire|net@2|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
+Awire|net@3|||1800|pmos4p@0|b|0|8|conn@1|a|3|8
+Awire|net@4|||0|conn@3|a|3|1|pin@1||0|1
+Awire|net@5|||2700|pin@1||0|1|pmos4p@0|d|0|5
+Eb||D5G2;|conn@1|y|B
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f_io18;1{ic}
+CPMOS4f_io18;1{ic}||artwork|1021415734000|1204528157020|E|ATTR_Delay(D5G1;HNPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX3;Y1;)S3|ATTR_goop(D5G1;HNPX3.25;Y-3.5;)I1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|||ART_color()I74
+NPin|pin@0||-0.5|0.25|1|1|YRR|
+NPin|pin@1||-0.5|0.75|1|1|YRR|
+NPin|pin@2||-0.75|0.5|1|1|Y|
+NPin|pin@3||0|0.5||||
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Ngeneric:Invisible-Pin|pin@5||0|0.5||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-3.5|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-3.5|0|||RR|
+NPin|pin@14||-3|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-2|-1|1|1||
+NPin|pin@17||-2|1|1|1||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+AThicker|net@0|||FS3150|pin@0||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@1|||FS450|pin@1||-0.5|0.75|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@2|||FS0|pin@3||0|0.5|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@3|||FS0|pin@8||0|1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-1|pin@11||0|-1|ART_color()I74
+AThicker|net@5|||FS1800|pin@13||-3.5|0|pin@14||-3|0|ART_color()I74
+AThicker|net@6|||FS2700|pin@8||0|1|pin@15||0|2|ART_color()I74
+AThicker|net@7|||FS900|pin@11||0|-1|pin@12||0|-2|ART_color()I74
+AThicker|net@8|||FS900|pin@9||-0.75|1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||-2|1|pin@16||-2|-1|ART_color()I74
+Eb||D5G1;|pin@5||B
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOS4f_io18;1{sch}
+CPMOS4f_io18;1{sch}||schematic|1021415734000|1217450448856||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_goop(D5G1;HNPX-8.75;Y-2.5;)I1|ATTR_CDL_template(D5G1;NTX1;Y-15.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)*0.05u' L='$(L)*0.05u' M='$(goop)'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  OD18-P-Transistor|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))' M='$(goop)'|ATTR_SPICE_template_calibre(D5G1;NTX1.5;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)*0.05u' L='$(L)*0.05u' M='$(goop)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)' L='$(L)' M='$(goop)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f_io18;1{ic}|PMOS4f@0||23.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S4|ATTR_W(D5FLeave alone;G1;NOLPX3;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||5|8||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|27|||||ART_message(D5G6;)SPMOS4f_io18
+Ngeneric:Invisible-Pin|pin@3||-1.5|21.5|||||ART_message(D5G2;)S4-terminal PMOS device for 1.8V I/O pads
+Ngeneric:Invisible-Pin|pin@4||-1|17.5|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 4
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3.5;)Spch_18
+Awire|net@0|||0|pmos4p@0|g|-3|7|conn@2|y|-10|7
+Awire|net@1|||1800|pin@0||0|11.5|conn@0|a|3|11.5
+Awire|net@2|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
+Awire|net@3|||1800|pmos4p@0|b|0|8|conn@1|a|3|8
+Awire|net@4|||0|conn@3|a|3|1|pin@1||0|1
+Awire|net@5|||2700|pin@1||0|1|pmos4p@0|d|0|5
+Eb||D5G2;|conn@1|y|B
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f_io25;1{ic}
+CPMOS4f_io25;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S5.6|ATTR_W(D5FLeave alone;G1;HNOLPX3;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|||ART_color()I74
+NPin|pin@0||-0.5|0.25|1|1|YRR|
+NPin|pin@1||-0.5|0.75|1|1|YRR|
+NPin|pin@2||-0.75|0.5|1|1|Y|
+NPin|pin@3||0|0.5||||
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Ngeneric:Invisible-Pin|pin@5||0|0.5||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-3.5|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-3.5|0|||RR|
+NPin|pin@14||-3|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-2|-1|1|1||
+NPin|pin@17||-2|1|1|1||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S2.5V
+AThicker|net@0|||FS1350|pin@2||-0.75|0.5|pin@0||-0.5|0.25|ART_color()I74
+AThicker|net@1|||FS2250|pin@2||-0.75|0.5|pin@1||-0.5|0.75|ART_color()I74
+AThicker|net@2|||FS1800|pin@2||-0.75|0.5|pin@3||0|0.5|ART_color()I74
+AThicker|net@3|||FS1800|pin@9||-0.75|1|pin@8||0|1|ART_color()I74
+AThicker|net@4|||FS0|pin@11||0|-1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@14||-3|0|pin@13||-3.5|0|ART_color()I74
+AThicker|net@6|||FS900|pin@15||0|2|pin@8||0|1|ART_color()I74
+AThicker|net@7|||FS2700|pin@12||0|-2|pin@11||0|-1|ART_color()I74
+AThicker|net@8|||FS2700|pin@10||-0.75|-1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@9|||FS2700|pin@16||-2|-1|pin@17||-2|1|ART_color()I74
+Eb||D5G1;|pin@5||B
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOS4f_io25;1{sch}
+CPMOS4f_io25;1{sch}||schematic|1021415734000|1159313450692||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S5.6|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_CDL_template(D5G1;NTX0.5;Y-15.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  OD25-P-Transistor|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) $(b) pch_25 W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) $(b) pch_25 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f_io25;1{ic}|PMOS4f@0||23.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S5.6|ATTR_W(D5FLeave alone;G1;NOLPX3;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||5|8||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|27|||||ART_message(D5G6;)SPMOS4f_io25
+Ngeneric:Invisible-Pin|pin@3||-1.5|21.5|||||ART_message(D5G2;)S4-terminal PMOS device for 2.5V I/O pads
+Ngeneric:Invisible-Pin|pin@4||-1|17.5|||||ART_message(D5G2;)Sminimum length for 2.5V thick-oxide devices is 5.6
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-4;)Spch_25
+Awire|net@0|||1800|conn@2|y|-10|7|pmos4p@0|g|-3|7
+Awire|net@1|||0|conn@0|a|3|11.5|pin@0||0|11.5
+Awire|net@2|||900|pin@0||0|11.5|pmos4p@0|s|0|9
+Awire|net@3|||0|conn@1|a|3|8|pmos4p@0|b|0|8
+Awire|net@4|||1800|pin@1||0|1|conn@3|a|3|1
+Awire|net@5|||900|pmos4p@0|d|0|5|pin@1||0|1
+Eb||D5G2;|conn@1|y|B
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f_io33;1{ic}
+CPMOS4f_io33;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S7.6|ATTR_W(D5FLeave alone;G1;HNOLPX3;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|||ART_color()I74
+NPin|pin@0||-0.5|0.25|1|1|YRR|
+NPin|pin@1||-0.5|0.75|1|1|YRR|
+NPin|pin@2||-0.75|0.5|1|1|Y|
+NPin|pin@3||0|0.5||||
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Ngeneric:Invisible-Pin|pin@5||0|0.5||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-3.5|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-3.5|0|||RR|
+NPin|pin@14||-3|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-2|-1|1|1||
+NPin|pin@17||-2|1|1|1||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S3.3V
+AThicker|net@0|||FS3150|pin@0||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@1|||FS450|pin@1||-0.5|0.75|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@2|||FS0|pin@3||0|0.5|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@3|||FS0|pin@8||0|1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-1|pin@11||0|-1|ART_color()I74
+AThicker|net@5|||FS1800|pin@13||-3.5|0|pin@14||-3|0|ART_color()I74
+AThicker|net@6|||FS2700|pin@8||0|1|pin@15||0|2|ART_color()I74
+AThicker|net@7|||FS900|pin@11||0|-1|pin@12||0|-2|ART_color()I74
+AThicker|net@8|||FS900|pin@9||-0.75|1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||-2|1|pin@16||-2|-1|ART_color()I74
+Eb||D5G1;|pin@5||B
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOS4f_io33;1{sch}
+CPMOS4f_io33;1{sch}||schematic|1021415734000|1159313431087||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S7.6|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_CDL_template(D5G1;NTX0.5;Y-15.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  OD33-P-Transistor|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) $(b) pch_33 W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) $(b) pch_33 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f_io33;1{ic}|PMOS4f@0||23.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S7.6|ATTR_W(D5FLeave alone;G1;NOLPX3;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||5|8||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|27|||||ART_message(D5G6;)SPMOS4f_io33
+Ngeneric:Invisible-Pin|pin@3||-1.5|21.5|||||ART_message(D5G2;)S4-terminal PMOS device for 3.3V I/O pads
+Ngeneric:Invisible-Pin|pin@4||-1|17.5|||||ART_message(D5G2;)Sminimum length for 3.3V thick-oxide devices is 7.6
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3.5;)Spch_33
+Awire|net@0|||0|pmos4p@0|g|-3|7|conn@2|y|-10|7
+Awire|net@1|||1800|pin@0||0|11.5|conn@0|a|3|11.5
+Awire|net@2|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
+Awire|net@3|||1800|pmos4p@0|b|0|8|conn@1|a|3|8
+Awire|net@4|||0|conn@3|a|3|1|pin@1||0|1
+Awire|net@5|||2700|pin@1||0|1|pmos4p@0|d|0|5
+Eb||D5G2;|conn@1|y|B
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4f_low;1{ic}
+CPMOS4f_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.5|0|1|1|||ART_color()I74
+NPin|pin@0||-0.5|0.25|1|1|YRR|
+NPin|pin@1||-0.5|0.75|1|1|YRR|
+NPin|pin@2||-0.75|0.5|1|1|Y|
+NPin|pin@3||0|0.5||||
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Ngeneric:Invisible-Pin|pin@5||0|0.5||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-2.5|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-2.5|0|||RR|
+NPin|pin@14||-2|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-1|-1|1|1||
+NPin|pin@17||-1|1|1|1||
+AThicker|net@0|||FS3150|pin@0||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@1|||FS450|pin@1||-0.5|0.75|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@2|||FS0|pin@3||0|0.5|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@3|||FS0|pin@8||0|1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-1|pin@11||0|-1|ART_color()I74
+AThicker|net@5|||FS1800|pin@13||-2.5|0|pin@14||-2|0|ART_color()I74
+AThicker|net@6|||FS2700|pin@8||0|1|pin@15||0|2|ART_color()I74
+AThicker|net@7|||FS900|pin@11||0|-1|pin@12||0|-2|ART_color()I74
+AThicker|net@8|||FS900|pin@9||-0.75|1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||-1|1|pin@16||-1|-1|ART_color()I74
+Eb||D5G1;|pin@5||B
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOS4f_low;1{sch}
+CPMOS4f_low;1{sch}||schematic|1021415734000|1158015601561||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_CDL_template(D5G1;NTX1;Y-15;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  VTL-P-Transistor|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1.5;Y-17;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4f_low;1{ic}|PMOS4f@0||17.25|10.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||5|8||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|24|||||ART_message(D5G6;)SPMOS4f_low
+Ngeneric:Invisible-Pin|pin@3||-1.5|18.5|||||ART_message(D5G2;)S4-terminal low-threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Spch_lvt
+Awire|net@0|||0|pmos4p@0|g|-3|7|conn@2|y|-10|7
+Awire|net@1|||1800|pin@0||0|11.5|conn@0|a|3|11.5
+Awire|net@2|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
+Awire|net@3|||1800|pmos4p@0|b|0|8|conn@1|a|3|8
+Awire|net@4|||0|conn@3|a|3|1|pin@1||0|1
+Awire|net@5|||2700|pin@1||0|1|pmos4p@0|d|0|5
+Eb||D5G2;|conn@1|y|B
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4fwk;1{ic}
+CPMOS4fwk;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I74
+Nschematic:Bus_Pin|pin@0||0|0.5||||
+NPin|pin@1||-0.75|0.5|1|1|Y|
+NPin|pin@2||0|0.5||||
+NPin|pin@3||-0.5|0.25|1|1|YRR|
+NPin|pin@4||-0.75|0.5|1|1|Y|
+NPin|pin@5||-0.5|0.75|1|1|YRR|
+NPin|pin@6||-0.75|0.5|1|1|Y|
+NPin|pin@7||-1.25|-0.75|1|1|Y|
+NPin|pin@8||-1.25|0.75|1|1|Y|
+NPin|pin@9||0|2||||
+NPin|pin@10||-1.75|0|1|1|RRR|
+NPin|pin@11||-3|0|||RR|
+NPin|pin@12||0|-2||||
+NPin|pin@13||0|-0.75||||
+NPin|pin@14||-0.75|-0.75|1|1||
+NPin|pin@15||-0.75|0.75|1|1||
+NPin|pin@16||0|0.75||||
+Nschematic:Bus_Pin|pin@17||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@18||0|-2|-2|-2||
+Ngeneric:Invisible-Pin|pin@19||0|2||||
+Ngeneric:Invisible-Pin|pin@20||-0.5|0|||||ART_message(D5G1;)S[wk]
+AThicker|net@0|||FS0|pin@2||0|0.5|pin@1||-0.75|0.5|ART_color()I74
+AThicker|net@1|||FS3150|pin@3||-0.5|0.25|pin@4||-0.75|0.5|ART_color()I74
+AThicker|net@2|||FS450|pin@5||-0.5|0.75|pin@6||-0.75|0.5|ART_color()I74
+AThicker|net@3|||FS2700|pin@7||-1.25|-0.75|pin@8||-1.25|0.75|ART_color()I74
+AThicker|net@4|||FS900|pin@15||-0.75|0.75|pin@14||-0.75|-0.75|ART_color()I74
+AThicker|net@5|||FS900|pin@13||0|-0.75|pin@12||0|-2|ART_color()I74
+AThicker|net@6|||FS2700|pin@16||0|0.75|pin@9||0|2|ART_color()I74
+AThicker|net@7|||FS1800|pin@11||-3|0|pin@10||-1.75|0|ART_color()I74
+AThicker|net@8|||FS1800|pin@14||-0.75|-0.75|pin@13||0|-0.75|ART_color()I74
+AThicker|net@9|||FS0|pin@16||0|0.75|pin@15||-0.75|0.75|ART_color()I74
+Eb||D5G1;|pin@0||B
+Ed||D8G1;|pin@18||B
+Eg||D6G1;|pin@17||I
+Es||D2G1;|pin@19||B
+X
+
+# Cell PMOS4fwk;1{sch}
+CPMOS4fwk;1{sch}||schematic|1021415734000|1159313551113||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y3;)S3|ATTR_CDL_template(D5G1;NTX-2;Y-12.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template(D5G1;NTX-2;Y-8;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-1.5;Y-14.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-5.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-2.5;Y-10;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4fwk;1{ic}|PMOS4fwk@0||23.25|13.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|8||||
+NOff-Page|conn@1||5|1||||
+NOff-Page|conn@2||-8|7||||
+NOff-Page|conn@3||5|11.5||||
+Ngeneric:Invisible-Pin|pin@0||-1.5|19.5|||||ART_message(D5G2;)S4-terminal standard threshold weak PMOS device
+Ngeneric:Invisible-Pin|pin@1||-1|26|||||ART_message(D5G6;)SPMOS4fwk
+NWire_Pin|pin@2||0|1||||
+NWire_Pin|pin@3||0|11.5||||
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch|SIM_weak_node(D5G1;)SWeak
+Awire|net@0|||1800|pmos4p@0|b|0|8|conn@0|a|3|8
+Awire|net@1|||1800|conn@2|y|-6|7|pmos4p@0|g|-3|7
+Awire|net@2|||2700|pin@2||0|1|pmos4p@0|d|0|5
+Awire|net@3|||0|conn@1|a|3|1|pin@2||0|1
+Awire|net@4|||2700|pmos4p@0|s|0|9|pin@3||0|11.5
+Awire|net@5|||1800|pin@3||0|11.5|conn@3|a|3|11.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@3|y|B
+X
+
+# Cell PMOS4fwk_high;1{ic}
+CPMOS4fwk_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.75|0|0.5|0.5|RR||ART_color()I74
+Nschematic:Bus_Pin|pin@0||0|0.5||||
+NPin|pin@1||-0.75|0.5|1|1|Y|
+NPin|pin@2||0|0.5||||
+NPin|pin@3||-0.5|0.25|1|1|YRR|
+NPin|pin@4||-0.75|0.5|1|1|Y|
+NPin|pin@5||-0.5|0.75|1|1|YRR|
+NPin|pin@6||-0.75|0.5|1|1|Y|
+NPin|pin@7||-1.5|-0.75|1|1|Y|
+NPin|pin@8||-1.5|0.75|1|1|Y|
+NPin|pin@9||0|2||||
+NPin|pin@10||-2|0|1|1|RRR|
+NPin|pin@11||-3|0|||RR|
+NPin|pin@12||0|-2||||
+NPin|pin@13||0|-0.75||||
+NPin|pin@14||-0.75|-0.75|1|1||
+NPin|pin@15||-0.75|0.75|1|1||
+NPin|pin@16||0|0.75||||
+Nschematic:Bus_Pin|pin@17||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@18||0|-2|-2|-2||
+Ngeneric:Invisible-Pin|pin@19||0|2||||
+Ngeneric:Invisible-Pin|pin@20||-0.5|0|||||ART_message(D5G1;)S[wk]
+AThicker|net@0|||FS0|pin@2||0|0.5|pin@1||-0.75|0.5|ART_color()I74
+AThicker|net@1|||FS3150|pin@3||-0.5|0.25|pin@4||-0.75|0.5|ART_color()I74
+AThicker|net@2|||FS450|pin@5||-0.5|0.75|pin@6||-0.75|0.5|ART_color()I74
+AThicker|net@3|||FS2700|pin@7||-1.5|-0.75|pin@8||-1.5|0.75|ART_color()I74
+AThicker|net@4|||FS900|pin@15||-0.75|0.75|pin@14||-0.75|-0.75|ART_color()I74
+AThicker|net@5|||FS900|pin@13||0|-0.75|pin@12||0|-2|ART_color()I74
+AThicker|net@6|||FS2700|pin@16||0|0.75|pin@9||0|2|ART_color()I74
+AThicker|net@7|||FS1800|pin@11||-3|0|pin@10||-2|0|ART_color()I74
+AThicker|net@8|||FS1800|pin@14||-0.75|-0.75|pin@13||0|-0.75|ART_color()I74
+AThicker|net@9|||FS0|pin@16||0|0.75|pin@15||-0.75|0.75|ART_color()I74
+Eb||D5G1;|pin@0||B
+Ed||D8G1;|pin@18||B
+Eg||D6G1;|pin@17||I
+Es||D2G1;|pin@19||B
+X
+
+# Cell PMOS4fwk_high;1{sch}
+CPMOS4fwk_high;1{sch}||schematic|1021415734000|1159313533312||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y3;)S3|ATTR_CDL_template(D5G1;NTX-0.5;Y-14;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTY-12;)StransistorType  VTH-P-Transistor|ATTR_SPICE_template(D5G1;NTX1.5;Y-8;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTY-16;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-5.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_hvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-3;Y-10;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4fwk_high;1{ic}|PMOS4fwk@0||23.25|13.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|8||||
+NOff-Page|conn@1||5|1||||
+NOff-Page|conn@2||-8|7||||
+NOff-Page|conn@3||5|11.5||||
+Ngeneric:Invisible-Pin|pin@0||-1.5|19.5|||||ART_message(D5G2;)S4-terminal high-threshold weak PMOS device
+Ngeneric:Invisible-Pin|pin@1||-1|26|||||ART_message(D5G6;)SPMOS4wk_high
+NWire_Pin|pin@2||0|1||||
+NWire_Pin|pin@3||0|11.5||||
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3.5;)Spch_hvt|SIM_weak_node(D5G1;)SWeak
+Awire|net@0|||1800|pmos4p@0|b|0|8|conn@0|a|3|8
+Awire|net@1|||1800|conn@2|y|-6|7|pmos4p@0|g|-3|7
+Awire|net@2|||2700|pin@2||0|1|pmos4p@0|d|0|5
+Awire|net@3|||0|conn@1|a|3|1|pin@2||0|1
+Awire|net@4|||2700|pmos4p@0|s|0|9|pin@3||0|11.5
+Awire|net@5|||1800|pin@3||0|11.5|conn@3|a|3|11.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@3|y|B
+X
+
+# Cell PMOS4fwk_io18;1{ic}
+CPMOS4fwk_io18;1{ic}||artwork|1021415734000|1213400548226|E|ATTR_Delay(D5G1;HNPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX3;Y1;)S3|ATTR_goop(D5G1;HNPX3.25;Y-3.5;)I1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|||ART_color()I74
+NPin|pin@0||-0.5|0.25|1|1|YRR|
+NPin|pin@1||-0.5|0.75|1|1|YRR|
+NPin|pin@2||-0.75|0.5|1|1|Y|
+NPin|pin@3||0|0.5||||
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Ngeneric:Invisible-Pin|pin@5||0|0.5||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-3.5|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-3.5|0|||RR|
+NPin|pin@14||-3|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-2|-1|1|1||
+NPin|pin@17||-2|1|1|1||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+Ngeneric:Invisible-Pin|pin@19||0|-0.5|||||ART_message(D5G1;)Swk
+AThicker|net@0|||FS3150|pin@0||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@1|||FS450|pin@1||-0.5|0.75|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@2|||FS0|pin@3||0|0.5|pin@2||-0.75|0.5|ART_color()I74
+AThicker|net@3|||FS0|pin@8||0|1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-1|pin@11||0|-1|ART_color()I74
+AThicker|net@5|||FS1800|pin@13||-3.5|0|pin@14||-3|0|ART_color()I74
+AThicker|net@6|||FS2700|pin@8||0|1|pin@15||0|2|ART_color()I74
+AThicker|net@7|||FS900|pin@11||0|-1|pin@12||0|-2|ART_color()I74
+AThicker|net@8|||FS900|pin@9||-0.75|1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||-2|1|pin@16||-2|-1|ART_color()I74
+Eb||D5G1;|pin@5||B
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOS4fwk_io18;1{sch}
+CPMOS4fwk_io18;1{sch}||schematic|1021415734000|1213400840108||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_goop(D5G1;HNPX-8.75;Y-2.5;)I1|ATTR_CDL_template(D5G1;NTX1;Y-15.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  OD18-P-Transistor|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1.5;Y-17.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)*0.05u' L='$(L)*0.05u' M='$(goop)'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) $(b) pch_18 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4fwk_io18;1{ic}|PMOS4fwk@0||23.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S4|ATTR_W(D5FLeave alone;G1;NOLPX3;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||5|8||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|27|||||ART_message(D5G6;)SPMOS4fwk_io18
+Ngeneric:Invisible-Pin|pin@3||-1.5|21.5|||||ART_message(D5G2;)S4-terminal PMOS device for 1.8V I/O pads
+Ngeneric:Invisible-Pin|pin@4||-1|17.5|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 4
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3.5;)Spch_18
+Awire|net@0|||0|pmos4p@0|g|-3|7|conn@2|y|-10|7
+Awire|net@1|||1800|pin@0||0|11.5|conn@0|a|3|11.5
+Awire|net@2|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
+Awire|net@3|||1800|pmos4p@0|b|0|8|conn@1|a|3|8
+Awire|net@4|||0|conn@3|a|3|1|pin@1||0|1
+Awire|net@5|||2700|pin@1||0|1|pmos4p@0|d|0|5
+Eb||D5G2;|conn@1|y|B
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4fwk_low;1{ic}
+CPMOS4fwk_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.25|0|0.5|0.5|RR||ART_color()I74
+Nschematic:Bus_Pin|pin@0||0|0.5||||
+NPin|pin@1||-0.75|0.5|1|1|Y|
+NPin|pin@2||0|0.5||||
+NPin|pin@3||-0.5|0.25|1|1|YRR|
+NPin|pin@4||-0.75|0.5|1|1|Y|
+NPin|pin@5||-0.5|0.75|1|1|YRR|
+NPin|pin@6||-0.75|0.5|1|1|Y|
+NPin|pin@7||-1|-0.75|1|1|Y|
+NPin|pin@8||-1|0.75|1|1|Y|
+NPin|pin@9||0|2||||
+NPin|pin@10||-1.5|0|1|1|RRR|
+NPin|pin@11||-2.5|0|||RR|
+NPin|pin@12||0|-2||||
+NPin|pin@13||0|-0.75||||
+NPin|pin@14||-0.75|-0.75|1|1||
+NPin|pin@15||-0.75|0.75|1|1||
+NPin|pin@16||0|0.75||||
+Nschematic:Bus_Pin|pin@17||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@18||0|-2|-2|-2||
+Ngeneric:Invisible-Pin|pin@19||0|2||||
+Ngeneric:Invisible-Pin|pin@20||-0.5|0|||||ART_message(D5G1;)S[wk]
+AThicker|net@0|||FS0|pin@2||0|0.5|pin@1||-0.75|0.5|ART_color()I74
+AThicker|net@1|||FS3150|pin@3||-0.5|0.25|pin@4||-0.75|0.5|ART_color()I74
+AThicker|net@2|||FS450|pin@5||-0.5|0.75|pin@6||-0.75|0.5|ART_color()I74
+AThicker|net@3|||FS2700|pin@7||-1|-0.75|pin@8||-1|0.75|ART_color()I74
+AThicker|net@4|||FS900|pin@15||-0.75|0.75|pin@14||-0.75|-0.75|ART_color()I74
+AThicker|net@5|||FS900|pin@13||0|-0.75|pin@12||0|-2|ART_color()I74
+AThicker|net@6|||FS2700|pin@16||0|0.75|pin@9||0|2|ART_color()I74
+AThicker|net@7|||FS1800|pin@11||-2.5|0|pin@10||-1.5|0|ART_color()I74
+AThicker|net@8|||FS1800|pin@14||-0.75|-0.75|pin@13||0|-0.75|ART_color()I74
+AThicker|net@9|||FS0|pin@16||0|0.75|pin@15||-0.75|0.75|ART_color()I74
+Eb||D5G1;|pin@0||B
+Ed||D8G1;|pin@18||B
+Eg||D6G1;|pin@17||I
+Es||D2G1;|pin@19||B
+X
+
+# Cell PMOS4fwk_low;1{sch}
+CPMOS4fwk_low;1{sch}||schematic|1021415734000|1159313568663||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y3;)S3|ATTR_CDL_template(D5G1;NTX-2;Y-14.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-2;Y-12;)StransistorType  VTL-P-Transistor|ATTR_SPICE_template(D5G1;NTX-2.5;Y-8;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-1.5;Y-16.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX-2;Y-5.5;)SM$(node_name) $(d) $(g) $(s) $(b) pch_lvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-3;Y-10;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOS4fwk_low;1{ic}|PMOS4fwk@0||23.25|13.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|8||||
+NOff-Page|conn@1||5|1||||
+NOff-Page|conn@2||-8|7||||
+NOff-Page|conn@3||5|11.5||||
+Ngeneric:Invisible-Pin|pin@0||-1.5|19.5|||||ART_message(D5G2;)S4-terminal low-threshold weak PMOS device
+Ngeneric:Invisible-Pin|pin@1||-1|26|||||ART_message(D5G6;)SPMOS4fwk_low
+NWire_Pin|pin@2||0|1||||
+NWire_Pin|pin@3||0|11.5||||
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Spch_lvt|SIM_weak_node(D5G1;)SWeak
+Awire|net@0|||1800|pmos4p@0|b|0|8|conn@0|a|3|8
+Awire|net@1|||1800|conn@2|y|-6|7|pmos4p@0|g|-3|7
+Awire|net@2|||2700|pin@2||0|1|pmos4p@0|d|0|5
+Awire|net@3|||0|conn@1|a|3|1|pin@2||0|1
+Awire|net@4|||2700|pmos4p@0|s|0|9|pin@3||0|11.5
+Awire|net@5|||1800|pin@3||0|11.5|conn@3|a|3|11.5
+Eb||D5G2;|conn@0|y|B
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@3|y|B
+X
+
+# Cell PMOS4x;1{ic}
+CPMOS4x;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|1|1|RR||ART_color()I10
+NPin|pin@0||0|0.5||||
+NPin|pin@1||-0.75|0.5|1|1|Y|
+NPin|pin@2||-0.75|0.5|1|1|Y|
+NPin|pin@3||-0.5|0.25|1|1|YRR|
+NPin|pin@4||-0.75|0.5|1|1|Y|
+NPin|pin@5||-0.5|0.75|1|1|YRR|
+Nschematic:Bus_Pin|pin@6||0|0.5||||
+NPin|pin@7||-1.5|-1|1|1|Y|
+NPin|pin@8||-1.5|1|1|1|Y|
+NPin|pin@9||0|2||||
+NPin|pin@10||-2.5|0|1|1|RRR|
+NPin|pin@11||-3|0|||RR|
+NPin|pin@12||0|-2||||
+NPin|pin@13||0|-1||||
+NPin|pin@14||-0.75|-1|1|1||
+NPin|pin@15||-0.75|1|1|1||
+NPin|pin@16||0|1||||
+Nschematic:Bus_Pin|pin@17||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@18||0|-2|-2|-2||
+Ngeneric:Invisible-Pin|pin@19||0|2||||
+AThicker|net@0|||FS3150|pin@3||-0.5|0.25|pin@2||-0.75|0.5|ART_color()I10
+AThicker|net@1|||FS450|pin@5||-0.5|0.75|pin@4||-0.75|0.5|ART_color()I10
+AThicker|net@2|||FS0|pin@0||0|0.5|pin@1||-0.75|0.5|ART_color()I10
+AThicker|net@3|||FS2700|pin@7||-1.5|-1|pin@8||-1.5|1|ART_color()I10
+AThicker|net@4|||FS900|pin@15||-0.75|1|pin@14||-0.75|-1|ART_color()I10
+AThicker|net@5|||FS900|pin@13||0|-1|pin@12||0|-2|ART_color()I10
+AThicker|net@6|||FS2700|pin@16||0|1|pin@9||0|2|ART_color()I10
+AThicker|net@7|||FS1800|pin@11||-3|0|pin@10||-2.5|0|ART_color()I10
+AThicker|net@8|||FS1800|pin@14||-0.75|-1|pin@13||0|-1|ART_color()I10
+AThicker|net@9|||FS0|pin@16||0|1|pin@15||-0.75|1|ART_color()I10
+Epower|b|D5G1;|pin@6||P
+Ed||D8G1;|pin@18||B
+Eg||D6G1;|pin@17||I
+Es||D2G1;|pin@19||B
+X
+
+# Cell PMOS4x;1{sch}
+CPMOS4x;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOS4x;1{ic}|PMOS4@0||18.75|14|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+IPMOS4f;1{ic}|PMOS4f@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||12.5|7.5|||YRR|
+NOff-Page|conn@1||5|1||||
+NOff-Page|conn@2||-17.5|7||||
+NOff-Page|conn@3||5|11.5||||
+Ngeneric:Invisible-Pin|pin@0||-0.5|18.5|||||ART_message(D5G2;)S[4 terminal strength-based PMOS device]
+Ngeneric:Invisible-Pin|pin@1||-0.5|23.5|||||ART_message(D5G6;)SPMOS4x
+NWire_Pin|pin@2||0|1||||
+NWire_Pin|pin@3||0|11.5||||
+Awire|net@0|||1800|PMOS4f@0|b|0|7.5|conn@0|y|10.5|7.5
+Awire|net@1|||900|pin@3||0|11.5|PMOS4f@0|s|0|9
+Awire|net@2|||0|PMOS4f@0|g|-3|7|conn@2|y|-15.5|7
+Awire|net@3|||2700|pin@2||0|1|PMOS4f@0|d|0|5
+Awire|net@4|||0|conn@1|a|3|1|pin@2||0|1
+Awire|net@5|||1800|pin@3||0|11.5|conn@3|a|3|11.5
+Epower|b|D4G2;|conn@0|a|P
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@3|y|B
+X
+
+# Cell PMOS4x_io18;1{ic}
+CPMOS4x_io18;1{ic}||artwork|1021415734000|1213379062394|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|RR||ART_color()I10
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3.5|0|||RR|
+NPin|pin@9||-3|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-2|1|1|1|Y|
+NPin|pin@12||-2|-1|1|1|Y|
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+Nschematic:Bus_Pin|pin@14||0|0.5|-2|-2||
+NPin|pin@15||0|0.5|1|1||
+NPin|pin@16||-0.75|0.5|1|1||
+NPin|pin@17||-0.5|0.75|1|1||
+NPin|pin@18||-0.5|0.25|1|1||
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I10
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I10
+AThicker|net@2|||FS1800|pin@8||-3.5|0|pin@9||-3|0|ART_color()I10
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I10
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I10
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I10
+AThicker|net@6|||FS2700|pin@12||-2|-1|pin@11||-2|1|ART_color()I10
+AThicker|net@7|||FS0|pin@15||0|0.5|pin@16||-0.75|0.5|ART_color()I10
+AThicker|net@9|||FS2250|pin@16||-0.75|0.5|pin@17||-0.5|0.75|ART_color()I10
+AThicker|net@10|||FS1350|pin@16||-0.75|0.5|pin@18||-0.5|0.25|ART_color()I10
+Eb||D8G1;|pin@14||B
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOS4x_io18;1{sch}
+CPMOS4x_io18;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOS4x_io18;1{ic}|PMOS@0||18.5|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+IPMOS4f_io18;1{ic}|PMOSf@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (4 - 0.4) / @X + 0.4) : 4|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||-9.5|7||||
+NOff-Page|conn@2||5|1||||
+NOff-Page|conn@3||5|7.5||||
+NWire_Pin|pin@1||0|11.5||||
+NWire_Pin|pin@2||0|1||||
+Ngeneric:Invisible-Pin|pin@3||-0.5|23.5|||||ART_message(D5G6;)SPMOS4x_io18
+Ngeneric:Invisible-Pin|pin@4||-0.5|18.5|||||ART_message(D5G2;)S4 terminal strength-based PMOS device for 1.8V I/O pads
+Awire|net@0|||0|PMOSf@0|g|-3.5|7|conn@1|y|-7.5|7
+Awire|net@1|||900|pin@1||0|11.5|PMOSf@0|s|0|9
+Awire|net@2|||2700|pin@2||0|1|PMOSf@0|d|0|5
+Awire|net@3|||1800|pin@1||0|11.5|conn@0|a|3|11.5
+Awire|net@4|||0|conn@2|a|3|1|pin@2||0|1
+Awire|net@8|||0|conn@3|a|3|7.5|PMOSf@0|b|0|7.5
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4x_io25;1{ic}
+CPMOS4x_io25;1{ic}||artwork|1021415734000|1213379062398|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|RR||ART_color()I10
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3.5|0|||RR|
+NPin|pin@9||-3|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-2|1|1|1|Y|
+NPin|pin@12||-2|-1|1|1|Y|
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S2.5V
+Nschematic:Bus_Pin|pin@14||0|0.5|-2|-2||
+NPin|pin@15||0|0.5|1|1||
+NPin|pin@16||-0.75|0.5|1|1||
+NPin|pin@17||-0.5|0.75|1|1||
+NPin|pin@18||-0.5|0.25|1|1||
+AThicker|net@0|||FS1800|pin@4||-0.75|1|pin@3||0|1|ART_color()I10
+AThicker|net@1|||FS0|pin@6||0|-1|pin@5||-0.75|-1|ART_color()I10
+AThicker|net@2|||FS0|pin@9||-3|0|pin@8||-3.5|0|ART_color()I10
+AThicker|net@3|||FS900|pin@10||0|2|pin@3||0|1|ART_color()I10
+AThicker|net@4|||FS2700|pin@7||0|-2|pin@6||0|-1|ART_color()I10
+AThicker|net@5|||FS2700|pin@5||-0.75|-1|pin@4||-0.75|1|ART_color()I10
+AThicker|net@6|||FS900|pin@11||-2|1|pin@12||-2|-1|ART_color()I10
+AThicker|net@7|||FS1800|pin@16||-0.75|0.5|pin@15||0|0.5|ART_color()I10
+AThicker|net@9|||FS450|pin@17||-0.5|0.75|pin@16||-0.75|0.5|ART_color()I10
+AThicker|net@10|||FS3150|pin@18||-0.5|0.25|pin@16||-0.75|0.5|ART_color()I10
+Eb||D8G1;|pin@14||B
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOS4x_io25;1{sch}
+CPMOS4x_io25;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOS4x_io25;1{ic}|PMOS@0||18.5|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+IPMOS4f_io25;1{ic}|PMOSf@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (5.6 - 0.4) / @X + 0.4) : 5.6|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||7|11.5||||
+NOff-Page|conn@1||-9.5|7||||
+NOff-Page|conn@2||7|1||||
+NOff-Page|conn@3||7|7.5||||
+NWire_Pin|pin@1||0|11.5||||
+NWire_Pin|pin@2||0|1||||
+Ngeneric:Invisible-Pin|pin@3||-0.5|23.5|||||ART_message(D5G6;)SPMOS4x_io25
+Ngeneric:Invisible-Pin|pin@4||-0.5|18.5|||||ART_message(D5G2;)S4 terminal strength-based PMOS device for 2.5V I/O pads
+Awire|net@0|||0|PMOSf@0|g|-3.5|7|conn@1|y|-7.5|7
+Awire|net@1|||900|pin@1||0|11.5|PMOSf@0|s|0|9
+Awire|net@2|||2700|pin@2||0|1|PMOSf@0|d|0|5
+Awire|net@3|||0|conn@0|a|5|11.5|pin@1||0|11.5
+Awire|net@4|||1800|pin@2||0|1|conn@2|a|5|1
+Awire|net@8|||0|conn@3|a|5|7.5|PMOSf@0|b|0|7.5
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4x_io33;1{ic}
+CPMOS4x_io33;1{ic}||artwork|1021415734000|1213379062400|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|RR||ART_color()I10
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3.5|0|||RR|
+NPin|pin@9||-3|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-2|1|1|1|Y|
+NPin|pin@12||-2|-1|1|1|Y|
+Ngeneric:Invisible-Pin|pin@13||-2.25|1.75|||||ART_message(D5G1;)S3.3V
+Nschematic:Bus_Pin|pin@14||0|0.5|-2|-2||
+NPin|pin@15||0|0.5|1|1||
+NPin|pin@16||-0.75|0.5|1|1||
+NPin|pin@17||-0.5|0.75|1|1||
+NPin|pin@18||-0.5|0.25|1|1||
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I10
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I10
+AThicker|net@2|||FS1800|pin@8||-3.5|0|pin@9||-3|0|ART_color()I10
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I10
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I10
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I10
+AThicker|net@6|||FS2700|pin@12||-2|-1|pin@11||-2|1|ART_color()I10
+AThicker|net@7|||FS0|pin@15||0|0.5|pin@16||-0.75|0.5|ART_color()I10
+AThicker|net@9|||FS2250|pin@16||-0.75|0.5|pin@17||-0.5|0.75|ART_color()I10
+AThicker|net@10|||FS1350|pin@16||-0.75|0.5|pin@18||-0.5|0.25|ART_color()I10
+Eb||D8G1;|pin@14||B
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOS4x_io33;1{sch}
+CPMOS4x_io33;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOS4x_io33;1{ic}|PMOS@0||18.5|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+IPMOS4f_io33;1{ic}|PMOSf@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (7.6 - 0.4) / @X + 0.4) : 7.6|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||7|11.5||||
+NOff-Page|conn@1||-9.5|7||||
+NOff-Page|conn@2||7|1||||
+NOff-Page|conn@3||7|7.5||||
+NWire_Pin|pin@1||0|11.5||||
+NWire_Pin|pin@2||0|1||||
+Ngeneric:Invisible-Pin|pin@3||-0.5|23.5|||||ART_message(D5G6;)SPMOS4x_io33
+Ngeneric:Invisible-Pin|pin@4||-0.5|18.5|||||ART_message(D5G2;)S4 terminal strength-based PMOS device for 3.3V I/O pads
+Awire|net@0|||0|PMOSf@0|g|-3.5|7|conn@1|y|-7.5|7
+Awire|net@1|||900|pin@1||0|11.5|PMOSf@0|s|0|9
+Awire|net@2|||2700|pin@2||0|1|PMOSf@0|d|0|5
+Awire|net@3|||1800|pin@1||0|11.5|conn@0|a|5|11.5
+Awire|net@4|||0|conn@2|a|5|1|pin@2||0|1
+Awire|net@8|||0|conn@3|a|5|7.5|PMOSf@0|b|0|7.5
+Eb||D5G2;|conn@3|y|B
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOS4xwk;1{ic}
+CPMOS4xwk;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5G1.5;HNPX3.5;Y0.5;)I1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I10
+NPin|pin@0||-0.5|0.25|1|1|YRR|
+NPin|pin@1||-0.75|0.5|1|1|Y|
+NPin|pin@2||-0.5|0.75|1|1|YRR|
+NPin|pin@3||-0.75|0.5|1|1|Y|
+NPin|pin@4||-0.75|0.5|1|1|Y|
+NPin|pin@5||0|0.5||||
+Nschematic:Bus_Pin|pin@6||0|0.5||||
+Ngeneric:Invisible-Pin|pin@7||0|2||||
+Nschematic:Bus_Pin|pin@8||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@9||-3|0|-2|-2||
+NPin|pin@10||0|0.75||||
+NPin|pin@11||-0.75|0.75|1|1||
+NPin|pin@12||-0.75|-0.75|1|1||
+NPin|pin@13||0|-0.75||||
+NPin|pin@14||0|-2||||
+NPin|pin@15||-3|0|||RR|
+NPin|pin@16||-1.75|0|1|1|RRR|
+NPin|pin@17||0|2||||
+NPin|pin@18||-1.25|0.75|1|1|Y|
+NPin|pin@19||-1.25|-0.75|1|1|Y|
+Ngeneric:Invisible-Pin|pin@20||-0.5|0|||||ART_message(D5G1;)S[wk]
+AThicker|net@0|||FS3150|pin@0||-0.5|0.25|pin@1||-0.75|0.5|ART_color()I10
+AThicker|net@1|||FS0|pin@5||0|0.5|pin@4||-0.75|0.5|ART_color()I10
+AThicker|net@2|||FS450|pin@2||-0.5|0.75|pin@3||-0.75|0.5|ART_color()I10
+AThicker|net@3|||FS0|pin@10||0|0.75|pin@11||-0.75|0.75|ART_color()I10
+AThicker|net@4|||FS1800|pin@12||-0.75|-0.75|pin@13||0|-0.75|ART_color()I10
+AThicker|net@5|||FS1800|pin@15||-3|0|pin@16||-1.75|0|ART_color()I10
+AThicker|net@6|||FS2700|pin@10||0|0.75|pin@17||0|2|ART_color()I10
+AThicker|net@7|||FS900|pin@13||0|-0.75|pin@14||0|-2|ART_color()I10
+AThicker|net@8|||FS900|pin@11||-0.75|0.75|pin@12||-0.75|-0.75|ART_color()I10
+AThicker|net@9|||FS2700|pin@19||-1.25|-0.75|pin@18||-1.25|0.75|ART_color()I10
+Ed||D8G1;|pin@8||B
+Eg||D6G1;|pin@9||I
+Epower||D5G1;|pin@6||P
+Es||D2G1;|pin@7||B
+X
+
+# Cell PMOS4xwk;1{sch}
+CPMOS4xwk;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5G1;HNPX-8.5;Y1.25;)I1|prototype_center()I[0,0]
+IPMOS4fwk;1{ic}|PMOS4fwk@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5G1;NOJPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6G1;NOJPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3
+IPMOS4xwk;1{ic}|PMOS4wk@0||23.25|15.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||9.5|7.5|||YRR|
+NOff-Page|conn@1||5|11.5||||
+NOff-Page|conn@2||-8|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)S[PMOS4wk]
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S[4 terminal weak PMOS device]
+Awire|net@0|||1800|PMOS4fwk@0|b|0|7.5|conn@0|y|7.5|7.5
+Awire|net@1|||900|pin@0||0|11.5|PMOS4fwk@0|s|0|9
+Awire|net@2|||1800|conn@2|y|-6|7|PMOS4fwk@0|g|-3|7
+Awire|net@3|||2700|pin@1||0|1|PMOS4fwk@0|d|0|5
+Awire|net@4|||1800|pin@0||0|11.5|conn@1|a|3|11.5
+Awire|net@5|||0|conn@3|a|3|1|pin@1||0|1
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Epower||D4G2;|conn@0|a|P
+Es||D5G2;|conn@1|y|B
+X
+
+# Cell PMOSf;1{ic}
+CPMOSf;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3|0|||RR|
+NPin|pin@9||-2.5|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-1.5|1|1|1|Y|
+NPin|pin@12||-1.5|-1|1|1|Y|
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3|0|pin@9||-2.5|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-1.5|-1|pin@11||-1.5|1|ART_color()I74
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSf;1{sch}
+CPMOSf;1{sch}||schematic|1021415734000|1159313495771||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y3;)S3|ATTR_CDL_template(D5G1;NTX1.5;Y-15;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)'  DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-8;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX2.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf;1{ic}|PMOSf@0||26.75|20.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)S[PMOSf]
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S3-terminal standard threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-3;)Spch
+NPower|pwr@0||6|8||||
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSf_high;1{ic}
+CPMOSf_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3.5|0|||RR|
+NPin|pin@9||-3|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-2|1|1|1|Y|
+NPin|pin@12||-2|-1|1|1|Y|
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-3.5|0|pin@9||-3|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-2|-1|pin@11||-2|1|ART_color()I74
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSf_high;1{sch}
+CPMOSf_high;1{sch}||schematic|1021415734000|1159313478011||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y3;)S3|ATTR_CDL_template(D5G1;NTX-3.5;Y-16.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-3;Y-14.5;)StransistorType  VTH-P-Transistor|ATTR_SPICE_template(D5G1;NTX1.5;Y-10.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)'  DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-3;Y-18.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-8.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-3.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_high;1{ic}|PMOSf@0||26.75|20.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)SPMOSf_high
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S3-terminal high-threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1;Y-3;)Spch_hvt
+NPower|pwr@0||6|8||||
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSf_io18;1{ic}
+CPMOSf_io18;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX3;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|||ART_color()I74
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-3.5|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-3.5|0|||RR|
+NPin|pin@14||-3|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-2|-1|1|1||
+NPin|pin@17||-2|1|1|1||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S1.8V
+AThicker|net@3|||FS1800|pin@9||-0.75|1|pin@8||0|1|ART_color()I74
+AThicker|net@4|||FS0|pin@11||0|-1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@14||-3|0|pin@13||-3.5|0|ART_color()I74
+AThicker|net@6|||FS900|pin@15||0|2|pin@8||0|1|ART_color()I74
+AThicker|net@7|||FS2700|pin@12||0|-2|pin@11||0|-1|ART_color()I74
+AThicker|net@8|||FS2700|pin@10||-0.75|-1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@9|||FS2700|pin@16||-2|-1|pin@17||-2|1|ART_color()I74
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOSf_io18;1{sch}
+CPMOSf_io18;1{sch}||schematic|1021415734000|1159313459905||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S4|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_CDL_template(D5G1;NTX1.5;Y-15.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_18 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  OD18-P-Transistor|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) vdd pch_18 W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX2;Y-17.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_18 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) vdd pch_18 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_io18;1{ic}|PMOS4f@0||23.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S4|ATTR_W(D5FLeave alone;G1;NOLPX3;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|27|||||ART_message(D5G6;)SPMOSf_io18
+Ngeneric:Invisible-Pin|pin@3||-1.5|21.5|||||ART_message(D5G2;)S3-terminal PMOS device for 1.8V I/O pads
+Ngeneric:Invisible-Pin|pin@4||-1|17.5|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 4
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3.5;)Spch_18
+NPower|pwr@0||7|8||||
+Awire|net@0|||1800|conn@2|y|-10|7|pmos4p@0|g|-3|7
+Awire|net@1|||0|conn@0|a|3|11.5|pin@0||0|11.5
+Awire|net@2|||900|pin@0||0|11.5|pmos4p@0|s|0|9
+Awire|net@4|||1800|pin@1||0|1|conn@3|a|3|1
+Awire|net@5|||900|pmos4p@0|d|0|5|pin@1||0|1
+Awire|net@6|||0|pwr@0||7|8|pmos4p@0|b|0|8
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSf_io25;1{ic}
+CPMOSf_io25;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S5.6|ATTR_W(D5FLeave alone;G1;HNOLPX3;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|||ART_color()I74
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-3.5|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-3.5|0|||RR|
+NPin|pin@14||-3|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-2|-1|1|1||
+NPin|pin@17||-2|1|1|1||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S2.5V
+AThicker|net@3|||FS0|pin@8||0|1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@4|||FS1800|pin@10||-0.75|-1|pin@11||0|-1|ART_color()I74
+AThicker|net@5|||FS1800|pin@13||-3.5|0|pin@14||-3|0|ART_color()I74
+AThicker|net@6|||FS2700|pin@8||0|1|pin@15||0|2|ART_color()I74
+AThicker|net@7|||FS900|pin@11||0|-1|pin@12||0|-2|ART_color()I74
+AThicker|net@8|||FS900|pin@9||-0.75|1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@9|||FS900|pin@17||-2|1|pin@16||-2|-1|ART_color()I74
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOSf_io25;1{sch}
+CPMOSf_io25;1{sch}||schematic|1021415734000|1159313441380||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S5.6|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_CDL_template(D5G1;NTX2.5;Y-15.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  OD25-P-Transistor|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) vdd pch_25 W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX3;Y-17.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) vdd pch_25 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_io25;1{ic}|PMOS4f@0||23.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S5.6|ATTR_W(D5FLeave alone;G1;NOLPX3;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|27|||||ART_message(D5G6;)SPMOSf_io25
+Ngeneric:Invisible-Pin|pin@3||-1.5|21.5|||||ART_message(D5G2;)S3-terminal PMOS device for 2.5V I/O pads
+Ngeneric:Invisible-Pin|pin@4||-1|17.5|||||ART_message(D5G2;)Sminimum length for 2.5V thick-oxide devices is 5.6
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3.5;)Spch_25
+NPower|pwr@0||7|8||||
+Awire|net@0|||0|pmos4p@0|g|-3|7|conn@2|y|-10|7
+Awire|net@1|||1800|pin@0||0|11.5|conn@0|a|3|11.5
+Awire|net@2|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
+Awire|net@4|||0|conn@3|a|3|1|pin@1||0|1
+Awire|net@5|||2700|pin@1||0|1|pmos4p@0|d|0|5
+Awire|net@6|||0|pwr@0||7|8|pmos4p@0|b|0|8
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSf_io33;1{ic}
+CPMOSf_io33;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S7.6|ATTR_W(D5FLeave alone;G1;HNOLPX3;Y1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|||ART_color()I74
+Ngeneric:Invisible-Pin|pin@4||0|2||||
+Nschematic:Bus_Pin|pin@6||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@7||-3.5|0|-2|-2||
+NPin|pin@8||0|1||||
+NPin|pin@9||-0.75|1|1|1||
+NPin|pin@10||-0.75|-1|1|1||
+NPin|pin@11||0|-1||||
+NPin|pin@12||0|-2||||
+NPin|pin@13||-3.5|0|||RR|
+NPin|pin@14||-3|0|1|1|RR|
+NPin|pin@15||0|2||||
+NPin|pin@16||-2|-1|1|1||
+NPin|pin@17||-2|1|1|1||
+Ngeneric:Invisible-Pin|pin@18||-2.25|1.75|||||ART_message(D5G1;)S3.3V
+AThicker|net@3|||FS1800|pin@9||-0.75|1|pin@8||0|1|ART_color()I74
+AThicker|net@4|||FS0|pin@11||0|-1|pin@10||-0.75|-1|ART_color()I74
+AThicker|net@5|||FS0|pin@14||-3|0|pin@13||-3.5|0|ART_color()I74
+AThicker|net@6|||FS900|pin@15||0|2|pin@8||0|1|ART_color()I74
+AThicker|net@7|||FS2700|pin@12||0|-2|pin@11||0|-1|ART_color()I74
+AThicker|net@8|||FS2700|pin@10||-0.75|-1|pin@9||-0.75|1|ART_color()I74
+AThicker|net@9|||FS2700|pin@16||-2|-1|pin@17||-2|1|ART_color()I74
+Ed||D5G1;|pin@6||B
+Eg||D5G1;|pin@7||I
+Es||D5G1;|pin@4||B
+X
+
+# Cell PMOSf_io33;1{sch}
+CPMOSf_io33;1{sch}||schematic|1021415734000|1159313419552||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S7.6|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_CDL_template(D5G1;NTX1;Y-15.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  OD33-P-Transistor|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) vdd pch_33 W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1.5;Y-17.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_33 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) vdd pch_33 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_io33;1{ic}|PMOS4f@0||23.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S7.6|ATTR_W(D5FLeave alone;G1;NOLPX3;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|27|||||ART_message(D5G6;)SPMOSf_io33
+Ngeneric:Invisible-Pin|pin@3||-1.5|21.5|||||ART_message(D5G2;)S3-terminal PMOS device for 3.3V I/O pads
+Ngeneric:Invisible-Pin|pin@4||-1|17.5|||||ART_message(D5G2;)Sminimum length for 3.3V thick-oxide devices is 7.6
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3.5;)Spch_33
+NPower|pwr@0||7|8||||
+Awire|net@0|||1800|conn@2|y|-10|7|pmos4p@0|g|-3|7
+Awire|net@1|||0|conn@0|a|3|11.5|pin@0||0|11.5
+Awire|net@2|||900|pin@0||0|11.5|pmos4p@0|s|0|9
+Awire|net@4|||1800|pin@1||0|1|conn@3|a|3|1
+Awire|net@5|||900|pmos4p@0|d|0|5|pin@1||0|1
+Awire|net@6|||0|pwr@0||7|8|pmos4p@0|b|0|8
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSf_low;1{ic}
+CPMOSf_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.5|0|1|1|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-2.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-2.5|0|||RR|
+NPin|pin@9||-2|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-1|1|1|1|Y|
+NPin|pin@12||-1|-1|1|1|Y|
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I74
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I74
+AThicker|net@2|||FS1800|pin@8||-2.5|0|pin@9||-2|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I74
+AThicker|net@6|||FS2700|pin@12||-1|-1|pin@11||-1|1|ART_color()I74
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSf_low;1{sch}
+CPMOSf_low;1{sch}||schematic|1021415734000|1159313513376||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y3;)S3|ATTR_CDL_template(D5G1;NTX-2;Y-16.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-3;Y-14.5;)StransistorType  VTL-P-Transistor|ATTR_SPICE_template(D5G1;NTX2.5;Y-10.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)'  DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-1.5;Y-18.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-8.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-3.5;Y-12.5;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_low;1{ic}|PMOSf@0||26.75|20.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||8|12.5||||
+NOff-Page|conn@1||-14|7||||
+NOff-Page|conn@2||8.5|0||||
+NWire_Pin|pin@0||0|12.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||-0.5|23.5|||||ART_message(D5G6;)SPMOSf_low
+Ngeneric:Invisible-Pin|pin@3||-0.5|18.5|||||ART_message(D5G2;)S3-terminal low-threshold PMOS device
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Spch_lvt
+NPower|pwr@0||6|8||||
+Awire|net@0|||0|conn@2|a|6.5|0|pin@1||0|0
+Awire|net@1|||0|pmos4p@0|g|-3|7|conn@1|y|-12|7
+Awire|net@2|||0|conn@0|a|6|12.5|pin@0||0|12.5
+Awire|net@3|||2700|pmos4p@0|s|0|9|pin@0||0|12.5
+Awire|net@4|||2700|pin@1||0|0|pmos4p@0|d|0|5
+Awire|net@5|||1800|pmos4p@0|b|0|8|pwr@0||6|8
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSfwk;1{ic}
+CPMOSfwk;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|2||||
+Nschematic:Bus_Pin|pin@2||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+NPin|pin@4||0|0.75||||
+NPin|pin@5||-0.75|0.75|1|1||
+NPin|pin@6||-0.75|-0.75|1|1||
+NPin|pin@7||0|-0.75||||
+NPin|pin@8||0|-2||||
+NPin|pin@9||-3|0|||RR|
+NPin|pin@10||-1.75|0|1|1|RRR|
+NPin|pin@11||0|2||||
+NPin|pin@12||-1.25|0.75|1|1|Y|
+NPin|pin@13||-1.25|-0.75|1|1|Y|
+AThicker|net@0|||FS0|pin@4||0|0.75|pin@5||-0.75|0.75|ART_color()I74
+AThicker|net@1|||FS1800|pin@6||-0.75|-0.75|pin@7||0|-0.75|ART_color()I74
+AThicker|net@2|||FS1800|pin@9||-3|0|pin@10||-1.75|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@4||0|0.75|pin@11||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@7||0|-0.75|pin@8||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@5||-0.75|0.75|pin@6||-0.75|-0.75|ART_color()I74
+AThicker|net@6|||FS2700|pin@13||-1.25|-0.75|pin@12||-1.25|0.75|ART_color()I74
+Ed||D8G1;|pin@2||B
+Eg||D6G1;|pin@3||I
+Es||D2G1;|pin@1||B
+X
+
+# Cell PMOSfwk;1{sch}
+CPMOSfwk;1{sch}||schematic|1021415734000|1159313542858||ATTR_Delay(D5G1;HNPX-8.5;Y-4.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y-1.75;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;)S3|ATTR_CDL_template(D5G1;NTX-1.5;Y-17;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template(D5G1;NTX2;Y-12.5;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX-1;Y-19;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2;Y-10;)SM$(node_name) $(d) $(g) $(s) vdd pch W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-2.5;Y-14.5;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSfwk;1{ic}|PMOSfwk@0||28.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|8.5||||
+NOff-Page|conn@1||-8|4||||
+NOff-Page|conn@2||5|-2||||
+NWire_Pin|pin@0||0|8.5||||
+NWire_Pin|pin@1||0|-2||||
+Ngeneric:Invisible-Pin|pin@2||-1|22|||||ART_message(D5G6;)SPMOSfwk
+Ngeneric:Invisible-Pin|pin@3||-1.5|16.5|||||ART_message(D5G2;T)S3 terminal standard threshold weak PMOS device
+N4-Port-Transistor|pmos4p@0||-2|4|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X2;Y-2.5;)Spch|SIM_weak_node(D5G1;)SWeak
+NPower|pwr@0||6|5||||
+Awire|net@0|||1800|pin@0||0|8.5|conn@0|a|3|8.5
+Awire|net@1|||2700|pmos4p@0|s|0|6|pin@0||0|8.5
+Awire|net@2|||0|conn@2|a|3|-2|pin@1||0|-2
+Awire|net@3|||2700|pin@1||0|-2|pmos4p@0|d|0|2
+Awire|net@4|||1800|conn@1|y|-6|4|pmos4p@0|g|-3|4
+Awire|net@5|||1800|pmos4p@0|b|0|5|pwr@0||6|5
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSfwk_high;1{ic}
+CPMOSfwk_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.75|0|0.5|0.5|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|2||||
+Nschematic:Bus_Pin|pin@2||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@3||-3|0|-2|-2||
+NPin|pin@4||0|0.75||||
+NPin|pin@5||-0.75|0.75|1|1||
+NPin|pin@6||-0.75|-0.75|1|1||
+NPin|pin@7||0|-0.75||||
+NPin|pin@8||0|-2||||
+NPin|pin@9||-3|0|||RR|
+NPin|pin@10||-2|0|1|1|RRR|
+NPin|pin@11||0|2||||
+NPin|pin@12||-1.5|0.75|1|1|Y|
+NPin|pin@13||-1.5|-0.75|1|1|Y|
+AThicker|net@0|||FS0|pin@4||0|0.75|pin@5||-0.75|0.75|ART_color()I74
+AThicker|net@1|||FS1800|pin@6||-0.75|-0.75|pin@7||0|-0.75|ART_color()I74
+AThicker|net@2|||FS1800|pin@9||-3|0|pin@10||-2|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@4||0|0.75|pin@11||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@7||0|-0.75|pin@8||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@5||-0.75|0.75|pin@6||-0.75|-0.75|ART_color()I74
+AThicker|net@6|||FS2700|pin@13||-1.5|-0.75|pin@12||-1.5|0.75|ART_color()I74
+Ed||D8G1;|pin@2||B
+Eg||D6G1;|pin@3||I
+Es||D2G1;|pin@1||B
+X
+
+# Cell PMOSfwk_high;1{sch}
+CPMOSfwk_high;1{sch}||schematic|1021415734000|1159313524375||ATTR_Delay(D5G1;HNPX-8.5;Y-4.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y-1.75;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;)S3|ATTR_CDL_template(D5G1;NTX0.5;Y-19;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX-1;Y-16.5;)StransistorType  VTH-P-Transistor|ATTR_SPICE_template(D5G1;NTX0.5;Y-12.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-21;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2;Y-10;)SM$(node_name) $(d) $(g) $(s) vdd pch_hvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX-2.5;Y-14.5;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSfwk_high;1{ic}|PMOSfwk@0||28.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|8.5||||
+NOff-Page|conn@1||-8|4||||
+NOff-Page|conn@2||5|-2||||
+NWire_Pin|pin@0||0|8.5||||
+NWire_Pin|pin@1||0|-2||||
+Ngeneric:Invisible-Pin|pin@2||-1|22|||||ART_message(D5G6;)SPMOSwk_high
+Ngeneric:Invisible-Pin|pin@3||-1.5|16.5|||||ART_message(D5G2;T)S3 terminal high-threshold weak PMOS device
+N4-Port-Transistor|pmos4p@0||-2|4|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1;Y-3;)Spch_hvt|SIM_weak_node(D5G1;)SWeak
+NPower|pwr@0||6|5||||
+Awire|net@0|||1800|pin@0||0|8.5|conn@0|a|3|8.5
+Awire|net@1|||2700|pmos4p@0|s|0|6|pin@0||0|8.5
+Awire|net@2|||0|conn@2|a|3|-2|pin@1||0|-2
+Awire|net@3|||2700|pin@1||0|-2|pmos4p@0|d|0|2
+Awire|net@4|||1800|conn@1|y|-6|4|pmos4p@0|g|-3|4
+Awire|net@5|||1800|pmos4p@0|b|0|5|pwr@0||6|5
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSfwk_low;1{ic}
+CPMOSfwk_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;HNOLPX2;Y1;)S3|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.25|0|0.5|0.5|RR||ART_color()I74
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+Ngeneric:Invisible-Pin|pin@1||0|2||||
+Nschematic:Bus_Pin|pin@2||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@3||-2.5|0|-2|-2||
+NPin|pin@4||0|0.75||||
+NPin|pin@5||-0.75|0.75|1|1||
+NPin|pin@6||-0.75|-0.75|1|1||
+NPin|pin@7||0|-0.75||||
+NPin|pin@8||0|-2||||
+NPin|pin@9||-2.5|0|||RR|
+NPin|pin@10||-1.5|0|1|1|RRR|
+NPin|pin@11||0|2||||
+NPin|pin@12||-1|0.75|1|1|Y|
+NPin|pin@13||-1|-0.75|1|1|Y|
+AThicker|net@0|||FS0|pin@4||0|0.75|pin@5||-0.75|0.75|ART_color()I74
+AThicker|net@1|||FS1800|pin@6||-0.75|-0.75|pin@7||0|-0.75|ART_color()I74
+AThicker|net@2|||FS1800|pin@9||-2.5|0|pin@10||-1.5|0|ART_color()I74
+AThicker|net@3|||FS2700|pin@4||0|0.75|pin@11||0|2|ART_color()I74
+AThicker|net@4|||FS900|pin@7||0|-0.75|pin@8||0|-2|ART_color()I74
+AThicker|net@5|||FS900|pin@5||-0.75|0.75|pin@6||-0.75|-0.75|ART_color()I74
+AThicker|net@6|||FS2700|pin@13||-1|-0.75|pin@12||-1|0.75|ART_color()I74
+Ed||D8G1;|pin@2||B
+Eg||D6G1;|pin@3||I
+Es||D2G1;|pin@1||B
+X
+
+# Cell PMOSfwk_low;1{sch}
+CPMOSfwk_low;1{sch}||schematic|1021415734000|1159313559676||ATTR_Delay(D5G1;HNPX-8.5;Y-4.75;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y-1.75;)S2|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;)S3|ATTR_CDL_template(D5G1;NTY-19;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-16.5;)StransistorType  VTL-P-Transistor|ATTR_SPICE_template(D5G1;NTX3;Y-12.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX0.5;Y-21;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX2;Y-10;)SM$(node_name) $(d) $(g) $(s) vdd pch_lvt W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-14.5;)Srtranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSfwk_low;1{ic}|PMOSfwk@0||28.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S3|ATTR_GEO(T)I0|ATTR_M(T)I1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|8.5||||
+NOff-Page|conn@1||-8|4||||
+NOff-Page|conn@2||5|-2||||
+NWire_Pin|pin@0||0|8.5||||
+NWire_Pin|pin@1||0|-2||||
+Ngeneric:Invisible-Pin|pin@2||-1|22|||||ART_message(D5G6;)SPMOSfwk_low
+Ngeneric:Invisible-Pin|pin@3||-1.5|16.5|||||ART_message(D5G2;T)S3 terminal low-threshold weak PMOS device
+N4-Port-Transistor|pmos4p@0||-2|4|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Spch_lvt|SIM_weak_node(D5G1;)SWeak
+NPower|pwr@0||6|5||||
+Awire|net@0|||1800|pin@0||0|8.5|conn@0|a|3|8.5
+Awire|net@1|||2700|pmos4p@0|s|0|6|pin@0||0|8.5
+Awire|net@2|||0|conn@2|a|3|-2|pin@1||0|-2
+Awire|net@3|||2700|pin@1||0|-2|pmos4p@0|d|0|2
+Awire|net@4|||1800|conn@1|y|-6|4|pmos4p@0|g|-3|4
+Awire|net@5|||1800|pmos4p@0|b|0|5|pwr@0||6|5
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSx;1{ic}
+CPMOSx;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|1|1|RR||ART_color()I10
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3|0|||RR|
+NPin|pin@9||-2.5|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-1.5|1|1|1|Y|
+NPin|pin@12||-1.5|-1|1|1|Y|
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I10
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I10
+AThicker|net@2|||FS1800|pin@8||-3|0|pin@9||-2.5|0|ART_color()I10
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I10
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I10
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I10
+AThicker|net@6|||FS2700|pin@12||-1.5|-1|pin@11||-1.5|1|ART_color()I10
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSx;1{sch}
+CPMOSx;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOSx;1{ic}|PMOS@0||15.25|12.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+IPMOSf;1{ic}|PMOSf@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||-9.5|7||||
+NOff-Page|conn@2||5|1||||
+NWire_Pin|pin@1||0|11.5||||
+NWire_Pin|pin@2||0|1||||
+Ngeneric:Invisible-Pin|pin@3||-0.5|23.5|||||ART_message(D5G6;)SPMOSx
+Ngeneric:Invisible-Pin|pin@4||-0.5|18.5|||||ART_message(D5G2;)S3 terminal standard-threshold strength-based PMOS device
+Awire|net@0|||0|PMOSf@0|g|-3|7|conn@1|y|-7.5|7
+Awire|net@1|||900|pin@1||0|11.5|PMOSf@0|s|0|9
+Awire|net@2|||2700|pin@2||0|1|PMOSf@0|d|0|5
+Awire|net@3|||1800|pin@1||0|11.5|conn@0|a|3|11.5
+Awire|net@4|||0|conn@2|a|3|1|pin@2||0|1
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSx_high;1{ic}
+CPMOSx_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2.5|0|1|1|RR||ART_color()I10
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-3.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-3.5|0|||RR|
+NPin|pin@9||-3|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-2|1|1|1|Y|
+NPin|pin@12||-2|-1|1|1|Y|
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I10
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I10
+AThicker|net@2|||FS1800|pin@8||-3.5|0|pin@9||-3|0|ART_color()I10
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I10
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I10
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I10
+AThicker|net@6|||FS2700|pin@12||-2|-1|pin@11||-2|1|ART_color()I10
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSx_high;1{sch}
+CPMOSx_high;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOSx_high;1{ic}|PMOS@0||15.25|12.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+IPMOSf_high;1{ic}|PMOSf@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||-9.5|7||||
+NOff-Page|conn@2||5|1||||
+NWire_Pin|pin@1||0|11.5||||
+NWire_Pin|pin@2||0|1||||
+Ngeneric:Invisible-Pin|pin@3||-0.5|23.5|||||ART_message(D5G6;)SPMOSx_high
+Ngeneric:Invisible-Pin|pin@4||-0.5|18.5|||||ART_message(D5G2;)S3 terminal high-threshold strength-based PMOS device
+Awire|net@0|||0|PMOSf@0|g|-3.5|7|conn@1|y|-7.5|7
+Awire|net@1|||900|pin@1||0|11.5|PMOSf@0|s|0|9
+Awire|net@2|||2700|pin@2||0|1|PMOSf@0|d|0|5
+Awire|net@3|||1800|pin@1||0|11.5|conn@0|a|3|11.5
+Awire|net@4|||0|conn@2|a|3|1|pin@2||0|1
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSx_low;1{ic}
+CPMOSx_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.5|0|1|1|RR||ART_color()I10
+Ngeneric:Invisible-Pin|pin@0||0|2||||
+Nschematic:Bus_Pin|pin@1||0|-2|-2|-2||
+Nschematic:Bus_Pin|pin@2||-2.5|0|-2|-2||
+NPin|pin@3||0|1||||
+NPin|pin@4||-0.75|1|1|1||
+NPin|pin@5||-0.75|-1|1|1||
+NPin|pin@6||0|-1||||
+NPin|pin@7||0|-2||||
+NPin|pin@8||-2.5|0|||RR|
+NPin|pin@9||-2|0|1|1|RRR|
+NPin|pin@10||0|2||||
+NPin|pin@11||-1|1|1|1|Y|
+NPin|pin@12||-1|-1|1|1|Y|
+AThicker|net@0|||FS0|pin@3||0|1|pin@4||-0.75|1|ART_color()I10
+AThicker|net@1|||FS1800|pin@5||-0.75|-1|pin@6||0|-1|ART_color()I10
+AThicker|net@2|||FS1800|pin@8||-2.5|0|pin@9||-2|0|ART_color()I10
+AThicker|net@3|||FS2700|pin@3||0|1|pin@10||0|2|ART_color()I10
+AThicker|net@4|||FS900|pin@6||0|-1|pin@7||0|-2|ART_color()I10
+AThicker|net@5|||FS900|pin@4||-0.75|1|pin@5||-0.75|-1|ART_color()I10
+AThicker|net@6|||FS2700|pin@12||-1|-1|pin@11||-1|1|ART_color()I10
+Ed||D8G1;|pin@1||B
+Eg||D6G1;|pin@2||I
+Es||D2G1;|pin@0||B
+X
+
+# Cell PMOSx_low;1{sch}
+CPMOSx_low;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOSx_low;1{ic}|PMOS@0||15.25|12.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+IPMOSf_low;1{ic}|PMOSf@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@1||-9.5|7||||
+NOff-Page|conn@2||5|1||||
+NWire_Pin|pin@1||0|11.5||||
+NWire_Pin|pin@2||0|1||||
+Ngeneric:Invisible-Pin|pin@3||-0.5|23.5|||||ART_message(D5G6;)SPMOSx_low
+Ngeneric:Invisible-Pin|pin@4||-0.5|18.5|||||ART_message(D5G2;)S3 terminal low_threshold strength-based PMOS device
+Awire|net@0|||0|PMOSf@0|g|-2.5|7|conn@1|y|-7.5|7
+Awire|net@1|||900|pin@1||0|11.5|PMOSf@0|s|0|9
+Awire|net@2|||2700|pin@2||0|1|PMOSf@0|d|0|5
+Awire|net@3|||1800|pin@1||0|11.5|conn@0|a|3|11.5
+Awire|net@4|||0|conn@2|a|3|1|pin@2||0|1
+Ed||D5G2;|conn@2|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@0|y|B
+X
+
+# Cell PMOSxwk;1{ic}
+CPMOSxwk;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.5|0|0.5|0.5|RR||ART_color()I10
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+NPin|pin@1||-1.25|-0.75|1|1|Y|
+NPin|pin@2||-1.25|0.75|1|1|Y|
+NPin|pin@3||0|2||||
+NPin|pin@4||-1.75|0|1|1|RRR|
+NPin|pin@5||-3|0|||RR|
+NPin|pin@6||0|-2||||
+NPin|pin@7||0|-0.75||||
+NPin|pin@8||-0.75|-0.75|1|1||
+NPin|pin@9||-0.75|0.75|1|1||
+NPin|pin@10||0|0.75||||
+Nschematic:Bus_Pin|pin@11||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@12||0|-2|-2|-2||
+Ngeneric:Invisible-Pin|pin@13||0|2||||
+AThicker|net@0|||FS2700|pin@1||-1.25|-0.75|pin@2||-1.25|0.75|ART_color()I10
+AThicker|net@1|||FS900|pin@9||-0.75|0.75|pin@8||-0.75|-0.75|ART_color()I10
+AThicker|net@2|||FS900|pin@7||0|-0.75|pin@6||0|-2|ART_color()I10
+AThicker|net@3|||FS2700|pin@10||0|0.75|pin@3||0|2|ART_color()I10
+AThicker|net@4|||FS1800|pin@5||-3|0|pin@4||-1.75|0|ART_color()I10
+AThicker|net@5|||FS1800|pin@8||-0.75|-0.75|pin@7||0|-0.75|ART_color()I10
+AThicker|net@6|||FS0|pin@10||0|0.75|pin@9||-0.75|0.75|ART_color()I10
+Ed||D8G1;|pin@12||B
+Eg||D6G1;|pin@11||I
+Es||D2G1;|pin@13||B
+X
+
+# Cell PMOSxwk;1{sch}
+CPMOSxwk;1{sch}||schematic|1021415734000|1158010267102||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOSfwk;1{ic}|PMOSfwk@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3|ATTR_GEO()I0
+IPMOSxwk;1{ic}|PMOSwk@0||22.25|13.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|1||||
+NOff-Page|conn@1||-8|7||||
+NOff-Page|conn@2||5|11.5||||
+Ngeneric:Invisible-Pin|pin@0||-0.5|18.5|||||ART_message(D5G2;)S3 terminal standard threshold strength based weak PMOS device
+Ngeneric:Invisible-Pin|pin@1||-0.5|23.5|||||ART_message(D5G6;)SPMOSxwk
+NWire_Pin|pin@2||0|1||||
+NWire_Pin|pin@3||0|11.5||||
+Awire|net@0|||900|pin@3||0|11.5|PMOSfwk@0|s|0|9
+Awire|net@1|||1800|conn@1|y|-6|7|PMOSfwk@0|g|-3|7
+Awire|net@2|||2700|pin@2||0|1|PMOSfwk@0|d|0|5
+Awire|net@3|||0|conn@0|a|3|1|pin@2||0|1
+Awire|net@4|||1800|pin@3||0|11.5|conn@2|a|3|11.5
+Ed||D5G2;|conn@0|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@2|y|B
+X
+
+# Cell PMOSxwk_high;1{ic}
+CPMOSxwk_high;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|0.5|0.5|RR||ART_color()I10
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+NPin|pin@1||-1.75|-0.75|1|1|Y|
+NPin|pin@2||-1.75|0.75|1|1|Y|
+NPin|pin@3||0|2||||
+NPin|pin@4||-2.25|0|1|1|RRR|
+NPin|pin@5||-3|0|||RR|
+NPin|pin@6||0|-2||||
+NPin|pin@7||0|-0.75||||
+NPin|pin@8||-0.75|-0.75|1|1||
+NPin|pin@9||-0.75|0.75|1|1||
+NPin|pin@10||0|0.75||||
+Nschematic:Bus_Pin|pin@11||-3|0|-2|-2||
+Nschematic:Bus_Pin|pin@12||0|-2|-2|-2||
+Ngeneric:Invisible-Pin|pin@13||0|2||||
+AThicker|net@0|||FS2700|pin@1||-1.75|-0.75|pin@2||-1.75|0.75|ART_color()I10
+AThicker|net@1|||FS900|pin@9||-0.75|0.75|pin@8||-0.75|-0.75|ART_color()I10
+AThicker|net@2|||FS900|pin@7||0|-0.75|pin@6||0|-2|ART_color()I10
+AThicker|net@3|||FS2700|pin@10||0|0.75|pin@3||0|2|ART_color()I10
+AThicker|net@4|||FS1800|pin@5||-3|0|pin@4||-2.25|0|ART_color()I10
+AThicker|net@5|||FS1800|pin@8||-0.75|-0.75|pin@7||0|-0.75|ART_color()I10
+AThicker|net@6|||FS0|pin@10||0|0.75|pin@9||-0.75|0.75|ART_color()I10
+Ed||D8G1;|pin@12||B
+Eg||D6G1;|pin@11||I
+Es||D2G1;|pin@13||B
+X
+
+# Cell PMOSxwk_high;1{sch}
+CPMOSxwk_high;1{sch}||schematic|1021415734000|1158100857746||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOSfwk_high;1{ic}|PMOSfwk@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3|ATTR_GEO()I0
+IPMOSxwk_high;1{ic}|PMOSwk@0||22.25|13.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|1||||
+NOff-Page|conn@1||-8|7||||
+NOff-Page|conn@2||5|11.5||||
+Ngeneric:Invisible-Pin|pin@0||-0.5|18.5|||||ART_message(D5G2;)S3 terminal high-threshold strength based weak PMOS device
+Ngeneric:Invisible-Pin|pin@1||-0.5|23.5|||||ART_message(D5G6;)SPMOSxwk_high
+NWire_Pin|pin@2||0|1||||
+NWire_Pin|pin@3||0|11.5||||
+Awire|net@0|||900|pin@3||0|11.5|PMOSfwk@0|s|0|9
+Awire|net@1|||1800|conn@1|y|-6|7|PMOSfwk@0|g|-3|7
+Awire|net@2|||2700|pin@2||0|1|PMOSfwk@0|d|0|5
+Awire|net@3|||0|conn@0|a|3|1|pin@2||0|1
+Awire|net@4|||1800|pin@3||0|11.5|conn@2|a|3|11.5
+Ed||D5G2;|conn@0|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@2|y|B
+X
+
+# Cell PMOSxwk_low;1{ic}
+CPMOSxwk_low;1{ic}||artwork|1021415734000|1204183998562|E|ATTR_Delay(D5G1;HNPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;HNOLPX3.5;Y0.5;)S1|prototype_center()I[-8000,16000]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.25|0|0.5|0.5|RR||ART_color()I10
+Ngeneric:Invisible-Pin|pin@0||-0.5|0|||||ART_message(D5G1;)S[wk]
+NPin|pin@1||-1|-0.75|1|1|Y|
+NPin|pin@2||-1|0.75|1|1|Y|
+NPin|pin@3||0|2||||
+NPin|pin@4||-1.5|0|1|1|RRR|
+NPin|pin@5||-2.5|0|||RR|
+NPin|pin@6||0|-2||||
+NPin|pin@7||0|-0.75||||
+NPin|pin@8||-0.75|-0.75|1|1||
+NPin|pin@9||-0.75|0.75|1|1||
+NPin|pin@10||0|0.75||||
+Nschematic:Bus_Pin|pin@11||-2.5|0|-2|-2||
+Nschematic:Bus_Pin|pin@12||0|-2|-2|-2||
+Ngeneric:Invisible-Pin|pin@13||0|2||||
+AThicker|net@0|||FS2700|pin@1||-1|-0.75|pin@2||-1|0.75|ART_color()I10
+AThicker|net@1|||FS900|pin@9||-0.75|0.75|pin@8||-0.75|-0.75|ART_color()I10
+AThicker|net@2|||FS900|pin@7||0|-0.75|pin@6||0|-2|ART_color()I10
+AThicker|net@3|||FS2700|pin@10||0|0.75|pin@3||0|2|ART_color()I10
+AThicker|net@4|||FS1800|pin@5||-2.5|0|pin@4||-1.5|0|ART_color()I10
+AThicker|net@5|||FS1800|pin@8||-0.75|-0.75|pin@7||0|-0.75|ART_color()I10
+AThicker|net@6|||FS0|pin@10||0|0.75|pin@9||-0.75|0.75|ART_color()I10
+Ed||D8G1;|pin@12||B
+Eg||D6G1;|pin@11||I
+Es||D2G1;|pin@13||B
+X
+
+# Cell PMOSxwk_low;1{sch}
+CPMOSxwk_low;1{sch}||schematic|1021415734000|1158100860825||ATTR_Delay(D5G1;HNPX-8.5;Y-0.25;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-8.5;Y1.25;)S1|prototype_center()I[0,0]
+IPMOSfwk_low;1{ic}|PMOSfwk@0||0|7|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S@X == 0 ? 0 : @X < 0.5 ? (0.5 * (2 - 0.4) / @X + 0.4) : 2|ATTR_W(D6FLeave alone;G1;NOLPX2;Y1;)S@X > 0.5 ? 6.0*@X : 3|ATTR_GEO()I0
+IPMOSxwk_low;1{ic}|PMOSwk@0||22.25|13.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S1
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|1||||
+NOff-Page|conn@1||-8|7||||
+NOff-Page|conn@2||5|11.5||||
+Ngeneric:Invisible-Pin|pin@0||-0.5|18.5|||||ART_message(D5G2;)S3 terminal low-threshold strength based weak PMOS device
+Ngeneric:Invisible-Pin|pin@1||-0.5|23.5|||||ART_message(D5G6;)SPMOSxwk_low
+NWire_Pin|pin@2||0|1||||
+NWire_Pin|pin@3||0|11.5||||
+Awire|net@0|||900|pin@3||0|11.5|PMOSfwk@0|s|0|9
+Awire|net@1|||1800|conn@1|y|-6|7|PMOSfwk@0|g|-2.5|7
+Awire|net@2|||2700|pin@2||0|1|PMOSfwk@0|d|0|5
+Awire|net@3|||0|conn@0|a|3|1|pin@2||0|1
+Awire|net@4|||1800|pin@3||0|11.5|conn@2|a|3|11.5
+Ed||D5G2;|conn@0|y|B
+Eg||D5G2;|conn@1|a|I
+Es||D5G2;|conn@2|y|B
+X
+
+# Cell R110;1{ic}
+CR110;1{ic}||artwork|1047945855000|1213379062425|E|ATTR_L(D5FLeave alone;G1;HNOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX2.25;Y-2.25;)S8.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||3|0|1|1|Y|
+NPin|pin@1||2|0|1|1|Y|
+NPin|pin@2||1.5|-1|1|1|Y|
+NPin|pin@3||1|1|1|1|Y|
+NPin|pin@4||0.5|-1|1|1|Y|
+NPin|pin@5||0|1|1|1|Y|
+NPin|pin@6||-0.5|-1|1|1|Y|
+NPin|pin@7||-1|1|1|1|Y|
+NPin|pin@8||-1.5|-1|1|1|Y|
+NPin|pin@9||-2|0|1|1|Y|
+NPin|pin@10||-3|0|1|1|Y|
+Nschematic:Bus_Pin|pin@11||3|0||||
+Nschematic:Bus_Pin|pin@12||-3|0||||
+NPin|pin@13||-2.5|-0.75|1|1||
+NPin|pin@14||2.5|-0.75|1|1||
+NPin|pin@15||0|-1.5|1|1|YRRR|
+NPin|pin@16||0|-0.75|1|1|YRRR|
+NPin|pin@18||1|-1.5|1|1|YRR|
+NPin|pin@19||-1|-1.5|1|1|YRR|
+NPin|pin@20||0.5|-2|1|1|YRR|
+NPin|pin@21||-0.5|-2|1|1|YRR|
+Ngeneric:Invisible-Pin|pin@22||0.5|1|||||ART_message(D5G1;)S110
+AThicker|net@0|||FS1800|pin@1||2|0|pin@0||3|0|ART_color()I74
+AThicker|net@1|||FS2434|pin@2||1.5|-1|pin@1||2|0|ART_color()I74
+AThicker|net@2|||FS1040|pin@3||1|1|pin@2||1.5|-1|ART_color()I74
+AThicker|net@3|||FS2560|pin@4||0.5|-1|pin@3||1|1|ART_color()I74
+AThicker|net@4|||FS1040|pin@5||0|1|pin@4||0.5|-1|ART_color()I74
+AThicker|net@5|||FS2560|pin@6||-0.5|-1|pin@5||0|1|ART_color()I74
+AThicker|net@6|||FS1040|pin@7||-1|1|pin@6||-0.5|-1|ART_color()I74
+AThicker|net@7|||FS2560|pin@8||-1.5|-1|pin@7||-1|1|ART_color()I74
+AThicker|net@8|||FS1166|pin@9||-2|0|pin@8||-1.5|-1|ART_color()I74
+AThicker|net@9|||FS1800|pin@10||-3|0|pin@9||-2|0|ART_color()I74
+AThicker|net@10|||FS1800|pin@13||-2.5|-0.75|pin@14||2.5|-0.75|ART_color()I74
+AThicker|net@11|||FS2700|pin@15||0|-1.5|pin@16||0|-0.75|ART_color()I74
+AThicker|net@12|||FS0|pin@18||1|-1.5|pin@19||-1|-1.5|ART_color()I74
+AThicker|net@13|||FS0|pin@20||0.5|-2|pin@21||-0.5|-2|ART_color()I74
+Ein||D5G2;|pin@12||I
+Eout||D5G2;|pin@11||O
+X
+
+# Cell R110;1{sch}
+CR110;1{sch}||schematic|1047945706000|1204659990686||ATTR_L(D5FLeave alone;G1;HNOLPX-22.5;Y-0.75;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX-22.25;Y-1.75;)S8.8|ATTR_CDL_template(D5G1;NTX-2.5;Y-14;)SXR$(node_name) $(in) $(out) /rnpolywo l='$(L)' w='$(W)' scale=0.05u|ATTR_NCC(D5G1;NTX-1.5;Y-18.5;)SresistorType  N-Poly-RPO-Resistor|ATTR_SPICE_template_assura(D5G1;NTX0.5;Y-23;)SXR$(node_name) $(in) $(out) rnpolywo l='$(L)' w='$(W)' scale=0.05u|ATTR_SPICE_template_calibre(D5G1;NTX0.5;Y-21;)SXR$(node_name) $(in) $(out) rnpolywo l='$(L)*0.05u' w='$(W)*0.05u'|ATTR_SPICE_template_hspice(D5G1;NTX-1.5;Y-16.25;)SXR$(node_name) $(in) $(out) rnpolywo l='$(L)' w='$(W)' scale=0.05u|ATTR_SPICE_template_smartspice(D5G1;NTY-12;)SXR$(node_name) $(in) $(out) rnpolywo l='$(L)' w='$(W)' scale=0.05u|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||-5.5|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NCapacitor|cap@1||4.75|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NOff-Page|conn@0||10|5||||
+NOff-Page|conn@1||-11.5|5||||
+IR110;1{ic}|gateResi@0||25.5|7.5|||D0G4;|ATTR_L(D5FLeave alone;G1;NOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;NOLPX2.25;Y-2.25;)S8.8
+NGround|gnd@0||0|-8.5||||
+Ngeneric:Invisible-Pin|pin@0||1|20.5|||||ART_message(D5G2;)Sn-type unsilicided polysilicon resistor for TSMC90nm process
+Ngeneric:Invisible-Pin|pin@1||2.5|26.5|||||ART_message(D5G5;)SR110 (rnpolywo)
+NWire_Pin|pin@2||-5.5|5||||
+NWire_Pin|pin@3||-5.5|-4.5||||
+NWire_Pin|pin@4||4.75|5||||
+NWire_Pin|pin@5||4.75|-4.5||||
+Ngeneric:Invisible-Pin|pin@6||1.5|15|||||ART_message(D5G2;)S["minumum recommended dimensions are l=2.0um, w=0.44um",target resistance is approx 110 ohm/sq]
+NWire_Pin|pin@7||0|-4.5||||
+NResistor|res@0||-0.5|5||||1|ATTR_length(D5FLeave alone;G1;NOLY-1;)S@L|ATTR_width(D5FLeave alone;G1;NOLY-2;)S@W|SCHEM_resistance(D5FLeave alone;G2;OLY1.5;)S(@L*110/@W)
+Awire|net@0|||0|pin@2||-5.5|5|conn@1|y|-9.5|5
+Awire|net@1|||1800|pin@4||4.75|5|conn@0|a|8|5
+Awire|net@2|||0|res@0|a|-2.5|5|pin@2||-5.5|5
+Awire|net@3|||2700|cap@0|a|-5.5|2|pin@2||-5.5|5
+Awire|net@4|||900|cap@0|b|-5.5|-2|pin@3||-5.5|-4.5
+Awire|net@6|||1800|res@0|b|1.5|5|pin@4||4.75|5
+Awire|net@7|||2700|cap@1|a|4.75|2|pin@4||4.75|5
+Awire|net@8|||900|cap@1|b|4.75|-2|pin@5||4.75|-4.5
+Awire|net@9|||0|pin@7||0|-4.5|pin@3||-5.5|-4.5
+Awire|net@10|||0|pin@5||4.75|-4.5|pin@7||0|-4.5
+Awire|net@11|||2700|gnd@0||0|-6.5|pin@7||0|-4.5
+Ein||D5G2;|conn@1|y|I
+Eout||D5G2;|conn@0|y|O
+X
+
+# Cell R440;1{ic}
+CR440;1{ic}||artwork|1047945855000|1213379062428|E|ATTR_L(D5FLeave alone;G1;HNOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX2.25;Y-2.25;)S8.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||3|0|1|1|Y|
+NPin|pin@1||2|0|1|1|Y|
+NPin|pin@2||1.5|-1|1|1|Y|
+NPin|pin@3||1|1|1|1|Y|
+NPin|pin@4||0.5|-1|1|1|Y|
+NPin|pin@5||0|1|1|1|Y|
+NPin|pin@6||-0.5|-1|1|1|Y|
+NPin|pin@7||-1|1|1|1|Y|
+NPin|pin@8||-1.5|-1|1|1|Y|
+NPin|pin@9||-2|0|1|1|Y|
+NPin|pin@10||-3|0|1|1|Y|
+Nschematic:Bus_Pin|pin@11||3|0||||
+Nschematic:Bus_Pin|pin@12||-3|0||||
+NPin|pin@13||-2.5|-0.75|1|1||
+NPin|pin@14||2.5|-0.75|1|1||
+NPin|pin@15||0|-1.5|1|1|YRRR|
+NPin|pin@16||0|-0.75|1|1|YRRR|
+NPin|pin@18||1|-1.5|1|1|YRR|
+NPin|pin@19||-1|-1.5|1|1|YRR|
+NPin|pin@20||0.5|-2|1|1|YRR|
+NPin|pin@21||-0.5|-2|1|1|YRR|
+Ngeneric:Invisible-Pin|pin@22||0.5|1|||||ART_message(D5G1;)S440
+AThicker|net@0|||FS1800|pin@1||2|0|pin@0||3|0|ART_color()I74
+AThicker|net@1|||FS2434|pin@2||1.5|-1|pin@1||2|0|ART_color()I74
+AThicker|net@2|||FS1040|pin@3||1|1|pin@2||1.5|-1|ART_color()I74
+AThicker|net@3|||FS2560|pin@4||0.5|-1|pin@3||1|1|ART_color()I74
+AThicker|net@4|||FS1040|pin@5||0|1|pin@4||0.5|-1|ART_color()I74
+AThicker|net@5|||FS2560|pin@6||-0.5|-1|pin@5||0|1|ART_color()I74
+AThicker|net@6|||FS1040|pin@7||-1|1|pin@6||-0.5|-1|ART_color()I74
+AThicker|net@7|||FS2560|pin@8||-1.5|-1|pin@7||-1|1|ART_color()I74
+AThicker|net@8|||FS1166|pin@9||-2|0|pin@8||-1.5|-1|ART_color()I74
+AThicker|net@9|||FS1800|pin@10||-3|0|pin@9||-2|0|ART_color()I74
+AThicker|net@10|||FS1800|pin@13||-2.5|-0.75|pin@14||2.5|-0.75|ART_color()I74
+AThicker|net@11|||FS2700|pin@15||0|-1.5|pin@16||0|-0.75|ART_color()I74
+AThicker|net@12|||FS0|pin@18||1|-1.5|pin@19||-1|-1.5|ART_color()I74
+AThicker|net@13|||FS0|pin@20||0.5|-2|pin@21||-0.5|-2|ART_color()I74
+Ein||D5G2;|pin@12||I
+Eout||D5G2;|pin@11||O
+X
+
+# Cell R440;1{sch}
+CR440;1{sch}||schematic|1047945706000|1204326078774||ATTR_L(D5FLeave alone;G1;HNOLPX-22.5;Y-0.75;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX-22.25;Y-1.75;)S8.8|ATTR_CDL_template(D5G1;NTX-2.5;Y-12.5;)SXR$(node_name) $(in) $(out) /rppolywo l='$(L)' w='$(W)' scale=0.05u|ATTR_NCC(D5G1;NTX-1.5;Y-17;)SresistorType  P-Poly-RPO-Resistor|ATTR_SPICE_template_assura(D5G1;NTX-1.5;Y-21;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)' w='$(W)' scale=0.05u|ATTR_SPICE_template_calibre(D5G1;NTX-1.5;Y-19;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)*0.05u' w='$(W)*0.05u'|ATTR_SPICE_template_hspice(D5G1;NTX-1.5;Y-14.75;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)' w='$(W)' scale=0.05u|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||-5.5|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NCapacitor|cap@1||4.75|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NOff-Page|conn@0||10|5||||
+NOff-Page|conn@1||-11.5|5||||
+IR440;1{ic}|gateResi@0||25.5|7.5|||D0G4;|ATTR_L(D5FLeave alone;G1;NOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;NOLPX2.25;Y-2.25;)S8.8
+NGround|gnd@0||0|-9||||
+Ngeneric:Invisible-Pin|pin@0||1|20.5|||||ART_message(D5G2;)Sp-type unsilicided polysilicon resistor for TSMC90nm process
+Ngeneric:Invisible-Pin|pin@1||2.5|26.5|||||ART_message(D5G5;)SR440 (rppolywo)
+NWire_Pin|pin@2||-5.5|5||||
+NWire_Pin|pin@3||-5.5|-4.5||||
+NWire_Pin|pin@4||4.75|5||||
+NWire_Pin|pin@5||4.75|-4.5||||
+Ngeneric:Invisible-Pin|pin@6||1.5|15|||||ART_message(D5G2;)S["minumum recommended dimensions are l=2.0um, w=0.44um",target resistance is approx 440 ohm/sq]
+NWire_Pin|pin@7||0|-4.5||||
+NResistor|pres@0||0|5||||1|ATTR_length(D5FLeave alone;G1;NOLY-1;)S@L|ATTR_width(D5FLeave alone;G1;NOLY-2;)S@W|SCHEM_resistance(D5FLeave alone;G2;OLY1.5;)S(@L*440/@W)
+Awire|net@0|||0|pin@2||-5.5|5|conn@1|y|-9.5|5
+Awire|net@1|||1800|pin@4||4.75|5|conn@0|a|8|5
+Awire|net@3|||2700|cap@0|a|-5.5|2|pin@2||-5.5|5
+Awire|net@4|||900|cap@0|b|-5.5|-2|pin@3||-5.5|-4.5
+Awire|net@7|||2700|cap@1|a|4.75|2|pin@4||4.75|5
+Awire|net@8|||900|cap@1|b|4.75|-2|pin@5||4.75|-4.5
+Awire|net@9|||0|pin@7||0|-4.5|pin@3||-5.5|-4.5
+Awire|net@10|||0|pin@5||4.75|-4.5|pin@7||0|-4.5
+Awire|net@11|||2700|gnd@0||0|-7|pin@7||0|-4.5
+Awire|net@12|||1800|pres@0|b|2|5|pin@4||4.75|5
+Awire|net@13|||0|pres@0|a|-2|5|pin@2||-5.5|5
+Ein||D5G2;|conn@1|y|I
+Eout||D5G2;|conn@0|y|O
+X
+
+# Cell R440Pwell;1{ic}
+CR440Pwell;1{ic}||artwork|1047945855000|1213379062428|E|ATTR_L(D5FLeave alone;G1;HNOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX2.25;Y-2.25;)S8.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||3|0|1|1|Y|
+NPin|pin@1||2|0|1|1|Y|
+NPin|pin@2||1.5|-1|1|1|Y|
+NPin|pin@3||1|1|1|1|Y|
+NPin|pin@4||0.5|-1|1|1|Y|
+NPin|pin@5||0|1|1|1|Y|
+NPin|pin@6||-0.5|-1|1|1|Y|
+NPin|pin@7||-1|1|1|1|Y|
+NPin|pin@8||-1.5|-1|1|1|Y|
+NPin|pin@9||-2|0|1|1|Y|
+NPin|pin@10||-3|0|1|1|Y|
+Nschematic:Bus_Pin|pin@11||3|0||||
+Nschematic:Bus_Pin|pin@12||-3|0||||
+NPin|pin@13||-2.5|-0.75|1|1||
+NPin|pin@14||2.5|-0.75|1|1||
+NPin|pin@15||0|-1.5|1|1|YRRR|
+NPin|pin@16||0|-0.75|1|1|YRRR|
+NPin|pin@18||1|-1.5|1|1|YRR|
+NPin|pin@19||-1|-1.5|1|1|YRR|
+NPin|pin@20||0.5|-2|1|1|YRR|
+NPin|pin@21||-0.5|-2|1|1|YRR|
+Ngeneric:Invisible-Pin|pin@22||0.5|1|||||ART_message(D5G1;)S440
+AThicker|net@0|||FS1800|pin@1||2|0|pin@0||3|0|ART_color()I74
+AThicker|net@1|||FS2434|pin@2||1.5|-1|pin@1||2|0|ART_color()I74
+AThicker|net@2|||FS1040|pin@3||1|1|pin@2||1.5|-1|ART_color()I74
+AThicker|net@3|||FS2560|pin@4||0.5|-1|pin@3||1|1|ART_color()I74
+AThicker|net@4|||FS1040|pin@5||0|1|pin@4||0.5|-1|ART_color()I74
+AThicker|net@5|||FS2560|pin@6||-0.5|-1|pin@5||0|1|ART_color()I74
+AThicker|net@6|||FS1040|pin@7||-1|1|pin@6||-0.5|-1|ART_color()I74
+AThicker|net@7|||FS2560|pin@8||-1.5|-1|pin@7||-1|1|ART_color()I74
+AThicker|net@8|||FS1166|pin@9||-2|0|pin@8||-1.5|-1|ART_color()I74
+AThicker|net@9|||FS1800|pin@10||-3|0|pin@9||-2|0|ART_color()I74
+AThicker|net@10|||FS1800|pin@13||-2.5|-0.75|pin@14||2.5|-0.75|ART_color()I74
+AThicker|net@11|||FS2700|pin@15||0|-1.5|pin@16||0|-0.75|ART_color()I74
+AThicker|net@12|||FS0|pin@18||1|-1.5|pin@19||-1|-1.5|ART_color()I74
+AThicker|net@13|||FS0|pin@20||0.5|-2|pin@21||-0.5|-2|ART_color()I74
+Ein||D5G2;|pin@12||I
+Eout||D5G2;|pin@11||O
+X
+
+# Cell R440Pwell;1{sch}
+CR440Pwell;1{sch}||schematic|1047945706000|1214600313998||ATTR_L(D5FLeave alone;G1;HNOLPX-22.5;Y-0.75;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX-22.25;Y-1.75;)S8.8|ATTR_CDL_template(D5G1;NTX-2.5;Y-12.5;)SXR$(node_name) $(in) $(out) /rppolywo l='$(L)' w='$(W)' scale=0.05u|ATTR_NCC(D5G1;NTX-1.5;Y-17;)SresistorType  P-Poly-RPO-Resistor|ATTR_SPICE_template_assura(D5G1;NTX-1.5;Y-21;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)' w='$(W)' scale=0.05u|ATTR_SPICE_template_calibre(D5G1;NTX-1.5;Y-19;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)*0.05u' w='$(W)*0.05u'|ATTR_SPICE_template_hspice(D5G1;NTX-1.5;Y-14.75;)SXR$(node_name) $(in) $(out) rppolywo l='$(L)' w='$(W)' scale=0.05u|prototype_center()I[0,0]
+IR440Pwell;1{ic}|R440Pwel@0||25.5|7.5|||D0G4;|ATTR_L(D5FLeave alone;G1;NOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;NOLPX2.25;Y-2.25;)S8.8
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||-5.5|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NCapacitor|cap@1||4.75|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX1.75;Y-1.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NOff-Page|conn@0||10|5||||
+NOff-Page|conn@1||-11.5|5||||
+Ngeneric:Invisible-Pin|pin@0||1|20.5|||||ART_message(D5G2;)Sp-type unsilicided polysilicon resistor for TSMC90nm process
+Ngeneric:Invisible-Pin|pin@1||2.5|26.5|||||ART_message(D5G5;)SR440 (rppolywo)
+NWire_Pin|pin@2||-5.5|5||||
+NWire_Pin|pin@3||-5.5|-4.5||||
+NWire_Pin|pin@4||4.75|5||||
+NWire_Pin|pin@5||4.75|-4.5||||
+Ngeneric:Invisible-Pin|pin@6||1.5|15|||||ART_message(D5G2;)S["minumum recommended dimensions are l=2.0um, w=0.44um",target resistance is approx 440 ohm/sq]
+NWire_Pin|pin@10||0|-4.5||||
+NResistor|pres@0||0|5||||1|ATTR_length(D5FLeave alone;G1;NOLY-1;)S@L|ATTR_width(D5FLeave alone;G1;NOLY-2;)S@W|SCHEM_resistance(D5FLeave alone;G2;OLY1.5;)S(@L*440/@W)
+NPower|pwr@0||0|-8||||
+Awire|net@0|||0|pin@2||-5.5|5|conn@1|y|-9.5|5
+Awire|net@1|||1800|pin@4||4.75|5|conn@0|a|8|5
+Awire|net@3|||2700|cap@0|a|-5.5|2|pin@2||-5.5|5
+Awire|net@4|||900|cap@0|b|-5.5|-2|pin@3||-5.5|-4.5
+Awire|net@7|||2700|cap@1|a|4.75|2|pin@4||4.75|5
+Awire|net@8|||900|cap@1|b|4.75|-2|pin@5||4.75|-4.5
+Awire|net@12|||1800|pres@0|b|2|5|pin@4||4.75|5
+Awire|net@13|||0|pres@0|a|-2|5|pin@2||-5.5|5
+Awire|net@18|||1800|pin@3||-5.5|-4.5|pin@10||0|-4.5
+Awire|net@19|||1800|pin@10||0|-4.5|pin@5||4.75|-4.5
+Awire|net@20|||2700|pwr@0||0|-8|pin@10||0|-4.5
+Ein||D5G2;|conn@1|y|I
+Eout||D5G2;|conn@0|y|O
+X
+
+# Cell gallery;1{lay}
+Cgallery;1{lay}||cmos90|1158345347649|1158345387584|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Ipnp2;1{lay}|pnp2@0||-113|6|||D5G4;
+Ipnp5;1{lay}|pnp2@1||357|6|||D5G4;
+Ipnp10;1{lay}|pnp2@2||905|6|||D5G4;
+X
+
+# Cell gallery;1{sch}
+Cgallery;1{sch}||schematic|1158082936168|1158346546100|
+INMOS4f;1{ic}|NMOS4f@0||-28|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_high;1{ic}|NMOS4f_h@0||-37|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_io18;1{ic}|NMOS4f_i@0||-45.5|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S4|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_io25;1{ic}|NMOS4f_i@1||-54.5|50.5|||D5G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S5.6|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_io33;1{ic}|NMOS4f_i@2||-63.5|50.5|||D5G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S7.6|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_low;1{ic}|NMOS4f_l@0||-19|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_native;1{ic}|NMOS4f_n@0||-10|50.5|||D5G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S4|ATTR_W(D6G1;NPX1.75;Y0.75;)S10
+INMOS4fwk;1{ic}|NMOS4fwk@0||11|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOS4fwk_low;1{ic}|NMOS4fwk@1||20|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOS4fwk_high;1{ic}|NMOS4fwk@2||2|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOS4fwk_native;1{ic}|NMOS4fwk@3||29|51|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D6G1;NPX2;Y1;)S10|ATTR_GEO()I0
+INMOS4x;1{ic}|NMOS4x@0||-28|74|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOLPX3.5;Y0.5;)S1
+INMOS4x_io25;1{ic}|NMOS4x_i@0||-54.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOS4x_io33;1{ic}|NMOS4x_i@1||-63|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOS4x_io18;1{ic}|NMOS4x_i@2||-45.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSf;1{ic}|NMOSf@0||-28|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_high;1{ic}|NMOSf_hi@0||-37|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_io25;1{ic}|NMOSf_io@0||-54.5|57.5|||D5G4;|ATTR_Delay(P)I100|ATTR_L(D5G1;NPX3.5;)S5.6|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_io33;1{ic}|NMOSf_io@1||-63.5|57.5|||D5G4;|ATTR_Delay(P)I100|ATTR_L(D5G1;NPX3.5;)S7.6|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_io18;1{ic}|NMOSf_io@2||-45.5|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S4|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOSf_low;1{ic}|NMOSf_lo@0||-19|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_native;1{ic}|NMOSf_na@0||-10|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D6G1;NPX2;Y1;)S10
+INMOSf_native_od25;1{ic}|NMOSf_na@1||-84.5|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S24|ATTR_W(D6G1;NPX2;Y1;)S10
+INMOSf_native_od18;1{ic}|NMOSf_na@2||-75.5|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S24|ATTR_W(D6G1;NPX2;Y1;)S10
+INMOSf_native_od33;1{ic}|NMOSf_na@3||-94.5|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S24|ATTR_W(D6G1;NPX2;Y1;)S10
+INMOSfwk;1{ic}|NMOSfwk@0||11|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOSfwk_low;1{ic}|NMOSfwk_@0||20|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOSfwk_high;1{ic}|NMOSfwk_@1||2|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOSfwk_native;1{ic}|NMOSfwk_@2||29|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D6G1;NPX2;Y1;)S10|ATTR_GEO()I0
+INMOSx;1{ic}|NMOSx@0||-28|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSx_high;1{ic}|NMOSx_hi@0||-37|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSx_low;1{ic}|NMOSx_lo@0||-19|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSx_native;1{ic}|NMOSx_na@0||-10|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S1
+INMOSx_native_od25;1{ic}|NMOSx_na@1||-84.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S1
+INMOSx_native_od18;1{ic}|NMOSx_na@2||-75.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S1
+INMOSx_native_od33;1{ic}|NMOSx_na@3||-94.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S1
+INMOSxwk;1{ic}|NMOSxwk@0||11|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSxwk_low;1{ic}|NMOSxwk_@0||20|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSxwk_high;1{ic}|NMOSxwk_@1||2|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSxwk_native;1{ic}|NMOSxwk_@2||29|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOS4f;1{ic}|PMOS4f@0||-28|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4f_high;1{ic}|PMOS4f_h@0||-37|13|||D0G4;|ATTR_Delay(D5G1;NPX3.75;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOS4f_io18;1{ic}|PMOS4f_i@0||-45.5|13|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOS4f_io25;1{ic}|PMOS4f_i@1||-54.5|13|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S5.6|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOS4f_io33;1{ic}|PMOS4f_i@2||-63.5|13|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S7.6|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOS4f_low;1{ic}|PMOS4f_l@0||-19|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4fwk;1{ic}|PMOS4fwk@0||11|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4fwk_high;1{ic}|PMOS4fwk@1||2|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4fwk_low;1{ic}|PMOS4fwk@2||20|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4x;1{ic}|PMOS4x@0||-28|35.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOS4x_io25;1{ic}|PMOS4x_i@0||-54.5|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_L()I2|ATTR_W()I3
+IPMOS4x_io33;1{ic}|PMOS4x_i@1||-63.5|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_L()I2|ATTR_W()I3
+IPMOS4x_io18;1{ic}|PMOS4x_i@2||-45.5|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_L()I2|ATTR_W()I3
+IPMOSf;1{ic}|PMOSf@0||-28|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOSf_high;1{ic}|PMOSf_hi@0||-37|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOSf_io18;1{ic}|PMOSf_io@0||-45.5|20|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOSf_io25;1{ic}|PMOSf_io@1||-54.5|20|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S5.6|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOSf_io33;1{ic}|PMOSf_io@2||-63.5|20|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S7.6|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOSf_low;1{ic}|PMOSf_lo@0||-18.75|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOSfwk;1{ic}|PMOSfwk@0||11|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+IPMOSfwk_high;1{ic}|PMOSfwk_@0||2|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+IPMOSfwk_low;1{ic}|PMOSfwk_@1||20|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+IPMOSx;1{ic}|PMOSx@0||-28|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSx_high;1{ic}|PMOSx_hi@0||-37|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSx_low;1{ic}|PMOSx_lo@0||-19|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSxwk;1{ic}|PMOSxwk@0||11|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSxwk_high;1{ic}|PMOSxwk_@0||2|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSxwk_low;1{ic}|PMOSxwk_@1||20|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IR110;1{ic}|R110@0||-95|17|||D5G1;T|ATTR_L(D5G1;NPX-2;Y-2.25;)I40|ATTR_W(D5G1;NPX2.25;Y-2.25;)D8.8
+IR440;1{ic}|R440@0||-95|10.5|||D5G1;T|ATTR_L(D5G1;NPX-2;Y-2.25;)I40|ATTR_W(D5G1;NPX2.25;Y-2.25;)D8.8
+Ngeneric:Facet-Center|art@0||0|0||||AV
+IgateResistor;1{ic}|gateResi@0||-95.5|40.5|||D0G4;|ATTR_W(D5G1;NPY-1.5;)I3
+Indio;1{ic}|ndio@0||-79|36|||D5G4;
+Ngeneric:Invisible-Pin|pin@1||-38|86|||||ART_message(D5G2;R)Shigh-threshold
+Ngeneric:Invisible-Pin|pin@2||-19.5|86|||||ART_message(D5G2;R)Slow-threshold
+Ngeneric:Invisible-Pin|pin@3||-10.5|86|||||ART_message(D5G2;R)Snative
+Ngeneric:Invisible-Pin|pin@4||-28.5|86|||||ART_message(D5G2;R)Sstandard
+Ngeneric:Invisible-Pin|pin@5||-46|86|||||ART_message(D5G2;R)S1.8V thick-ox
+Ngeneric:Invisible-Pin|pin@6||-55|86|||||ART_message(D5G2;R)S2.5V thick-ox
+Ngeneric:Invisible-Pin|pin@7||-64|86|||||ART_message(D5G2;R)S3.3V thick-ox
+Ngeneric:Invisible-Pin|pin@8||-76|86|||||ART_message(D5G2;R)S1.8V native
+Ngeneric:Invisible-Pin|pin@9||-84.5|86|||||ART_message(D5G2;R)S2.5V native
+Ngeneric:Invisible-Pin|pin@10||-95|86|||||ART_message(D5G2;R)S3.3V native
+Ngeneric:Invisible-Pin|pin@11||1.5|86|||||ART_message(D5G2;R)Sweak high-threshold
+Ngeneric:Invisible-Pin|pin@12||10|86|||||ART_message(D5G2;R)Sweak standard
+Ngeneric:Invisible-Pin|pin@13||19.5|86|||||ART_message(D5G2;R)Sweak low-threshold
+Ngeneric:Invisible-Pin|pin@14||28.5|86|||||ART_message(D5G2;R)Sweak native
+Ipnp5;1{ic}|pnp2@0||-79.5|20|||D5G4;
+Ipnp10;1{ic}|pnp2@1||-79.5|13|||D5G4;
+Ipnp2;1{ic}|singlepn@2||-79.5|27|||D5G4;
+Iwire90;1{ic}|wire90@0||-110.5|37|||D5G4;|ATTR_L(D5G1;PUD)I100|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)S2|ATTR_width(D5G1;NPY-2;)S2.8
+Iwire90xcpl2;1{ic}|wire90xc@0||-110.5|30|||D5G4;|ATTR_L(D5G1;PUDY1;)I100|ATTR_layer(D5G1;NPY-0.5;)S2|ATTR_width(D5G1;NPY-1.5;)S2.8
+Iwire90xcpl3;1{ic}|wire90xc@1||-110.5|23|||D5G4;|ATTR_L(D5G1;PUDY1;)I100|ATTR_layer(D5G1;NPY-0.5;)S2|ATTR_width(D5G1;NPY-1.5;)S2.8
+IwireC;1{ic}|wireC@0||-95|26.5|||D0G4;|ATTR_L(D6G1.5;NOJPX1.5;Y0.5;)S100|ATTR_layer(D5G1;NPX3;Y-1.5;)I1|ATTR_width(D5G1;NPX3;Y-0.5;)I3
+IwireR;1{ic}|wireC@1||-95|34|||D0G4;|ATTR_L(D6G1.5;NOJPX1.5;Y0.5;)S100|ATTR_layer(D5G1;NPX3;Y-1.5;)I1|ATTR_width(D5G1;NPX3;Y-0.5;)I3
+Iwire_xcp_gnd;1{ic}|wire_xcp@0||-110.5|17|||D5G4;|ATTR_C(D5G1;NPURX2.5;Y-1;)S0.223f|ATTR_L(D5G1;PURY1;)I100|ATTR_LEWIRE(PUR)I1|ATTR_R(D5G1;NPURX-3;Y-1;)S24m|ATTR_layer(PUR)I2|ATTR_width(PUR)D2.8
+Iwire_xcpl_sides;1{ic}|wire_xcp@1||-110.5|12|||D5G4;|ATTR_C(D5G1;NPUCY-1;)S0.0000223p|ATTR_L(D5G1;PUDY1;)I100|ATTR_LEIGNORE(PUD)I1
+X
+
+# Cell gateResistor;1{ic}
+CgateResistor;1{ic}||artwork|1047945855000|1204183998562|E|ATTR_W(D5G1;HNOLPY-1.5;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||3|0|1|1||
+NPin|pin@1||2|0|1|1||
+NPin|pin@2||1.5|1|1|1||
+NPin|pin@3||1|-1|1|1||
+NPin|pin@4||0.5|1|1|1||
+NPin|pin@5||0|-1|1|1||
+NPin|pin@6||-0.5|1|1|1||
+NPin|pin@7||-1|-1|1|1||
+NPin|pin@8||-1.5|1|1|1||
+NPin|pin@9||-2|0|1|1||
+NPin|pin@10||-3|0|1|1||
+Nschematic:Bus_Pin|pin@11||3|0||||
+Nschematic:Bus_Pin|pin@12||-3|0||||
+AThicker|net@0|||FS0|pin@0||3|0|pin@1||2|0|ART_color()I74
+AThicker|net@1|||FS2966|pin@1||2|0|pin@2||1.5|1|ART_color()I74
+AThicker|net@2|||FS760|pin@2||1.5|1|pin@3||1|-1|ART_color()I74
+AThicker|net@3|||FS2840|pin@3||1|-1|pin@4||0.5|1|ART_color()I74
+AThicker|net@4|||FS760|pin@4||0.5|1|pin@5||0|-1|ART_color()I74
+AThicker|net@5|||FS2840|pin@5||0|-1|pin@6||-0.5|1|ART_color()I74
+AThicker|net@6|||FS760|pin@6||-0.5|1|pin@7||-1|-1|ART_color()I74
+AThicker|net@7|||FS2840|pin@7||-1|-1|pin@8||-1.5|1|ART_color()I74
+AThicker|net@8|||FS634|pin@8||-1.5|1|pin@9||-2|0|ART_color()I74
+AThicker|net@9|||FS0|pin@9||-2|0|pin@10||-3|0|ART_color()I74
+Ein||D5G2;|pin@12||I
+Eout||D5G2;|pin@11||O
+X
+
+# Cell gateResistor;1{sch}
+CgateResistor;1{sch}||schematic|1047945706000|1158010267102||ATTR_W(D5G1;HNOLPX-13;Y-1;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||10|3||||
+NOff-Page|conn@1||-11.5|3||||
+IgateResistor;1{ic}|gateResi@0||18|10.5|||D0G4;|ATTR_W(D5G1;NOLPY-1.5;)S3
+Ngeneric:Invisible-Pin|pin@0||0|15.5|||||ART_message(D5G2;)S[models gate resistor in TSMC 180nm technology,where gate resistance is not felt to be important]
+Ngeneric:Invisible-Pin|pin@1||1.5|20.5|||||ART_message(D5G5;)S[gateResistor]
+NResistor|res@0||-0.5|3|||||SCHEM_resistance(D5G1;OL)S0.0010
+Awire|net@0|||1800|conn@1|y|-9.5|3|res@0|a|-2.5|3
+Awire|net@1|||0|conn@0|a|8|3|res@0|b|1.5|3
+Ein||D5G2;|conn@1|y|I
+Eout||D5G2;|conn@0|y|O
+X
+
+# Cell ndio;1{ic}
+Cndio;1{ic}||artwork|1158345992616|1158346111652|E
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NFilled-Triangle|art@2||0|1|3|2|Y||ART_color()I-4323839
+Ngeneric:Universal-Pin|pin@0||0|-1|-1|-1||
+Ngeneric:Universal-Pin|pin@2||0|3|-1|-1||
+Ngeneric:Invisible-Pin|pin@3||2|1|||||ART_message(D5G1;)Sndio
+NPin|pin@4||0|2|1|1||
+NPin|pin@5||0|3|1|1||
+NPin|pin@6||0|-1|1|1||
+NPin|pin@7||0|0|1|1||
+NPin|pin@8||-1.5|0|1|1||
+NPin|pin@9||1.5|0|1|1||
+AThicker|net@0|||FS2700|pin@4||0|2|pin@5||0|3|ART_color()I-4323839
+AThicker|net@1|||FS2700|pin@6||0|-1|pin@7||0|0|ART_color()I-4323839
+AThicker|net@2|||FS1800|pin@8||-1.5|0|pin@9||1.5|0|ART_color()I-4323839
+Eminus||D5G2;|pin@0||B
+Eplus||D5G2;|pin@2||B
+X
+
+# Cell ndio;1{sch}
+Cndio;1{sch}||schematic|1158345864878|1158346461571||ATTR_CDL_template(D5G1;NTX-7;Y-12.5;)SD$(node_name) $(plus) $(minus) ndio|ATTR_SPICE_template(D5G1;NTX-7;Y-10;)SD$(node_name) $(plus) $(minus) ndio|ATTR_SPICE_template_assura(D5G1;NTX-7;Y-14.5;)SD$(node_name) $(plus) $(minus) ndio|ATTR_SPICE_template_calibre(D5G1;NTX-7;Y-16.5;)SD$(node_name) $(plus) $(minus) ndio
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-7|11|||RRR|
+NOff-Page|conn@1||-7|-3|||YRRR|
+NDiode|diode@0||-7|4|||Y||SCHEM_diode(D5G1;)S10
+Indio;1{ic}|ndio@0||19|19|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||-7|23|||||ART_message(D5G5;)Sndio
+Ngeneric:Invisible-Pin|pin@1||-7|18|||||ART_message(D5G2;)Sn-type diode for TSMC90 process
+Awire|net@0|||900|conn@0|y|-7|9|diode@0|b|-7|6
+Awire|net@1|||2700|conn@1|y|-7|-1|diode@0|a|-7|2
+Eminus||D5G2;|conn@1|a|B
+Eplus||D5G2;|conn@0|a|B
+X
+
+# Cell ndio18;1{ic}
+Cndio18;1{ic}||artwork|1158345992616|1204786357596|E|ATTR_L(D5G1;HNOLPX-3.5;Y0.5;)S20|ATTR_W(D5G1;HNOLPX-3.5;Y1.5;)S20|ATTR_area(D5G1;HNOLPX-3.5;Y-0.5;)S400
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NFilled-Triangle|art@2||0|1|3|2|Y||ART_color()I-4323839
+Ngeneric:Universal-Pin|pin@0||0|-1|-1|-1||
+Ngeneric:Universal-Pin|pin@2||0|3|-1|-1||
+Ngeneric:Invisible-Pin|pin@3||2.5|1|||||ART_message(D5G1;)Sndio18
+NPin|pin@4||0|2|1|1||
+NPin|pin@5||0|3|1|1||
+NPin|pin@6||0|-1|1|1||
+NPin|pin@7||0|0|1|1||
+NPin|pin@8||-1.5|0|1|1||
+NPin|pin@9||1.5|0|1|1||
+AThicker|net@0|||FS2700|pin@4||0|2|pin@5||0|3|ART_color()I-4323839
+AThicker|net@1|||FS2700|pin@6||0|-1|pin@7||0|0|ART_color()I-4323839
+AThicker|net@2|||FS1800|pin@8||-1.5|0|pin@9||1.5|0|ART_color()I-4323839
+Eminus||D5G2;|pin@0||B
+Eplus||D5G2;|pin@2||B
+X
+
+# Cell ndio18;1{sch}
+Cndio18;1{sch}||schematic|1158345864878|1204786363159||ATTR_L(D5G1;HNOLPX-32.5;Y-9.5;)S20|ATTR_W(D5G1;HNOLPX-32.5;Y-7.5;)S20|ATTR_area(D5G1;HNOLPX-32.5;Y-11;)S400|ATTR_CDL_template(D5G1;NTX-7;Y-12.5;)SD$(node_name) $(plus) $(minus) ndio_18|ATTR_SPICE_template(D5G1;NTX-7;Y-10;)SD$(node_name) $(plus) $(minus) ndio_18|ATTR_SPICE_template_assura(D5G1;NTX-7;Y-14.5;)SD$(node_name) $(plus) $(minus) ndio_18|ATTR_SPICE_template_calibre(D5G1;NTX-7;Y-16.5;)SD$(node_name) $(plus) $(minus) ndio_18 area='$(W)*$(L)*0.05u*0.05u'
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-7|11|||RRR|
+NOff-Page|conn@1||-7|-3|||YRRR|
+NDiode|diode@0||-7|4|||Y||SCHEM_diode(D5G1;OL)S@W*@L
+Indio18;1{ic}|ndio@0||23|19|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||-7|23|||||ART_message(D5G5;)Sndio18
+Ngeneric:Invisible-Pin|pin@1||-7|18|||||ART_message(D5G2;)Sthick-oxide n-type diode for TSMC90 process
+Awire|net@0|||900|conn@0|y|-7|9|diode@0|b|-7|6
+Awire|net@1|||2700|conn@1|y|-7|-1|diode@0|a|-7|2
+Eminus||D5G2;|conn@1|a|B
+Eplus||D5G2;|conn@0|a|B
+X
+
+# Cell pdio18;1{ic}
+Cpdio18;1{ic}||artwork|1158345992616|1204786413364|E|ATTR_L(D5G1;HNOLPX-3.5;Y0.5;)S20|ATTR_W(D5G1;HNOLPX-3.5;Y1.5;)S20|ATTR_area(D5G1;HNOLPX-3.5;Y-0.5;)S400
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NFilled-Triangle|art@2||0|1|3|2|Y||ART_color()I-4323839
+Ngeneric:Universal-Pin|pin@0||0|-1|-1|-1||
+Ngeneric:Universal-Pin|pin@2||0|3|-1|-1||
+Ngeneric:Invisible-Pin|pin@3||2.5|1|||||ART_message(D5G1;)Spdio18
+NPin|pin@4||0|2|1|1||
+NPin|pin@5||0|3|1|1||
+NPin|pin@6||0|-1|1|1||
+NPin|pin@7||0|0|1|1||
+NPin|pin@8||-1.5|0|1|1||
+NPin|pin@9||1.5|0|1|1||
+AThicker|net@0|||FS2700|pin@4||0|2|pin@5||0|3|ART_color()I-4323839
+AThicker|net@1|||FS2700|pin@6||0|-1|pin@7||0|0|ART_color()I-4323839
+AThicker|net@2|||FS1800|pin@8||-1.5|0|pin@9||1.5|0|ART_color()I-4323839
+Eminus||D5G2;|pin@0||B
+Eplus||D5G2;|pin@2||B
+X
+
+# Cell pdio18;1{sch}
+Cpdio18;1{sch}||schematic|1158345864878|1204786544777||ATTR_L(D5G1;HNOLPX-32.5;Y-9.5;)S20|ATTR_W(D5G1;HNOLPX-32.5;Y-7.5;)S20|ATTR_area(D5G1;HNOLPX-32.5;Y-11;)S400|ATTR_CDL_template(D5G1;NTX-7;Y-12.5;)SD$(node_name) $(plus) $(minus) pdio_18|ATTR_SPICE_template(D5G1;NTX-7;Y-10;)SD$(node_name) $(plus) $(minus) pdio_18|ATTR_SPICE_template_assura(D5G1;NTX-7;Y-14.5;)SD$(node_name) $(plus) $(minus) pdio_18|ATTR_SPICE_template_calibre(D5G1;NTX-7;Y-16.5;)SD$(node_name) $(plus) $(minus) pdio_18 area='$(W)*$(L)*0.05u*0.05u'
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-7|11|||RRR|
+NOff-Page|conn@1||-7|-3|||YRRR|
+NDiode|diode@0||-7|4|||Y||SCHEM_diode(D5G1;OL)S@W*@L
+Ipdio18;1{ic}|ndio@0||23|19|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||-7|23|||||ART_message(D5G5;)Spdio18
+Ngeneric:Invisible-Pin|pin@1||-7|18|||||ART_message(D5G2;)Sthick-oxide p-type diode for TSMC90 process
+Awire|net@0|||900|conn@0|y|-7|9|diode@0|b|-7|6
+Awire|net@1|||2700|conn@1|y|-7|-1|diode@0|a|-7|2
+Eminus||D5G2;|conn@1|a|B
+Eplus||D5G2;|conn@0|a|B
+X
+
+# Cell pnp2;1{ic}
+Cpnp2;1{ic}||artwork|1075166155000|1158173269713|E|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NFilled-Triangle|art@1||1|1|1|2|1350||ART_color()I-4323839
+NPin|pin@0||-2|0|1|1||
+NPin|pin@1||2|-2|1|1||
+NPin|pin@2||0|-2|1|1||
+NPin|pin@3||0|2|1|1||
+NPin|pin@4||0|0|1|1||
+NPin|pin@5||2|2|1|1||
+Ngeneric:Invisible-Pin|pin@6||2|2||||
+Ngeneric:Invisible-Pin|pin@7||2|-2|||Y|
+Ngeneric:Invisible-Pin|pin@8||-2|0|||R|
+Ngeneric:Invisible-Pin|pin@9||3|0|||||ART_message(C74;D5G2;)S2X2
+AThicker|net@0|||FS0|pin@4||0|0|pin@0||-2|0|ART_color()I-4323839
+AThicker|net@1|||FS1350|pin@4||0|0|pin@1||2|-2|ART_color()I-4323839
+AThicker|net@2|||FS2700|pin@2||0|-2|pin@3||0|2|ART_color()I-4323839
+AThicker|net@3|||FS2250|pin@4||0|0|pin@5||2|2|ART_color()I-4323839
+Ebase||D5G2;|pin@8||B
+Ecol||D5G2;|pin@7||B
+Eemit||D5G2;|pin@6||B
+X
+
+# Cell pnp2;1{lay}
+Cpnp2;1{lay}||cmos90|1158278317514|1158342712850||DRC_last_good_drc_bit()I6|DRC_last_good_drc_date()G1158342736114
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NMetal-1-P-Active-Con|contact@0||0|0|34.8|34.8||
+NMetal-1-N-Well-Con|contact@2||50|-8|14.8|102.8||
+NMetal-1-N-Well-Con|contact@3||0|54|14.8|114.8|R|
+NMetal-1-N-Well-Con|contact@4||-50|-8|14.8|102.8||
+NMetal-1-P-Well-Con|contact@8||120|0|34.8|274.8||
+NMetal-1-P-Well-Con|contact@9||-120|0|34.8|274.8||
+NMetal-1-Pin|pin@0||0|0||||
+NMetal-1-Pin|pin@1||0|54||||
+NMetal-1-Pin|pin@2||-120|0||||
+NMetal-1-Pin|pin@3||120|0||||
+NBJTDMY-Node|plnode@0||0|0|320|320||
+NN-Well-Node|plnode@1||0|0|160|160||A
+NP-Select-Node|plnode@2||-120|0|80|320||
+NP-Select-Node|plnode@3||120|0|80|320||
+NP-Select-Node|plnode@4||0|120|160|80||
+NP-Select-Node|plnode@5||0|-120|160|80||
+NN-Select-Node|plnode@6||50|0|40|140||
+NN-Select-Node|plnode@7||-50|0|40|140||
+NN-Select-Node|plnode@8||0|50|60|40||
+NN-Select-Node|plnode@9||0|-50|60|40||
+NP-Select-Node|plnode@10||0|0|60|60||
+NMetal-1-P-Well-Con|well@3||-81|120|34.8|34.8||
+NMetal-1-P-Well-Con|well@4||-81|-120|34.8|34.8||
+NMetal-1-P-Well-Con|well@5||81|120|34.8|34.8||
+NMetal-1-P-Well-Con|well@6||81|-120|34.8|34.8||
+Ametal-1|net@8|||S2700|contact@2||47|43.4|contact@3||47|46.6
+Ametal-1|net@9|||S900|contact@3||-50|46.6|contact@4||-50|43.4
+Ametal-1|net@10||36.6|IJS1800|well@6||98.4|-120|contact@8||102.6|-120
+Ametal-1|net@11||36.6|IJS0|well@4||-98.4|-120|contact@9||-102.6|-120
+Ametal-1|net@12||36.6|IJS0|well@3||-98.4|120|contact@9||-102.6|120
+Ametal-1|net@13||36.6|IJS1800|well@5||98.4|120|contact@8||102.6|120
+Ametal-1|net@14|||S0|contact@0||0|0|pin@0||0|0
+Ametal-1|net@15|||S0|contact@9||-120|0|pin@2||-120|0
+Ametal-1|net@16|||S0|contact@8||120|0|pin@3||120|0
+Ametal-1|net@17|||S0|contact@3||0|54|pin@1||0|54
+Eemit_1|base|D5G5;|pin@1||B
+Eemit_2|col|D5G5;|pin@2||B
+Ecol_1||D5G5;|pin@3||B
+Eemit||D5G5;|pin@0||B
+X
+
+# Cell pnp2;1{sch}
+Cpnp2;1{sch}||schematic|1075166061000|1158173414105||ATTR_CDL_template(D5G1;NTX9.5;Y-8;)SQ$(node_name) $(col) $(base) $(emit) pnp2 area=4p|ATTR_NCC(D5G1;NTX9.5;Y-4;)SblackBox does not detect PNPs|ATTR_SPICE_template(D5G1;NTX9.5;Y-6;)SQ$(node_name) $(col) $(base) $(emit) pnp2|ATTR_SPICE_template_assura(D5G1;NTX9;Y-10;)SQ$(node_name) $(col) $(base) $(emit) pnp2 area=4p|ATTR_SPICE_template_calibre(D5G1;NTX10;Y-12;)SQ$(node_name) $(col) $(base) $(emit) pnp2 area=4p|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||10|13|||RRR|
+NOff-Page|conn@1||10|2|||R|
+NOff-Page|conn@2||2|8||||
+Ngeneric:Invisible-Pin|pin@0||10|26.5|||||ART_message(D5G5;)Spnp2
+Ngeneric:Invisible-Pin|pin@1||10|21.5|||||ART_message(D5G2;)S2x2 vertical bipolar transistor
+NTransistor|pnp@0||8|8|||YR|4
+Ipnp2;1{ic}|singlepn@0||24.75|13|||D0G4;
+Awire|net@0|||2700|pnp@0|s|10|10|conn@0|y|10|11
+Awire|net@1|||900|pnp@0|d|10|6|conn@1|y|10|4
+Awire|net@2|||0|pnp@0|g|7|8|conn@2|y|4|8
+Ebase||D4G2;|conn@2|a|B
+Ecol||D6G2;X-6;|conn@1|y|B
+Eemit||D4G2;|conn@0|a|B
+X
+
+# Cell pnp5;1{ic}
+Cpnp5;1{ic}||artwork|1075166155000|1158173333366|E|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NFilled-Triangle|art@1||1|1|1|2|1350||ART_color()I-4323839
+NPin|pin@0||-2|0|1|1||
+NPin|pin@1||2|-2|1|1||
+NPin|pin@2||0|-2|1|1||
+NPin|pin@3||0|2|1|1||
+NPin|pin@4||0|0|1|1||
+NPin|pin@5||2|2|1|1||
+Ngeneric:Invisible-Pin|pin@6||2|2||||
+Ngeneric:Invisible-Pin|pin@7||2|-2|||Y|
+Ngeneric:Invisible-Pin|pin@8||-2|0|||R|
+Ngeneric:Invisible-Pin|pin@9||3|0|||||ART_message(C74;D5G2;)S5X5
+AThicker|net@0|||FS0|pin@4||0|0|pin@0||-2|0|ART_color()I-4323839
+AThicker|net@1|||FS1350|pin@4||0|0|pin@1||2|-2|ART_color()I-4323839
+AThicker|net@2|||FS2700|pin@2||0|-2|pin@3||0|2|ART_color()I-4323839
+AThicker|net@3|||FS2250|pin@4||0|0|pin@5||2|2|ART_color()I-4323839
+Ebase||D5G2;|pin@8||B
+Ecol||D5G2;|pin@7||B
+Eemit||D5G2;|pin@6||B
+X
+
+# Cell pnp5;1{lay}
+Cpnp5;1{lay}||cmos90|1158278317514|1158344578345||DRC_last_good_drc_bit()I6|DRC_last_good_drc_date()G1158344046229
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NMetal-1-N-Well-Con|contact@2||85|-8|14.8|164.8||
+NMetal-1-N-Well-Con|contact@3||0|85|14.8|184.8|R|
+NMetal-1-N-Well-Con|contact@4||-85|-8|14.8|164.8||
+NMetal-1-P-Well-Con|contact@8||150|0|34.8|334.8||
+NMetal-1-P-Well-Con|contact@9||-150|0|34.8|334.8||
+NMetal-1-P-Active-Con|contact@10||-30|0|34.8|94.8||
+NMetal-1-P-Active-Con|contact@11||30|0|34.8|94.8||
+NMetal-1-Pin|pin@0||-30|0||||
+NMetal-1-Pin|pin@1||0|85||||
+NMetal-1-Pin|pin@2||-148|0||||
+NMetal-1-Pin|pin@3||151.5|0||||
+NMetal-1-Pin|pin@4||30|0||||
+NBJTDMY-Node|plnode@0||0|0|380|380||
+NN-Well-Node|plnode@1||0|0|220|220||A
+NP-Select-Node|plnode@2||-150|0|80|380||
+NP-Select-Node|plnode@3||150|0|80|380||
+NP-Select-Node|plnode@4||0|150|220|80||
+NP-Select-Node|plnode@5||0|-150|220|80||
+NN-Select-Node|plnode@6||85|0|50|220||
+NN-Select-Node|plnode@7||-85|0|50|220||
+NN-Select-Node|plnode@8||0|85|120|50||
+NN-Select-Node|plnode@9||0|-85|120|50||
+NP-Select-Node|plnode@11||0|0|120|120||
+NMetal-1-P-Well-Con|well@3||-111|150|34.8|34.8||
+NMetal-1-P-Well-Con|well@4||-111|-150|34.8|34.8||
+NMetal-1-P-Well-Con|well@5||111|150|34.8|34.8||
+NMetal-1-P-Well-Con|well@6||111|-150|34.8|34.8||
+Ametal-1|net@10||36.6|IJS1800|well@6||128.4|-150|contact@8||132.6|-150
+Ametal-1|net@11||36.6|IJS0|well@4||-128.4|-150|contact@9||-132.6|-150
+Ametal-1|net@12||36.6|IJS0|well@3||-128.4|150|contact@9||-132.6|150
+Ametal-1|net@13||36.6|IJS1800|well@5||128.4|150|contact@8||132.6|150
+Ametal-1|net@15|||S0|contact@9||-148|0|pin@2||-148|0
+Ametal-1|net@16|||S0|contact@8||151.5|0|pin@3||151.5|0
+Ametal-1|net@18|||S0|contact@10||-30|0|pin@0||-30|0
+Ametal-1|net@19|||S0|contact@11||30|0|pin@4||30|0
+Ametal-1|net@20|||S2700|contact@2||88|74.4|contact@3||88|77.6
+Ametal-1|net@21|||S2700|contact@4||-84|74.4|contact@3||-84|77.6
+Ametal-1|net@22|||S0|contact@3||0|85|pin@1||0|85
+Ebase||D5G5;|pin@1||B
+Ecol||D5G5;|pin@2||B
+Ecol_1||D5G5;|pin@3||B
+Eemit||D5G5;|pin@0||B
+Eemit_1||D5G5;|pin@4||B
+X
+
+# Cell pnp5;1{sch}
+Cpnp5;1{sch}||schematic|1075166061000|1158173400067||ATTR_CDL_template(D5G1;NTX9.5;Y-8;)SQ$(node_name) $(col) $(base) $(emit) pnp5 area=25p|ATTR_NCC(D5G1;NTX9.5;Y-4;)SblackBox does not detect PNPs|ATTR_SPICE_template(D5G1;NTX9.5;Y-6;)SQ$(node_name) $(col) $(base) $(emit) pnp5|ATTR_SPICE_template_assura(D5G1;NTX9;Y-10;)SQ$(node_name) $(col) $(base) $(emit) pnp5 area=25p|ATTR_SPICE_template_calibre(D5G1;NTX10;Y-12;)SQ$(node_name) $(col) $(base) $(emit) pnp5 area=25p|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||10|13|||RRR|
+NOff-Page|conn@1||10|2|||R|
+NOff-Page|conn@2||2|8||||
+Ngeneric:Invisible-Pin|pin@0||10|26.5|||||ART_message(D5G5;)Spnp2
+Ngeneric:Invisible-Pin|pin@1||10|21.5|||||ART_message(D5G2;)S5x5 vertical bipolar transistor
+NTransistor|pnp@0||8|8|||YR|4
+Ipnp5;1{ic}|singlepn@0||24.75|13|||D0G4;
+Awire|net@0|||2700|pnp@0|s|10|10|conn@0|y|10|11
+Awire|net@1|||900|pnp@0|d|10|6|conn@1|y|10|4
+Awire|net@2|||0|pnp@0|g|7|8|conn@2|y|4|8
+Ebase||D4G2;|conn@2|a|B
+Ecol||D6G2;X-6;|conn@1|y|B
+Eemit||D4G2;|conn@0|a|B
+X
+
+# Cell pnp10;1{ic}
+Cpnp10;1{ic}||artwork|1075166155000|1158173452448|E|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NFilled-Triangle|art@1||1|1|1|2|1350||ART_color()I-4323839
+NPin|pin@0||-2|0|1|1||
+NPin|pin@1||2|-2|1|1||
+NPin|pin@2||0|-2|1|1||
+NPin|pin@3||0|2|1|1||
+NPin|pin@4||0|0|1|1||
+NPin|pin@5||2|2|1|1||
+Ngeneric:Invisible-Pin|pin@6||2|2||||
+Ngeneric:Invisible-Pin|pin@7||2|-2|||Y|
+Ngeneric:Invisible-Pin|pin@8||-2|0|||R|
+Ngeneric:Invisible-Pin|pin@9||3|0|||||ART_message(C74;D5G1.5;)S10X10
+AThicker|net@0|||FS0|pin@4||0|0|pin@0||-2|0|ART_color()I-4323839
+AThicker|net@1|||FS1350|pin@4||0|0|pin@1||2|-2|ART_color()I-4323839
+AThicker|net@2|||FS2700|pin@2||0|-2|pin@3||0|2|ART_color()I-4323839
+AThicker|net@3|||FS2250|pin@4||0|0|pin@5||2|2|ART_color()I-4323839
+Ebase||D5G2;|pin@8||B
+Ecol||D5G2;|pin@7||B
+Eemit||D5G2;|pin@6||B
+X
+
+# Cell pnp10;1{lay}
+Cpnp10;1{lay}||cmos90|1158278317514|1158345317356||DRC_last_good_drc_bit()I6|DRC_last_good_drc_date()G1158345327528
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NMetal-1-N-Well-Con|contact@2||135|-8|14.8|264.8||
+NMetal-1-N-Well-Con|contact@3||0|135|14.8|284.8|R|
+NMetal-1-N-Well-Con|contact@4||-135|-8|14.8|264.8||
+NMetal-1-P-Well-Con|contact@8||200|0|34.8|434.8||
+NMetal-1-P-Well-Con|contact@9||-200|0|34.8|434.8||
+NMetal-1-P-Active-Con|contact@10||-75|0|49.8|194.8||
+NMetal-1-P-Active-Con|contact@11||0|0|49.8|194.8||
+NMetal-1-P-Active-Con|contact@12||75|0|49.8|194.8||
+NMetal-1-Pin|pin@0||-75|0||||
+NMetal-1-Pin|pin@1||0|135||||
+NMetal-1-Pin|pin@2||-198|0||||
+NMetal-1-Pin|pin@3||201.5|0||||
+NMetal-1-Pin|pin@4||0|0||||
+NMetal-1-Pin|pin@5||75|0||||
+NBJTDMY-Node|plnode@0||0|0|480|480||
+NN-Well-Node|plnode@1||0|0|320|320||A
+NP-Select-Node|plnode@2||-200|0|80|480||
+NP-Select-Node|plnode@3||200|0|80|480||
+NP-Select-Node|plnode@4||0|200|320|80||
+NP-Select-Node|plnode@5||0|-200|320|80||
+NN-Select-Node|plnode@6||135|0|50|320||
+NN-Select-Node|plnode@7||-135|0|50|320||
+NN-Select-Node|plnode@8||0|135|220|50||
+NN-Select-Node|plnode@9||0|-135|220|50||
+NP-Select-Node|plnode@11||0|0|220|220||
+NMetal-1-P-Well-Con|well@3||-161|200|34.8|34.8||
+NMetal-1-P-Well-Con|well@4||-161|-200|34.8|34.8||
+NMetal-1-P-Well-Con|well@5||161|200|34.8|34.8||
+NMetal-1-P-Well-Con|well@6||161|-200|34.8|34.8||
+Ametal-1|net@10||36.6|IJS1800|well@6||178.4|-200|contact@8||182.6|-200
+Ametal-1|net@11||36.6|IJS0|well@4||-178.4|-200|contact@9||-182.6|-200
+Ametal-1|net@12||36.6|IJS0|well@3||-178.4|200|contact@9||-182.6|200
+Ametal-1|net@13||36.6|IJS1800|well@5||178.4|200|contact@8||182.6|200
+Ametal-1|net@15|||S0|contact@9||-198|0|pin@2||-198|0
+Ametal-1|net@16|||S0|contact@8||201.5|0|pin@3||201.5|0
+Ametal-1|net@18|||S0|contact@10||-75|0|pin@0||-75|0
+Ametal-1|net@19|||S0|contact@11||0|0|pin@4||0|0
+Ametal-1|net@22|||S0|contact@3||0|135|pin@1||0|135
+Ametal-1|net@23|||S2700|contact@2||138|124.4|contact@3||138|127.6
+Ametal-1|net@24|||S2700|contact@4||-134|124.4|contact@3||-134|127.6
+Ametal-1|net@25|||S0|contact@12||75|0|pin@5||75|0
+Ebase||D5G5;|pin@1||B
+Ecol||D5G5;|pin@2||B
+Ecol_1||D5G5;|pin@3||B
+Eemit||D5G5;|pin@0||B
+Eemit_1||D5G5;|pin@4||B
+Eemit_2||D5G5;|pin@5||B
+X
+
+# Cell pnp10;1{sch}
+Cpnp10;1{sch}||schematic|1075166061000|1158173555088||ATTR_CDL_template(D5G1;NTX9.5;Y-8;)SQ$(node_name) $(col) $(base) $(emit) pnp10 area=100p|ATTR_NCC(D5G1;NTX9.5;Y-4;)SblackBox does not detect PNPs|ATTR_SPICE_template(D5G1;NTX9.5;Y-6;)SQ$(node_name) $(col) $(base) $(emit) pnp10|ATTR_SPICE_template_assura(D5G1;NTX9.5;Y-10;)SQ$(node_name) $(col) $(base) $(emit) pnp10 area=100p|ATTR_SPICE_template_calibre(D5G1;NTX9.5;Y-12;)SQ$(node_name) $(col) $(base) $(emit) pnp10 area=100p|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||10|13|||RRR|
+NOff-Page|conn@1||10|2|||R|
+NOff-Page|conn@2||2|8||||
+Ngeneric:Invisible-Pin|pin@0||10|26.5|||||ART_message(D5G5;)Spnp10
+Ngeneric:Invisible-Pin|pin@1||10|21.5|||||ART_message(D5G2;)S10x10 vertical bipolar transistor
+NTransistor|pnp@0||8|8|||YR|4
+Ipnp10;1{ic}|singlepn@0||24.75|13|||D0G4;
+Awire|net@0|||2700|pnp@0|s|10|10|conn@0|y|10|11
+Awire|net@1|||900|pnp@0|d|10|6|conn@1|y|10|4
+Awire|net@2|||0|pnp@0|g|7|8|conn@2|y|4|8
+Ebase||D4G2;|conn@2|a|B
+Ecol||D6G2;X-6;|conn@1|y|B
+Eemit||D4G2;|conn@0|a|B
+X
+
+# Cell rnwod_m;1{ic}
+Crnwod_m;1{ic}||artwork|1047945855000|1223599831852|E|ATTR_L(D5FLeave alone;G1;HNOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX2.25;Y-2.25;)S8.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||3|0|1|1|Y|
+NPin|pin@1||2|0|1|1|Y|
+NPin|pin@2||1.5|-1|1|1|Y|
+NPin|pin@3||1|1|1|1|Y|
+NPin|pin@4||0.5|-1|1|1|Y|
+NPin|pin@5||0|1|1|1|Y|
+NPin|pin@6||-0.5|-1|1|1|Y|
+NPin|pin@7||-1|1|1|1|Y|
+NPin|pin@8||-1.5|-1|1|1|Y|
+NPin|pin@9||-2|0|1|1|Y|
+NPin|pin@10||-3|0|1|1|Y|
+Nschematic:Bus_Pin|pin@11||3|0||||
+Nschematic:Bus_Pin|pin@12||-3|0||||
+NPin|pin@13||-2.5|-0.75|1|1||
+NPin|pin@14||2.5|-0.75|1|1||
+NPin|pin@15||0|-1.5|1|1|YRRR|
+NPin|pin@16||0|-0.75|1|1|YRRR|
+Ngeneric:Invisible-Pin|pin@22||0.5|1|||||ART_message(D5G1;)S110
+Nschematic:Bus_Pin|pin@23||0|-1.5||||
+AThicker|net@0|||FS1800|pin@1||2|0|pin@0||3|0|ART_color()I74
+AThicker|net@1|||FS2434|pin@2||1.5|-1|pin@1||2|0|ART_color()I74
+AThicker|net@2|||FS1040|pin@3||1|1|pin@2||1.5|-1|ART_color()I74
+AThicker|net@3|||FS2560|pin@4||0.5|-1|pin@3||1|1|ART_color()I74
+AThicker|net@4|||FS1040|pin@5||0|1|pin@4||0.5|-1|ART_color()I74
+AThicker|net@5|||FS2560|pin@6||-0.5|-1|pin@5||0|1|ART_color()I74
+AThicker|net@6|||FS1040|pin@7||-1|1|pin@6||-0.5|-1|ART_color()I74
+AThicker|net@7|||FS2560|pin@8||-1.5|-1|pin@7||-1|1|ART_color()I74
+AThicker|net@8|||FS1166|pin@9||-2|0|pin@8||-1.5|-1|ART_color()I74
+AThicker|net@9|||FS1800|pin@10||-3|0|pin@9||-2|0|ART_color()I74
+AThicker|net@10|||FS1800|pin@13||-2.5|-0.75|pin@14||2.5|-0.75|ART_color()I74
+AThicker|net@11|||FS2700|pin@15||0|-1.5|pin@16||0|-0.75|ART_color()I74
+Ein_1|b|D5G2;|pin@23||I
+Ein||D5G2;|pin@12||I
+Eout||D5G2;|pin@11||O
+X
+
+# Cell rnwod_m;1{sch}
+Crnwod_m;1{sch}||schematic|1047945706000|1218132369505||ATTR_L(D5FLeave alone;G1;HNOLPX-22.5;Y-0.75;)S40|ATTR_W(D5FLeave alone;G1;HNOLPX-22.25;Y-1.75;)S8.8|ATTR_CDL_template(D5G1;NTX-2.5;Y-17;)SXR$(node_name) $(in) $(out) ($b) /rnwod l='$(L)*0.05u' w='$(W)*0.05u'|ATTR_NCC(D5G1;NTX-1.5;Y-21.5;)SresistorType  N-Poly-RPO-Resistor|ATTR_SPICE_template_assura(D5G1;NTX0.5;Y-25.5;)SXR$(node_name) $(in) $(out) $(b) rnwod l='$(L)*0.05u' w='$(W)*0.05u'|ATTR_SPICE_template_calibre(D5G1;NTX0.5;Y-23.5;)SXR$(node_name) $(in) $(out) $(b) rnwod_m lr='$(L)*0.05u' wr='$(W)*0.05u'|ATTR_SPICE_template_hspice(D5G1;NTX-1.5;Y-19.25;)SXR$(node_name) $(in) $(out) rnwod l='$(L)*0.05u' w='$(W)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTY-15;)SXR$(node_name) $(in) $(out) $(b) rnwod l='$(L)*0.05u' w='$(W)*0.05u'|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||-5.5|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX5.25;Y-5.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NCapacitor|cap@1||4.75|0|||||SCHEM_capacitance(D5FLeave alone;G1.5;OLUCX-4.25;Y-9.25;)S(0.265*@W*@L + 8.882*@W + 4.43*@L + 74.42)*1e-18/2
+NOff-Page|conn@0||10|5||||
+NOff-Page|conn@1||-11.5|5||||
+NOff-Page|conn@2||-0.5|-9|||RRR|
+Irnwod_m;1{ic}|gateResi@0||25.5|7.5|||D0G4;|ATTR_L(D5FLeave alone;G1;NOLPX-2;Y-2.25;)S40|ATTR_W(D5FLeave alone;G1;NOLPX2.25;Y-2.25;)S8.8
+Ngeneric:Invisible-Pin|pin@0||1|20.5|||||ART_message(D5G2;)Sn-type well resistor for TSMC90nm process
+Ngeneric:Invisible-Pin|pin@1||2.5|26.5|||||ART_message(D5G5;)Srnwod_m
+NWire_Pin|pin@2||-5.5|5||||
+NWire_Pin|pin@3||-5.5|-4.5||||
+NWire_Pin|pin@4||4.75|5||||
+NWire_Pin|pin@5||4.75|-4.5||||
+Ngeneric:Invisible-Pin|pin@6||1.5|15|||||ART_message(D5G2;)S["minumum recommended dimensions are l=2.0um, w=0.44um",target resistance is approx 330 ohm/sq]
+NWire_Pin|pin@9||-0.5|-4.5||||
+NResistor|res@0||-0.5|5||||1|ATTR_length(D5FLeave alone;G1;NOLY-1;)S@L|ATTR_width(D5FLeave alone;G1;NOLY-2;)S@W|SCHEM_resistance(D5FLeave alone;G2;OLY3;)S(@L*330/@W)
+Awire|net@0|||0|pin@2||-5.5|5|conn@1|y|-9.5|5
+Awire|net@1|||1800|pin@4||4.75|5|conn@0|a|8|5
+Awire|net@2|||0|res@0|a|-2.5|5|pin@2||-5.5|5
+Awire|net@3|||2700|cap@0|a|-5.5|2|pin@2||-5.5|5
+Awire|net@4|||900|cap@0|b|-5.5|-2|pin@3||-5.5|-4.5
+Awire|net@6|||1800|res@0|b|1.5|5|pin@4||4.75|5
+Awire|net@7|||2700|cap@1|a|4.75|2|pin@4||4.75|5
+Awire|net@8|||900|cap@1|b|4.75|-2|pin@5||4.75|-4.5
+Awire|net@12|||1800|pin@9||-0.5|-4.5|pin@5||4.75|-4.5
+Awire|net@14|||1800|pin@3||-5.5|-4.5|pin@9||-0.5|-4.5
+Awire|net@16|||2700|conn@2|a|-0.5|-7|pin@9||-0.5|-4.5
+Ein_1|b|D5G2;|conn@2|y|I
+Ein||D5G2;|conn@1|y|I
+Eout||D5G2;|conn@0|y|O
+X
+
+# Cell wire;1{ic}
+Cwire;1{ic}||artwork|1083964052000|1204183998562|E|ATTR_C(D5G1;HNOLPUCY-2.5;)S0.0000223p|ATTR_L(D5G1;HOLPUD)S100|ATTR_R(D5G1;HNOLPURY-1.5;)S0.024|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@2||2|0|1.5|1.5|||ART_color()I74
+NPin|pin@0||-2.75|0|1|1||
+NPin|pin@1||-4|0||||
+NPin|pin@2||2|0|1|1||
+NPin|pin@3||4|0||||
+NPin|pin@4||-2|0.75|1|1||
+NPin|pin@5||2|0.75|1|1||
+NPin|pin@6||2|-0.75|1|1||
+NPin|pin@7||-2|-0.75|1|1||
+Nschematic:Bus_Pin|pin@8||4|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||-4|0|-2|-2||
+AThicker|net@0|||IJS0|pin@0||-2.75|0|pin@1||-4|0|ART_color()I74
+AThicker|net@1|||IJS1800|pin@2||2|0|pin@3||4|0|ART_color()I74
+AThicker|net@2|||IJS0|pin@5||2|0.75|pin@4||-2|0.75|ART_color()I74
+AThicker|net@3|||IJS0|pin@6||2|-0.75|pin@7||-2|-0.75|ART_color()I74
+Ea||D5G2;|pin@9||U
+Eb||D5G2;|pin@8||U
+X
+
+# Cell wire;1{sch}
+Cwire;1{sch}||schematic|1083961993000|1173982560561||ATTR_C(D5G1;HNOLPUCX-19;Y-9;)S0.0000223p|ATTR_L(D5G1;HNOLPUDX-19;Y-7;)S100|ATTR_R(D5G1;HNOLPURX-19;Y-8;)S0.024|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||-10|0|||||SCHEM_capacitance(D5G1;OLUC)S@C*@L/3
+NCapacitor|cap@1||10|0|||||SCHEM_capacitance(D5G1;OLUC)S@C*@L/3
+NCapacitor|cap@2||0|0|||||SCHEM_capacitance(D5G1;OLUC)S@C*@L/3
+NOff-Page|conn@0||21|4|||RR|
+NOff-Page|conn@1||-21|4||||
+NGround|gnd@0||0|-8||||
+Ngeneric:Invisible-Pin|pin@0||15|7|||||ART_message(D5G1;)S[R2 ]
+Ngeneric:Invisible-Pin|pin@1||-15|7|||||ART_message(D5G1;)S[R1 = @R*@L/6]
+Ngeneric:Invisible-Pin|pin@2||0|7|||||ART_message(D5G1;)S[R12= @R*@L/3]
+Ngeneric:Invisible-Pin|pin@3||16.5|-2|||||ART_message(D5G1;)S[C = @C*@L/3]
+Ngeneric:Invisible-Pin|pin@4||0|14|||||ART_message(D5G2;)S[this is a wire 'L' lambda long,with resistance 'R' ohms/lambda,and capacitance 'C' F/lambda]
+Ngeneric:Invisible-Pin|pin@5||-1|22|||||ART_message(D5G6;)S[wire]
+NWire_Pin|pin@6||0|-4||||
+NWire_Pin|pin@7||10|-4||||
+NWire_Pin|pin@8||-10|-4||||
+NWire_Pin|pin@9||10|4||||
+NWire_Pin|pin@10||0|4||||
+NWire_Pin|pin@11||-10|4||||
+NResistor|res@0||-15|4|||||SCHEM_resistance(D5G1;OLURY1.5;)S@R*@L/6
+NResistor|res@1||-5|4|||||SCHEM_resistance(D5G1;OLURY1.5;)S@R*@L/3
+NResistor|res@2||15|4|||||SCHEM_resistance(D5G1;OLURY1.5;)S@R*@L/6
+NResistor|res@3||5|4|||||SCHEM_resistance(D5G1;OLURY1.5;)S@R*@L/3
+Iwire;1{ic}|wire@0||15|24|||D0G4;|ATTR_C(D5G1;NOLPUCY-2.5;)S2.23E-16|ATTR_L(D5G1;OLPUD)S100|ATTR_R(D5G1;NOLPURY-1.5;)S0.24
+Awire|net@0|||IJS1800|res@2|b|17|4|conn@0|y|19|4
+Awire|net@1|||IJS0|res@0|a|-17|4|conn@1|y|-19|4
+Awire|net@2|||IJS900|pin@6||0|-4|gnd@0||0|-6
+Awire|net@3|||IJS2700|pin@6||0|-4|cap@2|b|0|-2
+Awire|net@4|||IJS0|pin@7||10|-4|pin@6||0|-4
+Awire|net@5|||IJS0|pin@6||0|-4|pin@8||-10|-4
+Awire|net@6|||IJS900|cap@1|b|10|-2|pin@7||10|-4
+Awire|net@7|||IJS2700|pin@8||-10|-4|cap@0|b|-10|-2
+Awire|net@8|||IJS900|pin@9||10|4|cap@1|a|10|2
+Awire|net@9|||IJS0|res@2|a|13|4|pin@9||10|4
+Awire|net@10|||IJS0|pin@9||10|4|res@3|b|7|4
+Awire|net@11|||IJS900|pin@10||0|4|cap@2|a|0|2
+Awire|net@12|||IJS0|res@3|a|3|4|pin@10||0|4
+Awire|net@13|||IJS0|pin@10||0|4|res@1|b|-3|4
+Awire|net@14|||IJS900|pin@11||-10|4|cap@0|a|-10|2
+Awire|net@15|||IJS0|res@1|a|-7|4|pin@11||-10|4
+Awire|net@16|||IJS0|pin@11||-10|4|res@0|b|-13|4
+Ea||D4G2;|conn@1|a|U
+Eb||D6G2;X-5;|conn@0|y|U
+X
+
+# Cell wire90;1{ic}
+Cwire90;1{ic}||artwork|1083966364000|1204183998562|E|ATTR_L(D5FLeave alone;G1;HOLPUD)S100|ATTR_LEWIRE(D5G1;HPT)I1|ATTR_layer(D5FLeave alone;G1;HNOLPY-1;)S2|ATTR_width(D5FLeave alone;G1;HNOLPY-2;)S2.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.75|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@2||1.75|0|1.5|1.5|RRR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NPin|pin@0||-1.75|0.75|1|1||
+NPin|pin@1||1.75|0.75|1|1||
+NPin|pin@2||1.75|-0.75|1|1||
+NPin|pin@3||-1.75|-0.75|1|1||
+Nschematic:Bus_Pin|pin@4||2.5|0|-1|-1||
+Nschematic:Bus_Pin|pin@5||-2.5|0|-1|-1||
+AThicker|net@0|||FS0|pin@1||1.75|0.75|pin@0||-1.75|0.75|ART_color()I74
+AThicker|net@1|||FS0|pin@2||1.75|-0.75|pin@3||-1.75|-0.75|ART_color()I74
+Ea||D5G2;|pin@5||B
+Eb||D5G2;|pin@4||B
+X
+
+# Cell wire90;1{sch}
+Cwire90;1{sch}||schematic|1083965121000|1173982468235||ATTR_L(D5G1;HNOLPUDX-20.5;Y-6.5;)S100|ATTR_LEWIRE(D5G1;HNPTX-20.5;Y-9.5;)I1|ATTR_layer(D5FLeave alone;G1;HNOLPX-20.5;Y-7.5;)S2|ATTR_width(D5FLeave alone;G1;HNOLPX-20.5;Y-8.5;)S2.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-23|-1||||
+NOff-Page|conn@1||-5.5|-1|||YRR|
+Ngeneric:Invisible-Pin|pin@0||-4|6|||||ART_message(BD5G2;)Swire90
+Ngeneric:Invisible-Pin|pin@1||7|-8|||||ART_message(D5G1;)SR = (@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width
+Ngeneric:Invisible-Pin|pin@2||7|-6|||||ART_message(D5G1;)SC = (@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15
+Ngeneric:Invisible-Pin|pin@3||-9|2|||||ART_message(D6G1;)S["wire in layer 'layer', 'L' lambda long,","'width' lambda wide, for the 90nm tech"]
+Ngeneric:Invisible-Pin|pin@4||-12|-14|||||ART_message(D5G1;)Scapacitance (fF/lambda)
+Ngeneric:Invisible-Pin|pin@5||3.5|-14|||||ART_message(D5G1;)Sresistance (ohm/square)
+Ngeneric:Invisible-Pin|pin@6||3.5|-17.5|||||ART_message(D5G1;)SM1 - 0.104
+Ngeneric:Invisible-Pin|pin@7||3.5|-19|||||ART_message(D5G1;)SM2 - M7 : 0.0661
+Ngeneric:Invisible-Pin|pin@8||3.5|-20.5|||||ART_message(D5G1;)SM8 - M9 : 0.0221
+Ngeneric:Invisible-Pin|pin@9||3.5|-16|||||ART_message(D5G1;)Spoly - 8.5
+Ngeneric:Invisible-Pin|pin@10||18|-14|||||ART_message(D5G1;)Swidth (um/lambda)
+Ngeneric:Invisible-Pin|pin@11||18|-17.5|||||ART_message(D5G1;)SM1 - 0.12/2.4L
+Ngeneric:Invisible-Pin|pin@12||18|-19|||||ART_message(D5G1;)SM2 - M7 : 0.14/2.8L
+Ngeneric:Invisible-Pin|pin@13||18|-20.5|||||ART_message(D5G1;)SM8 - M9 : 0.42/8.4L
+Ngeneric:Invisible-Pin|pin@14||18|-16|||||ART_message(D5G1;)Spoly - 0.10/2L
+Ngeneric:Invisible-Pin|pin@15||-12|-18|||||ART_message(D5G1;)SM1 - 0.011
+Ngeneric:Invisible-Pin|pin@17||-12|-20.5|||||ART_message(D5G1;)SM8 - M9 : 0.016
+Ngeneric:Invisible-Pin|pin@18||-12|-16|||||ART_message(D5G1;)Spoly - 0.00441
+Iwire90;1{ic}|wire90@1||14|7.88|||D0G4;|ATTR_L(D5FLeave alone;G1;OLPUD)S100|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NOLPY-1;)S1|ATTR_width(D5FLeave alone;G1;NOLPY-2;)S3
+Iwire;1{ic}|wire@0||-15|-1|||D0G4;|ATTR_C(D5G1;NOLPUCY-2.5;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPUD)S@L|ATTR_R(D5G1;NOLPURY-1.5;)S(@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width
+Awire|net@0|||0|wire@0|a|-19|-1|conn@0|y|-21|-1
+Awire|net@1|||1800|wire@0|b|-11|-1|conn@1|y|-7.5|-1
+Ea||D4G2;|conn@0|a|B
+Eb||D4G2;|conn@1|a|B
+X
+
+# Cell wire90xcpl2;1{ic}
+Cwire90xcpl2;1{ic}||artwork|1083966364000|1204183998562|E|ATTR_L(D5FLeave alone;G1;HOLPUDY1;)S100|ATTR_layer(D5FLeave alone;G1;HNOLPY-0.5;)S2|ATTR_width(D5FLeave alone;G1;HNOLPY-1.5;)S2.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.75|1|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@2||1.75|1|1.5|1.5|RRR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@5||-1.75|-1|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@6||1.75|-1|1.5|1.5|RRR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NOpened-Polygon|art@8||-0.25|0|2.5|2|||ART_color()I74|trace()V[1.25/-1,-1.25/0,1.25/0,-1.25/1]
+NPin|pin@0||-1.75|1.75|1|1||
+NPin|pin@1||1.75|1.75|1|1||
+NPin|pin@2||1.75|0.25|1|1||
+NPin|pin@3||-1.75|0.25|1|1||
+Nschematic:Bus_Pin|pin@4||2.5|1|-1|-1||
+Nschematic:Bus_Pin|pin@5||-2.5|1|-1|-1||
+Ngeneric:Universal-Pin|pin@8||-2.5|-1|-1|-1||
+Ngeneric:Universal-Pin|pin@10||2.5|-1|-1|-1||
+NPin|pin@18||-1.75|-0.25|1|1||
+NPin|pin@19||1.75|-0.25|1|1||
+NPin|pin@20||1.75|-1.75|1|1||
+NPin|pin@21||-1.75|-1.75|1|1||
+AThicker|net@0|||FS0|pin@1||1.75|1.75|pin@0||-1.75|1.75|ART_color()I74
+AThicker|net@1|||FS0|pin@2||1.75|0.25|pin@3||-1.75|0.25|ART_color()I74
+AThicker|net@8|||FS0|pin@19||1.75|-0.25|pin@18||-1.75|-0.25|ART_color()I74
+AThicker|net@9|||FS0|pin@20||1.75|-1.75|pin@21||-1.75|-1.75|ART_color()I74
+Ea||D5G2;|pin@5||B
+Eb||D5G2;|pin@4||B
+Ec||D5G2;|pin@8||U
+Ed||D5G2;|pin@10||U
+X
+
+# Cell wire90xcpl2;1{sch}
+Cwire90xcpl2;1{sch}||schematic|1083965121000|1173982902241||ATTR_L(D5G1;HNOLPUDX-22.5;Y-12;)S100|ATTR_layer(D5G1;HNOLPX-22.5;Y-13;)S2|ATTR_width(D5G1;HNOLPX-22.5;Y-14;)S2.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-9|3.5||||
+NOff-Page|conn@1||8.5|3.5|||YRR|
+NOff-Page|conn@3||-9|-3.5||||
+NOff-Page|conn@4||8.5|-3.5|||YRR|
+Iwire_xcpl_sides;1{ic}|cplR[1:0]|D5G1;X5.5;|-0.5|0|||D0G4;|ATTR_C(D5FLeave alone;G1;NOLPUCY-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S@L|ATTR_LEIGNORE(PUD)I1
+NGround|gnd@0||-6.5|10|||RRR|
+NGround|gnd@1||-6.5|-9.5|||RRR|
+Ngeneric:Invisible-Pin|pin@0||0|18.5|||||ART_message(BD5G2;)Swire90xcpl2
+Ngeneric:Invisible-Pin|pin@1||1.5|-14.5|||||ART_message(D5G1;)SR = (@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width
+Ngeneric:Invisible-Pin|pin@2||1.5|-13|||||ART_message(D5G1;)SC = (@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15
+Ngeneric:Invisible-Pin|pin@3||-8.75|16|||||ART_message(D6G1;)S["wire in layer 'layer', 'L' lambda long,","'width' lambda wide, for the 90nm tech"]
+Ngeneric:Invisible-Pin|pin@4||-13|-17.5|||||ART_message(D5G1;)Scapacitance (fF/lambda)
+Ngeneric:Invisible-Pin|pin@5||2.5|-17.5|||||ART_message(D5G1;)Sresistance (ohm/square)
+Ngeneric:Invisible-Pin|pin@6||2.5|-21|||||ART_message(D5G1;)SM1 - 0.104
+Ngeneric:Invisible-Pin|pin@7||2.5|-22.5|||||ART_message(D5G1;)SM2 - M7 : 0.0661
+Ngeneric:Invisible-Pin|pin@8||2.5|-24|||||ART_message(D5G1;)SM8 - M9 : 0.0221
+Ngeneric:Invisible-Pin|pin@9||2.5|-19.5|||||ART_message(D5G1;)Spoly - 8.5
+Ngeneric:Invisible-Pin|pin@10||17|-17.5|||||ART_message(D5G1;)Swidth (um/lambda)
+Ngeneric:Invisible-Pin|pin@11||17|-21|||||ART_message(D5G1;)SM1 - 0.12/2.4L
+Ngeneric:Invisible-Pin|pin@12||17|-22.5|||||ART_message(D5G1;)SM2 - M7 : 0.14/2.8L
+Ngeneric:Invisible-Pin|pin@13||17|-24|||||ART_message(D5G1;)SM8 - M9 : 0.42/8.4L
+Ngeneric:Invisible-Pin|pin@14||17|-19.5|||||ART_message(D5G1;)Spoly - 0.10/2L
+Ngeneric:Invisible-Pin|pin@15||-13|-21.5|||||ART_message(D5G1;)SM1 - 0.011
+Ngeneric:Invisible-Pin|pin@17||-13|-24|||||ART_message(D5G1;)SM8 - M9 : 0.016
+Ngeneric:Invisible-Pin|pin@18||-13|-19.5|||||ART_message(D5G1;)Spoly - 0.00441
+NWire_Pin|pin@32||-2|10||||
+NWire_Pin|pin@33||1|10||||
+NWire_Pin|pin@34||-0.5|10||||
+NWire_Pin|pin@35||-2|-9.5||||
+NWire_Pin|pin@36||1|-9.5||||
+NWire_Pin|pin@37||-0.5|-9.5||||
+Iwire90xcpl2;1{ic}|wire90xc@3||21|14.38|||D0G4;|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S100|ATTR_layer(D5FLeave alone;G1;NOLPY-0.5;)S1|ATTR_width(D5FLeave alone;G1;NOLPY-1.5;)S3|ATTR_LEWIRE()I1
+Iwire_xcp_gnd;1{ic}|wire_xcp@3||-0.5|3.5|||D5G4;|ATTR_C(D5FLeave alone;G1;NOLPURX2.5;Y-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPURY1;)S@L|ATTR_LEWIRE(PUR)I1|ATTR_R(D5FLeave alone;G1;NOLPURX-3;Y-1;)S(@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width|ATTR_layer(OJPUR)S@layer|ATTR_width(OJPUR)S@width
+Iwire_xcp_gnd;1{ic}|wire_xcp@4||-0.5|-3.5|||D5G4;|ATTR_C(D5FLeave alone;G1;NOLPURX2.5;Y-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OJPURY1;)S@L|ATTR_LEWIRE(PUR)I1|ATTR_R(D5FLeave alone;G1;NOLPURX-3;Y-1;)S(@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width|ATTR_layer(OJPUR)S@layer|ATTR_width(OJPUR)S@width
+Iwire_xcpl_sides;1{ic}|wire_xcp@7||-0.5|7.5|||D0G4;|ATTR_C(D5FLeave alone;G1;NOLPUCY-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S@L|ATTR_LEIGNORE(PUD)I1
+Iwire_xcpl_sides;1{ic}|wire_xcp@8||-0.5|-7|||D0G4;|ATTR_C(D5FLeave alone;G1;NOLPUCY-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S@L|ATTR_LEIGNORE(PUD)I1
+Awire|net@10|||0|wire_xcp@3|a|-4.5|3.5|conn@0|y|-7|3.5
+Awire|net@12|||0|wire_xcp@4|a|-4.5|-3.5|conn@3|y|-7|-3.5
+Awire|net@13|||1800|wire_xcp@4|b|3.5|-3.5|conn@4|y|6.5|-3.5
+Awire|net@15|||1800|wire_xcp@3|b|3.5|3.5|conn@1|y|6.5|3.5
+Awire|net@40|||2700|cplR[1:0]|sL3|1|1|wire_xcp@3|sL3|1|3.5
+Awire|net@41|||2700|cplR[1:0]|sL2|-0.5|1|wire_xcp@3|sL2|-0.5|3.5
+Awire|net@45|||2700|cplR[1:0]|sL1|-2|1|wire_xcp@3|sL1|-2|3.5
+Awire|net@47|||2700|wire_xcp@4|sL3|1|-3.5|cplR[1:0]|sR3|1|-1
+Awire|net@50|||2700|wire_xcp@4|sL1|-2|-3.5|cplR[1:0]|sR1|-2|-1
+Awire|net@51|||2700|wire_xcp@4|sL2|-0.5|-3.5|cplR[1:0]|sR2|-0.5|-1
+Awire|net@55|||2700|wire_xcp@7|sL1|-2|8.5|pin@32||-2|10
+Awire|net@56|||1800|pin@34||-0.5|10|pin@33||1|10
+Awire|net@57|||900|pin@33||1|10|wire_xcp@7|sL3|1|8.5
+Awire|net@58|||1800|pin@32||-2|10|pin@34||-0.5|10
+Awire|net@59|||2700|wire_xcp@7|sL2|-0.5|8.5|pin@34||-0.5|10
+Awire|net@60|||1800|gnd@0||-4.5|10|pin@32||-2|10
+Awire|net@61|||2700|wire_xcp@8|sL3|1|-6|wire_xcp@4|sL3|1|-3.5
+Awire|net@62|||2700|wire_xcp@8|sL1|-2|-6|wire_xcp@4|sL1|-2|-3.5
+Awire|net@63|||2700|wire_xcp@8|sL2|-0.5|-6|wire_xcp@4|sL2|-0.5|-3.5
+Awire|net@64|||900|wire_xcp@8|sR1|-2|-8|pin@35||-2|-9.5
+Awire|net@65|||1800|pin@37||-0.5|-9.5|pin@36||1|-9.5
+Awire|net@66|||2700|pin@36||1|-9.5|wire_xcp@8|sR3|1|-8
+Awire|net@67|||1800|pin@35||-2|-9.5|pin@37||-0.5|-9.5
+Awire|net@68|||900|wire_xcp@8|sR2|-0.5|-8|pin@37||-0.5|-9.5
+Awire|net@69|||1800|gnd@1||-4.5|-9.5|pin@35||-2|-9.5
+Awire|net@73|||900|wire_xcp@7|sR3|1|6.5|wire_xcp@3|sL3|1|3.5
+Awire|net@74|||900|wire_xcp@7|sR1|-2|6.5|wire_xcp@3|sL1|-2|3.5
+Awire|net@75|||900|wire_xcp@7|sR2|-0.5|6.5|wire_xcp@3|sL2|-0.5|3.5
+Ea||D4G2;|conn@0|a|B
+Eb||D4G2;|conn@1|a|B
+Ec||D4G2;|conn@3|a|B
+Ed||D4G2;|conn@4|a|B
+X
+
+# Cell wire90xcpl3;1{ic}
+Cwire90xcpl3;1{ic}||artwork|1083966364000|1204183998562|E|ATTR_L(D5FLeave alone;G1;HOLPUDY1;)S100|ATTR_layer(D5FLeave alone;G1;HNOLPY-0.5;)S2|ATTR_width(D5FLeave alone;G1;HNOLPY-1.5;)S2.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-1.75|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@2||1.75|0|1.5|1.5|RRR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@3||-1.75|2|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@4||1.75|2|1.5|1.5|RRR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@5||-1.75|-2|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@6||1.75|-2|1.5|1.5|RRR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NOpened-Polygon|art@7||-0.25|1|2.5|2|||ART_color()I74|trace()V[1.25/-1,-1.25/0,1.25/0,-1.25/1]
+NOpened-Polygon|art@8||-0.25|-1|2.5|2|||ART_color()I74|trace()V[1.25/-1,-1.25/0,1.25/0,-1.25/1]
+NPin|pin@0||-1.75|0.75|1|1||
+NPin|pin@1||1.75|0.75|1|1||
+NPin|pin@2||1.75|-0.75|1|1||
+NPin|pin@3||-1.75|-0.75|1|1||
+Nschematic:Bus_Pin|pin@4||2.5|0|-1|-1||
+Nschematic:Bus_Pin|pin@5||-2.5|0|-1|-1||
+Ngeneric:Universal-Pin|pin@6||-2.5|2|-1|-1||
+Ngeneric:Universal-Pin|pin@8||-2.5|-2|-1|-1||
+Ngeneric:Universal-Pin|pin@10||2.5|-2|-1|-1||
+Ngeneric:Universal-Pin|pin@12||2.5|2|-1|-1||
+NPin|pin@14||-1.75|2.75|1|1||
+NPin|pin@15||1.75|2.75|1|1||
+NPin|pin@16||1.75|1.25|1|1||
+NPin|pin@17||-1.75|1.25|1|1||
+NPin|pin@18||-1.75|-1.25|1|1||
+NPin|pin@19||1.75|-1.25|1|1||
+NPin|pin@20||1.75|-2.75|1|1||
+NPin|pin@21||-1.75|-2.75|1|1||
+AThicker|net@0|||FS0|pin@1||1.75|0.75|pin@0||-1.75|0.75|ART_color()I74
+AThicker|net@1|||FS0|pin@2||1.75|-0.75|pin@3||-1.75|-0.75|ART_color()I74
+AThicker|net@6|||FS0|pin@15||1.75|2.75|pin@14||-1.75|2.75|ART_color()I74
+AThicker|net@7|||FS0|pin@16||1.75|1.25|pin@17||-1.75|1.25|ART_color()I74
+AThicker|net@8|||FS0|pin@19||1.75|-1.25|pin@18||-1.75|-1.25|ART_color()I74
+AThicker|net@9|||FS0|pin@20||1.75|-2.75|pin@21||-1.75|-2.75|ART_color()I74
+Ea||D5G2;|pin@5||B
+EaL||D5G2;|pin@6||U
+EaR||D5G2;|pin@8||U
+Eb||D5G2;|pin@4||B
+EbL||D5G2;|pin@12||U
+EbR||D5G2;|pin@10||U
+X
+
+# Cell wire90xcpl3;1{sch}
+Cwire90xcpl3;1{sch}||schematic|1083965121000|1158010267102||ATTR_L(D5FLeave alone;G1;HNOLPUDX-22.5;Y-15.5;)S100|ATTR_layer(D5FLeave alone;G1;HNOLPX-22.5;Y-16.5;)S2|ATTR_width(D5FLeave alone;G1;HNOLPX-22.5;Y-17.5;)S2.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-9|0||||
+NOff-Page|conn@1||8.5|0|||YRR|
+NOff-Page|conn@2||-9|7||||
+NOff-Page|conn@3||-9|-7||||
+NOff-Page|conn@4||8.5|-7|||YRR|
+NOff-Page|conn@5||8.5|7|||YRR|
+Iwire_xcpl_sides;1{ic}|cplL[1:0]|D5G1;X5.5;|-0.5|3.5|||D0G4;|ATTR_C(D5FLeave alone;G1;NOLPUCY-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S@L|ATTR_LEIGNORE(PUD)I1
+Iwire_xcpl_sides;1{ic}|cplR[1:0]|D5G1;X5.5;|-0.5|-3.5|||D0G4;|ATTR_C(D5FLeave alone;G1;NOLPUCY-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S@L|ATTR_LEIGNORE(PUD)I1
+NGround|gnd@0||-6.5|13.5|||RRR|
+NGround|gnd@1||-6.5|-13|||RRR|
+Ngeneric:Invisible-Pin|pin@0||0|20.5|||||ART_message(BD5G2;)Swire90xcpl2
+Ngeneric:Invisible-Pin|pin@1||1.5|-18|||||ART_message(D5G1;)SR = (@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width
+Ngeneric:Invisible-Pin|pin@2||1.5|-16.5|||||ART_message(D5G1;)SC = (@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15
+Ngeneric:Invisible-Pin|pin@3||-8.75|18|||||ART_message(D6G1;)S["wire in layer 'layer', 'L' lambda long,","'width' lambda wide, for the 90nm tech"]
+Ngeneric:Invisible-Pin|pin@4||-13|-21|||||ART_message(D5G1;)Scapacitance (fF/lambda)
+Ngeneric:Invisible-Pin|pin@5||2.5|-21|||||ART_message(D5G1;)Sresistance (ohm/square)
+Ngeneric:Invisible-Pin|pin@6||2.5|-24.5|||||ART_message(D5G1;)SM1 - 0.104
+Ngeneric:Invisible-Pin|pin@7||2.5|-26|||||ART_message(D5G1;)SM2 - M7 : 0.0661
+Ngeneric:Invisible-Pin|pin@8||2.5|-27.5|||||ART_message(D5G1;)SM8 - M9 : 0.0221
+Ngeneric:Invisible-Pin|pin@9||2.5|-23|||||ART_message(D5G1;)Spoly - 8.5
+Ngeneric:Invisible-Pin|pin@10||17|-21|||||ART_message(D5G1;)Swidth (um/lambda)
+Ngeneric:Invisible-Pin|pin@11||17|-24.5|||||ART_message(D5G1;)SM1 - 0.12/2.4L
+Ngeneric:Invisible-Pin|pin@12||17|-26|||||ART_message(D5G1;)SM2 - M7 : 0.14/2.8L
+Ngeneric:Invisible-Pin|pin@13||17|-27.5|||||ART_message(D5G1;)SM8 - M9 : 0.42/8.4L
+Ngeneric:Invisible-Pin|pin@14||17|-23|||||ART_message(D5G1;)Spoly - 0.10/2L
+Ngeneric:Invisible-Pin|pin@15||-13|-25|||||ART_message(D5G1;)SM1 - 0.011
+Ngeneric:Invisible-Pin|pin@17||-13|-27.5|||||ART_message(D5G1;)SM8 - M9 : 0.016
+Ngeneric:Invisible-Pin|pin@18||-13|-23|||||ART_message(D5G1;)Spoly - 0.00441
+NWire_Pin|pin@32||-2|13.5||||
+NWire_Pin|pin@33||1|13.5||||
+NWire_Pin|pin@34||-0.5|13.5||||
+NWire_Pin|pin@35||-2|-13||||
+NWire_Pin|pin@36||1|-13||||
+NWire_Pin|pin@37||-0.5|-13||||
+Iwire90xcpl3;1{ic}|wire90xc@1||20.5|15.88|||D0G4;|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S100|ATTR_layer(D5FLeave alone;G1;NOLPY-0.5;)S1|ATTR_width(D5FLeave alone;G1;NOLPY-1.5;)S3|ATTR_LEWIRE()I1
+Iwire_xcp_gnd;1{ic}|wire_xcp@2||-0.5|7|||D5G4;|ATTR_C(D5FLeave alone;G1;NOLPURX2.5;Y-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPURY1;)S@L|ATTR_LEWIRE(PUR)I1|ATTR_R(D5G1;NOLPURX-3;Y-1;)S(@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width|ATTR_layer(OJPUR)S@layer|ATTR_width(OJPUR)S@width
+Iwire_xcp_gnd;1{ic}|wire_xcp@3||-0.5|0|||D5G4;|ATTR_C(D5FLeave alone;G1;NOLPURX2.5;Y-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPURY1;)S@L|ATTR_LEWIRE(PUR)I1|ATTR_R(D5FLeave alone;G1;NOLPURX-3;Y-1;)S(@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width|ATTR_layer(OJPUR)S@layer|ATTR_width(OJPUR)S@width
+Iwire_xcp_gnd;1{ic}|wire_xcp@4||-0.5|-7|||D5G4;|ATTR_C(D5FLeave alone;G1;NOLPURX2.5;Y-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPURY1;)S@L|ATTR_LEWIRE(PUR)I1|ATTR_R(D5FLeave alone;G1;NOLPURX-3;Y-1;)S(@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width|ATTR_layer(OJPUR)S@layer|ATTR_width(OJPUR)S@width
+Iwire_xcpl_sides;1{ic}|wire_xcp@7||-0.5|11|||D0G4;|ATTR_C(D5FLeave alone;G1;NOLPUCY-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S@L|ATTR_LEIGNORE(PUD)I1
+Iwire_xcpl_sides;1{ic}|wire_xcp@8||-0.5|-10.5|||D0G4;|ATTR_C(D5FLeave alone;G1;NOLPUCY-1;)S(@layer==0?0.00441:@layer<8?0.011:0.016)*1e-15|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S@L|ATTR_LEIGNORE(PUD)I1
+Awire|net@10|||0|wire_xcp@3|a|-4.5|0|conn@0|y|-7|0
+Awire|net@11|||0|wire_xcp@2|a|-4.5|7|conn@2|y|-7|7
+Awire|net@12|||0|wire_xcp@4|a|-4.5|-7|conn@3|y|-7|-7
+Awire|net@13|||1800|wire_xcp@4|b|3.5|-7|conn@4|y|6.5|-7
+Awire|net@14|||1800|wire_xcp@2|b|3.5|7|conn@5|y|6.5|7
+Awire|net@15|||1800|wire_xcp@3|b|3.5|0|conn@1|y|6.5|0
+Awire|net@40|||2700|cplR[1:0]|sL3|1|-2.5|wire_xcp@3|sL3|1|0
+Awire|net@41|||2700|cplR[1:0]|sL2|-0.5|-2.5|wire_xcp@3|sL2|-0.5|0
+Awire|net@42|||2700|cplL[1:0]|sL2|-0.5|4.5|wire_xcp@2|sL2|-0.5|7
+Awire|net@43|||2700|cplL[1:0]|sL1|-2|4.5|wire_xcp@2|sL1|-2|7
+Awire|net@44|||2700|cplL[1:0]|sL3|1|4.5|wire_xcp@2|sL3|1|7
+Awire|net@45|||2700|cplR[1:0]|sL1|-2|-2.5|wire_xcp@3|sL1|-2|0
+Awire|net@46|||2700|wire_xcp@3|sL3|1|0|cplL[1:0]|sR3|1|2.5
+Awire|net@47|||2700|wire_xcp@4|sL3|1|-7|cplR[1:0]|sR3|1|-4.5
+Awire|net@48|||2700|wire_xcp@3|sL1|-2|0|cplL[1:0]|sR1|-2|2.5
+Awire|net@49|||2700|wire_xcp@3|sL2|-0.5|0|cplL[1:0]|sR2|-0.5|2.5
+Awire|net@50|||2700|wire_xcp@4|sL1|-2|-7|cplR[1:0]|sR1|-2|-4.5
+Awire|net@51|||2700|wire_xcp@4|sL2|-0.5|-7|cplR[1:0]|sR2|-0.5|-4.5
+Awire|net@52|||900|wire_xcp@7|sR3|1|10|wire_xcp@2|sL3|1|7
+Awire|net@53|||900|wire_xcp@7|sR1|-2|10|wire_xcp@2|sL1|-2|7
+Awire|net@54|||900|wire_xcp@7|sR2|-0.5|10|wire_xcp@2|sL2|-0.5|7
+Awire|net@55|||2700|wire_xcp@7|sL1|-2|12|pin@32||-2|13.5
+Awire|net@56|||1800|pin@34||-0.5|13.5|pin@33||1|13.5
+Awire|net@57|||900|pin@33||1|13.5|wire_xcp@7|sL3|1|12
+Awire|net@58|||1800|pin@32||-2|13.5|pin@34||-0.5|13.5
+Awire|net@59|||2700|wire_xcp@7|sL2|-0.5|12|pin@34||-0.5|13.5
+Awire|net@60|||1800|gnd@0||-4.5|13.5|pin@32||-2|13.5
+Awire|net@61|||2700|wire_xcp@8|sL3|1|-9.5|wire_xcp@4|sL3|1|-7
+Awire|net@62|||2700|wire_xcp@8|sL1|-2|-9.5|wire_xcp@4|sL1|-2|-7
+Awire|net@63|||2700|wire_xcp@8|sL2|-0.5|-9.5|wire_xcp@4|sL2|-0.5|-7
+Awire|net@64|||900|wire_xcp@8|sR1|-2|-11.5|pin@35||-2|-13
+Awire|net@65|||1800|pin@37||-0.5|-13|pin@36||1|-13
+Awire|net@66|||2700|pin@36||1|-13|wire_xcp@8|sR3|1|-11.5
+Awire|net@67|||1800|pin@35||-2|-13|pin@37||-0.5|-13
+Awire|net@68|||900|wire_xcp@8|sR2|-0.5|-11.5|pin@37||-0.5|-13
+Awire|net@69|||1800|gnd@1||-4.5|-13|pin@35||-2|-13
+Ea||D4G2;|conn@0|a|B
+EaL||D4G2;|conn@2|a|B
+EaR||D4G2;|conn@3|a|B
+Eb||D4G2;|conn@1|a|B
+EbL||D4G2;|conn@5|a|B
+EbR||D4G2;|conn@4|a|B
+X
+
+# Cell wireC;1{ic}
+CwireC;1{ic}||artwork|1014599103000|1204183998562|E|ATTR_L(D6FLeave alone;G1.5;HNOLPX1.5;Y0.5;)S100|ATTR_layer(D5FLeave alone;G1;HNOLPX3;Y-1.5;)S1|ATTR_width(D5FLeave alone;G1;HNOLPX3;Y-0.5;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||0|-3|1|1||
+NPin|pin@1||-1|-2|1|1|||ART_color()I78
+NPin|pin@2||1|-2|1|1|||ART_color()I78
+NPin|pin@3||0|-2|1|1||
+NPin|pin@4||0|-0.25|1|1|||ART_color()I78
+NPin|pin@5||0|2|1|1||
+NPin|pin@6||0|0.25|1|1|||ART_color()I78
+NPin|pin@7||-1|0.25|1|1|||ART_color()I78
+NPin|pin@8||1|0.25|1|1|||ART_color()I78
+NPin|pin@9||1|-0.25|1|1|||ART_color()I78
+NPin|pin@10||-1|-0.25|1|1|||ART_color()I78
+Nschematic:Bus_Pin|pin@11||0|2|-2|-2||
+AThicker|net@0|||FS450|pin@2||1|-2|pin@0||0|-3|ART_color()I74
+AThicker|net@1|||FS3150|pin@0||0|-3|pin@1||-1|-2|ART_color()I74
+AThicker|net@2|||FS0|pin@2||1|-2|pin@1||-1|-2|ART_color()I74
+AThicker|net@3|||FS900|pin@4||0|-0.25|pin@3||0|-2|ART_color()I74
+AThicker|net@4|||FS900|pin@5||0|2|pin@6||0|0.25|ART_color()I74
+AThicker|net@5|||FS0|pin@8||1|0.25|pin@7||-1|0.25|ART_color()I74
+AThicker|net@6|||FS0|pin@9||1|-0.25|pin@10||-1|-0.25|ART_color()I74
+Ea||D5G1;|pin@11||I
+X
+
+# Cell wireC;1{sch}
+CwireC;1{sch}||schematic|1014598612000|1158084188511||ATTR_L(D5FLeave alone;G1;HNOLPX-16;Y-4;)S100|ATTR_layer(D5FLeave alone;G1;HNOLPX-16;Y-5;)S1|ATTR_width(D5FLeave alone;G1;HNOLPX-16;Y-6;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||0|0|||||SCHEM_capacitance(D5G1;OLUC)S(@layer==0?0.015:@layer<6?0.025:0.030) * @L * 1e-15
+NOff-Page|conn@0||0|7|||RRR|
+NGround|gnd@0||0|-6||||
+Ngeneric:Invisible-Pin|pin@0||0|-9|||||ART_message(D5G1;)S[(@layer==0?0.015:@layer<6?0.025:0.030)*@L*1e-15]
+Ngeneric:Invisible-Pin|pin@1||-20|9|||||ART_message(D6G2;)S[the capacitance in fF of,a layer 'layer' wire,L lambda long and,'width' lambda wide]
+Ngeneric:Invisible-Pin|pin@2||-2|18|||||ART_message(D5G6;)SwireC90
+IwireC;1{ic}|wireC@0||9|9|||D0G4;|ATTR_L(D6FLeave alone;G1.5;NOLPX1.5;Y0.5;)S100|ATTR_layer(D5FLeave alone;G1;NOLPX3;Y-1.5;)S1|ATTR_width(D5FLeave alone;G1;NOLPX3;Y-0.5;)S3
+Awire|net@0|||2700|cap@0|a|0|2|conn@0|y|0|5
+Awire|net@1|||2700|gnd@0||0|-4|cap@0|b|0|-2
+Ea||D5G2;|conn@0|a|I
+X
+
+# Cell wireR;1{ic}
+CwireR;1{ic}||artwork|1012169520000|1204183998562|E|ATTR_L(D5FLeave alone;G1.5;HNOLPY1;)S100|ATTR_layer(D5G1;HNOLPY-2.5;)S1|ATTR_width(D5FLeave alone;G1;HNOLPY-1.5;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NPin|pin@0||-4|0|1|1||
+NPin|pin@1||4|0|1|1||
+NPin|pin@2||2.5|0|1|1||
+NPin|pin@3||2|-1|1|1||
+NPin|pin@4||1|1|1|1||
+NPin|pin@5||0|-1|1|1||
+NPin|pin@6||-1|1|1|1||
+NPin|pin@7||-2|-1|1|1||
+NPin|pin@8||-2.5|0|1|1||
+Nschematic:Bus_Pin|pin@9||-4|0|-2|-2||
+Nschematic:Bus_Pin|pin@10||4|0|-2|-2||
+AThicker|net@0|||FS1800|pin@0||-4|0|pin@8||-2.5|0|ART_color()I74
+AThicker|net@1|||FS0|pin@1||4|0|pin@2||2.5|0|ART_color()I74
+AThicker|net@2|||FS634|pin@2||2.5|0|pin@3||2|-1|ART_color()I74
+AThicker|net@3|||FS2966|pin@3||2|-1|pin@4||1|1|ART_color()I74
+AThicker|net@4|||FS634|pin@4||1|1|pin@5||0|-1|ART_color()I74
+AThicker|net@5|||FS2966|pin@5||0|-1|pin@6||-1|1|ART_color()I74
+AThicker|net@6|||FS634|pin@6||-1|1|pin@7||-2|-1|ART_color()I74
+AThicker|net@7|||FS2966|pin@7||-2|-1|pin@8||-2.5|0|ART_color()I74
+Ea||D5G1;|pin@9||U
+Eb||D5G1;|pin@10||U
+X
+
+# Cell wireR;1{sch}
+CwireR;1{sch}||schematic|1012169378000|1158084177716||ATTR_L(D5FLeave alone;G1;HNOLPX-5.5;Y-5;)S100|ATTR_layer(D5FLeave alone;G1;HNOLPX-5.5;Y-6;)S1|ATTR_width(D5FLeave alone;G1;HNOLPX-5.5;Y-7;)S3|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-14|0||||
+NOff-Page|conn@1||14|0|||RR|
+Ngeneric:Invisible-Pin|pin@0||-16|12|||||ART_message(D6G2;)S[the resistance in ohms of,a layer 'layer' wire,L lambda long and,'width' lambda wide]
+Ngeneric:Invisible-Pin|pin@1||0|5|||||ART_message(D5G1;)S(@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width
+Ngeneric:Invisible-Pin|pin@2||-4|20.5|||||ART_message(D5G6;)SwireR90
+NResistor|res@0||0|0|||||SCHEM_resistance(D5G1;OLURY1.5;)S(@layer==0?8.5:@layer==1?0.104:@layer<8?0.0661:0.0221)/@width
+IwireR;1{ic}|wireR@0||11|10|||D0G4;|ATTR_L(D5FLeave alone;G1.5;NOLPY1;)S100|ATTR_layer(D5G1;NOLPY-2.5;)S1|ATTR_width(D5FLeave alone;G1;NOLPY-1.5;)S3
+Awire|net@0|||0|conn@1|y|12|0|res@0|b|2|0
+Awire|net@1|||0|res@0|a|-2|0|conn@0|y|-12|0
+Ea||D5G2;|conn@0|a|U
+Eb||D5G2;|conn@1|a|U
+X
+
+# Cell wire_xcp_gnd;1{ic}
+Cwire_xcp_gnd;1{ic}||artwork|1083964052000|1213379062437|E|ATTR_C(D5G1;HNOLPURX2.5;Y-1;)S0.223f|ATTR_L(D5G1;HOLPURY1;)S100|ATTR_LEWIRE(D5G1;HPTUR)I1|ATTR_R(D5G1;HNOLPURX-3;Y-1;)S24m|ATTR_layer(D5G1;HOLPTUR)S2|ATTR_width(D5G1;HOLPTUR)S2.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@3||-2|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@4||2|0|1.5|1.5|||ART_color()I74
+Nschematic:Bus_Pin|pin@8||4|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||-4|0|-2|-2||
+NPin|pin@20||-2|0.75|1|1||
+NPin|pin@21||2|0.75|1|1||
+NPin|pin@22||2|-0.75|1|1||
+NPin|pin@23||-2|-0.75|1|1||
+NPin|pin@24||2|0|1|1||
+NPin|pin@25||4|0||||
+NPin|pin@26||-2.75|0|1|1||
+NPin|pin@27||-4|0||||
+Ngeneric:Universal-Pin|pin@46||-1.5|0|-1|-1||
+Ngeneric:Universal-Pin|pin@48||0|0|-1|-1||
+Ngeneric:Universal-Pin|pin@50||1.5|0|-1|-1||
+NPin|pin@56||0.25|-0.25|1|1||
+NPin|pin@57||-0.25|-0.25||||
+NPin|pin@58||0.25|0.25|1|1||
+NPin|pin@59||-0.25|0.25|1|1||
+NPin|pin@60||-1.25|-0.25|1|1||
+NPin|pin@61||-1.75|-0.25||||
+NPin|pin@62||-1.25|0.25|1|1||
+NPin|pin@63||-1.75|0.25|1|1||
+NPin|pin@64||1.75|-0.25|1|1||
+NPin|pin@65||1.25|-0.25||||
+NPin|pin@66||1.75|0.25|1|1||
+NPin|pin@67||1.25|0.25|1|1||
+AThicker|net@8|||IJS0|pin@21||2|0.75|pin@20||-2|0.75|ART_color()I74
+AThicker|net@9|||IJS0|pin@22||2|-0.75|pin@23||-2|-0.75|ART_color()I74
+AThicker|net@10|||IJS1800|pin@24||2|0|pin@25||4|0|ART_color()I74
+AThicker|net@11|||IJS0|pin@26||-2.75|0|pin@27||-4|0|ART_color()I74
+AThicker|net@27|||IJS0|pin@56||0.25|-0.25|pin@57||-0.25|-0.25|ART_color()I74
+AThicker|net@28|||IJS2700|pin@56||0.25|-0.25|pin@58||0.25|0.25|ART_color()I74
+AThicker|net@29|||IJS0|pin@58||0.25|0.25|pin@59||-0.25|0.25|ART_color()I74
+AThicker|net@30|||IJS900|pin@59||-0.25|0.25|pin@57||-0.25|-0.25|ART_color()I74
+AThicker|net@31|||IJS0|pin@60||-1.25|-0.25|pin@61||-1.75|-0.25|ART_color()I74
+AThicker|net@32|||IJS2700|pin@60||-1.25|-0.25|pin@62||-1.25|0.25|ART_color()I74
+AThicker|net@33|||IJS0|pin@62||-1.25|0.25|pin@63||-1.75|0.25|ART_color()I74
+AThicker|net@34|||IJS900|pin@63||-1.75|0.25|pin@61||-1.75|-0.25|ART_color()I74
+AThicker|net@35|||IJS0|pin@64||1.75|-0.25|pin@65||1.25|-0.25|ART_color()I74
+AThicker|net@36|||IJS2700|pin@64||1.75|-0.25|pin@66||1.75|0.25|ART_color()I74
+AThicker|net@37|||IJS0|pin@66||1.75|0.25|pin@67||1.25|0.25|ART_color()I74
+AThicker|net@38|||IJS900|pin@67||1.25|0.25|pin@65||1.25|-0.25|ART_color()I74
+Ea||D5G2;|pin@9||U
+Eb||D5G2;|pin@8||U
+EsL1||D5G2;|pin@46||U
+EsL2||D5G2;|pin@48||U
+EsL3||D5G2;|pin@50||U
+X
+
+# Cell wire_xcp_gnd;1{sch}
+Cwire_xcp_gnd;1{sch}||schematic|1083961993000|1173982789482||ATTR_C(D5FLeave alone;G1;HNOLPURX-20.5;Y-10.5;)S0.223f|ATTR_L(D5FLeave alone;G1;HNOLPURX-20.5;Y-7.5;)S100|ATTR_LEWIRE(D5G1;HNPTURX-20.5;Y-12;)I1|ATTR_R(D5FLeave alone;G1;HNOLPURX-20.5;Y-9;)S24m|ATTR_layer(D5FLeave alone;G1;HNOLPTURX-20.5;Y-13;)S2|ATTR_width(D5FLeave alone;G1;HNOLPTURX-20.5;Y-15;)S2.8|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@9||-10|-5.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.1
+NCapacitor|cap@10||10|-5.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.1
+NCapacitor|cap@11||0|-5.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.1
+NOff-Page|conn@0||24.5|0|||RR|
+NOff-Page|conn@1||-21|0||||
+NOff-Page|conn@6||-10|8|||RRR|
+NOff-Page|conn@7||0|8|||RRR|
+NOff-Page|conn@8||10|8|||RRR|
+NGround|gnd@1||15|-10|||R|
+Ngeneric:Invisible-Pin|pin@0||15|17.5|||||ART_message(D5G1;)S[R2 ]
+Ngeneric:Invisible-Pin|pin@1||-15|17.5|||||ART_message(D5G1;)S[R1 = @R*@L/6]
+Ngeneric:Invisible-Pin|pin@2||0|17.5|||||ART_message(D5G1;)S[R12= @R*@L/3]
+Ngeneric:Invisible-Pin|pin@4||0|25.5|||||ART_message(D5G2;)S[this is a wire 'L' lambda long,with resistance 'R' ohms/lambda,and capacitance 'C' F/lambda]
+Ngeneric:Invisible-Pin|pin@5||-1|33.5|||||ART_message(D5G6;)Swire_xcpl_gnd
+NWire_Pin|pin@15||10|0||||
+NWire_Pin|pin@16||0|0||||
+NWire_Pin|pin@17||-10|0||||
+NWire_Pin|pin@21||-10|-10||||
+NWire_Pin|pin@22||0|-10||||
+NWire_Pin|pin@23||10|-10||||
+Ngeneric:Invisible-Pin|pin@38||28|-6.5|||||ART_message(D5G1;)SCc = 0.45Ctotal
+NResistor|res@0||-15|0|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/6
+NResistor|res@1||-5|0|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/3
+NResistor|res@2||18.5|0|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/6
+NResistor|res@3||5|0|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/3
+Iwire_xcp_gnd;1{ic}|wire_xcp@3||30|29.5|||D0G4;|ATTR_C(D5G1;NOLPURX2.5;Y-1;)S0.223f|ATTR_L(D5G1;OLPURY1;)S100|ATTR_LEWIRE(PUR)I1|ATTR_R(D5G1;NOLPURX-3;Y-1;)S24m|ATTR_layer(PUR)I2|ATTR_width(PUR)D2.8
+Awire|net@0|||IJS1800|res@2|b|20.5|0|conn@0|y|22.5|0
+Awire|net@1|||IJS0|res@0|a|-17|0|conn@1|y|-19|0
+Awire|net@17|||0|pin@15||10|0|res@3|b|7|0
+Awire|net@18|||0|pin@16||0|0|res@1|b|-3|0
+Awire|net@19|||0|pin@17||-10|0|res@0|b|-13|0
+Awire|net@36|||0|res@2|a|16.5|0|pin@15||10|0
+Awire|net@41|||0|res@3|a|3|0|pin@16||0|0
+Awire|net@43|||0|res@1|a|-7|0|pin@17||-10|0
+Awire|net@54|||900|cap@9|b|-10|-7.5|pin@21||-10|-10
+Awire|net@55|||1800|pin@21||-10|-10|pin@22||0|-10
+Awire|net@56|||2700|pin@22||0|-10|cap@11|b|0|-7.5
+Awire|net@57|||1800|pin@22||0|-10|pin@23||10|-10
+Awire|net@58|||2700|pin@23||10|-10|cap@10|b|10|-7.5
+Awire|net@59|||0|gnd@1||13|-10|pin@23||10|-10
+Awire|net@79|||900|conn@6|y|-10|6|pin@17||-10|0
+Awire|net@80|||900|conn@7|y|0|6|pin@16||0|0
+Awire|net@81|||900|conn@8|y|10|6|pin@15||10|0
+Awire|net@85|||2700|cap@11|a|0|-3.5|pin@16||0|0
+Awire|net@86|||900|pin@15||10|0|cap@10|a|10|-3.5
+Awire|net@87|||900|pin@17||-10|0|cap@9|a|-10|-3.5
+Ea||D4G2;|conn@1|a|U
+Eb||D6G2;X-5;|conn@0|y|U
+EsL1||D4G2;|conn@6|a|U
+EsL2||D4G2;|conn@7|a|U
+EsL3||D4G2;|conn@8|a|U
+X
+
+# Cell wire_xcpl;1{ic}
+Cwire_xcpl;1{ic}||artwork|1083964052000|1204183998562|E|ATTR_C(D5FLeave alone;G1;HNOLPUCY-2;)S0.0000223p|ATTR_L(D5FLeave alone;G1;HOLPUDY1;)S100|ATTR_R(D5FLeave alone;G1;HNOLPURY-1;)S0.024|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@1||-2|-2|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@2||2|-2|1.5|1.5|||ART_color()I74
+NThick-Circle|art@3||-2|0|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@4||2|0|1.5|1.5|||ART_color()I74
+NThick-Circle|art@7||-2|2|1.5|1.5|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@8||2|2|1.5|1.5|||ART_color()I74
+NOpened-Polygon|art@9||-0.25|-1|2.5|2|||ART_color()I74|trace()V[1.25/-1,-1.25/0,1.25/0,-1.25/1]
+NOpened-Polygon|art@10||-0.25|1|2.5|2|||ART_color()I74|trace()V[1.25/-1,-1.25/0,1.25/0,-1.25/1]
+NPin|pin@0||-2.75|-2|1|1||
+NPin|pin@1||-4|-2||||
+NPin|pin@2||2|-2|1|1||
+NPin|pin@3||4|-2||||
+NPin|pin@4||-2|-1.25|1|1||
+NPin|pin@5||2|-1.25|1|1||
+NPin|pin@6||2|-2.75|1|1||
+NPin|pin@7||-2|-2.75|1|1||
+Nschematic:Bus_Pin|pin@8||4|0|-2|-2||
+Nschematic:Bus_Pin|pin@9||-4|0|-2|-2||
+Ngeneric:Universal-Pin|pin@10||-4|2|-1|-1||
+Ngeneric:Universal-Pin|pin@12||4|2|-1|-1||
+Ngeneric:Universal-Pin|pin@14||4|-2|-1|-1||
+Ngeneric:Universal-Pin|pin@16||-4|-2|-1|-1||
+NPin|pin@20||-2|0.75|1|1||
+NPin|pin@21||2|0.75|1|1||
+NPin|pin@22||2|-0.75|1|1||
+NPin|pin@23||-2|-0.75|1|1||
+NPin|pin@24||2|0|1|1||
+NPin|pin@25||4|0||||
+NPin|pin@26||-2.75|0|1|1||
+NPin|pin@27||-4|0||||
+NPin|pin@38||-2|2.75|1|1||
+NPin|pin@39||2|2.75|1|1||
+NPin|pin@40||2|1.25|1|1||
+NPin|pin@41||-2|1.25|1|1||
+NPin|pin@42||2|2|1|1||
+NPin|pin@43||4|2||||
+NPin|pin@44||-2.75|2|1|1||
+NPin|pin@45||-4|2||||
+AThicker|net@0|||IJS0|pin@0||-2.75|-2|pin@1||-4|-2|ART_color()I74
+AThicker|net@1|||IJS1800|pin@2||2|-2|pin@3||4|-2|ART_color()I74
+AThicker|net@2|||IJS0|pin@5||2|-1.25|pin@4||-2|-1.25|ART_color()I74
+AThicker|net@3|||IJS0|pin@6||2|-2.75|pin@7||-2|-2.75|ART_color()I74
+AThicker|net@8|||IJS0|pin@21||2|0.75|pin@20||-2|0.75|ART_color()I74
+AThicker|net@9|||IJS0|pin@22||2|-0.75|pin@23||-2|-0.75|ART_color()I74
+AThicker|net@10|||IJS1800|pin@24||2|0|pin@25||4|0|ART_color()I74
+AThicker|net@11|||IJS0|pin@26||-2.75|0|pin@27||-4|0|ART_color()I74
+AThicker|net@16|||IJS0|pin@39||2|2.75|pin@38||-2|2.75|ART_color()I74
+AThicker|net@17|||IJS0|pin@40||2|1.25|pin@41||-2|1.25|ART_color()I74
+AThicker|net@18|||IJS1800|pin@42||2|2|pin@43||4|2|ART_color()I74
+AThicker|net@19|||IJS0|pin@44||-2.75|2|pin@45||-4|2|ART_color()I74
+Ea||D5G2;|pin@9||U
+EaL||D5G2;|pin@10||U
+EaR||D5G2;|pin@16||U
+Eb||D5G2;|pin@8||U
+EbL||D5G2;|pin@12||U
+EbR||D5G2;|pin@14||U
+X
+
+# Cell wire_xcpl;1{sch}
+Cwire_xcpl;1{sch}||schematic|1083961993000|1173982721429||ATTR_C(D5FLeave alone;G1;HNOLPUCX-19;Y-23;)S0.0000223p|ATTR_L(D5FLeave alone;G1;HNOLPUDX-19;Y-21;)S100|ATTR_R(D5FLeave alone;G1;HNOLPURX-19;Y-22;)S0.024|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@0||-10|-22.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.55
+NCapacitor|cap@1||10|-22.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.55
+NCapacitor|cap@2||0|-22.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.55
+NCapacitor|cap@3||-10|-13.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.9
+NCapacitor|cap@4||10|-13.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.9
+NCapacitor|cap@5||0|-13.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.9
+NCapacitor|cap@6||-10|4.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.9
+NCapacitor|cap@7||10|4.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.9
+NCapacitor|cap@8||0|4.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.9
+NCapacitor|cap@9||-6.5|-5.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.1
+NCapacitor|cap@10||13.5|-5.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.1
+NCapacitor|cap@11||3.5|-5.5|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.1
+NCapacitor|cap@12||-10|13.5|||Y||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.55
+NCapacitor|cap@13||10|13.5|||Y||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.55
+NCapacitor|cap@14||0|13.5|||Y||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.55
+NOff-Page|conn@0||24.5|0|||RR|
+NOff-Page|conn@1||-21|0||||
+NOff-Page|conn@2||-21|9||||
+NOff-Page|conn@3||21|9|||RR|
+NOff-Page|conn@4||21|-18|||RR|
+NOff-Page|conn@5||-21|-18||||
+NGround|gnd@0||16|-26|||R|
+NGround|gnd@1||18.5|-10|||R|
+NGround|gnd@2||16|17|||YR|
+Ngeneric:Invisible-Pin|pin@0||15|21.5|||||ART_message(D5G1;)S[R2 ]
+Ngeneric:Invisible-Pin|pin@1||-15|21.5|||||ART_message(D5G1;)S[R1 = @R*@L/6]
+Ngeneric:Invisible-Pin|pin@2||0|21.5|||||ART_message(D5G1;)S[R12= @R*@L/3]
+Ngeneric:Invisible-Pin|pin@3||22|-22.5|||||ART_message(D5G1;)S[C = @C*@L/3]
+Ngeneric:Invisible-Pin|pin@4||0|29.5|||||ART_message(D5G2;)S[this is a wire 'L' lambda long,with resistance 'R' ohms/lambda,and capacitance 'C' F/lambda]
+Ngeneric:Invisible-Pin|pin@5||-1|37.5|||||ART_message(D5G6;)Swire_xcpl
+NWire_Pin|pin@6||0|-26||||
+NWire_Pin|pin@7||10|-26||||
+NWire_Pin|pin@8||-10|-26||||
+NWire_Pin|pin@12||10|-18||||
+NWire_Pin|pin@13||0|-18||||
+NWire_Pin|pin@14||-10|-18||||
+NWire_Pin|pin@15||10|0||||
+NWire_Pin|pin@16||0|0||||
+NWire_Pin|pin@17||-10|0||||
+NWire_Pin|pin@18||10|9||||
+NWire_Pin|pin@19||0|9||||
+NWire_Pin|pin@20||-10|9||||
+NWire_Pin|pin@21||-6.5|-10||||
+NWire_Pin|pin@22||3.5|-10||||
+NWire_Pin|pin@23||13.5|-10||||
+NWire_Pin|pin@24||0|17|||Y|
+NWire_Pin|pin@25||10|17|||Y|
+NWire_Pin|pin@26||-10|17|||Y|
+NWire_Pin|pin@27||-6.5|-2||||
+NWire_Pin|pin@28||-10|-2||||
+NWire_Pin|pin@29||0|-2||||
+NWire_Pin|pin@30||3.5|-2||||
+NWire_Pin|pin@31||10|-2||||
+NWire_Pin|pin@32||13.5|-2||||
+Ngeneric:Invisible-Pin|pin@38||37|-5.5|||||ART_message(D5G1;)SCc = 0.45Ctotal
+NResistor|res@0||-15|0|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/6
+NResistor|res@1||-5|0|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/3
+NResistor|res@2||18.5|0|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/6
+NResistor|res@3||5|0|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/3
+NResistor|res@4||-15|-18|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/6
+NResistor|res@5||-5|-18|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/3
+NResistor|res@6||15|-18|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/6
+NResistor|res@7||5|-18|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/3
+NResistor|res@8||-15|9|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/6
+NResistor|res@9||-5|9|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/3
+NResistor|res@10||15|9|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/6
+NResistor|res@11||5|9|||||SCHEM_resistance(D5FLeave alone;G1;OLURY1.5;)S@R*@L/3
+Iwire_xcpl;1{ic}|wire_xcp@1||24|32.5|||D0G4;|ATTR_C(D5FLeave alone;G1;NOLPUCY-2;)S2.23E-16|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S100|ATTR_R(D5FLeave alone;G1;NOLPURY-1;)S0.24
+Awire|net@0|||IJS1800|res@2|b|20.5|0|conn@0|y|22.5|0
+Awire|net@1|||IJS0|res@0|a|-17|0|conn@1|y|-19|0
+Awire|net@3|||IJS2700|pin@6||0|-26|cap@2|b|0|-24.5
+Awire|net@4|||IJS0|pin@7||10|-26|pin@6||0|-26
+Awire|net@5|||IJS0|pin@6||0|-26|pin@8||-10|-26
+Awire|net@6|||IJS900|cap@1|b|10|-24.5|pin@7||10|-26
+Awire|net@7|||IJS2700|pin@8||-10|-26|cap@0|b|-10|-24.5
+Awire|net@17|||0|pin@15||10|0|res@3|b|7|0
+Awire|net@18|||0|pin@16||0|0|res@1|b|-3|0
+Awire|net@19|||0|pin@17||-10|0|res@0|b|-13|0
+Awire|net@20|||0|pin@12||10|-18|res@7|b|7|-18
+Awire|net@21|||0|pin@13||0|-18|res@5|b|-3|-18
+Awire|net@22|||0|pin@14||-10|-18|res@4|b|-13|-18
+Awire|net@23|||0|pin@18||10|9|res@11|b|7|9
+Awire|net@24|||0|pin@19||0|9|res@9|b|-3|9
+Awire|net@25|||0|pin@20||-10|9|res@8|b|-13|9
+Awire|net@26|||0|conn@3|y|19|9|res@10|b|17|9
+Awire|net@27|||1800|conn@2|y|-19|9|res@8|a|-17|9
+Awire|net@28|||0|res@4|a|-17|-18|conn@5|y|-19|-18
+Awire|net@29|||0|conn@4|y|19|-18|res@6|b|17|-18
+Awire|net@30|||0|res@6|a|13|-18|pin@12||10|-18
+Awire|net@31|||2700|cap@1|a|10|-20.5|pin@12||10|-18
+Awire|net@32|||0|res@7|a|3|-18|pin@13||0|-18
+Awire|net@33|||2700|cap@2|a|0|-20.5|pin@13||0|-18
+Awire|net@34|||0|res@5|a|-7|-18|pin@14||-10|-18
+Awire|net@35|||2700|cap@0|a|-10|-20.5|pin@14||-10|-18
+Awire|net@36|||0|res@2|a|16.5|0|pin@15||10|0
+Awire|net@37|||2700|cap@4|a|10|-11.5|pin@31||10|-2
+Awire|net@38|||900|cap@4|b|10|-15.5|pin@12||10|-18
+Awire|net@39|||900|cap@3|b|-10|-15.5|pin@14||-10|-18
+Awire|net@40|||900|cap@5|b|0|-15.5|pin@13||0|-18
+Awire|net@41|||0|res@3|a|3|0|pin@16||0|0
+Awire|net@42|||2700|cap@5|a|0|-11.5|pin@29||0|-2
+Awire|net@43|||0|res@1|a|-7|0|pin@17||-10|0
+Awire|net@44|||2700|cap@3|a|-10|-11.5|pin@28||-10|-2
+Awire|net@45|||900|cap@7|b|10|2.5|pin@15||10|0
+Awire|net@46|||900|cap@6|b|-10|2.5|pin@17||-10|0
+Awire|net@47|||900|cap@8|b|0|2.5|pin@16||0|0
+Awire|net@48|||0|res@10|a|13|9|pin@18||10|9
+Awire|net@49|||2700|cap@7|a|10|6.5|pin@18||10|9
+Awire|net@50|||0|res@11|a|3|9|pin@19||0|9
+Awire|net@51|||2700|cap@8|a|0|6.5|pin@19||0|9
+Awire|net@52|||0|res@9|a|-7|9|pin@20||-10|9
+Awire|net@53|||2700|cap@6|a|-10|6.5|pin@20||-10|9
+Awire|net@54|||900|cap@9|b|-6.5|-7.5|pin@21||-6.5|-10
+Awire|net@55|||1800|pin@21||-6.5|-10|pin@22||3.5|-10
+Awire|net@56|||2700|pin@22||3.5|-10|cap@11|b|3.5|-7.5
+Awire|net@57|||1800|pin@22||3.5|-10|pin@23||13.5|-10
+Awire|net@58|||2700|pin@23||13.5|-10|cap@10|b|13.5|-7.5
+Awire|net@59|||0|gnd@1||16.5|-10|pin@23||13.5|-10
+Awire|net@60|||0|gnd@0||14|-26|pin@7||10|-26
+Awire|net@61|||IJS900|pin@24||0|17|cap@14|b|0|15.5
+Awire|net@62|||IJS0|pin@25||10|17|pin@24||0|17
+Awire|net@63|||IJS0|pin@24||0|17|pin@26||-10|17
+Awire|net@64|||IJS2700|cap@13|b|10|15.5|pin@25||10|17
+Awire|net@65|||IJS900|pin@26||-10|17|cap@12|b|-10|15.5
+Awire|net@66|||0|gnd@2||14|17|pin@25||10|17
+Awire|net@67|||900|cap@14|a|0|11.5|pin@19||0|9
+Awire|net@68|||900|cap@12|a|-10|11.5|pin@20||-10|9
+Awire|net@69|||900|cap@13|a|10|11.5|pin@18||10|9
+Awire|net@70|||2700|cap@9|a|-6.5|-3.5|pin@27||-6.5|-2
+Awire|net@71|||2700|pin@28||-10|-2|pin@17||-10|0
+Awire|net@72|||0|pin@27||-6.5|-2|pin@28||-10|-2
+Awire|net@73|||2700|pin@29||0|-2|pin@16||0|0
+Awire|net@74|||1800|pin@29||0|-2|pin@30||3.5|-2
+Awire|net@75|||900|pin@30||3.5|-2|cap@11|a|3.5|-3.5
+Awire|net@76|||2700|pin@31||10|-2|pin@15||10|0
+Awire|net@77|||1800|pin@31||10|-2|pin@32||13.5|-2
+Awire|net@78|||900|pin@32||13.5|-2|cap@10|a|13.5|-3.5
+Ea||D4G2;|conn@1|a|U
+EaL||D4G2;|conn@2|a|U
+EaR||D4G2;|conn@5|a|U
+Eb||D6G2;X-5;|conn@0|y|U
+EbL||D6G2;X-5;|conn@3|y|U
+EbR||D6G2;X-5;|conn@4|y|U
+X
+
+# Cell wire_xcpl_sides;1{ic}
+Cwire_xcpl_sides;1{ic}||artwork|1083964052000|1204183998562|E|ATTR_C(D5FLeave alone;G1;HNOLPUCY-1;)S0.0000223p|ATTR_L(D5FLeave alone;G1;HOLPUDY1;)S100|ATTR_LEIGNORE(D5G1;HNPTUDX-20.5;Y-1.5;)I1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NThick-Circle|art@3||-2|0|2|2|R||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NThick-Circle|art@11||2|0|2|2|XR||ART_color()I74|ART_degrees()F[0.0,3.1415927]
+NPin|pin@38||-2|1|1|1||
+NPin|pin@39||2|1|1|1||
+Ngeneric:Universal-Pin|pin@46||-1.5|1|-1|-1||
+Ngeneric:Universal-Pin|pin@48||0|1|-1|-1||
+Ngeneric:Universal-Pin|pin@50||1.5|1|-1|-1||
+Ngeneric:Universal-Pin|pin@52||-1.5|-1|-1|-1||
+Ngeneric:Universal-Pin|pin@54||0|-1|-1|-1||
+Ngeneric:Universal-Pin|pin@56||1.5|-1|-1|-1||
+NPin|pin@58||-2|-0.25|1|1||
+NPin|pin@59||-1|-0.25||||
+NPin|pin@60||-2|0.25|1|1||
+NPin|pin@61||-1|0.25||||
+NPin|pin@62||-1.5|1|1|1|RRR|
+NPin|pin@63||-1.5|0.25|||RRR|
+NPin|pin@64||-1.5|-0.25|1|1|RRR|
+NPin|pin@65||-1.5|-1|||RRR|
+NPin|pin@66||-0.5|-0.25|1|1||
+NPin|pin@67||0.5|-0.25||||
+NPin|pin@68||-0.5|0.25|1|1||
+NPin|pin@69||0.5|0.25||||
+NPin|pin@70||0|1|1|1|RRR|
+NPin|pin@71||0|0.25|||RRR|
+NPin|pin@72||0|-0.25|1|1|RRR|
+NPin|pin@73||0|-1|||RRR|
+NPin|pin@74||1|-0.25|1|1||
+NPin|pin@75||2|-0.25||||
+NPin|pin@76||1|0.25|1|1||
+NPin|pin@77||2|0.25||||
+NPin|pin@78||1.5|1|1|1|RRR|
+NPin|pin@79||1.5|0.25|||RRR|
+NPin|pin@80||1.5|-0.25|1|1|RRR|
+NPin|pin@81||1.5|-1|||RRR|
+NPin|pin@82||-2|-1|1|1||
+NPin|pin@83||2|-1|1|1||
+AThicker|net@16|||IJS0|pin@39||2|1|pin@38||-2|1|ART_color()I74
+AThicker|net@26|||IJS1800|pin@58||-2|-0.25|pin@59||-1|-0.25|ART_color()I74
+AThicker|net@27|||IJS1800|pin@60||-2|0.25|pin@61||-1|0.25|ART_color()I74
+AThicker|net@28|||IJS900|pin@62||-1.5|1|pin@63||-1.5|0.25|ART_color()I74
+AThicker|net@29|||IJS900|pin@64||-1.5|-0.25|pin@65||-1.5|-1|ART_color()I74
+AThicker|net@30|||IJS1800|pin@66||-0.5|-0.25|pin@67||0.5|-0.25|ART_color()I74
+AThicker|net@31|||IJS1800|pin@68||-0.5|0.25|pin@69||0.5|0.25|ART_color()I74
+AThicker|net@32|||IJS900|pin@70||0|1|pin@71||0|0.25|ART_color()I74
+AThicker|net@33|||IJS900|pin@72||0|-0.25|pin@73||0|-1|ART_color()I74
+AThicker|net@34|||IJS1800|pin@74||1|-0.25|pin@75||2|-0.25|ART_color()I74
+AThicker|net@35|||IJS1800|pin@76||1|0.25|pin@77||2|0.25|ART_color()I74
+AThicker|net@36|||IJS900|pin@78||1.5|1|pin@79||1.5|0.25|ART_color()I74
+AThicker|net@37|||IJS900|pin@80||1.5|-0.25|pin@81||1.5|-1|ART_color()I74
+AThicker|net@38|||IJS0|pin@83||2|-1|pin@82||-2|-1|ART_color()I74
+EsL1||D5G2;|pin@46||U
+EsL2||D5G2;|pin@48||U
+EsL3||D5G2;|pin@50||U
+EsR1||D5G2;|pin@52||U
+EsR2||D5G2;|pin@54||U
+EsR3||D5G2;|pin@56||U
+X
+
+# Cell wire_xcpl_sides;1{sch}
+Cwire_xcpl_sides;1{sch}||schematic|1083961993000|1173982739755||ATTR_C(D5FLeave alone;G1;HNOLPUCX-20.5;Y-5.5;)S0.0000223p|ATTR_L(D5FLeave alone;G1;HNOLPUDX-20.5;Y-3.5;)S100|ATTR_LEIGNORE(D5G1;HNPTUDX-20.5;Y-1.5;)I1|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NCapacitor|cap@6||-10|0|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.45
+NCapacitor|cap@7||10|0|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.45
+NCapacitor|cap@8||0|0|||||SCHEM_capacitance(D5FLeave alone;G1;OLUC)S@C*@L/3*0.45
+NOff-Page|conn@6||-10|8|||RRR|
+NOff-Page|conn@7||0|8|||RRR|
+NOff-Page|conn@8||10|8|||RRR|
+NOff-Page|conn@9||-10|-7.5|||YRRR|
+NOff-Page|conn@10||0|-7.5|||YRRR|
+NOff-Page|conn@11||10|-7.5|||YRRR|
+Ngeneric:Invisible-Pin|pin@3||20.5|-6.5|||||ART_message(D5G1;)S[C = @C*@L/3]
+Ngeneric:Invisible-Pin|pin@4||0|24|||||ART_message(D5G2;)S[this is a wire 'L' lambda long,with resistance 'R' ohms/lambda,and capacitance 'C' F/lambda]
+Ngeneric:Invisible-Pin|pin@5||-1|32|||||ART_message(D5G6;)Swire_xcpl
+Ngeneric:Invisible-Pin|pin@38||37|-5.5|||||ART_message(D5G1;)SCc = 0.45Ctotal
+Iwire_xcpl_sides;1{ic}|wire_xcp@3||24|27|||D0G4;|ATTR_C(D5FLeave alone;G1;NOLPUCY-1;)S2.23E-16|ATTR_L(D5FLeave alone;G1;OLPUDY1;)S100
+Awire|net@84|||900|conn@8|y|10|6|cap@7|a|10|2
+Awire|net@85|||900|conn@6|y|-10|6|cap@6|a|-10|2
+Awire|net@86|||900|conn@7|y|0|6|cap@8|a|0|2
+Awire|net@93|||2700|conn@9|y|-10|-5.5|cap@6|b|-10|-2
+Awire|net@94|||2700|conn@10|y|0|-5.5|cap@8|b|0|-2
+Awire|net@95|||2700|conn@11|y|10|-5.5|cap@7|b|10|-2
+EsL1||D4G2;|conn@6|a|U
+EsL2||D4G2;|conn@7|a|U
+EsL3||D4G2;|conn@8|a|U
+EsR1||D4G2;|conn@9|a|U
+EsR2||D4G2;|conn@10|a|U
+EsR3||D4G2;|conn@11|a|U
+X