implement port percolation

diff --git a/ships/DRAM.ship b/ships/DRAM.ship
index e3bdbb6..322c3c1 100644 (file)
--- a/ships/DRAM.ship
+++ b/ships/DRAM.ship
@@ -7,17 +7,18 @@ data  in:    inDataWrite
 
 data  out:   out
 
-percolate up:     dram_addr_                32
-percolate up:     dram_addr_r_              1
-percolate down:   dram_addr_a               1
-percolate up:     dram_isread_              1
-percolate up:     dram_write_data_          64
-percolate up:     dram_write_data_push_     1
-percolate down:   dram_write_data_full      1
-percolate down:   dram_read_data            64
-percolate up:     dram_read_data_pop_       1
-percolate down:   dram_read_data_empty      1
-percolate down:   dram_read_data_latency    2
+percolate up:            ddr1_Clk_pin       1
+percolate up:            ddr1_Clk_n_pin     1
+percolate up:            ddr1_Addr_pin      13
+percolate up:            ddr1_BankAddr_pin  2
+percolate up:            ddr1_CAS_n_pin     1
+percolate up:            ddr1_CE_pin        1
+percolate up:            ddr1_CS_n_pin      1
+percolate up:            ddr1_RAS_n_pin     1
+percolate up:            ddr1_WE_n_pin      1
+percolate up:            ddr1_DM_pin        4
+percolate inout:         ddr1_DQS           4
+percolate inout:         ddr1_DQ            32
 
 == TeX ==============================================================
 
@@ -27,6 +28,18 @@ percolate down:   dram_read_data_latency    2
 
 == FPGA ==============================================================
 
+  wire  [31:0]  dram_addr;
+  wire          dram_addr_r_;
+  wire          dram_addr_a;
+  wire          dram_isread_;
+  wire  [63:0]  dram_write_data_;
+  wire          dram_write_data_push_;
+  wire          dram_write_data_full;
+  wire   [63:0] dram_read_data;
+  wire          dram_read_data_pop_;
+  wire          dram_read_data_empty;
+  wire   [1:0]  dram_read_data_latency;
+
   reg         dram_addr_r;
   reg         dram_isread;
   reg         dram_write_data_push;
@@ -41,9 +54,42 @@ percolate down:   dram_read_data_latency    2
   assign dram_write_data_push_ = dram_write_data_push;
   assign dram_read_data_pop_ = dram_read_data_pop;
   assign dram_write_data_ = inDataWrite_d;
-//  assign dram_write_data_ = inDataWrite_d[(`WORDWIDTH-1):0];
   assign out_d_ = out_d;
 
+   ddr_ctrl 
+   #(
+       .clk_freq( 50000000 ),
+       .clk_multiply( 12 ),
+       .clk_divide( 5 ),
+       .phase_shift( 0 ),
+       .wait200_init( 26 )
+   ) ddr_ctrl (
+          .ddr_a( ddr1_Addr_pin ),
+          .ddr_clk( ddr1_Clk_pin ),
+          .ddr_clk_n( ddr1_Clk_n_pin ),
+          .ddr_ba( ddr1_BankAddr_pin ),
+          .ddr_dq( ddr1_DQ ),
+          .ddr_dm( ddr1_DM_pin ),
+          .ddr_dqs( ddr1_DQS ),
+          .ddr_cs_n( ddr1_CS_n_pin ),
+          .ddr_ras_n( ddr1_RAS_n_pin ),
+          .ddr_cas_n( ddr1_CAS_n_pin ),
+          .ddr_we_n( ddr1_WE_n_pin ),
+          .ddr_cke( ddr1_CE_pin ),
+   
+          .clk(clk),
+          .reset(!sys_rst_pin),
+          .rot(3'b100),
+   
+          .fml_wr(!dram_isread && dram_addr_r),
+          .fml_done(dram_addr_a),
+          .fml_rd( dram_isread && dram_addr_r),
+          .fml_adr(dram_addr),
+          .fml_din(dram_write_data),
+          .fml_dout(dram_read_data),
+          .fml_msk(16'h0)
+   );
+
   always @(posedge clk) begin
 
     if (!rst) begin

diff --git a/ships/Debug.ship b/ships/Debug.ship
index 77bc622..a2076f1 100644 (file)
--- a/ships/Debug.ship
+++ b/ships/Debug.ship
@@ -3,6 +3,16 @@ ship: Debug
 == Ports ===========================================================
 data  in:   in
 
+percolate up:   root_in_r   1
+percolate down: root_in_a   1
+percolate up:   root_in_d   8
+percolate down: uart_in     1
+percolate up:   uart_out    1
+percolate up:   uart_rts    1
+percolate down: uart_cts    1
+percolate up:   rst_out     1
+percolate down: rst_in      1
+
 == Constants ========================================================
 
 == TeX ==============================================================
@@ -30,8 +40,131 @@ public void service() {
 
 == FPGA ==============================================================
 
-  reg [`WORDWIDTH-1:0] out_d;
-  assign  out_d_ = out_d;
+  wire break_i;
+  reg break_last;
+  reg send_k;                initial send_k = 0;
+
+  wire       data_to_host_full;
+  wire       data_to_host_write_enable;
+  wire [7:0] data_to_host;
+
+  wire       data_to_fleet_empty;
+  wire       data_to_fleet_read_enable;
+  wire [7:0] data_to_fleet;
+
+  reg we;
+  reg re;
+  reg [7:0] data_to_host_r;
+  assign data_to_host = data_to_host_r;
+
+  wire ser_rst;
+  reg ser_rst_r;
+  initial ser_rst_r = 0;
+  assign ser_rst = (rst_in & ser_rst_r);
+
+  wire sio_ce;
+  wire sio_ce_x4;
+
+  wire break;
+  assign rst_out = rst_in && !break;
+
+  sasc_brg sasc_brg(clk, ser_rst, 3, 65, sio_ce, sio_ce_x4);
+  sasc_top sasc_top(clk, ser_rst,
+                    uart_in,
+                    uart_out,
+                    uart_cts,
+                    uart_rts, 
+                    sio_ce,
+                    sio_ce_x4,
+                    data_to_host,
+                    data_to_fleet,
+                    data_to_fleet_read_enable,
+                    data_to_host_write_enable,
+                    data_to_host_full,
+                    data_to_fleet_empty,
+                    break,
+                    break_i);
+
+   // break and break are _active high_
+   always @(posedge clk) break_last <= break;
+   assign break_i    =  break && !break_last;
+   assign break_done = !break &&  break_last;
+
+   reg data_to_host_write_enable_reg;
+   reg data_to_fleet_read_enable_reg;
+
+   reg [`WORDWIDTH-1:0] root_out_d;
+   reg root_out_r; initial root_out_r = 0;
+   wire root_out_a;
+
+   reg root_out_a_reg;
+   reg root_in_r_reg;
+   reg [7:0] root_in_d_reg;
+   initial root_in_r_reg = 0;
+   initial root_in_d_reg = 0;
+   initial root_out_a_reg = 0;
+   initial data_to_fleet_read_enable_reg = 0;
+   initial data_to_host_write_enable_reg = 0;
+
+   assign root_out_a                = root_out_a_reg;                
+   assign root_in_r                 = root_in_r_reg;
+   assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
+   assign data_to_host_write_enable = data_to_host_write_enable_reg;
+   assign root_in_d                 = root_in_d_reg;
+
+   // fpga -> host
+   always @(posedge clk)
+   begin
+     if (break_i) begin
+       root_out_a_reg = 0;
+       data_to_host_write_enable_reg <= 0;
+
+     end else if (break_done) begin
+       data_to_host_write_enable_reg <= 1;
+       data_to_host_r <= 111;
+       send_k <= 1;
+     end else if (send_k) begin
+       data_to_host_write_enable_reg <= 1;
+       data_to_host_r <= 107;
+       send_k <= 0;
+
+
+     end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
+       data_to_host_write_enable_reg <= 1;
+       data_to_host_r <= root_out_d[7:0];
+       root_out_a_reg = 1;
+     end else if (root_out_a_reg && !root_out_r) begin
+       data_to_host_write_enable_reg <= 0;
+       root_out_a_reg = 0;
+     end else begin
+       data_to_host_write_enable_reg <= 0;
+     end
+   end
+
+   // host -> fpga
+   always @(posedge clk)
+   begin
+     ser_rst_r <= 1;
+     if (break_i) begin
+       root_in_r_reg <= 0;
+       root_in_d_reg <= 0;
+       data_to_fleet_read_enable_reg <= 0;
+     end else
+  
+     if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
+        root_in_r_reg <= 1;
+        root_in_d_reg <= data_to_fleet;
+        data_to_fleet_read_enable_reg <= 1;
+     end else begin
+       data_to_fleet_read_enable_reg <= 0;
+        if (root_in_a) begin
+          root_in_r_reg <= 0;
+        end
+     end
+   end
+
+  reg [7:0] count;
+  initial count = 0;
 
   always @(posedge clk) begin
     if (!rst) begin
@@ -39,10 +172,17 @@ public void service() {
     end else begin
       `flush
       `cleanup
-      if (`in_full && `out_empty) begin
+      if (root_out_r && root_out_a) root_out_r <= 0;
+      if (`in_full && !root_out_r && !root_out_a && count==0) begin
         `drain_in
-        `fill_out
-        out_d <= in_d;
+        root_out_d <= in_d;
+        root_out_r <= 1;
+        count <= 5;
+      end
+      if (count!=0 && !root_out_r && !root_out_a) begin
+        count <= count-1;
+        root_out_r <= 1;
+        root_out_d <= (root_out_d >> 8);
       end
     end
   end

diff --git a/ships/Video.ship b/ships/Video.ship
index 03f463c..bfc01a9 100644 (file)
--- a/ships/Video.ship
+++ b/ships/Video.ship
@@ -5,7 +5,6 @@ data  in:    inX
 data  in:    inY
 data  in:    inData
 
-percolate down:       vga_clk     1
 percolate up:         vga_psave   1
 percolate up:         vga_hsync   1
 percolate up:         vga_vsync   1
@@ -54,6 +53,24 @@ percolate up:         vga_clkout  1
 
 == FPGA ==============================================================
 
+  wire vga_clk_unbuffered;  // synthesis attribute period of vga_clk_unbuffered is "40 ns";
+
+  wire vga_clk;
+  wire vga_clk_fb;
+
+  BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk));
+  DCM  // 25Mhz VGA clock
+   #(
+      .CLKFX_MULTIPLY(4),
+      .CLKFX_DIVIDE(16),
+      .CLKIN_PERIOD("20 ns")
+    ) vgadcm (
+      .CLKIN (clk),
+      .CLKFB(vga_clk_fb),
+      .CLKFX (vga_clk_unbuffered),
+      .CLK0  (vga_clk_fb)
+    );
+
 
   wire [31:0] vga_pixel_addr_;
   wire        vga_pixel_r;

diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java
index b0aa067..e0cbab0 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Fpga.java
+++ b/src/edu/berkeley/fleet/fpga/Fpga.java
@@ -34,7 +34,7 @@ public class Fpga extends FleetTwoFleet {
     }
 
     public static void main(String[] s) throws Exception { 
-        new Fpga(new Module("root")).top.dump(s[0]);
+        new Fpga(new Module("main")).top.dump(s[0]);
         PrintWriter pw;
 
         pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/timescale.v")));
@@ -79,7 +79,7 @@ public class Fpga extends FleetTwoFleet {
         return ship;
     }
 
-    public Fpga() throws Exception { this(new Module("root")); }
+    public Fpga() throws Exception { this(new Module("main")); }
     public Fpga(Module top) throws Exception {
         this.top = top;
         debugShip = createShip("Debug",     "debug");
@@ -121,21 +121,11 @@ public class Fpga extends FleetTwoFleet {
         createShip("DRAM",    "dram");
         createShip("Video",   "video");
 
-        //Module.SourcePort  debug_in    = top.createWireSourcePort("debug_in", WIDTH_PACKET);
-        Module.SourcePort  debug_out   = null;
-        for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
-            if (ship.getType().toLowerCase().equals("debug"))
-                debug_out = ship.getVerilogModule().getOutputPort("debug_out");
-        }
-
         // for FifoShip
         new Module.InstantiatedModule(top, new FifoModule(8, WIDTH_WORD));
 
-        Module.SourcePort  in          = top.createInputPort("in", 8);
-        Module.SinkPort    out         = top.createOutputPort("out", 8, "");
         Module.Latch       temp_in     = top.new Latch("temp", WIDTH_PACKET);
         Module.Latch       count       = top.new Latch("count", 8);
-        Module.Latch       count_out   = top.new Latch("count_out", 8);
 
         ArrayList inbox_sources = new ArrayList<FabricElement>();
         ArrayList inbox_dests   = new ArrayList<FabricElement>();
@@ -144,8 +134,6 @@ public class Fpga extends FleetTwoFleet {
         ArrayList instruction_dests   = new ArrayList<FabricElement>();
         int numdocks = 0;
         for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
-            if (ship.getType().toLowerCase().equals("debug"))
-                debug_out = ship.getVerilogModule().getOutputPort("debug_out");
             for(Dock port : ship) {
                 if (port.isInputDock()) {
                     inbox_sources.add(((FpgaDock)port));
@@ -173,23 +161,20 @@ public class Fpga extends FleetTwoFleet {
         top_funnel.addOutput(top_horn, top_horn.getInputPort());
         Module.SinkPort debug_in = top_funnel.getInputPort("in1");
 
-        top.new Event(new Object[] { in, "count<=7" },
-                      new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], in[7:0] };"),
+        top.addPreCrap("reg root_in_a_;");
+        top.addPreCrap("assign root_in_a = root_in_a_;");
+        top.new Event(new Object[] { "(root_in_r && root_in_a)" },
+                      new Object[] { new SimpleAction("root_in_a_<=0;") });
+        top.new Event(new Object[] { "(root_in_r && !root_in_a)", "count<=7" },
+                      new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], root_in_d[7:0] };"),
                                      new AssignAction(count, count.getVerilogName()+"+1"),
-                                     in
+                                     new SimpleAction("root_in_a_<=1;")
                       });
         top.new Event(new Object[] { debug_in, "count>7" },
                       new Object[] { new AssignAction(count, "0"),
                                      new AssignAction(debug_in, temp_in),
                                      debug_in
                       });
-        top.new Event(new Object[] { out, debug_out },
-                      new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
-                                     new ConditionalAction("count_out >= 5", debug_out),
-                                     new ConditionalAction("count_out >= 5", new AssignAction(count_out, "0")),
-                                     new ConditionalAction("count_out <  5", new AssignAction(count_out, "count_out+1")),
-                                     out });
-
     }
 
     public FabricElement mkNode(FabricElement[] ports, boolean is_horn) { return mkNode(ports, is_horn, 0, ports.length); }
@@ -220,8 +205,6 @@ public class Fpga extends FleetTwoFleet {
             FileOutputStream out = new FileOutputStream(outf);
             PrintWriter pw = new PrintWriter(out);
 
-            boolean debug = "debug".equals(filename);
-
             pw.println("`define WORDWIDTH                "+WIDTH_WORD);
             pw.println("`define CODEBAG_SIZE_BITS        "+CBD_SIZE.valmaskwidth);
             pw.println();
@@ -237,13 +220,6 @@ public class Fpga extends FleetTwoFleet {
                     pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
                 }
             }
-            if (debug) {
-                String name = "out";
-                pw.println("`define "+name+"_full    ("+name+"_r && !"+name+"_a)");
-                pw.println("`define "+name+"_empty  (!"+name+"_r && !"+name+"_a)");
-                pw.println("`define fill_"+name+"  "+name+"_r <= 1;");
-                pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
-            }
 
             pw.print("`define reset ");
             for(DockDescription bb : sd) {
@@ -251,10 +227,6 @@ public class Fpga extends FleetTwoFleet {
                 if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
                 else                  pw.print(bb_name+"_r <= 0; ");
             }
-            if (debug) {
-                String bb_name = "out";
-                pw.print(bb_name+"_r <= 0; ");
-            }
             pw.println();
 
             pw.print("`define cleanup ");
@@ -263,10 +235,6 @@ public class Fpga extends FleetTwoFleet {
                 if (bb.isInputDock()) pw.print("if (!"+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_a <= 0; ");
                 else                  pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
             }
-            if (debug) {
-                String bb_name = "out";
-                pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
-            }
             pw.println();
 
             // FIXME: this corresponds to something
@@ -328,11 +296,6 @@ public class Fpga extends FleetTwoFleet {
                 }
                 pw.println();
             }
-            if (filename.equals("debug")) {
-                pw.println("    , out_r_");
-                pw.println("    , out_a");
-                pw.println("    , out_d_");
-            }
             for(PercolatedPort pp : sd.percolatedPorts) {
                 pw.print("    , ");
                 pw.println(pp.name);
@@ -342,7 +305,11 @@ public class Fpga extends FleetTwoFleet {
             pw.println("    input clk;");
             pw.println("    input rst;");
             for(PercolatedPort pp : sd.percolatedPorts) {
-                pw.print(pp.up ? "output" : "input");
+                switch(pp.type) {
+                    case UP:    pw.print("output"); break;
+                    case DOWN:  pw.print("input");  break;
+                    case INOUT: pw.print("inout");  break;
+                }
                 pw.print("  ");
                 if (pp.width > 1)
                     pw.print("["+(pp.width-1)+":0]");
@@ -374,15 +341,6 @@ public class Fpga extends FleetTwoFleet {
                 }
                 pw.println();
             }
-            if (filename.equals("debug")) {
-                String bb_name = "out";
-                pw.println("        output  ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
-                pw.println("        input   "+bb_name+"_a;");
-                pw.println("        output  "+bb_name+"_r_;");
-                pw.println("        reg     "+bb_name+"_r;");
-                pw.println("        initial "+bb_name+"_r  = 0;");
-                pw.println("        assign  "+bb_name+"_r_ = "+bb_name+"_r;");
-            }
 
             if (filename.equals("fifo")) {
                 pw.println("  wire in_a__;");

diff --git a/src/edu/berkeley/fleet/fpga/FpgaShip.java b/src/edu/berkeley/fleet/fpga/FpgaShip.java
index 332970e..82b729d 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/FpgaShip.java
+++ b/src/edu/berkeley/fleet/fpga/FpgaShip.java
@@ -23,8 +23,6 @@ public class FpgaShip extends FleetTwoShip {
             else                module.createOutputPort(sdbb.getName(), getFleet().getWordWidth()+1, "");
             ports.put(sdbb.getName(), new FpgaDock(this, sdbb));
         }
-        if (getType().toLowerCase().equals("debug"))
-            module.createOutputPort("debug_out", getFleet().getWordWidth(), "");
         for(PercolatedPort pp : sd.percolatedPorts)
             this.module.percolatedPorts.add(pp);
     }

diff --git a/src/edu/berkeley/fleet/fpga/main.ucf b/src/edu/berkeley/fleet/fpga/main.ucf
index dd91600..478d803 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/main.ucf
+++ b/src/edu/berkeley/fleet/fpga/main.ucf
@@ -4,50 +4,32 @@
 ## user constraints to this file based on customer design specifications.
 ############################################################################
 
-#Net fpga_0_PCI32_BRIDGE_PCI_INTA LOC=P5;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTA IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTA TIG;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTB LOC=R8;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTB IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTB TIG;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTC LOC=P9;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTC IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTC TIG;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTD LOC=V4;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTD IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_PCI_INTD TIG;
-#Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT LOC=AE21;
-#Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT IOSTANDARD = LVCMOS25;
-#Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT TIG;
-Net sys_clk_pin LOC=J16;
-Net sys_clk_pin IOSTANDARD = LVCMOS25;
-Net sys_rst_pin LOC=H7;
-Net sys_rst_pin PULLUP;
-Net sys_rst_pin IOSTANDARD = LVCMOS33;
+Net clk_pin LOC=J16;
+Net clk_pin IOSTANDARD = LVCMOS25;
+Net rst_pin LOC=H7;
+Net rst_pin PULLUP;
+Net rst_pin IOSTANDARD = LVCMOS33;
 
 ### System level constraints
 
-Net sys_clk_pin TNM_NET = sys_clk_pin;
-TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10 ns HIGH 50%;
+Net clk_pin TNM_NET = clk_pin;
+TIMESPEC TS_clk_pin = PERIOD clk_pin 10 ns HIGH 50%;
 
 Net clk_unbuffered TNM_NET = clk_unbuffered;
 TIMESPEC TS_clk_unbuffered = PERIOD clk_unbuffered 20 ns;
 
-Net vga_clk_unbuffered TNM_NET = vga_clk_unbuffered;
-TIMESPEC TS_vga_clk_unbuffered = PERIOD vga_clk_unbuffered 40 ns;
+Net rst_pin TIG;
 
-Net sys_rst_pin TIG;
-
-NET "sys_clk_pin"               TNM="SYS_CLK";
-NET "*/clkgen/write_clk_u"    TNM="WRITE_CLK";
-NET "*/clkgen/write_clk90_u"  TNM="WRITE_CLK";
-NET "*/clkgen/read_clk_u"     TNM="READ_CLK";
-TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG;
-TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG;
-TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG;
-TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG;
-TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG;
-TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG;
+NET "clk_pin"               TNM="SYS_CLK";
+#NET "*/*/clkgen/write_clk_u"    TNM="WRITE_CLK";
+#NET "*/*/clkgen/write_clk90_u"  TNM="WRITE_CLK";
+#NET "*/*/clkgen/read_clk_u"     TNM="READ_CLK";
+#TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG;
+#TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG;
+#TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG;
+#TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG;
+#TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG;
+#TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG;
 
 net "vga_hsync" loc   = f9;
 net "vga_hsync" slew  = slow;
@@ -97,915 +79,22 @@ net "vga_b<*>" drive = 2;
 net "vga_*" iostandard = lvcmos33;
 
 
-#NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";
-#NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";
-#NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";
-#TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;
-#Net fpga_0_PCI_CLK_FB LOC=H17;
-#Net fpga_0_PCI_CLK_FB IOSTANDARD = LVCMOS25;
-#Net fpga_0_PCI_CLK_FB TNM_NET = PCI_CLK;
-#Net PCI32_BRIDGE/OPB_Clk TNM_NET = SYS_CLK;
-##TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 10000 ps;
-#TIMESPEC "TS_PCI_BUS" = FROM "PCI_CLK" TO "SYS_CLK" 9.9ns datapathonly; 
-#TIMESPEC TS_BUS_PCI = FROM SYS_CLK TO PCI_CLK 30000 ps;
-#Net fpga_0_PCI_CLK_OUT0 LOC=V5;
-#Net fpga_0_PCI_CLK_OUT0 IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI_CLK_OUT1 LOC=T11;
-#Net fpga_0_PCI_CLK_OUT1 IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI_CLK_OUT2 LOC=U6;
-#Net fpga_0_PCI_CLK_OUT2 IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI_CLK_OUT3 LOC=U7;
-#Net fpga_0_PCI_CLK_OUT3 IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI_CLK_OUT4 LOC=U3;
-#Net fpga_0_PCI_CLK_OUT4 IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI_CLK_OUT5 LOC=U5;
-#Net fpga_0_PCI_CLK_OUT5 IOSTANDARD = PCI33_3;
-#Net fpga_0_DDR_CLK_FB LOC=K18;
-#Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS25;
-#
-### IO Devices constraints
-#
-##### Module RS232_Uart_1 constraints
-#
-Net fpga_0_RS232_Uart_1_ctsN_pin LOC=G6;
-Net fpga_0_RS232_Uart_1_ctsN_pin IOSTANDARD = LVCMOS33;
-Net fpga_0_RS232_Uart_1_ctsN_pin TIG;
-Net fpga_0_RS232_Uart_1_rtsN_pin LOC=F6;
-Net fpga_0_RS232_Uart_1_rtsN_pin IOSTANDARD = LVCMOS33;
-Net fpga_0_RS232_Uart_1_rtsN_pin TIG;
-
-Net fpga_0_RS232_Uart_1_sin_pin LOC=E6;
-Net fpga_0_RS232_Uart_1_sin_pin IOSTANDARD = LVCMOS33;
-Net fpga_0_RS232_Uart_1_sin_pin TIG;
-Net fpga_0_RS232_Uart_1_sin_pin PULLUP;
-
-Net fpga_0_RS232_Uart_1_sout_pin LOC=D6;
-Net fpga_0_RS232_Uart_1_sout_pin IOSTANDARD = LVCMOS33;
-Net fpga_0_RS232_Uart_1_sout_pin TIG;
-Net fpga_0_RS232_Uart_1_sout_pin PULLUP;
-
-##### Module DDR_SDRAM_32Mx64 constraints
-#
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> LOC=P24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> LOC=P22;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> LOC=N22;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> LOC=N23;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> LOC=N24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> LOC=M23;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> LOC=L24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> LOC=L25;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> LOC=L26;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> LOC=K23;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> LOC=K24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> LOC=K26;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> LOC=J24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> LOC=J25;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> LOC=J26;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin LOC=D26;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin LOC=H14;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin LOC=C27;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin LOC=D27;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin LOC=E27;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> LOC=G23;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> LOC=E23;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> LOC=G22;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> LOC=F21;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> LOC=F25;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> LOC=G25;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> LOC=G20;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> LOC=F20;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> LOC=E22;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> LOC=E24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> LOC=H24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> LOC=H25;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> LOC=G26;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> LOC=F26;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> LOC=F24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> LOC=F23;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> LOC=C28;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> LOC=D25;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> LOC=D24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> LOC=D22;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> LOC=C25;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> LOC=C24;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> LOC=C23;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> LOC=C22;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> LOC=H22;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> LOC=J22;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> LOC=L21;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> LOC=K21;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> LOC=J21;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> LOC=J20;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> LOC=H20;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> LOC=G21;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> LOC=E21;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> LOC=D21;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> LOC=E19;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> LOC=F19;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> LOC=G18;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> LOC=F18;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> LOC=E18;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> LOC=E17;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin LOC=F28;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin IOSTANDARD = SSTL2_I;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin LOC=E28;
-#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin IOSTANDARD = SSTL2_I;
-#
-##### Module SPI_EEPROM constraints
-#
-#Net fpga_0_SPI_EEPROM_SCK_pin LOC=AF21;
-#Net fpga_0_SPI_EEPROM_SCK_pin IOSTANDARD = LVCMOS25;
-#Net fpga_0_SPI_EEPROM_SCK_pin TIG;
-#Net fpga_0_SPI_EEPROM_SCK_pin PULLUP;
-#Net fpga_0_SPI_EEPROM_MOSI_pin LOC=AH22;
-#Net fpga_0_SPI_EEPROM_MOSI_pin TIG;
-#Net fpga_0_SPI_EEPROM_MOSI_pin PULLUP;
-#Net fpga_0_SPI_EEPROM_MISO_pin LOC=AJ22;
-#Net fpga_0_SPI_EEPROM_MISO_pin TIG;
-#Net fpga_0_SPI_EEPROM_MISO_pin PULLUP;
-#Net fpga_0_SPI_EEPROM_SS_pin<0> LOC=AG22;
-#Net fpga_0_SPI_EEPROM_SS_pin<0> TIG;
-#Net fpga_0_SPI_EEPROM_SS_pin<0> PULLUP;
-#
-##### Module LEDs_8Bit constraints
-#
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC=AF19;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> TIG;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC=AD5;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS33;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> TIG;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC=AD6;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS33;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> TIG;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC=AD7;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS33;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> TIG;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC=AB8;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS33;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> TIG;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC=AC7;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS33;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> TIG;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC=AC9;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS33;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> TIG;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC=AC10;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS33;
-Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> TIG;
-#
-##### Module LCD_OPTIONAL constraints
-#
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> LOC=AH19;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> LOC=AJ19;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> LOC=AK19;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> LOC=AG20;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> LOC=AH20;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> LOC=AJ20;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> LOC=AG21;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> LOC=AJ21;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> LOC=AK17;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> LOC=AH18;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> LOC=AK18;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> TIG;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> LOC=AJ17;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> IOSTANDARD = LVCMOS25;
-#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> TIG;
-#
-##### Module pci_arbiter_0 constraints
-#
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> LOC=T4;
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> IOSTANDARD = PCI33_3;
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> LOC=T5;
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> IOSTANDARD = PCI33_3;
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> LOC=U8;
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> IOSTANDARD = PCI33_3;
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> LOC=V3;
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> IOSTANDARD = PCI33_3;
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> LOC=T6;
-#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> IOSTANDARD = PCI33_3;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> LOC=T3;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> IOSTANDARD = PCI33_3;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> LOC=R7;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> IOSTANDARD = PCI33_3;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> LOC=T8;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> IOSTANDARD = PCI33_3;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> LOC=T9;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> IOSTANDARD = PCI33_3;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> LOC=R9;
-#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> IOSTANDARD = PCI33_3;
-#
-##### Module PCI32_BRIDGE constraints
-#
-#Net fpga_0_PCI32_BRIDGE_PAR LOC=L8;
-#Net fpga_0_PCI32_BRIDGE_PAR IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_PAR BYPASS;
-#Net fpga_0_PCI32_BRIDGE_PERR_N LOC=M6;
-#Net fpga_0_PCI32_BRIDGE_PERR_N IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_PERR_N BYPASS;
-#Net fpga_0_PCI32_BRIDGE_SERR_N LOC=M7;
-#Net fpga_0_PCI32_BRIDGE_SERR_N IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_SERR_N BYPASS;
-#Net fpga_0_PCI32_BRIDGE_IRDY_N LOC=N5;
-#Net fpga_0_PCI32_BRIDGE_IRDY_N IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_IRDY_N BYPASS;
-#Net fpga_0_PCI32_BRIDGE_FRAME_N LOC=N8;
-#Net fpga_0_PCI32_BRIDGE_FRAME_N IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_FRAME_N BYPASS;
-#Net fpga_0_PCI32_BRIDGE_DEVSEL_N LOC=R3;
-#Net fpga_0_PCI32_BRIDGE_DEVSEL_N IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_DEVSEL_N BYPASS;
-#Net fpga_0_PCI32_BRIDGE_STOP_N LOC=P11;
-#Net fpga_0_PCI32_BRIDGE_STOP_N IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_STOP_N BYPASS;
-#Net fpga_0_PCI32_BRIDGE_TRDY_N LOC=M3;
-#Net fpga_0_PCI32_BRIDGE_TRDY_N IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_TRDY_N BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<31> LOC=P7;
-#Net fpga_0_PCI32_BRIDGE_AD<31> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<31> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<30> LOC=P6;
-#Net fpga_0_PCI32_BRIDGE_AD<30> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<30> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<29> LOC=K7;
-#Net fpga_0_PCI32_BRIDGE_AD<29> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<29> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<28> LOC=K6;
-#Net fpga_0_PCI32_BRIDGE_AD<28> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<28> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<27> LOC=L3;
-#Net fpga_0_PCI32_BRIDGE_AD<27> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<27> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<26> LOC=K8;
-#Net fpga_0_PCI32_BRIDGE_AD<26> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<26> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<25> LOC=M10;
-#Net fpga_0_PCI32_BRIDGE_AD<25> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<25> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<24> LOC=M8;
-#Net fpga_0_PCI32_BRIDGE_AD<24> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<24> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<23> LOC=J7;
-#Net fpga_0_PCI32_BRIDGE_AD<23> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<23> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<22> LOC=J6;
-#Net fpga_0_PCI32_BRIDGE_AD<22> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<22> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<21> LOC=K4;
-#Net fpga_0_PCI32_BRIDGE_AD<21> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<21> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<20> LOC=K3;
-#Net fpga_0_PCI32_BRIDGE_AD<20> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<20> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<19> LOC=N10;
-#Net fpga_0_PCI32_BRIDGE_AD<19> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<19> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<18> LOC=N9;
-#Net fpga_0_PCI32_BRIDGE_AD<18> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<18> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<17> LOC=H5;
-#Net fpga_0_PCI32_BRIDGE_AD<17> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<17> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<16> LOC=H4;
-#Net fpga_0_PCI32_BRIDGE_AD<16> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<16> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<15> LOC=J5;
-#Net fpga_0_PCI32_BRIDGE_AD<15> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<15> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<14> LOC=J4;
-#Net fpga_0_PCI32_BRIDGE_AD<14> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<14> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<13> LOC=L10;
-#Net fpga_0_PCI32_BRIDGE_AD<13> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<13> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<12> LOC=L9;
-#Net fpga_0_PCI32_BRIDGE_AD<12> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<12> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<11> LOC=G3;
-#Net fpga_0_PCI32_BRIDGE_AD<11> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<11> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<10> LOC=F5;
-#Net fpga_0_PCI32_BRIDGE_AD<10> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<10> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<9> LOC=F3;
-#Net fpga_0_PCI32_BRIDGE_AD<9> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<9> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<8> LOC=G5;
-#Net fpga_0_PCI32_BRIDGE_AD<8> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<8> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<7> LOC=N4;
-#Net fpga_0_PCI32_BRIDGE_AD<7> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<7> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<6> LOC=N3;
-#Net fpga_0_PCI32_BRIDGE_AD<6> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<6> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<5> LOC=E4;
-#Net fpga_0_PCI32_BRIDGE_AD<5> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<5> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<4> LOC=E3;
-#Net fpga_0_PCI32_BRIDGE_AD<4> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<4> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<3> LOC=F4;
-#Net fpga_0_PCI32_BRIDGE_AD<3> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<3> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<2> LOC=H3;
-#Net fpga_0_PCI32_BRIDGE_AD<2> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<2> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<1> LOC=L5;
-#Net fpga_0_PCI32_BRIDGE_AD<1> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<1> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_AD<0> LOC=L4;
-#Net fpga_0_PCI32_BRIDGE_AD<0> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_AD<0> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_CBE<3> LOC=R6;
-#Net fpga_0_PCI32_BRIDGE_CBE<3> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_CBE<3> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_CBE<2> LOC=R4;
-#Net fpga_0_PCI32_BRIDGE_CBE<2> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_CBE<2> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_CBE<1> LOC=L6;
-#Net fpga_0_PCI32_BRIDGE_CBE<1> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_CBE<1> BYPASS;
-#Net fpga_0_PCI32_BRIDGE_CBE<0> LOC=M5;
-#Net fpga_0_PCI32_BRIDGE_CBE<0> IOSTANDARD = PCI33_3;
-#Net fpga_0_PCI32_BRIDGE_CBE<0> BYPASS;
-#
-##### Module SysACE_CompactFlash constraints
-#
-#Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF16;
-#Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 29000 ps;
-#Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin LOC=AD4;
-#Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AE6;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AE4;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AE3;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AF6;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AF5;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AF4;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AF3;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AG6;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AG5;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG3;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AH5;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AH4;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AH3;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AJ6;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AJ5;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ4;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AK6;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AK4;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AK3;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AL6;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AL5;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AL4;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA3;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB6;
-#Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AM5;
-#Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AB3;
-#Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AM6;
-#Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33;
-#
-##### Module IIC_Bus constraints
-#
-#Net fpga_0_IIC_Bus_Scl_pin LOC=E7;
-#Net fpga_0_IIC_Bus_Scl_pin IOSTANDARD = LVCMOS33;
-#Net fpga_0_IIC_Bus_Sda_pin LOC=D7;
-#Net fpga_0_IIC_Bus_Sda_pin IOSTANDARD = LVCMOS33;
-#
-##### Module ORGate_1 constraints
-#
-#Net fpga_0_ORGate_1_Res_pin LOC=AE18;
-#Net fpga_0_ORGate_1_Res_pin TIG;
-#Net fpga_0_ORGate_1_Res_1_pin LOC=AE17;
-#Net fpga_0_ORGate_1_Res_1_pin TIG;
-#Net fpga_0_ORGate_1_Res_2_pin LOC=R11;
-#Net fpga_0_ORGate_1_Res_2_pin IOSTANDARD = PCI33_3;
-#
-##### Module TriMode_MAC_GMII constraints
-#
-#Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin LOC = M12;
-#Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin IOSTANDARD=LVCMOS33;
-#Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin TIG;
-#
-##### Module Hard_Temac_0 constraints
-#
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<3> LOC = K9;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<3> IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<3> SLEW=FAST;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<2> LOC = K11;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<2> IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<2> SLEW=FAST;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<1> LOC = K12;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<1> IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<1> SLEW=FAST;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<0> LOC = K13;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<0> IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_TXD_0<0> SLEW=FAST;
-#Net fpga_0_Hard_Temac_0_MII_TX_EN_0 LOC = L11;
-#Net fpga_0_Hard_Temac_0_MII_TX_EN_0 IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_TX_EN_0 SLEW=FAST;
-#Net fpga_0_Hard_Temac_0_MII_TX_ER_0 LOC = L14;
-#Net fpga_0_Hard_Temac_0_MII_TX_ER_0 IOSTANDARD=LVCMOS25;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<3> LOC = J9;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOBDELAY = NONE;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<2> LOC = J10;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOBDELAY = NONE;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<1> LOC = J11;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOBDELAY = NONE;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<0> LOC = J12;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOBDELAY = NONE;
-#Net fpga_0_Hard_Temac_0_MII_RX_DV_0 LOC = H12;
-#Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOBDELAY = NONE;
-#Net fpga_0_Hard_Temac_0_MII_RX_ER_0 LOC = H18;
-#Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOSTANDARD=LVCMOS25;
-#Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOBDELAY = NONE;
-#Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 LOC=J14;
-#Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 MAXSKEW= 2.0 ns;
-#Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 IOSTANDARD=LVCMOS25;
-#Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 LOC=K19;
-#Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 MAXSKEW= 2.0 ns;
-#Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 IOSTANDARD=LVCMOS25;
-#Net fpga_0_Hard_Temac_0_MDIO_0_pin LOC = L13;
-#Net fpga_0_Hard_Temac_0_MDIO_0_pin IOSTANDARD=LVCMOS33;
-#Net fpga_0_Hard_Temac_0_MDC_0_pin LOC = M13;
-#Net fpga_0_Hard_Temac_0_MDC_0_pin IOSTANDARD=LVCMOS33;
-#
-#Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB;
-#TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 10000 ps;
-#
-##### AR 22677
-#
-#AREA_GROUP "opb2plb" RANGE=SLICE_X20Y104:SLICE_X33Y139, SLICE_X34Y96:SLICE_X51Y139;
-#INST "opb2plb" AREA_GROUP = "opb2plb";
-#AREA_GROUP "pblock_spi_eeprom" RANGE=SLICE_X54Y92:SLICE_X67Y111;
-#INST "spi_eeprom" AREA_GROUP = "pblock_spi_eeprom";
-#AREA_GROUP "pblock_plb2opb" RANGE= SLICE_X34Y140:SLICE_X51Y191;
-#INST "plb2opb" AREA_GROUP = "pblock_plb2opb";
-## These two items here no longer exist in 8.2i
-## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CARRY_MUX*" AREA_GROUP = "pblock_plb2opb";
-## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CYMUX_FIRST*" AREA_GROUP = "pblock_plb2opb";
-#
-## The path "I_PLB_ADDRPATH/I_PLBADDR_MUX" doesn't exist either; using *? to replace it
-## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/_n*" AREA_GROUP = "pblock_plb2opb";
-#INST "plb/plb/*?/_n*" AREA_GROUP = "pblock_plb2opb";
-#INST "plb/plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/*" AREA_GROUP = "pblock_plb2opb";
-#
-###################################
-#### Virtex-4 FX60-FF1152 MGT Null Tile LOCs ###
-###################################
-##MGT113A
-#INST MGT113AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y7;
-#NET "MGT113AB_TXN<1>" LOC = "A3"; #TXN
-#NET "MGT113AB_TXP<1>" LOC = "A4"; #TXP
-#NET "MGT113AB_RXN<1>" LOC = "A6"; #RXN
-#NET "MGT113AB_RXP<1>" LOC = "A7"; #RXP
-##MGT113B
-#INST MGT113AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y6;
-#NET "MGT113AB_TXN<0>" LOC = "D1"; #TXN
-#NET "MGT113AB_TXP<0>" LOC = "C1"; #TXP
-#NET "MGT113AB_RXN<0>" LOC = "G1"; #RXN
-#NET "MGT113AB_RXP<0>" LOC = "F1"; #RXP
-##MGT112A
-#INST MGT112AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y5;
-#NET "MGT112AB_TXN<1>" LOC = "T1"; #TXN
-#NET "MGT112AB_TXP<1>" LOC = "R1"; #TXP
-#NET "MGT112AB_RXN<1>" LOC = "N1"; #RXN
-#NET "MGT112AB_RXP<1>" LOC = "M1"; #RXP
-##MGT112B
-#INST MGT112AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y4;
-#NET "MGT112AB_TXN<0>" LOC = "V1"; #TXN
-#NET "MGT112AB_TXP<0>" LOC = "U1"; #TXP
-#NET "MGT112AB_RXN<0>" LOC = "AA1"; #RXN
-#NET "MGT112AB_RXP<0>" LOC = "Y1"; #RXP
-##MGT110A
-#INST MGT110AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y3;
-#NET "MGT110AB_TXN<1>" LOC = "AG1"; #TXN
-#NET "MGT110AB_TXP<1>" LOC = "AF1"; #TXP
-#NET "MGT110AB_RXN<1>" LOC = "AD1"; #RXN
-#NET "MGT110AB_RXP<1>" LOC = "AC1"; #RXP
-##MGT110B
-#INST MGT110AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y2;
-#NET "MGT110AB_TXN<0>" LOC = "AJ1"; #TXN
-#NET "MGT110AB_TXP<0>" LOC = "AH1"; #TXP
-#NET "MGT110AB_RXN<0>" LOC = "AM1"; #RXN
-#NET "MGT110AB_RXP<0>" LOC = "AL1"; #RXP
-##MGT109A
-#INST MGT109AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y1;
-#NET "MGT109AB_TXN<1>" LOC = "AP10"; #TXN
-#NET "MGT109AB_TXP<1>" LOC = "AP9"; #TXP
-#NET "MGT109AB_RXN<1>" LOC = "AP7"; #RXN
-#NET "MGT109AB_RXP<1>" LOC = "AP6"; #RXP
-##MGT109B
-#INST MGT109AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y0;
-#NET "MGT109AB_TXN<0>" LOC = "AP12"; #TXN
-#NET "MGT109AB_TXP<0>" LOC = "AP11"; #TXP
-#NET "MGT109AB_RXN<0>" LOC = "AP15"; #RXN
-#NET "MGT109AB_RXP<0>" LOC = "AP14"; #RXP
-##MGT102A
-#INST MGT102AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y7;
-#NET "MGT102AB_TXN<1>" LOC = "E34"; #TXN
-#NET "MGT102AB_TXP<1>" LOC = "D34"; #TXP
-#NET "MGT102AB_RXN<1>" LOC = "A32"; #RXN
-#NET "MGT102AB_RXP<1>" LOC = "A31"; #RXP
-#
-##MGT102B
-#INST MGT102AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y6;
-#NET "MGT102AB_TXN<0>" LOC = "G34"; #TXN
-#NET "MGT102AB_TXP<0>" LOC = "F34"; #TXP
-#NET "MGT102AB_RXN<0>" LOC = "K34"; #RXN
-#NET "MGT102AB_RXP<0>" LOC = "J34"; #RXP
-##MGT103A
-#INST MGT103AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y5;
-#NET "MGT103AB_TXN<1>" LOC = "W34"; #TXN
-#NET "MGT103AB_TXP<1>" LOC = "V34"; #TXP
-#NET "MGT103AB_RXN<1>" LOC = "T34"; #RXN
-#NET "MGT103AB_RXP<1>" LOC = "R34"; #RXP
-##MGT103B
-#INST MGT103AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y4;
-#NET "MGT103AB_TXN<0>" LOC = "AA34"; #TXN
-#NET "MGT103AB_TXP<0>" LOC = "Y34"; #TXP
-#NET "MGT103AB_RXN<0>" LOC = "AD34"; #RXN
-#NET "MGT103AB_RXP<0>" LOC = "AC34"; #RXP
-##MGT105A
-#INST MGT105AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y3;
-#NET "MGT105AB_TXN<1>" LOC = "AK34"; #TXN
-#NET "MGT105AB_TXP<1>" LOC = "AJ34"; #TXP
-#NET "MGT105AB_RXN<1>" LOC = "AG34"; #RXN
-#NET "MGT105AB_RXP<1>" LOC = "AF34"; #RXP
-##MGT105B
-#INST MGT105AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y2;
-#NET "MGT105AB_TXN<0>" LOC = "AM34"; #TXN
-#NET "MGT105AB_TXP<0>" LOC = "AL34"; #TXP
-#NET "MGT105AB_RXN<0>" LOC = "AP31"; #RXN
-#NET "MGT105AB_RXP<0>" LOC = "AP32"; #RXP
-##MGT106A
-#INST MGT106AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y1;
-#NET "MGT106AB_TXN<1>" LOC = "AP22"; #TXN
-#NET "MGT106AB_TXP<1>" LOC = "AP23"; #TXP
-#NET "MGT106AB_RXN<1>" LOC = "AP25"; #RXN
-#NET "MGT106AB_RXP<1>" LOC = "AP26"; #RXP
-##MGT106B
-#INST MGT106AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y0;
-#NET "MGT106AB_TXN<0>" LOC = "AP20"; #TXN
-#NET "MGT106AB_TXP<0>" LOC = "AP21"; #TXP
-#NET "MGT106AB_RXN<0>" LOC = "AP17"; #RXN
-#NET "MGT106AB_RXP<0>" LOC = "AP18"; #RXP 
-#
-
-
-
-## DDR ##############################################################################
-
-
-## IO Devices constraints
-
-#### Module ORGate_1 constraints
-
-# Net fpga_0_ORGate_1_Res_pin LOC=AE18;
-# Net fpga_0_ORGate_1_Res_pin TIG;
-# Net fpga_0_ORGate_1_Res_1_pin LOC=AE17;
-# Net fpga_0_ORGate_1_Res_1_pin TIG;
-# Net fpga_0_ORGate_1_Res_2_pin LOC=R11;
-# Net fpga_0_ORGate_1_Res_2_pin IOSTANDARD = PCI33_3;
+Net uart_cts LOC=G6;
+Net uart_cts IOSTANDARD = LVCMOS33;
+Net uart_cts TIG;
+Net uart_rts LOC=F6;
+Net uart_rts IOSTANDARD = LVCMOS33;
+Net uart_rts TIG;
 
-#### Module DDR2_SDRAM constraints
+Net uart_in LOC=E6;
+Net uart_in IOSTANDARD = LVCMOS33;
+Net uart_in TIG;
+Net uart_in PULLUP;
 
-# Net ddr2_ODT_pin LOC=AA25;
-# Net ddr2_ODT_pin IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<0> LOC=H28;
-# Net ddr2_Addr_pin<0> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<1> LOC=K28;
-# Net ddr2_Addr_pin<1> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<2> LOC=L28;
-# Net ddr2_Addr_pin<2> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<3> LOC=M25;
-# Net ddr2_Addr_pin<3> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<4> LOC=Y24;
-# Net ddr2_Addr_pin<4> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<5> LOC=N27;
-# Net ddr2_Addr_pin<5> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<6> LOC=AD26;
-# Net ddr2_Addr_pin<6> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<7> LOC=AC25;
-# Net ddr2_Addr_pin<7> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<8> LOC=R26;
-# Net ddr2_Addr_pin<8> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<9> LOC=R28;
-# Net ddr2_Addr_pin<9> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<10> LOC=T26;
-# Net ddr2_Addr_pin<10> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<11> LOC=T28;
-# Net ddr2_Addr_pin<11> IOSTANDARD = SSTL18_I;
-# Net ddr2_Addr_pin<12> LOC=U27;
-# Net ddr2_Addr_pin<12> IOSTANDARD = SSTL18_I;
-# Net ddr2_BankAddr_pin<0> LOC=V28;
-# Net ddr2_BankAddr_pin<0> IOSTANDARD = SSTL18_I;
-# Net ddr2_BankAddr_pin<1> LOC=W26;
-# Net ddr2_BankAddr_pin<1> IOSTANDARD = SSTL18_I;
-# Net ddr2_CAS_n_pin LOC=R31;
-# Net ddr2_CAS_n_pin IOSTANDARD = SSTL18_I;
-# Net ddr2_CE_pin LOC=AJ31;
-# Net ddr2_CE_pin IOSTANDARD = SSTL18_I;
-# Net ddr2_CS_n_pin LOC=AJ30;
-# Net ddr2_CS_n_pin IOSTANDARD = SSTL18_I;
-# Net ddr2_RAS_n_pin LOC=R32;
-# Net ddr2_RAS_n_pin IOSTANDARD = SSTL18_I;
-# Net ddr2_WE_n_pin LOC=T31;
-# Net ddr2_WE_n_pin IOSTANDARD = SSTL18_I;
-# Net ddr2_DM_pin<0> LOC=AH30;
-# Net ddr2_DM_pin<0> IOSTANDARD = SSTL18_II;
-# Net ddr2_DM_pin<1> LOC=M31;
-# Net ddr2_DM_pin<1> IOSTANDARD = SSTL18_II;
-# Net ddr2_DM_pin<2> LOC=T30;
-# Net ddr2_DM_pin<2> IOSTANDARD = SSTL18_II;
-# Net ddr2_DM_pin<3> LOC=U28;
-# Net ddr2_DM_pin<3> IOSTANDARD = SSTL18_II;
-# Net ddr2_DM_pin<4> LOC=AJ32;
-# Net ddr2_DM_pin<4> IOSTANDARD = SSTL18_II;
-# Net ddr2_DM_pin<5> LOC=AG31;
-# Net ddr2_DM_pin<5> IOSTANDARD = SSTL18_II;
-# Net ddr2_DM_pin<6> LOC=AG30;
-# Net ddr2_DM_pin<6> IOSTANDARD = SSTL18_II;
-# Net ddr2_DM_pin<7> LOC=AF29;
-# Net ddr2_DM_pin<7> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS<0> LOC=F29;
-# Net ddr2_DQS<0> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS<1> LOC=K29;
-# Net ddr2_DQS<1> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS<2> LOC=P27;
-# Net ddr2_DQS<2> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS<3> LOC=P32;
-# Net ddr2_DQS<3> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS<4> LOC=W27;
-# Net ddr2_DQS<4> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS<5> LOC=W31;
-# Net ddr2_DQS<5> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS<6> LOC=AG32;
-# Net ddr2_DQS<6> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS<7> LOC=AE32;
-# Net ddr2_DQS<7> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS_n<0> LOC=E29;
-# Net ddr2_DQS_n<0> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS_n<1> LOC=J29;
-# Net ddr2_DQS_n<1> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS_n<2> LOC=P26;
-# Net ddr2_DQS_n<2> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS_n<3> LOC=N32;
-# Net ddr2_DQS_n<3> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS_n<4> LOC=V27;
-# Net ddr2_DQS_n<4> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS_n<5> LOC=W30;
-# Net ddr2_DQS_n<5> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS_n<6> LOC=AH32;
-# Net ddr2_DQS_n<6> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQS_n<7> LOC=AE31;
-# Net ddr2_DQS_n<7> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<0> LOC=C32;
-# Net ddr2_DQ<0> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<1> LOC=D32;
-# Net ddr2_DQ<1> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<2> LOC=E32;
-# Net ddr2_DQ<2> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<3> LOC=G32;
-# Net ddr2_DQ<3> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<4> LOC=H32;
-# Net ddr2_DQ<4> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<5> LOC=J32;
-# Net ddr2_DQ<5> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<6> LOC=K32;
-# Net ddr2_DQ<6> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<7> LOC=M32;
-# Net ddr2_DQ<7> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<8> LOC=N28;
-# Net ddr2_DQ<8> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<9> LOC=D31;
-# Net ddr2_DQ<9> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<10> LOC=E31;
-# Net ddr2_DQ<10> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<11> LOC=F31;
-# Net ddr2_DQ<11> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<12> LOC=G31;
-# Net ddr2_DQ<12> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<13> LOC=J31;
-# Net ddr2_DQ<13> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<14> LOC=K31;
-# Net ddr2_DQ<14> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<15> LOC=L31;
-# Net ddr2_DQ<15> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<16> LOC=C30;
-# Net ddr2_DQ<16> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<17> LOC=D30;
-# Net ddr2_DQ<17> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<18> LOC=F30;
-# Net ddr2_DQ<18> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<19> LOC=G30;
-# Net ddr2_DQ<19> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<20> LOC=Y28;
-# Net ddr2_DQ<20> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<21> LOC=Y27;
-# Net ddr2_DQ<21> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<22> LOC=L30;
-# Net ddr2_DQ<22> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<23> LOC=M30;
-# Net ddr2_DQ<23> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<24> LOC=N30;
-# Net ddr2_DQ<24> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<25> LOC=C29;
-# Net ddr2_DQ<25> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<26> LOC=D29;
-# Net ddr2_DQ<26> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<27> LOC=J30;
-# Net ddr2_DQ<27> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<28> LOC=L29;
-# Net ddr2_DQ<28> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<29> LOC=N29;
-# Net ddr2_DQ<29> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<30> LOC=P29;
-# Net ddr2_DQ<30> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<31> LOC=R29;
-# Net ddr2_DQ<31> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<32> LOC=T29;
-# Net ddr2_DQ<32> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<33> LOC=U32;
-# Net ddr2_DQ<33> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<34> LOC=V32;
-# Net ddr2_DQ<34> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<35> LOC=W32;
-# Net ddr2_DQ<35> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<36> LOC=Y32;
-# Net ddr2_DQ<36> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<37> LOC=AB32;
-# Net ddr2_DQ<37> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<38> LOC=AC32;
-# Net ddr2_DQ<38> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<39> LOC=AD32;
-# Net ddr2_DQ<39> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<40> LOC=AB27;
-# Net ddr2_DQ<40> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<41> LOC=U31;
-# Net ddr2_DQ<41> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<42> LOC=W25;
-# Net ddr2_DQ<42> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<43> LOC=Y31;
-# Net ddr2_DQ<43> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<44> LOC=AA31;
-# Net ddr2_DQ<44> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<45> LOC=AB31;
-# Net ddr2_DQ<45> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<46> LOC=AD31;
-# Net ddr2_DQ<46> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<47> LOC=AB28;
-# Net ddr2_DQ<47> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<48> LOC=AF31;
-# Net ddr2_DQ<48> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<49> LOC=U30;
-# Net ddr2_DQ<49> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<50> LOC=V30;
-# Net ddr2_DQ<50> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<51> LOC=Y26;
-# Net ddr2_DQ<51> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<52> LOC=AA30;
-# Net ddr2_DQ<52> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<53> LOC=AB30;
-# Net ddr2_DQ<53> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<54> LOC=AC30;
-# Net ddr2_DQ<54> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<55> LOC=AD30;
-# Net ddr2_DQ<55> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<56> LOC=AF30;
-# Net ddr2_DQ<56> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<57> LOC=V29;
-# Net ddr2_DQ<57> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<58> LOC=W29;
-# Net ddr2_DQ<58> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<59> LOC=Y29;
-# Net ddr2_DQ<59> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<60> LOC=AA29;
-# Net ddr2_DQ<60> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<61> LOC=AC29;
-# Net ddr2_DQ<61> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<62> LOC=AD29;
-# Net ddr2_DQ<62> IOSTANDARD = SSTL18_II;
-# Net ddr2_DQ<63> LOC=AE29;
-# Net ddr2_DQ<63> IOSTANDARD = SSTL18_II;
-# Net ddr2_Clk_pin LOC=H30;
-# Net ddr2_Clk_pin IOSTANDARD = SSTL18_II;
-# Net ddr2_Clk_n_pin LOC=H29;
-# Net ddr2_Clk_n_pin IOSTANDARD = SSTL18_II;
-# 
-#### Module DDR_SDRAM constraints
+Net uart_out LOC=D6;
+Net uart_out IOSTANDARD = LVCMOS33;
+Net uart_out TIG;
+Net uart_out PULLUP;
 
 Net ddr1_Addr_pin<12> LOC=J24;
 Net ddr1_Addr_pin<12> IOSTANDARD = SSTL2_I;

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
deleted file mode 100644 (file)
index 51eed13..0000000
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ /dev/null
@@ -1,318 +0,0 @@
-
-module main
- (sys_clk_pin,   /* 100Mhz */
-  sys_rst_pin,
-  fpga_0_RS232_Uart_1_ctsN_pin,
-  fpga_0_RS232_Uart_1_rtsN_pin,
-  fpga_0_RS232_Uart_1_sin_pin,
-  fpga_0_RS232_Uart_1_sout_pin,
-
-  ddr1_Clk_pin,
-  ddr1_Clk_n_pin,
-  ddr1_Addr_pin,
-  ddr1_BankAddr_pin,
-  ddr1_CAS_n_pin,
-  ddr1_CE_pin,
-  ddr1_CS_n_pin,
-  ddr1_RAS_n_pin,
-  ddr1_WE_n_pin,
-  ddr1_DM_pin,
-  ddr1_DQS,
-  ddr1_DQ,
-
-  vga_psave,
-  vga_hsync,
-  vga_vsync,
-  vga_sync,
-  vga_blank,
-  vga_r,
-  vga_g,
-  vga_b,
-  vga_clkout,
-
-  fpga_0_LEDs_8Bit_GPIO_IO_pin
- );
-
-  input  sys_clk_pin;
-  input  sys_rst_pin;
-  input  fpga_0_RS232_Uart_1_ctsN_pin;
-  output fpga_0_RS232_Uart_1_rtsN_pin;
-  input  fpga_0_RS232_Uart_1_sin_pin;
-  output fpga_0_RS232_Uart_1_sout_pin;
-
-  output        ddr1_Clk_pin;
-  output        ddr1_Clk_n_pin;
-  output [12:0] ddr1_Addr_pin;
-  output [1:0]  ddr1_BankAddr_pin;
-  output        ddr1_CAS_n_pin;
-  output        ddr1_CE_pin;
-  output        ddr1_CS_n_pin;
-  output        ddr1_RAS_n_pin;
-  output        ddr1_WE_n_pin;
-  output [3:0]  ddr1_DM_pin;
-  inout  [3:0]  ddr1_DQS;
-  inout  [31:0] ddr1_DQ;
-
-  wire  [31:0]  dram_addr;
-  wire          dram_addr_r;
-  wire          dram_addr_a;
-  wire          dram_isread;
-  wire  [63:0]  dram_write_data;
-  wire          dram_write_data_push;
-  wire          dram_write_data_full;
-  wire   [63:0] dram_read_data;
-  wire          dram_read_data_pop;
-  wire          dram_read_data_empty;
-  wire   [1:0]  dram_read_data_latency;
-
-  output vga_psave;
-  output vga_hsync;
-  output vga_vsync;
-  output vga_sync;
-  output vga_blank;
-  output [7:0] vga_r;
-  output [7:0] vga_g;
-  output [7:0] vga_b;
-  output vga_clkout;
-
-  wire clk;
-  wire clk_fb;
-  wire clk50mhz;
-  wire clk_unbuffered;
-
-  wire vga_clk;
-  wire vga_clk_fb;
-  wire vga_clk_unbuffered;
-
-  output [7:0] fpga_0_LEDs_8Bit_GPIO_IO_pin;
-  wire [7:0] leds;
-  assign fpga_0_LEDs_8Bit_GPIO_IO_pin = ~leds;
-
-  assign leds[5:0] = dram_read_data[5:0];
-  assign leds[6] = dram_addr_r;
-  assign leds[7] = dram_addr_a;
-
-  BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));
-
-  DCM
-   #(
-      .CLKFX_MULTIPLY(4),
-      .CLKFX_DIVIDE(8),
-      .CLKIN_PERIOD("10 ns")
-    ) mydcm(
-      .CLKIN (sys_clk_pin),
-      .CLKFB(clk_fb),
-      .CLKFX (clk_unbuffered),
-      .CLK0  (clk_fb)
-    );
-
-  BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk));
-  DCM  // 25Mhz VGA clock
-   #(
-      .CLKFX_MULTIPLY(4),
-      .CLKFX_DIVIDE(16),
-      .CLKIN_PERIOD("20 ns")
-    ) vgadcm (
-      .CLKIN (clk_unbuffered),
-      .CLKFB(vga_clk_fb),
-      .CLKFX (vga_clk_unbuffered),
-      .CLK0  (vga_clk_fb)
-    );
-
-
-  wire break_o;
-  wire break;
-  reg break_last;
-  reg send_k;                initial send_k = 0;
-  wire rst;
-  assign rst = sys_rst_pin;
-
-  wire       data_to_host_full;
-  wire       data_to_host_write_enable;
-  wire [7:0] data_to_host;
-
-  wire       data_to_fleet_empty;
-  wire       data_to_fleet_read_enable;
-  wire [7:0] data_to_fleet;
-
-  reg we;
-  reg re;
-  reg [7:0] data_to_host_r;
-  assign data_to_host = data_to_host_r;
-
-  wire ser_rst;
-  reg ser_rst_r;
-  initial ser_rst_r = 0;
-  assign ser_rst = (rst & ser_rst_r);
-
-  wire sio_ce;
-  wire sio_ce_x4;
-
-  sasc_brg sasc_brg(sys_clk_pin, ser_rst, 8, 65, sio_ce, sio_ce_x4);
-  sasc_top sasc_top(clk, ser_rst,
-                    fpga_0_RS232_Uart_1_sin_pin,
-                    fpga_0_RS232_Uart_1_sout_pin,
-                    fpga_0_RS232_Uart_1_ctsN_pin,
-                    fpga_0_RS232_Uart_1_rtsN_pin, 
-                    sio_ce,
-                    sio_ce_x4,
-                    data_to_host,
-                    data_to_fleet,
-                    data_to_fleet_read_enable,
-                    data_to_host_write_enable,
-                    data_to_host_full,
-                    data_to_fleet_empty,
-                    break_o,
-                    break);
-
-   // break and break_o are _active high_
-   always @(posedge clk) break_last <= break_o;
-   assign break      =  break_o && !break_last;
-   assign break_done = !break_o &&  break_last;
-
-   reg data_to_host_write_enable_reg;
-   reg data_to_fleet_read_enable_reg;
-
-   reg root_out_a_reg;
-   reg root_in_r_reg;
-   reg [7:0] root_in_d_reg;
-   wire root_in_a;
-   wire root_in_r;
-   wire root_out_a;
-   wire root_out_r;
-   wire [7:0] root_in_d;
-   wire [7:0] root_out_d;
-
-   /*
-    * There is some very weird timing thing going on here; we need to
-    * hold reset low for more than one clock in order for it to propagate
-    * all the way to the docks.
-    */
-   root my_root(clk, rst && !break_o,
-                root_in_r,  root_in_a,  root_in_d,
-                root_out_r, root_out_a, root_out_d,
-                dram_addr,
-                dram_addr_r,
-                dram_addr_a,
-                dram_isread,
-                dram_write_data,
-                dram_write_data_push,
-                dram_write_data_full,
-                dram_read_data,
-                dram_read_data_pop,
-                dram_read_data_empty,
-                dram_read_data_latency,
-                vga_clk,
-                vga_psave,
-                vga_hsync,
-                vga_vsync,
-                vga_sync,
-                vga_blank,
-                vga_r,
-                vga_g,
-                vga_b,
-                vga_clkout
-               );
-
-   assign root_out_a                = root_out_a_reg;                
-   assign root_in_r                 = root_in_r_reg;
-   assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
-   assign data_to_host_write_enable = data_to_host_write_enable_reg;
-   assign root_in_d                 = root_in_d_reg;
-
-   // fpga -> host
-   always @(posedge clk)
-   begin
-     if (break) begin
-       root_out_a_reg = 0;
-       data_to_host_write_enable_reg <= 0;
-
-     end else if (break_done) begin
-       data_to_host_write_enable_reg <= 1;
-       data_to_host_r <= 111;
-       send_k <= 1;
-     end else if (send_k) begin
-       data_to_host_write_enable_reg <= 1;
-       data_to_host_r <= 107;
-       send_k <= 0;
-
-
-     end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
-       data_to_host_write_enable_reg <= 1;
-       data_to_host_r <= root_out_d;
-       root_out_a_reg = 1;
-     end else if (root_out_a_reg && !root_out_r) begin
-       data_to_host_write_enable_reg <= 0;
-       root_out_a_reg = 0;
-     end else begin
-       data_to_host_write_enable_reg <= 0;
-     end
-   end
-
-   // host -> fpga
-   always @(posedge clk)
-   begin
-     ser_rst_r <= 1;
-     if (break) begin
-       root_in_r_reg <= 0;
-       root_in_d_reg <= 0;
-       data_to_fleet_read_enable_reg <= 0;
-     end else
-  
-     if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
-        root_in_r_reg <= 1;
-        root_in_d_reg <= data_to_fleet;
-        data_to_fleet_read_enable_reg <= 1;
-     end else begin
-       data_to_fleet_read_enable_reg <= 0;
-        if (root_in_a) begin
-          root_in_r_reg <= 0;
-        end
-     end
-   end
-
-   initial
-   begin
-     root_in_r_reg = 0;
-     root_in_d_reg = 0;
-     root_out_a_reg = 0;
-     data_to_fleet_read_enable_reg = 0;
-     data_to_host_write_enable_reg = 0;
-   end
-
-   ddr_ctrl 
-   #(
-       .clk_freq( 50000000 ),
-       .clk_multiply( 12 ),
-       .clk_divide( 5 ),
-       .phase_shift( 0 ),
-       .wait200_init( 26 )
-   ) ddr_ctrl (
-          .ddr_a( ddr1_Addr_pin ),
-          .ddr_clk( ddr1_Clk_pin ),
-          .ddr_clk_n( ddr1_Clk_n_pin ),
-          .ddr_ba( ddr1_BankAddr_pin ),
-          .ddr_dq( ddr1_DQ ),
-          .ddr_dm( ddr1_DM_pin ),
-          .ddr_dqs( ddr1_DQS ),
-          .ddr_cs_n( ddr1_CS_n_pin ),
-          .ddr_ras_n( ddr1_RAS_n_pin ),
-          .ddr_cas_n( ddr1_CAS_n_pin ),
-          .ddr_we_n( ddr1_WE_n_pin ),
-          .ddr_cke( ddr1_CE_pin ),
-   
-          .clk(clk),
-          .reset(!rst),
-          .rot(3'b100),
-   
-          .fml_wr(!dram_isread && dram_addr_r),
-          .fml_done(dram_addr_a),
-          .fml_rd( dram_isread && dram_addr_r),
-          .fml_adr(dram_addr),
-          .fml_din(dram_write_data),
-          .fml_dout(dram_read_data),
-          .fml_msk(16'h0)
-   );
-
-endmodule
-   

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index 838d823..21d6179 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -12,18 +12,20 @@ import static edu.berkeley.fleet.two.FleetTwoFleet.*;
 => get rid of getInputPort(String) and instead use members
 => get rid of addcrap
 => automatic width-setting/checking on ports
+=> mangle the names given for strings
 */
 
 public class Verilog {
 
     public static class PercolatedPort {
-        public final boolean up;
-        public final int width;
+        public static enum PortType { UP, DOWN, INOUT };
         public final String name;
-        public PercolatedPort(String name, int width, boolean up) {
+        public final int width;
+        public final PortType type;
+        public PercolatedPort(String name, int width, PortType type) {
             this.name = name;
             this.width = width;
-            this.up = up;
+            this.type = type;
         }
     }
 
@@ -465,21 +467,57 @@ public class Verilog {
         }
 
         public void dump(PrintWriter pw, boolean fix) {
-            pw.println("module "+name+"(clk, rst ");
+            boolean isRoot = name.equals("main");
+            pw.print("module "+name);
+            if (isRoot) {
+                pw.println("(clk_pin, rst_pin ");
+            } else {
+                pw.println("(clk, rst ");
+            }
             for(String name : portorder) {
                 Port p = ports.get(name);
                 pw.println("    , " + p.getInterface());
             }
             for (InstantiatedModule im : this.instantiatedModules)
                 for(PercolatedPort pp : im.module.percolatedPorts)
-                    pw.println("    , "+pp.name);
+                    if (!isRoot || (!pp.name.startsWith("root_in_") && !pp.name.startsWith("rst_")))
+                        pw.println("    , "+pp.name);
             pw.println("   );");
             pw.println();
-            pw.println("    input clk;");
-            pw.println("    input rst;");
+
+            if (isRoot) {
+                pw.println("  input clk_pin;");
+                pw.println("  input rst_pin;");
+                pw.println("  wire clk;");
+                pw.println("  wire clk_fb;");
+                pw.println("  wire clk_unbuffered;");
+                pw.println("  BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));");
+                pw.println("  DCM");
+                pw.println("   #(");
+                pw.println("      .CLKFX_MULTIPLY(4),");
+                pw.println("      .CLKFX_DIVIDE(8),");
+                pw.println("      .CLKIN_PERIOD(\"10 ns\")");
+                pw.println("    ) mydcm(");
+                pw.println("      .CLKIN (clk_pin),");
+                pw.println("      .CLKFB(clk_fb),");
+                pw.println("      .CLKFX (clk_unbuffered),");
+                pw.println("      .CLK0  (clk_fb)");
+                pw.println("    );");
+                pw.println("  wire rst;");
+            } else {
+                pw.println("    input clk;");
+                pw.println("    input rst;");
+            }
+
             for (InstantiatedModule im : this.instantiatedModules)
                 for(PercolatedPort pp : im.module.percolatedPorts) {
-                    pw.print(pp.up ? "output" : "input");
+                    if (isRoot && (pp.name.startsWith("root_in_") || pp.name.startsWith("rst_")))
+                        pw.print("wire");
+                    else  switch(pp.type) {
+                            case UP:    pw.print("output"); break;
+                            case DOWN:  pw.print("input");  break;
+                            case INOUT: pw.print("inout");  break;
+                        }
                     pw.print("  ");
                     if (pp.width > 1)
                         pw.print("["+(pp.width-1)+":0]");
@@ -487,6 +525,12 @@ public class Verilog {
                     pw.print(pp.name);
                     pw.println(";");
                 }
+
+            if (isRoot) {
+                pw.println("  assign rst    = rst_out;");
+                pw.println("  assign rst_in = rst_pin;");
+            }
+
             for(String name : ports.keySet()) {
                 Port p = ports.get(name);
                 pw.println("    " + p.getDeclaration());

diff --git a/src/edu/berkeley/fleet/two/ShipDescription.java b/src/edu/berkeley/fleet/two/ShipDescription.java
index d1158ea..3c8a5ae 100644 (file)
--- a/src/edu/berkeley/fleet/two/ShipDescription.java
+++ b/src/edu/berkeley/fleet/two/ShipDescription.java
@@ -86,11 +86,14 @@ public class ShipDescription implements Iterable<DockDescription> {
                 else if (key.startsWith("percolate")) { 
                     key = s;
                     key = key.substring("percolate".length()+1).trim();
-                    boolean up = key.startsWith("up");
+                    PercolatedPort.PortType type = null;
+                    if (key.startsWith("up")) type = PercolatedPort.PortType.UP;
+                    if (key.startsWith("down")) type = PercolatedPort.PortType.DOWN;
+                    if (key.startsWith("inout")) type = PercolatedPort.PortType.INOUT;
                     key = key.substring(key.indexOf(':')+1).trim();
                     String name = key.substring(0, key.indexOf(' '));
                     int width = Integer.parseInt(key.substring(key.indexOf(' ')).trim());
-                    percolatedPorts.add(new PercolatedPort(name, width, up));
+                    percolatedPorts.add(new PercolatedPort(name, width, type));
                     continue;
                 }
                 else if (key.startsWith("constant")) {