send olcZ, not olcNZ, to requeue

diff --git a/electric/skipL.jelib b/electric/skipL.jelib
index 1cf26e5..d437ac6 100755 (executable)
--- a/electric/skipL.jelib
+++ b/electric/skipL.jelib
@@ -1,5 +1,5 @@
 # header information:
-HskipL|8.08j
+HskipL|8.08k
 
 # Views:
 Vicon|ic
@@ -2751,7 +2751,7 @@ Eolc[load,dec][T,F]|olc[load,dec][F]|D4G2;|conn@2|a|I
 X
 
 # Cell skipAll;2{ic}
-CskipAll;2{ic}||artwork|1222616071020|1226848088644|E
+CskipAll;2{ic}||artwork|1222616071020|1227139677270|E
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NThick-Circle|art@2||9.5|5|1|1||
 NThick-Circle|art@5||9.5|2|1|1||
@@ -2818,7 +2818,7 @@ EinLO[7]||D5G2;|pin@6||I
 Ein[1:9][T,F]|in[1:18]|D5G2;|pin@8||I
 Etorp|kill|D5G2;|pin@22||I
 Emc||D5G2;|pin@12||I
-EolcNZ||D5G2;|pin@14||O
+EolcNZ|olcZ|D5G2;|pin@14||O
 Eolc[load,dec][1:2]||D5G2;|pin@63||O
 EselLO[Lf,Lo,Co]|selLO[Lf,Lo,Co,Dm,Dl,Li]|D5G2;|pin@18||I
 Edo[7]|zooLO|D5G2;|pin@2||I
@@ -3785,14 +3785,14 @@ Evdd_62||D5G2;|skipTime@6|vdd_28|P
 X
 
 # Cell skipAll;5{sch}
-CskipAll;5{sch}||schematic|1222262993079|1226848088644|
+CskipAll;5{sch}||schematic|1222262993079|1227139677270|
 Iarray;1{ic}|array@0||0|4|||D5G4;
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-35.5|2||||
 NOff-Page|conn@2||18|0|||YRR|
 NOff-Page|conn@5||36|-6|||YRRR|
 NOff-Page|conn@10||13|-30|||YRRR|
-NOff-Page|conn@11||15.5|-12|||XRR|
+NOff-Page|conn@11||26.5|-12|||XRR|
 NOff-Page|conn@12||-12|-9|||Y|
 NOff-Page|conn@13||6|-32|||XYRRR|
 NOff-Page|conn@14||-12|-19|||Y|
@@ -3805,6 +3805,7 @@ IredFour:inv;1{ic}|inv@0||-23|18|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D
 IredFour:inv;1{ic}|inv@1||-39|-30|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S80|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFour:inv;1{ic}|inv@2||-23|-30|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S40|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFour:inv;1{ic}|inv@3||-39|18|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFour:inv;1{ic}|inv@4||17|-12|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 Ngeneric:Invisible-Pin|pin@0||1|38|||||ART_message(D5G6;)SskipAll
 Ngeneric:Invisible-Pin|pin@1||1|33|||||ART_message(D5G4;)Sflags and amplifiers
 Ngeneric:Invisible-Pin|pin@2||1|28|||||ART_message(D5G3;)Sies 13 November 2008
@@ -3883,7 +3884,6 @@ Awire|net@103|||2700|pin@49||-6|-17|pin@39||-6|-9
 Awire|net@106|||1800|conn@14|y|-10|-19|proposeZ@1|torp|1|-19
 Awire|net@107|||2700|conn@13|y|6|-30|proposeZ@1|do[7]|6|-24
 Awire|net@110|||900|pin@51||8|-12|proposeZ@1|olcNZ|8|-15
-Awire|net@111|||0|conn@11|a|13.5|-12|pin@51||8|-12
 Awire|net@126|||0|wire90@3|b|0|-12|pin@26||-2|-12
 Abus|net@133||-0.5|IJ1800|pin@61||-9|9|array@0|m1[T,F]|-3|9
 Awire|net@142|||1800|array@0|flag[Z]|4|2|pin@67||6|2
@@ -3926,6 +3926,8 @@ Awire|net@344|||0|wire90@19|a|23|8|pin@159||16|8
 Awire|net@348|||0|conn@2|y|16|0|pin@161||9|0
 Awire|net@349|||2700|pin@161||9|0|pin@162||9|4
 Awire|net@350|||0|pin@162||9|4|array@0|in[C]|4|4
+Awire|net@351|||0|inv@4|in|14.5|-12|pin@51||8|-12
+Awire|net@352|||1800|inv@4|out|19.5|-12|conn@11|a|24.5|-12
 Awire|olc[dec][F]|D5G2;||900|pin@148||54|-18|pin@149||54|-21
 Abus|olc[load,dec][F]|D5G2;|-0.5|IJ900|pin@104||23.5|-18|pin@105||23.5|-21
 Awire|olc[load][F]|D5G2;||900|pin@146||54|-12|pin@147||54|-15
@@ -3938,7 +3940,7 @@ EinLO[7]||D4G2;|conn@10|a|I
 Ein[1:18]||D4G2;|conn@0|a|I
 Ekill||D4G2;|conn@14|a|I
 Emc||D4G2;|conn@12|a|I
-EolcNZ||D6G2;|conn@11|y|O
+EolcNZ|olcZ|D6G2;|conn@11|y|O
 Eolc[load,dec][1:2]||D6G2;|conn@23|y|O
 EselLO[Lf,Lo,Co,Dm,Dl,Li]||D4G2;|conn@5|a|I
 EzooLO||D4G2;|conn@13|a|I

diff --git a/testCode/marina.spi b/testCode/marina.spi
index 1aec23d..f132236 100644 (file)
--- a/testCode/marina.spi
+++ b/testCode/marina.spi
@@ -1,7 +1,7 @@
 *** SPICE deck for cell marina{sch} from library marinaL
 *** Created on Mon Nov 17, 2008 08:47:24
 *** Last revised on Tue Nov 18, 2008 12:17:39
-*** Written on Tue Nov 18, 2008 17:28:19 by Electric VLSI Design System, 
+*** Written on Wed Nov 19, 2008 16:09:17 by Electric VLSI Design System, 
 *version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -1977,7 +1977,7 @@ Xinv@51 od[18] ign[D] inv-X_10
 Xinv@52 od[19] ign[T] inv-X_10
 XmoveE@0 fire[AE] fire[A] ilc[cnt] net@1682 fire[M] ilc[dLO] ilc[i] ilc[zLO] 
 +ilc[zoo] moveE
-Xnand2@3 m1[20] net@860 net@925 nand2-X_10
+Xnand2@3 od[20] net@860 net@925 nand2-X_10
 Xnand2_sy@0 net@1612 net@1335 net@1574 nand2_sy-X_20
 Xnand2n@1 net@877 net@926 net@1334 nand2n-X_10
 Xnor2n@5 fire[A] okLO net@652 nor2n-X_20
@@ -2009,7 +2009,7 @@ XdStates@0 clS[F] clS[T] cl[F] cl[T] fire[M] mc od[15] od[16] od[18] od[19]
 +pred[D] pred[T] rd[F] rd[T] s[1] do[M] torp sin sout succ[D] succ[T] moveD
 XlitStage@0 do[L] fire[L] mc s[1] succ[D] succ[T] litStage
 XmoveC@0 do[M] fire[M] fire[T] ilc[cnt] ilc[dLO] ilc[i] ilc[zLO] ilc[zoo] mc 
-+m1[18] m1[19] m1[20] pred[D] pred[T] succ[D] succ[T] torp moveC
++od[18] od[19] od[20] pred[D] pred[T] succ[D] succ[T] torp moveC
 .ENDS moveLit
 
 *** CELL: redFour:nms2_sy{sch}
@@ -9390,7 +9390,7 @@ Xwire@0 a b wire-C_0_011f-306-R_34_667m
 .SUBCKT skipAll do[L] do[M] fire[ODE] fire[m1] fire[m2] flagOut[A] flagOut[B] 
 +flag[C] ilc[load][F] inLO[7] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
 +in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] kill mc 
-+olcNZ olc[dec][1] olc[dec][2] olc[load][1] olc[load][2] selLO[Co] selLO[Dl] 
++olcZ olc[dec][1] olc[dec][2] olc[load][1] olc[load][2] selLO[Co] selLO[Dl] 
 +selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo] zooLO
 Xarray@0 net@331 flagOut[A] flagOut[B] flag[C] flag[NZ] in[1][F] in[1][T] 
 +in[2][F] in[2][T] in[3][F] in[3][T] in[4][F] in[4][T] in[5][F] in[5][T] 
@@ -9400,7 +9400,8 @@ Xinv@0 m1[F] net@179 inv-X_20
 Xinv@1 fire[m2] net@302 inv-X_80
 Xinv@2 m2[F] net@304 inv-X_40
 Xinv@3 fire[m1] net@308 inv-X_30
-XproposeZ@1 zooLO net@177 inLO[7] kill mc olcNZ olc[dec][F] olc[load][F] 
+Xinv@4 net@110 olcZ inv-X_20
+XproposeZ@1 zooLO net@177 inLO[7] kill mc net@110 olc[dec][F] olc[load][F] 
 +proposeZero
 XskipReg1@0 m2[F] m2[T] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
 +in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[5][F]