fix bug relating to zero-width ports

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index 848f80c..39c9035 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -424,7 +424,7 @@ public class Verilog {
                 return sb.toString();
             }
             public String doReset() {
-                return (forceNoLatch||latchDriver!=null)
+                return (forceNoLatch||latchDriver!=null||width==0)
                     ? name+"_r<=0;"
                     : hasLatch
                     ? (name+"_r<=0; "+("/*NORESET*/".equals(resetBehavior) ? "" : (name+"<=0;")))