== FPGA ==============================================================
- wire [`DATAWIDTH*2-1:0] double;
- assign double = { in_d[`DATAWIDTH-1:0], in_d[`DATAWIDTH-1:0] };
+ reg [(`DATAWIDTH-1):0] out_d;
+ assign out_d_ = out_d;
+
+ reg [5:0] shamt;
+ initial shamt = 0;
+
+ wire shamt_eq;
+ assign shamt_eq = (shamt[5:0] == (inAmount_d[5:0]));
always @(posedge clk) begin
if (!rst) begin
`reset
end else begin
- if (!in_r && in_a) in_a <= 0;
+ if (!in_r && in_a && !inAmount_r) in_a <= 0;
if (!inAmount_r && inAmount_a) inAmount_a <= 0;
- if (out_r && out_a) out_r <= 0;
+ if (out_r && out_a) out_r <= 0;
if (in_r && !in_a && inAmount_r && !inAmount_a && !out_r && !out_a) begin
- in_a <= 1;
- inAmount_a <= 1;
- out_r <= 1;
- out_d <= double >> (`DATAWIDTH - inAmount_d);
+ in_a <= 1;
+ out_d <= in_d;
+ shamt <= 0;
+ end else if (in_a && inAmount_r && !inAmount_a && !out_r && !out_a) begin
+ if (!shamt_eq) begin
+ out_d <= { out_d[`DATAWIDTH-2:0], out_d[`DATAWIDTH-1] };
+ shamt <= shamt+1;
+ end else begin
+ inAmount_a <= 1;
+ out_r <= 1;
+ end
end
end
end