remove macros

diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java
index 5e5c434..9db10b3 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Fpga.java
+++ b/src/edu/berkeley/fleet/fpga/Fpga.java
@@ -201,7 +201,8 @@ public class Fpga extends FleetTwoFleet {
 
             boolean debug = "debug".equals(filename);
 
-            pw.println("`include \"bitfields.v\"");
+            pw.println("`define DATAWIDTH                "+WIDTH_WORD);
+            pw.println("`define CODEBAG_SIZE_BITS        "+CBD_SIZE.valmaskwidth);
             pw.println();
 
             pw.print("`define reset ");

diff --git a/src/edu/berkeley/fleet/fpga/FpgaDock.java b/src/edu/berkeley/fleet/fpga/FpgaDock.java
index 921bf2c..4528202 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/FpgaDock.java
+++ b/src/edu/berkeley/fleet/fpga/FpgaDock.java
@@ -72,7 +72,7 @@ public class FpgaDock extends FleetTwoDock implements FabricElement {
             out.hasLatch = false;
             torpedo.hasLatch = false;
 
-            addPreCrap("assign out        = `packet_data(in);");
+            addPreCrap("assign out        = "+PACKET_DATA.verilogVal("in")+";");
             addPreCrap("assign out_r      = in_r && !("+PACKET_TOKEN.verilogVal("in")+");");
             addPreCrap("assign torpedo_r  = in_r &&   "+PACKET_TOKEN.verilogVal("in")+";");
             addPreCrap("assign in_a       = out_a || torpedo_a;");
@@ -196,12 +196,12 @@ public class FpgaDock extends FleetTwoDock implements FabricElement {
             fanout_module_out0.connect(requeue_ondeck);
             Module.SourcePort ondeck = fanout_module_out1;
 
-            addPreCrap("assign data_latch_output = " + (inbox ? data_out.getName() : "`packet_data("+data_out.getName()+")")+";");
+            addPreCrap("assign data_latch_output = " + (inbox ? data_out.getName() : PACKET_DATA.verilogVal(data_out.getName()))+";");
             addPreCrap("wire ["+(Math.max(ilc.width,olc.width)-1)+":0] decremented;");
             addPreCrap("assign decremented = ("+SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName())+" ? {1'b0, olc} : ilc)-1;");
             addPreCrap("assign "+requeue_olc_in.getName()+" = olc;");
 
-            Assignable data_latch    = new SimpleAssignable(inbox ? data_out.getName() : "`packet_data("+data_out.getName()+")");
+            Assignable data_latch    = new SimpleAssignable(inbox ? data_out.getName() : PACKET_DATA.verilogVal(data_out.getName()));
             String data_latch_input  = inbox ? data_in.getName() : data_in.getName();
 
             String magic_standing_value = "(1<<"+SET_ILC_FROM_IMMEDIATE.valmaskwidth+")";
@@ -301,7 +301,7 @@ public class FpgaDock extends FleetTwoDock implements FabricElement {
                           new ConditionalAction(TI.verilog(ondeck.getName()),    token_in),
                           new ConditionalAction(TO.verilog(ondeck.getName()),    token_out),
                           new ConditionalAction(DC.verilog(ondeck.getName()),   new AssignAction(data_latch, data_latch_input)),
-                          new AssignAction(new SimpleAssignable("`packet_token("+token_out.getName()+")"), "("+TO.verilog(ondeck.getName())+")?1:0"),
+                          new AssignAction(new SimpleAssignable(PACKET_TOKEN.verilogVal(token_out.getName())), "("+TO.verilog(ondeck.getName())+")?1:0"),
                           new ConditionalAction(PATH_DATA.verilog(ondeck.getName()),
                                                 new AssignAction(new SimpleAssignable("{ "+PACKET_SIGNAL.verilogVal(token_out.getName())+", "+
                                                                                       PACKET_DEST.verilogVal(token_out.getName())+" }"),

diff --git a/src/edu/berkeley/fleet/fpga/bram14.v b/src/edu/berkeley/fleet/fpga/bram14.v
index 8a23c0b..cb1496f 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/bram14.v
+++ b/src/edu/berkeley/fleet/fpga/bram14.v
@@ -1,5 +1,5 @@
 `define BRAM_ADDR_WIDTH 14
-`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
+`define BRAM_DATA_WIDTH `DATAWIDTH
 `define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))
 `define BRAM_NAME bram14
 

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index fd4f52a..05a4f33 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -122,17 +122,11 @@ public class Verilog {
 
     public static class Module {
         public void dump(String prefix) throws IOException {
-            PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/bitfields.v")));
+            PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v")));
+            /*
             pw.println("`define DATAWIDTH                "+WIDTH_WORD);
             pw.println("`define CODEBAG_SIZE_BITS        "+CBD_SIZE.valmaskwidth);
-            pw.println("`define INSTRUCTION_WIDTH        "+WIDTH_WORD);
-            pw.println("`define packet_token(p)          "+PACKET_TOKEN.verilogVal("p"));
-            pw.println("`define packet_data(p)           "+PACKET_DATA.verilogVal("p"));
-            pw.println("`define packet_dest(p)           "+PACKET_DEST.verilogVal("p"));
-            pw.println("`define instruction_dest(p)      "+DISPATCH_PATH.verilogVal("p"));
-            pw.flush();
-            pw.close();
-            pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v")));
+            */
             dump(pw, true);
             pw.flush();
             for(InstantiatedModule m : instantiatedModules)
@@ -470,7 +464,6 @@ public class Verilog {
         }
 
         public void dump(PrintWriter pw, boolean fix) {
-            pw.println("`include \"bitfields.v\"");
             pw.println("module "+name+"(clk, rst ");
             for(String name : portorder) {
                 Port p = ports.get(name);