ship_in.hasLatch = true;
}
- Module.Latch ilc = new Latch("ilc", fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1);
- Module.Latch olc = new Latch("olc", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1);
+ Module.Latch ilc = new Latch("ilc", fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1);
+ Module.Latch olc = new Latch("olc", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1);
Module.Latch flag_a = new Latch("flag_a", 1);
Module.Latch flag_b = new Latch("flag_b", 1);
Module.Latch flag_c = new Latch("flag_c", 1);
+ Module.Latch flag_z = new Latch("flag_z", 1);
Module.StateWire torpedoWaiting = new StateWire("torpedoWaiting", false);
"("+
fpga.P_ALWAYS.verilog(ondeck.getName())+
") || ("+
- fpga.P_OLC_ZERO.verilog(ondeck.getName())+"==(olc==0)"+
+ fpga.P_OLC_ZERO.verilog(ondeck.getName())+"==flag_z"+
")"+
") && ("+
" " + fpga.P_A.verilog(ondeck.getName())+" ? flag_a"+
new Object[] {
ondeck,
torpedoWaiting.doDrain(),
- new AssignAction(olc, "0"),
- new AssignAction(ilc, "1")
+ new AssignAction(olc, "0"),
+ new AssignAction(flag_z, "1"),
+ new AssignAction(ilc, "1")
});
// Predicate not met
new AssignAction(olc, fpga.SET_OLC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),
new ConditionalAction(fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName()),
new AssignAction(olc, "olc==0 ? 0 : decremented")),
+
+ new ConditionalAction(fpga.SET_OLC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(flag_z, "0")),
+ new ConditionalAction(fpga.SET_OLC_FROM_IMMEDIATE.verilog(ondeck.getName()), new AssignAction(flag_z, "0")),
+ new ConditionalAction(fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName()), new AssignAction(flag_z, "(olc==0 || olc==1)")),
+
new ConditionalAction(fpga.SET_ILC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(ilc, "data_latch_output")),
new ConditionalAction(fpga.SET_ILC_FROM_IMMEDIATE.verilog(ondeck.getName()),
new AssignAction(ilc, fpga.SET_ILC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),