}
}
- private void testFlagZ(Marina marina) {
- prln("Begin testFlagZ");
+ private void testFlagD(Marina marina) {
+ prln("Begin testFlagD");
adjustIndent(2);
List<BitVector> toks;
}
}
adjustIndent(-2);
- prln("End testFlagZ");
+ prln("End testFlagD");
}
private void testPredicationOnAB(Marina marina) {
List<BitVector> dItems;
- prln("Setting OLC=63");
- setOLC(marina, 63);
+ prln("Setting ILC=1");
+ marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.InnerLoopCounter, 1));
for(boolean flag_a : new boolean[] { false, true }) {
for(boolean flag_b : new boolean[] { false, true }) {
Predicate.NotFlagB,
}) {
- prln("Attempting send data with a="+flag_a+", b="+flag_b+", predicate="+predicate.getClass().getName());
+ prln("Attempting send data with a="+flag_a+", b="+flag_b+", predicate="+predicate);
adjustIndent(2);
- marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.InnerLoopCounter, 1));
marina.instrIn.fill(new Instruction.Move(dock,
predicate, /* predicate */
false, /* torpedoable */
private void walkOneOLC(Marina marina) {
prln("Begin walkOneOLC");
adjustIndent(2);
- for (int i=6; i>=0; i--) {
+ for (int i=5; i>=0; i--) {
int inOlc = 1<<i;
prln("Set inOlc="+inOlc);
marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.OuterLoopCounter, inOlc));
false /* tokenOut */
);
- private static final Instruction REQUEUEING_NOP =
- new Instruction.Move(dock,
- Predicate.IgnoreFlagD, /* predicate */
- false, /* torpedoable */
- null, /* path */
- false, /* tokenIn */
- false, /* dataIn */
- false, /* latchData */
- false, /* latchPath */
- false, /* dataOut */
- false /* tokenOut */
- );
+ private static final Instruction REQUEUEING_NOP = NOP;
private static final Instruction SEND_DATA =
new Instruction.Move(dock,
false /* tokenOut */
);
- private static final Instruction REQUEUEING_SEND_DATA =
- new Instruction.Move(dock,
- Predicate.IgnoreFlagD, /* predicate */
- false, /* torpedoable */
- null_path, /* path */
- false, /* tokenIn */
- false, /* dataIn */
- false, /* latchData */
- false, /* latchPath */
- true, /* dataOut */
- false /* tokenOut */
- );
+ private static final Instruction REQUEUEING_SEND_DATA = SEND_DATA;
private void testRequeueStage0(Marina marina) {
prln("Begin testRequeueStage0");
prln("inserting instruction: Set OLC=63");
setOLC(marina, 63);
- prln("inserting instruction: [Rq] Nop; this will cause 0->1 transition and possibly be discarded");
- marina.instrIn.fill(REQUEUEING_NOP);
-
- // just in case there is some capacity between the execution
- // stage and the requeue stage, we stick in a whole bunch of
- // NOPs.
- for(int i=0; i<4; i++) {
- prln("inserting instruction: [Rq] Nop; this (and subsequent instructions) should not execute until Tail is inserted");
- marina.instrIn.fill(REQUEUEING_NOP);
- }
+ prln("inserting instruction: head");
+ marina.instrIn.fill(new Instruction.Head(dock));
prln("inserting instruction: [Rq] Set ILC=1");
marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.InnerLoopCounter,1));
prln("inserting instruction: [Rq] Send Data");
- marina.instrIn.fill(REQUEUEING_SEND_DATA);
+ marina.instrIn.fill(SEND_DATA);
dataItems = marina.data.drainMany(1);
fatal(dataItems.size()!=0, "Expected exactly no data items to emerge but got at least: "+dataItems.size());
- adjustIndent(-2);
- prln("End testWaitForTail");
- }
-
- // This test case will FAIL if the requeue stage behaves as
- // described in IES50. If we determine that the behavior
- // described there is actually desirable, then this test should be
- // modified.
- private void testRequeueStageDrop(Marina marina) {
- List<BitVector> dataItems;
-
- prln("Begin testRequeueStageDrop");
- adjustIndent(2);
-
- // We have decided that this issue will not be fixed in
- // Marina. Therefore, the test is commented out.
-
- /*
- prln("inserting instruction: Set OLC=63");
- setOLC(marina, 63);
-
- prln("inserting instruction: Set ILC=1");
- marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.InnerLoopCounter,1));
-
- // if you uncomment this, then the NOP will be dropped and the test will pass
- //prln("inserting instruction: [Rq] Nop; this will cause 0->1 transition and possibly be discarded");
- //marina.instrIn.fill(REQUEUEING_NOP);
-
- prln("inserting instruction: [Rq] Send Data; this will cause 0->1 transition and be discarded");
- marina.instrIn.fill(REQUEUEING_SEND_DATA);
-
- prln("inserting instruction: [Rq] Set ILC=1");
- marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.InnerLoopCounter,1));
-
- prln("inserting instruction: Tail");
- marina.instrIn.fill(new Instruction.Tail(dock));
+ prln("inserting instruction: head");
+ marina.instrIn.fill(new Instruction.Tail(dock));
- dataItems = marina.data.drainMany(3);
- fatal(dataItems.size()<3, "Expected exactly unlimited data items to emerge but got only: "+dataItems.size());
- */
+ BitVector bv = marina.data.drain();
+ fatal(bv==null, "Expected at least one data item to emerge but got none");
adjustIndent(-2);
- prln("End testRequeueStageDrop");
+ prln("End testWaitForTail");
}
-
private void testFlagAB(Marina marina) {
prln("Begin testFlagAB");
adjustIndent(2);
adjustIndent(2);
// walk a bit from 0 to 5
- for(int bit=0; bit<6; bit++) {
+ for(int bit=5; bit>=0; bit--) {
prln("inserting data item in north fifo ring");
BitVector data = new BitVector(37, "empty");
BitVector addr = new BitVector(14, "empty");
marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.InnerLoopCounter,1));
marina.instrIn.fill(RECV_DATA);
marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.InnerLoopCounter,SetSource.DataLatch));
+ model.waitNS(CYCLE_TIME_NS * 64);
int ilc = marina.getILC().getCount();
fatal(ilc != (1<<bit), "expected ilc to be " + (1<<bit) + ", but got " + ilc);
fatal(dataItems.size()!=1, "Expected one data item to emerge but got: "+dataItems.size()+" data items");
MarinaPacket mp = new MarinaPacket(dataItems.get(0));
- fatalIfBitVectorsDoNotMatch(packet_data.get(26,11), mp.path.get(0,11));
+ fatalIfBitVectorsDoNotMatch(packet_data.get(25,11), mp.path.get(0,11));
}
adjustIndent(-2);
getCtrsFlags(marina);
- // Note: It's tempting to test that OLC==0 here. However, hardware doesn't
- // actually set counter bits to zero; it just sets the OLCZERO bit
-
prln("A and B should remain false");
fatal(marina.getFlagA(), "bad A flag: true");
fatal(marina.getFlagB(), "bad B flag: true");
prln("Verify OLC count using scan chain");
int outOlc = marina.getOLC();
fatal(outOlc!=notZero, "bad OLC count: "+outOlc+" expected: "+notZero);
-
- prln("Verify OLC zero bit using predication");
- prln("if (OLC==0) {A=1; B=1;} // should not get executed");
- marina.instrIn.fill(new
- Instruction.Set(dock,Predicate.FlagD, SET_FLAG, SET_FLAG));
- fatal(marina.getFlagA(), "bad A flag. expected: false");
-
+
prln("Set OLC="+notZero);
marina.instrIn.fill(new
Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.OuterLoopCounter, notZero));
prln("Verify OLC count using scan chain");
outOlc = marina.getOLC();
fatal(outOlc!=0, "bad OLC count: "+outOlc+" expected: 0");
-
- prln("Verify OLC zero bit using predication");
- prln("if (OLC!=0) {A=1; B=1;} // should not get executed");
- marina.instrIn.fill(new
- Instruction.Set(dock,Predicate.Default, SET_FLAG, SET_FLAG));
- fatal(marina.getFlagA(), "bad A flag. expected: false");
}
adjustIndent(-2);
doOneTest(1);
doOneTest(2);
doOneTest(4);
+ doOneTest(5);
doOneTest(1001);
doOneTest(3000);
doOneTest(3001);
- doOneTest(3006);
+ doOneTest(3009);
+ doOneTest(3010);
doOneTest(3011);
+ doOneTest(3012);
doOneTest(3013);
doOneTest(3014);
doOneTest(3015);
- doOneTest(3018);
// these tests take a while and usually pass
doOneTest(1000);
doOneTest(1004);
+ doOneTest(1005);
doOneTest(1006);
+ doOneTest(3002);
+ doOneTest(3016);
+ doOneTest(3021);
doOneTest(3024);
break;
case 2: sendInstructions(marina); break; // passes, 24-Mar (+verilog)
case 4: getCtrsFlags(marina); break; // 20-Apr (+verilog)
- case 5: walkOneOLC(marina); break;
+ case 5: walkOneOLC(marina); break; // 21-Apr (+verilog)
// Russell's tests begin with 1000
case 1000: walkOneILC(marina); break; // 20-Apr (+verilog)
case 1003: sendTorpedo(marina); break;
case 1004: flipIlcBit(marina); break; // 20-Apr (+verilog)
- case 1005: flipOlcBit(marina); break;
+ case 1005: flipOlcBit(marina); break; // 21-Apr (+verilog)
case 1006: testSouthRecirculate(marina); break; // passes, 24-Mar (+verilog)
// Adam's tests begin with 3000
case 3000: sendToken(marina); break; // passes, 24-Mar (+verilog)
case 3001: testFlagAB(marina); break; // passes, 08-Apr (+verilog)
- case 3002: testRequeueStage0(marina); break;
- case 3003: testRequeueStage0to1(marina); break;
- case 3004: testFlagZ(marina); break;
- case 3005: testPredicationOnAB(marina); break;
- case 3006: sendData(marina); break; // passes, 24-Mar (+verilog)
+ case 3002: testPredicationOnAB(marina); break; // 22-Apr (+verilog)
+ case 3003: testFlagC(marina); break;
+ case 3004: testFlagD(marina); break;
+
+ case 3005: testRequeueStage0(marina); break;
+ case 3006: testRequeueStage0to1(marina); break;
case 3007: testRequeueStage0to1to3to0(marina); break;
- case 3008: testWaitForTail(marina); break;
- case 3009: testRequeueStageDrop(marina); break;
- case 3010: testRequeueStage0to2to3to0(marina); break;
+ case 3008: testRequeueStage0to2to3to0(marina); break;
+ case 3009: testWaitForTail(marina); break; // 22-Apr (+verilog)
+
+ //case 3010: testRequeueStageDrop(marina); break; // no longer relevant (behavior changed)
+
+ case 3010: sendData(marina); break; // passes, 24-Mar (+verilog)
case 3011: recvData(marina); break; // 21-Apr (+verilog)
- case 3012: testFlagC(marina); break;
+ case 3012: sendDataWithPath(marina); break; // passes, 13-Apr (+verilog)
+
case 3013: testSignExtendedLiteral(marina); break; // 20-Apr (+verilog)
case 3014: testShiftedLiteral(marina); break; // 20-Apr (+verilog)
case 3015: testSendAndRecvToken(marina); break; // 21-Apr (+verilog)
- case 3016: sendDataIlcInfinite(marina); break;
+
+ case 3016: sendDataIlcInfinite(marina); break; // 22-Apr (+verilog)
case 3017: testFlagTruthTable(marina); break;
- case 3018: sendDataWithPath(marina); break; // passes, 13-Apr (+verilog)
+
case 3019: setOlcFromDataLatch(marina); break;
case 3020: setIlcFromDataLatch(marina); break;
- case 3021: recvPath(marina); break;
+ case 3021: recvPath(marina); break; // 22-Apr (+verilog)
case 3022: testILC(marina); break;
case 3023: testTorpedoOnAnInfiniteNop(marina); break;
case 3024: testRecvAndSendWalkingOne(marina); break; // 21-Apr (+verilog)
projects / fleet.git / commitdiff