public Module.InstantiatedModule getInstance() { return instance; }
+ private Fpga fpga;
+
public Destination getDataDestination() { return dataDestination; }
public Destination getInstructionDestination() { return instructionDestination; }
public int getInstructionFifoSize() { return INSTRUCTION_FIFO_SIZE; }
FpgaDock(FpgaShip ship, DockDescription bbd) {
super(ship, bbd);
+ this.fpga = (Fpga)ship.getFleet();
this.instance = new Module.InstantiatedModule(((Fpga)ship.getFleet()).top, new DockModule(isInputDock()));
this.dataDestination = new FpgaDestination(this, this.instance.getInputPort("fabric_in"), false);
this.instructionDestination = new FpgaDestination(this, this.instance.getInputPort("instruction"), true);
instance.getOutputPort("fabric_out").connect((Module.SinkPort)outPort);
}
- public static class TorpedoBranchModule extends Module {
+ public class TorpedoBranchModule extends Module {
public TorpedoBranchModule() {
super("torpedobranch");
- Module.SourcePort in = createInputPort ("in", WIDTH_PACKET);
+ Module.SourcePort in = createInputPort ("in", fpga.WIDTH_PACKET);
// FIXME: assumes DISPATCH_PATH is at top of word!!!
- Module.SinkPort out = createOutputPort("out", WIDTH_WORD-DISPATCH_PATH.valmaskwidth, "");
+ Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth, "");
Module.SinkPort torpedo = createOutputPort("torpedo", 0, "");
in.hasLatch = false;
out.hasLatch = false;
torpedo.hasLatch = false;
- addPreCrap("assign out = "+PACKET_DATA.verilogVal("in")+";");
- addPreCrap("assign out_r = in_r && !("+PACKET_TOKEN.verilogVal("in")+");");
- addPreCrap("assign torpedo_r = in_r && "+PACKET_TOKEN.verilogVal("in")+";");
+ addPreCrap("assign out = "+fpga.PACKET_DATA.verilogVal("in")+";");
+ addPreCrap("assign out_r = in_r && !("+fpga.PACKET_TOKEN.verilogVal("in")+");");
+ addPreCrap("assign torpedo_r = in_r && "+fpga.PACKET_TOKEN.verilogVal("in")+";");
addPreCrap("assign in_a = out_a || torpedo_a;");
}
}
- public static class RequeueModule extends Module {
+ public class RequeueModule extends Module {
public RequeueModule() {
super("requeue");
- Module.SourcePort fabric_in = createInputPort ("fabric_in", WIDTH_WORD-DISPATCH_PATH.valmaskwidth);
- Module.SourcePort ondeck_in = createInputPort ("ondeck_in", WIDTH_WORD-DISPATCH_PATH.valmaskwidth);
- Module.SourcePort olc_in = createInputPort ("olc_in", SET_OLC_FROM_IMMEDIATE.valmaskwidth);
- Module.SinkPort out = createOutputPort("out", WIDTH_WORD-DISPATCH_PATH.valmaskwidth, "");
+ Module.SourcePort fabric_in = createInputPort ("fabric_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ Module.SourcePort ondeck_in = createInputPort ("ondeck_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ Module.SourcePort olc_in = createInputPort ("olc_in", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth);
+ Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth, "");
out.forceNoLatch = true;
Module.StateWire using = new StateWire("using", false);
addPreCrap("assign out = "+circulating.isEmpty()+" ? "+fabric_in.getName()+" : "+ondeck_in.getName()+";");
// always: discard one-shot instructions
- new Event(new Object[] { ondeck_in, /*olc_in,*/ OS.verilog(ondeck_in.getName()) },
+ new Event(new Object[] { ondeck_in, /*olc_in,*/ fpga.OS.verilog(ondeck_in.getName()) },
new Action[] { ondeck_in, /*olc_in */});
new Event(new Object[] { doResetFabric.isFull(), out },
new Event(new Object[] { doResetOndeck.isFull(), out },
new Action[] { doResetOndeck.doDrain(), ondeck_in });
- new Event(new Object[] { circulating.isEmpty(), fabric_in, TAIL.verilog(fabric_in.getName()) },
+ new Event(new Object[] { circulating.isEmpty(), fabric_in, fpga.TAIL.verilog(fabric_in.getName()) },
new Action[] { circulating.doFill(), fabric_in });
- new Event(new Object[] { circulating.isEmpty(), fabric_in, "!("+TAIL.verilog(fabric_in.getName())+")", doResetFabric.isEmpty() },
+ new Event(new Object[] { circulating.isEmpty(), fabric_in, "!("+fpga.TAIL.verilog(fabric_in.getName())+")", doResetFabric.isEmpty() },
new Action[] { out, doResetFabric.doFill() });
- new Event(new Object[] { using.isEmpty(), ondeck_in, /*olc_in,*/ "!("+OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
+ new Event(new Object[] { using.isEmpty(), ondeck_in, /*olc_in,*/ "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
new Action[] { ondeck_in, /*olc_in */ });
- new Event(new Object[] { using.isEmpty(), ondeck_in, /*olc_in,*/ "!("+OS.verilog(ondeck_in.getName())+")", "olc_in!=0" },
+ new Event(new Object[] { using.isEmpty(), ondeck_in, /*olc_in,*/ "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in!=0" },
new Action[] { using.doFill() });
- new Event(new Object[] { circulating.isFull(), using.isFull(), ondeck_in, /*olc_in,*/ "!("+OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
+ new Event(new Object[] { circulating.isFull(), using.isFull(), ondeck_in, /*olc_in,*/ "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
new Action[] { circulating.doDrain(), using.doDrain(), ondeck_in, /*olc_in */});
- new Event(new Object[] { circulating.isFull(), using.isFull(), ondeck_in, /*olc_in,*/ "!("+OS.verilog(ondeck_in.getName())+")", "olc_in!=0", doResetOndeck.isEmpty() },
+ new Event(new Object[] { circulating.isFull(), using.isFull(), ondeck_in, /*olc_in,*/ "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in!=0", doResetOndeck.isEmpty() },
new Action[] { out, /*olc_in,*/ doResetOndeck.doFill() });
}
}
- public static class DockModule extends Module {
+ public class DockModule extends Module {
public DockModule(boolean inbox) {
super(inbox ? "inbox" : "outbox");
- int dfifo_width = inbox ? WIDTH_WORD+1 : 1;
+ int dfifo_width = inbox ? fpga.getWordWidth()+1 : 1;
- // FIXME: assumes DISPATCH_PATH is at top of word!!!
- Module ififo_m = new FifoModule(INSTRUCTION_FIFO_SIZE, WIDTH_WORD-DISPATCH_PATH.valmaskwidth);
+ // FIXME: assumes fpga.DISPATCH_PATH is at top of word!!!
+ Module ififo_m = new FifoModule(INSTRUCTION_FIFO_SIZE, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
Module dfifo_m = new FifoModule(DATA_FIFO_SIZE, dfifo_width);
- Module.SourcePort instruction = createInputPort("instruction", WIDTH_PACKET);
- Module.SourcePort fabric_in = createInputPort("fabric_in", WIDTH_PACKET);
+ Module.SourcePort instruction = createInputPort("instruction", fpga.WIDTH_PACKET);
+ Module.SourcePort fabric_in = createInputPort("fabric_in", fpga.WIDTH_PACKET);
// FIXME: at inboxes, no need for a full set of latches
- Module.SinkPort fabric_out = createOutputPort("fabric_out", WIDTH_PACKET, "");
+ Module.SinkPort fabric_out = createOutputPort("fabric_out", fpga.WIDTH_PACKET, "");
Module.InstantiatedModule dfifo = new Module.InstantiatedModule(this, dfifo_m);
addPreCrap("assign fabric_in_a = "+dfifo.getInputPort("in").getName()+"_a;\n");
if (inbox)
addPreCrap("assign "+dfifo.getInputPort("in").getName()+
- " = { "+PACKET_SIGNAL.verilogVal("fabric_in")+
- ", "+PACKET_DATA.verilogVal("fabric_in")+" };\n");
+ " = { "+fpga.PACKET_SIGNAL.verilogVal("fabric_in")+
+ ", "+fpga.PACKET_DATA.verilogVal("fabric_in")+" };\n");
else
addPreCrap("assign "+dfifo.getInputPort("in").getName()+
- " = "+PACKET_SIGNAL.verilogVal("fabric_in")+";\n");
+ " = "+fpga.PACKET_SIGNAL.verilogVal("fabric_in")+";\n");
Module.SourcePort dfifo_out = dfifo.getOutputPort("out");
Module.SourcePort ship_out = null;
if (!inbox) {
- ship_out = createInputPort("ship", WIDTH_WORD+1);
+ ship_out = createInputPort("ship", fpga.getWordWidth()+1);
ship_out.hasLatch = true;
}
Module.SinkPort ship_in = null;
if (inbox) {
- ship_in = createOutputPort("ship", WIDTH_WORD+1, "");
+ ship_in = createOutputPort("ship", fpga.getWordWidth()+1, "");
ship_in.hasLatch = true;
}
- Module.Latch ilc = new Latch("ilc", SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1);
- Module.Latch olc = new Latch("olc", SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1);
+ Module.Latch ilc = new Latch("ilc", fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1);
+ Module.Latch olc = new Latch("olc", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1);
Module.Latch flag_a = new Latch("flag_a", 1);
Module.Latch flag_b = new Latch("flag_b", 1);
Module.Latch flag_c = new Latch("flag_c", 1);
Module.SinkPort ififo_in = ififo.getInputPort("in");
Module.SourcePort ififo_out = ififo.getOutputPort("out");
- Module.SinkPort data_latch_output_p = createWirePort("data_latch_output", inbox ? WIDTH_WORD+1 : WIDTH_WORD);
+ Module.SinkPort data_latch_output_p = createWirePort("data_latch_output", inbox ? fpga.getWordWidth()+1 : fpga.getWordWidth());
Module.InstantiatedModule torpedo_branch = new Module.InstantiatedModule(this, new TorpedoBranchModule());
instruction.connect(torpedo_branch.getInputPort("in"));
Module.SourcePort efifo_out = torpedo_branch.getOutputPort("out");
Module.SourcePort torpedo_branch_torpedo = torpedo_branch.getOutputPort("torpedo");
- Module.InstantiatedModule fanout_module = new Module.InstantiatedModule(this, new FanoutModule(WIDTH_WORD-DISPATCH_PATH.valmaskwidth));
+ Module.InstantiatedModule fanout_module = new Module.InstantiatedModule(this, new FanoutModule(fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth));
Module.SinkPort fanout_module_in = fanout_module.getInputPort("in");
Module.SourcePort fanout_module_out0 = fanout_module.getOutputPort("out0");
Module.SourcePort fanout_module_out1 = fanout_module.getOutputPort("out1");
fanout_module_out0.connect(requeue_ondeck);
Module.SourcePort ondeck = fanout_module_out1;
- addPreCrap("assign data_latch_output = " + (inbox ? data_out.getName() : PACKET_DATA.verilogVal(data_out.getName()))+";");
+ addPreCrap("assign data_latch_output = " + (inbox ? data_out.getName() : fpga.PACKET_DATA.verilogVal(data_out.getName()))+";");
addPreCrap("wire ["+(Math.max(ilc.width,olc.width)-1)+":0] decremented;");
- addPreCrap("assign decremented = ("+SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName())+" ? {1'b0, olc} : ilc)-1;");
+ addPreCrap("assign decremented = ("+fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName())+" ? {1'b0, olc} : ilc)-1;");
addPreCrap("assign "+requeue_olc_in.getName()+" = olc;");
- Assignable data_latch = new SimpleAssignable(inbox ? data_out.getName() : PACKET_DATA.verilogVal(data_out.getName()));
+ Assignable data_latch = new SimpleAssignable(inbox ? data_out.getName() : fpga.PACKET_DATA.verilogVal(data_out.getName()));
String data_latch_input = inbox ? data_in.getName() : data_in.getName();
- String magic_standing_value = "(1<<"+SET_ILC_FROM_IMMEDIATE.valmaskwidth+")";
- String done_executing = "(ilc==0 || ilc==1 || !"+MOVE.verilog(ondeck.getName())+")";
+ String magic_standing_value = "(1<<"+fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+")";
+ String done_executing = "(ilc==0 || ilc==1 || !"+fpga.MOVE.verilog(ondeck.getName())+")";
// Torpedo Arrival
new Event(new Object[] { torpedo_branch_torpedo, torpedoWaiting.isEmpty() },
String predicate_met =
"("+
"("+
- "!"+MOVE.verilog(ondeck.getName())+" || ilc!=0"+
+ "!"+fpga.MOVE.verilog(ondeck.getName())+" || ilc!=0"+
") && ("+
"("+
- P_ALWAYS.verilog(ondeck.getName())+
+ fpga.P_ALWAYS.verilog(ondeck.getName())+
") || ("+
- P_OLC_ZERO.verilog(ondeck.getName())+"==(olc==0)"+
+ fpga.P_OLC_ZERO.verilog(ondeck.getName())+"==(olc==0)"+
")"+
") && ("+
- " " + P_A.verilog(ondeck.getName())+" ? flag_a"+
- ":" + P_B.verilog(ondeck.getName())+" ? flag_b"+
- ":" + P_NOT_A.verilog(ondeck.getName())+" ? !flag_a"+
- ":" + P_NOT_B.verilog(ondeck.getName())+" ? !flag_b "+
+ " " + fpga.P_A.verilog(ondeck.getName())+" ? flag_a"+
+ ":" + fpga.P_B.verilog(ondeck.getName())+" ? flag_b"+
+ ":" + fpga.P_NOT_A.verilog(ondeck.getName())+" ? !flag_a"+
+ ":" + fpga.P_NOT_B.verilog(ondeck.getName())+" ? !flag_b "+
": 1"+
")"+
")";
data_out,
token_out,
predicate_met,
- MOVE.verilog(ondeck.getName()),
- I.verilog(ondeck.getName()),
+ fpga.MOVE.verilog(ondeck.getName()),
+ fpga.I.verilog(ondeck.getName()),
torpedoWaiting.isFull()
},
new Object[] {
// Predicate not met
new Event(new Object[] { ondeck, "!("+predicate_met+")" },
new Action[] { ondeck,
- new ConditionalAction(MOVE.verilog(ondeck.getName()), new AssignAction(ilc, "1"))
+ new ConditionalAction(fpga.MOVE.verilog(ondeck.getName()), new AssignAction(ilc, "1"))
});
new Event(new Object[] { ondeck,
data_out,
token_out,
predicate_met,
- "(!"+MOVE.verilog(ondeck.getName())+" || !"+I.verilog(ondeck.getName())+" || !"+torpedoWaiting.isFull()+")",
- new ConditionalTrigger(DI.verilog(ondeck.getName()), data_in),
- new ConditionalTrigger(TI.verilog(ondeck.getName()), token_in)
+ "(!"+fpga.MOVE.verilog(ondeck.getName())+" || !"+fpga.I.verilog(ondeck.getName())+" || !"+torpedoWaiting.isFull()+")",
+ new ConditionalTrigger(fpga.DI.verilog(ondeck.getName()), data_in),
+ new ConditionalTrigger(fpga.TI.verilog(ondeck.getName()), token_in)
},
new Action[] {
- new ConditionalAction(done_executing+" && "+MOVE.verilog(ondeck.getName()), new AssignAction(ilc, "1")),
+ new ConditionalAction(done_executing+" && "+fpga.MOVE.verilog(ondeck.getName()), new AssignAction(ilc, "1")),
new ConditionalAction(done_executing, ondeck),
new ConditionalAction("!"+done_executing,
new AssignAction(ilc,
"ilc=="+magic_standing_value+"?"+magic_standing_value+":decremented")),
- new ConditionalAction(SET_OLC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(olc, "data_latch_output")),
- new ConditionalAction(SET_OLC_FROM_IMMEDIATE.verilog(ondeck.getName()),
- new AssignAction(olc, SET_OLC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),
- new ConditionalAction(SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName()),
+ new ConditionalAction(fpga.SET_OLC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(olc, "data_latch_output")),
+ new ConditionalAction(fpga.SET_OLC_FROM_IMMEDIATE.verilog(ondeck.getName()),
+ new AssignAction(olc, fpga.SET_OLC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),
+ new ConditionalAction(fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName()),
new AssignAction(olc, "olc==0 ? 0 : decremented")),
- new ConditionalAction(SET_ILC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(ilc, "data_latch_output")),
- new ConditionalAction(SET_ILC_FROM_IMMEDIATE.verilog(ondeck.getName()),
- new AssignAction(ilc, SET_ILC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),
- new ConditionalAction(SET_ILC_FROM_INFINITY.verilog(ondeck.getName()), new AssignAction(ilc, magic_standing_value)),
- new ConditionalAction(SHIFT.verilog(ondeck.getName()),
+ new ConditionalAction(fpga.SET_ILC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(ilc, "data_latch_output")),
+ new ConditionalAction(fpga.SET_ILC_FROM_IMMEDIATE.verilog(ondeck.getName()),
+ new AssignAction(ilc, fpga.SET_ILC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),
+ new ConditionalAction(fpga.SET_ILC_FROM_INFINITY.verilog(ondeck.getName()), new AssignAction(ilc, magic_standing_value)),
+ new ConditionalAction(fpga.SHIFT.verilog(ondeck.getName()),
new AssignAction(data_latch,
- "{ data_latch_output["+(WIDTH_WORD-1-SHIFT.valmaskwidth)+":0], "+
- SHIFT.verilogVal(ondeck.getName())+"}")),
- new ConditionalAction(SET_IMMEDIATE.verilog(ondeck.getName()),
+ "{ data_latch_output["+(fpga.getWordWidth()-1-fpga.SHIFT.valmaskwidth)+":0], "+
+ fpga.SHIFT.verilogVal(ondeck.getName())+"}")),
+ new ConditionalAction(fpga.SET_IMMEDIATE.verilog(ondeck.getName()),
new AssignAction(data_latch,
- "{ {"+(WIDTH_WORD-FleetTwoFleet.DataLatch_WIDTH)+
- "{"+SET_IMMEDIATE_EXTEND.verilogVal(ondeck.getName())+"}}, "+
- SET_IMMEDIATE.verilogVal(ondeck.getName())+" }")),
- new ConditionalAction(SET_FLAGS.verilog(ondeck.getName()), new AssignAction(flag_a, new_flag(SET_FLAGS_A.verilogVal(ondeck.getName())))),
- new ConditionalAction(SET_FLAGS.verilog(ondeck.getName()), new AssignAction(flag_b, new_flag(SET_FLAGS_B.verilogVal(ondeck.getName())))),
+ "{ {"+(fpga.getWordWidth()-fpga.DataLatch_WIDTH)+
+ "{"+fpga.SET_IMMEDIATE_EXTEND.verilogVal(ondeck.getName())+"}}, "+
+ fpga.SET_IMMEDIATE.verilogVal(ondeck.getName())+" }")),
+ new ConditionalAction(fpga.SET_FLAGS.verilog(ondeck.getName()), new AssignAction(flag_a, new_flag(fpga.SET_FLAGS_A.verilogVal(ondeck.getName())))),
+ new ConditionalAction(fpga.SET_FLAGS.verilog(ondeck.getName()), new AssignAction(flag_b, new_flag(fpga.SET_FLAGS_B.verilogVal(ondeck.getName())))),
new ConditionalAction(inbox
- ? "("+DI.verilog(ondeck.getName())+" || "+TI.verilog(ondeck.getName())+")"
- : "(!"+DI.verilog(ondeck.getName())+" && "+TI.verilog(ondeck.getName())+")",
+ ? "("+fpga.DI.verilog(ondeck.getName())+" || "+fpga.TI.verilog(ondeck.getName())+")"
+ : "(!"+fpga.DI.verilog(ondeck.getName())+" && "+fpga.TI.verilog(ondeck.getName())+")",
new AssignAction(flag_c, dfifo_out.getBits(dfifo_width-1, dfifo_width-1))),
- new ConditionalAction(DI.verilog(ondeck.getName()), data_in),
- new ConditionalAction(DO.verilog(ondeck.getName()), data_out),
- new ConditionalAction(FLUSH.verilog(ondeck.getName()), data_out),
+ new ConditionalAction(fpga.DI.verilog(ondeck.getName()), data_in),
+ new ConditionalAction(fpga.DO.verilog(ondeck.getName()), data_out),
+ new ConditionalAction(fpga.FLUSH.verilog(ondeck.getName()), data_out),
inbox
- ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+WIDTH_WORD+"]"), FLUSH.verilog(ondeck.getName())+"?1:0")
- : new ConditionalAction(DI.verilog(ondeck.getName()), new AssignAction(flag_c, data_latch_input+"["+WIDTH_WORD+"]")),
- new ConditionalAction(TI.verilog(ondeck.getName()), token_in),
- new ConditionalAction(TO.verilog(ondeck.getName()), token_out),
- new ConditionalAction(DC.verilog(ondeck.getName()), new AssignAction(data_latch, data_latch_input)),
- new AssignAction(new SimpleAssignable(PACKET_TOKEN.verilogVal(token_out.getName())), "("+TO.verilog(ondeck.getName())+")?1:0"),
- new ConditionalAction(PATH_DATA.verilog(ondeck.getName()),
- new AssignAction(new SimpleAssignable("{ "+PACKET_SIGNAL.verilogVal(token_out.getName())+", "+
- PACKET_DEST.verilogVal(token_out.getName())+" }"),
- DISPATCH_PATH.verilogVal(data_latch_input))),
- new ConditionalAction(PATH_IMMEDIATE.verilog(ondeck.getName()),
- new AssignAction(new SimpleAssignable("{ "+PACKET_SIGNAL.verilogVal(token_out.getName())+", "+
- PACKET_DEST.verilogVal(token_out.getName())+" }"),
- PATH_IMMEDIATE.verilogVal(ondeck.getName()))),
+ ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+fpga.getWordWidth()+"]"), fpga.FLUSH.verilog(ondeck.getName())+"?1:0")
+ : new ConditionalAction(fpga.DI.verilog(ondeck.getName()), new AssignAction(flag_c, data_latch_input+"["+fpga.getWordWidth()+"]")),
+ new ConditionalAction(fpga.TI.verilog(ondeck.getName()), token_in),
+ new ConditionalAction(fpga.TO.verilog(ondeck.getName()), token_out),
+ new ConditionalAction(fpga.DC.verilog(ondeck.getName()), new AssignAction(data_latch, data_latch_input)),
+ new AssignAction(new SimpleAssignable(fpga.PACKET_TOKEN.verilogVal(token_out.getName())), "("+fpga.TO.verilog(ondeck.getName())+")?1:0"),
+ new ConditionalAction(fpga.PATH_DATA.verilog(ondeck.getName()),
+ new AssignAction(new SimpleAssignable("{ "+fpga.PACKET_SIGNAL.verilogVal(token_out.getName())+", "+
+ fpga.PACKET_DEST.verilogVal(token_out.getName())+" }"),
+ fpga.DISPATCH_PATH.verilogVal(data_latch_input))),
+ new ConditionalAction(fpga.PATH_IMMEDIATE.verilog(ondeck.getName()),
+ new AssignAction(new SimpleAssignable("{ "+fpga.PACKET_SIGNAL.verilogVal(token_out.getName())+", "+
+ fpga.PACKET_DEST.verilogVal(token_out.getName())+" }"),
+ fpga.PATH_IMMEDIATE.verilogVal(ondeck.getName()))),
}
);
}
- private static String new_flag(String x) {
+ private String new_flag(String x) {
return "("+
"( (("+x+" >> 0) & 1) & !flag_c) |" +
"( (("+x+" >> 1) & 1) & flag_c) |" +
projects / fleet.git / commitdiff