*** SPICE deck for cell marinaOut{sch} from library aMarinaM
*** Created on Mon Nov 17, 2008 08:47:24
*** Last revised on Mon Mar 30, 2009 06:59:15
-*** Written on Tue Apr 28, 2009 10:46:28 by Electric VLSI Design System,
+*** Written on Thu Apr 30, 2009 17:07:37 by Electric VLSI Design System,
*version 8.08k
*** Layout tech: cmos90, foundry TSMC
*** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
Xwire@0 a b wire-C_0_011f-698_4-R_34_667m
.ENDS wire90-698_4-layer_1-width_3
-*** CELL: driversL:dataDriver60{sch}
+*** CELL: driversM:dataDriver60{sch}
.SUBCKT dataDriver60 inA inB out
Xinv@0 net@8 out inv-X_60
Xnand2@1 inA inB net@7 nand2-X_20
Xwire@0 a b wire-C_0_011f-243_6-R_34_667m
.ENDS wire90-243_6-layer_1-width_3
-*** CELL: driversJ:predDri60wMC{sch}
-.SUBCKT driversJ__predDri60wMC in mc pred
+*** CELL: driversM:predDri60wMC{sch}
+.SUBCKT predDri60wMC in mc pred
XNMOSx@0 pred in gnd NMOSx-X_60
XNMOSx@1 pred mc gnd NMOSx-X_10
Xinv@0 pred net@145 inv-X_10
Xpms3@0 pred mc in net@174 pms3-X_3_333
Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3
-.ENDS driversJ__predDri60wMC
+.ENDS predDri60wMC
*** CELL: orangeTSMC090nm:NMOSx{sch}
.SUBCKT NMOSx-X_16 d g s
Xwire@0 a b wire-C_0_011f-124_7-R_34_667m
.ENDS wire90-124_7-layer_1-width_3
-*** CELL: driversL:sucANDdri60{sch}
+*** CELL: driversM:sucANDdri60{sch}
.SUBCKT sucANDdri60 inA inB succ
XPMOSx@0 succ net@51 vdd PMOSx-X_60
Xinv@0 succ net@71 inv-X_5
Xinv@5 silent net@463 inv-X_10
XinvI@0 net@357 net@409 inv-X_10
XinvI@1 net@475 s[1] inv-X_10
-XpredDri6@0 fire clear pred driversJ__predDri60wMC
+XpredDri6@1 fire clear pred predDri60wMC
XsucANDdr@4 net@499 fire succ sucANDdri60
Xtc[1] tranCap
Xtc[2] tranCap
Xwire@0 a b wire-C_0_011f-544_2-R_34_667m
.ENDS wire90-544_2-layer_1-width_3
-*** CELL: driversJ:latchDriver60{sch}
+*** CELL: driversM:latchDriver60{sch}
.SUBCKT latchDriver60 in out
Xinv@1 in net@16 inv-X_20
XinvI@2 net@17 out inv-X_60
Xwire90@0 net@16 net@17 wire90-544_2-layer_1-width_3
.ENDS latchDriver60
-*** CELL: driversL:predDri60wMC{sch}
-.SUBCKT driversL__predDri60wMC in mc pred
-XNMOSx@0 pred in gnd NMOSx-X_60
-XNMOSx@1 pred mc gnd NMOSx-X_10
-Xinv@0 pred net@145 inv-X_10
-Xpms3@0 pred mc in net@174 pms3-X_3_333
-Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3
-.ENDS driversL__predDri60wMC
-
*** CELL: redFive:pms2{sch}
.SUBCKT pms2-X_10 d g g2
XPMOS@0 net@2 g vdd PMOSx-X_20
Xwire@0 a b wire-C_0_011f-209-R_34_667m
.ENDS wire90-209-layer_1-width_3
-*** CELL: driversJ:sucORdri60{sch}
+*** CELL: driversM:sucORdri60{sch}
.SUBCKT sucORdri60 inA inB succ
XPMOSx@0 succ net@51 vdd PMOSx-X_60
Xinv@0 succ net@71 inv-X_5
Xinv@1 fill net@537 inv-X_5
XinvI@0 net@454 s[1] inv-X_10
XinvI@1 net@602 s[2] inv-X_10
-XlatchDri@0 fire take latchDriver60
-XpredDri6@2 fire si[9] pred driversL__predDri60wMC
-XsucORdri@1 fire net@320 succ sucORdri60
+XlatchDri@1 fire take latchDriver60
+XpredDri6@2 fire si[9] pred predDri60wMC
+XsucORdri@2 fire net@320 succ sucORdri60
Xtc[1] tranCap
Xtc[2] tranCap
Xwire90@1 net@537 net@602 wire90-602_3-layer_1-width_3
Xwire@0 a b wire-C_0_011f-106_7-R_34_667m
.ENDS wire90-106_7-layer_1-width_3
-*** CELL: driversL:predDri20wMC{sch}
+*** CELL: driversM:predDri20wMC{sch}
.SUBCKT predDri20wMC in mc pred
XNMOSx@0 pred in gnd NMOSx-X_20
XNMOSx@1 pred mc gnd NMOSx-X_4
Xwire@0 a b wire-C_0_011f-503_4-R_34_667m
.ENDS wire90-503_4-layer_1-width_3
-*** CELL: driversL:sucDri20{sch}
+*** CELL: driversM:sucDri20{sch}
.SUBCKT sucDri20 in succ
Xinv@1 succ net@94 inv-X_4
Xinv@2 in net@110 inv-X_6
Xwire90@1 net@188 net@193 wire90-228_5-layer_1-width_3
.ENDS rsLatchA
-*** CELL: driversL:sucORdri20{sch}
+*** CELL: driversM:sucORdri20{sch}
.SUBCKT sucORdri20 inA inB succ
XPMOSx@0 succ net@51 vdd PMOSx-X_20
Xinv@0 succ net@71 inv-X_4
+out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26]
+out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34]
+out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax36
-XlatchDri@0 net@3 net@27 latchDriver60
-XlatchDri@1 net@7 net@23 latchDriver60
+XlatchDri@2 net@3 net@27 latchDriver60
+XlatchDri@3 net@7 net@23 latchDriver60
XscanEx3@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
+sir[7] sir[8] sor[1] scanEx3
Xtc[1] tranCap
+outB[21] outB[22] outB[23] outB[24] outB[25] outB[26] outB[27] outB[28]
+outB[29] outB[2] outB[30] outB[31] outB[32] outB[33] outB[34] outB[35]
+outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] outB[8] outB[9] ins1in20Bx36
-XlatchDri@0 net@5 net@20 latchDriver60
-XlatchDri@1 net@6 net@22 latchDriver60
+XlatchDri@2 net@5 net@20 latchDriver60
+XlatchDri@3 net@6 net@22 latchDriver60
XscanEx2v@1 net@48[1] net@48[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
+sir[6] sir[7] sir[8] sor[1] scanEx2
Xtc[1] tranCap
+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30]
+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6]
+out[7] out[8] out[9] ins1in20Bx36
-XlatchDri@0 fire[1] take[1] latchDriver60
+XlatchDri@1 fire[1] take[1] latchDriver60
XscanEx1@0 net@41 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
+sir[8] sor[1] scanEx1
Xtc[1] tranCap
Xwire@0 a b wire-C_0_011f-114_9-R_34_667m
.ENDS wire90-114_9-layer_1-width_3
-*** CELL: driversL:suc3ANDdri20{sch}
+*** CELL: driversM:suc3ANDdri20{sch}
.SUBCKT suc3ANDdri20 inA inB inC succ
XPMOSx@0 succ net@51 vdd PMOSx-X_20
Xinv@0 succ net@71 inv-X_4
Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3
.ENDS suc3ANDdri20
-*** CELL: driversL:sucANDdri20{sch}
+*** CELL: driversM:sucANDdri20{sch}
.SUBCKT sucANDdri20 inA inB succ
XPMOSx@0 succ net@51 vdd PMOSx-X_20
Xinv@0 succ net@71 inv-X_4
+epi[23] epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30]
+epi[31] epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6]
+epi[7] epi[8] epi[9] ins1in20Bx36
-XlatchDri@0 net@0 take[epi] latchDriver60
+XlatchDri@1 net@0 take[epi] latchDriver60
XscanEx1@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
+sir[8] sor[1] scanEx1
XtranCap@0 tranCap
+od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25]
+od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35]
+od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] ins1in20Bx36
-XlatchDri@0 fire[1] take[od] latchDriver60
+XlatchDri@1 fire[1] take[od] latchDriver60
XonDeck@0 m1[29] m1[30] net@11 flag[A][clr] flag[A][set] flag[D][clr]
+flag[D][set] sir[9] od[ABORT] od[HEAD] od[OTHER] do[od] net@62[1] net@62[0]
+onDeck
+rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2]
+rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6]
+rq[7] rq[8] rq[9] ins2in20Ax36
-XlatchDri@0 net@3 take[E] latchDriver60
-XlatchDri@1 net@7 take[P] latchDriver60
+XlatchDri@2 net@3 take[E] latchDriver60
+XlatchDri@3 net@7 take[P] latchDriver60
XreQueue@0 epi[OTHER] epi[TAIL] fire[E] fire[R] sir[9] od[ABORT] od[HEAD]
+od[OTHER] ps[do] ps[skip] rq[succ] s[1] s[2] s[3] s[4] reQueue
XscanEx1@0 s[1] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
+rqDockStage
.ENDS epiRQod
+*** CELL: wiresL:bitAssignments{sch}
+.SUBCKT bitAssignments
+.ENDS bitAssignments
+
*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-161_8-R_34_667m a b
Ccap@0 gnd net@14 0.593f
Xwire90@1 net@24 net@9 wire90-372_8-layer_1-width_3
.ENDS ctrAND2in30A
+*** CELL: driversM:predDri40{sch}
+.SUBCKT predDri40 in pred
+XNMOSx@0 pred in gnd NMOSx-X_40
+.ENDS predDri40
+
*** CELL: gaspM:gaspLit{sch}
-.SUBCKT gaspLit do[Lt] fire[L] mc ready s[1]
+.SUBCKT gaspLit do[ins] fire[L] ready sel[Lt]
XctrAND2i@0 net@189 ready fire[L] ctrAND2in30A
-Xinv@1 do[Lt] net@190 inv-X_5
-XinvI@0 net@189 s[1] inv-X_10
-XpredDri2@1 fire[L] mc do[Lt] predDri20wMC
-Xwire90@1 net@190 net@189 wire90-414-layer_1-width_3
+Xnand2@0 sel[Lt] do[ins] net@233 nand2-X_5
+XpredDri4@0 fire[L] do[ins] predDri40
+Xwire90@1 net@233 net@189 wire90-414-layer_1-width_3
.ENDS gaspLit
-*** CELL: driversJ:latchAndDriver60{sch}
-.SUBCKT latchAndDriver60 inA inB out
-Xinv@0 net@8 out inv-X_60
-Xnand2@0 inA inB net@26 nand2-X_20
-Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3
-.ENDS latchAndDriver60
-
*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-387_3-R_34_667m a b
Ccap@0 gnd net@14 1.42f
Xwire@0 a b wire-C_0_011f-387_3-R_34_667m
.ENDS wire90-387_3-layer_1-width_3
-*** CELL: driversJ:latchAndDriver30{sch}
+*** CELL: driversM:latchAndDriver30{sch}
.SUBCKT latchAndDriver30 inA inB out
Xinv@0 net@8 out inv-X_30
Xnand2@0 inA inB net@26 nand2-X_10
Xwire90@0 net@26 net@8 wire90-387_3-layer_1-width_3
.ENDS latchAndDriver30
+*** CELL: driversM:latchAndDriver60{sch}
+.SUBCKT latchAndDriver60 inA inB out
+Xinv@0 net@8 out inv-X_60
+Xnand2@0 inA inB net@26 nand2-X_20
+Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3
+.ENDS latchAndDriver60
+
*** CELL: registersM:data2in60Cx18{sch}
.SUBCKT data2in60Cx18 dcl[A] dcl[B] inA[10] inA[11] inA[12] inA[13] inA[14]
+inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6]
Xwire90@6 fire[A] fire[A2] wire90-2330-layer_1-width_3
.ENDS addr2in60Cx15
-*** CELL: gates3inM:nand3in6.6{sch}
-.SUBCKT nand3in6_6 inA inB inC out
-Xnand3@0 inA inB inC out nand3-X_6_667
-.ENDS nand3in6_6
-
*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-3495_7-R_34_667m a b
Ccap@0 gnd net@14 12.818f
Xwire@0 a b wire-C_0_011f-433_4-R_34_667m
.ENDS wire90-433_4-layer_1-width_3
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-425_6-R_34_667m a b
+Ccap@0 gnd net@14 1.561f
+Ccap@1 gnd net@8 1.561f
+Ccap@2 gnd net@11 1.561f
+Rres@0 net@14 a 2.459
+Rres@1 net@11 net@14 4.918
+Rres@2 b net@8 2.459
+Rres@3 net@8 net@11 4.918
+.ENDS wire-C_0_011f-425_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-425_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-425_6-R_34_667m
+.ENDS wire90-425_6-layer_1-width_3
+
*** CELL: registersM:newPathReg{sch}
.SUBCKT newPathReg aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
Xinv@1 ps[13] net@46 inv-X_10
Xinv@2 ps[14] net@47 inv-X_10
Xinv@3 ps[15] net@52 inv-X_10
-XinvI@0 net@19 net@40 inv-X_30
-XlatchAnd@0 ps[14] fire[M] net@43 latchAndDriver30
-Xnand3in6@1 net@25 net@28 fire[M] net@19 nand3in6_6
+XinvI@0 net@58 net@40 inv-X_30
+XlatchAnd@1 ps[14] fire[M] net@43 latchAndDriver30
+Xnand3@1 net@25 net@28 fire[M] net@59 nand3-X_6_667
Xwire90@0 net@43 take[ps] wire90-3495_7-layer_1-width_3
Xwire90@1 net@40 take[dp] wire90-3616_3-layer_1-width_3
Xwire90@3 net@46 net@28 wire90-270-layer_1-width_3
Xwire90@4 net@47 net@25 wire90-358-layer_1-width_3
Xwire90@5 net@52 ps[15not] wire90-433_4-layer_1-width_3
+Xwire90@6 net@59 net@58 wire90-425_6-layer_1-width_3
.ENDS newPathReg
*** CELL: redFive:nor2_sy{sch}
Xnor2@0 ina inb out nor2_sy-X_10
.ENDS nor2n_sy-X_10
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-632_9-R_34_667m a b
+Ccap@0 gnd net@14 2.321f
+Ccap@1 gnd net@8 2.321f
+Ccap@2 gnd net@11 2.321f
+Rres@0 net@14 a 3.657
+Rres@1 net@11 net@14 7.314
+Rres@2 b net@8 3.657
+Rres@3 net@8 net@11 7.314
+.ENDS wire-C_0_011f-632_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-632_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-632_9-R_34_667m
+.ENDS wire90-632_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-402-R_34_667m a b
+Ccap@0 gnd net@14 1.474f
+Ccap@1 gnd net@8 1.474f
+Ccap@2 gnd net@11 1.474f
+Rres@0 net@14 a 2.323
+Rres@1 net@11 net@14 4.645
+Rres@2 b net@8 2.323
+Rres@3 net@8 net@11 4.645
+.ENDS wire-C_0_011f-402-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-402-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-402-R_34_667m
+.ENDS wire90-402-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-419_5-R_34_667m a b
+Ccap@0 gnd net@14 1.538f
+Ccap@1 gnd net@8 1.538f
+Ccap@2 gnd net@11 1.538f
+Rres@0 net@14 a 2.424
+Rres@1 net@11 net@14 4.848
+Rres@2 b net@8 2.424
+Rres@3 net@8 net@11 4.848
+.ENDS wire-C_0_011f-419_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-419_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-419_5-R_34_667m
+.ENDS wire90-419_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-276_8-R_34_667m a b
+Ccap@0 gnd net@14 1.015f
+Ccap@1 gnd net@8 1.015f
+Ccap@2 gnd net@11 1.015f
+Rres@0 net@14 a 1.599
+Rres@1 net@11 net@14 3.199
+Rres@2 b net@8 1.599
+Rres@3 net@8 net@11 3.199
+.ENDS wire-C_0_011f-276_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-276_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-276_8-R_34_667m
+.ENDS wire90-276_8-layer_1-width_3
+
*** CELL: stagesM:litDandP{sch}
-.SUBCKT litDandP do[Lt] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16]
+.SUBCKT litDandP do[ins] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16]
+dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26]
+dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36]
+dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11]
+dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32]
+dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7]
+dsD[8] dsD[9] fire[M] flag[C] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
-+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7]
-+ps[8] ps[9] signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4]
-+sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T]
-XgaspLit@0 do[Lt] net@10 sir[9] net@99 net@27 gaspLit
-Xinv@0 ps[17] net@77 inv-X_10
-Xlatch2in@0 take[A] net@81 dp[B] signalBitFromInboundSwitchFabric flag[C]
++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6]
++ps[7] ps[8] ps[9] signalBitFromInboundSwitchFabric succ[D] succ[T]
+XbitAssig@0 bitAssignments
+XgaspLit@1 do[ins] net@10 net@108 ps[27] gaspLit
+Xinv@0 ps[17] net@112 inv-X_10
+Xlatch2in@0 take[A] net@83 dp[B] signalBitFromInboundSwitchFabric flag[C]
+latch2in60C
-XlatchAnd@1 ps[17] fire[M] take[A] latchAndDriver60
-XlatchAnd@2 net@77 fire[M] net@81 latchAndDriver30
-XlatchDri@0 net@13 take[B] latchDriver60
+XlatchAnd@3 net@111 fire[M] net@109 latchAndDriver30
+XlatchAnd@4 ps[17] fire[M] take[A] latchAndDriver60
+XlatchDri@1 net@13 take[B] latchDriver60
XnewDregi@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
+dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28]
+dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3]
+dp[27] dp[28] dp[29] dp[30] dp[31] dp[32] dp[33] dp[34] fire[M] ps[10] ps[11]
+ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8]
+ps[9] newPathReg
-Xnor2n_sy@0 succ[T] succ[D] net@99 nor2n_sy-X_10
-XscanEx1@0 net@27 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx1
+Xnor2n_sy@0 succ[T] succ[D] net@107 nor2n_sy-X_10
XsucANDdr@0 ps[16] fire[M] succ[D] sucANDdri60
XsucANDdr@1 ps[15] fire[M] succ[T] sucANDdri60
Xtc[1] tranCap
Xtc[8] tranCap
Xtc[9] tranCap
Xtc[10] tranCap
-Xwire90@0 net@10 net@13 wire90-4175_4-layer_1-width_3
+Xtc[11] tranCap
+Xwire90@0 net@10 net@13 wire90-632_9-layer_1-width_3
+Xwire90@1 net@108 net@107 wire90-402-layer_1-width_3
+Xwire90@2 net@109 net@83 wire90-419_5-layer_1-width_3
+Xwire90@3 net@112 net@111 wire90-276_8-layer_1-width_3
.ENDS litDandP
*** CELL: redFive:pms2{sch}
.ENDS pms1-X_10
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-403-R_34_667m a b
-Ccap@0 gnd net@14 1.478f
-Ccap@1 gnd net@8 1.478f
-Ccap@2 gnd net@11 1.478f
-Rres@0 net@14 a 2.328
-Rres@1 net@11 net@14 4.657
-Rres@2 b net@8 2.328
-Rres@3 net@8 net@11 4.657
-.ENDS wire-C_0_011f-403-R_34_667m
+.SUBCKT wire-C_0_011f-288_3-R_34_667m a b
+Ccap@0 gnd net@14 1.057f
+Ccap@1 gnd net@8 1.057f
+Ccap@2 gnd net@11 1.057f
+Rres@0 net@14 a 1.666
+Rres@1 net@11 net@14 3.331
+Rres@2 b net@8 1.666
+Rres@3 net@8 net@11 3.331
+.ENDS wire-C_0_011f-288_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-288_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-288_3-R_34_667m
+.ENDS wire90-288_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-255_4-R_34_667m a b
+Ccap@0 gnd net@14 0.936f
+Ccap@1 gnd net@8 0.936f
+Ccap@2 gnd net@11 0.936f
+Rres@0 net@14 a 1.476
+Rres@1 net@11 net@14 2.951
+Rres@2 b net@8 1.476
+Rres@3 net@8 net@11 2.951
+.ENDS wire-C_0_011f-255_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-255_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-255_4-R_34_667m
+.ENDS wire90-255_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-120_2-R_34_667m a b
+Ccap@0 gnd net@14 0.441f
+Ccap@1 gnd net@8 0.441f
+Ccap@2 gnd net@11 0.441f
+Rres@0 net@14 a 0.694
+Rres@1 net@11 net@14 1.389
+Rres@2 b net@8 0.694
+Rres@3 net@8 net@11 1.389
+.ENDS wire-C_0_011f-120_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-120_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-120_2-R_34_667m
+.ENDS wire90-120_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-112_1-R_34_667m a b
+Ccap@0 gnd net@14 0.411f
+Ccap@1 gnd net@8 0.411f
+Ccap@2 gnd net@11 0.411f
+Rres@0 net@14 a 0.648
+Rres@1 net@11 net@14 1.295
+Rres@2 b net@8 0.648
+Rres@3 net@8 net@11 1.295
+.ENDS wire-C_0_011f-112_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-112_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-112_1-R_34_667m
+.ENDS wire90-112_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-66_6-R_34_667m a b
+Ccap@0 gnd net@14 0.244f
+Ccap@1 gnd net@8 0.244f
+Ccap@2 gnd net@11 0.244f
+Rres@0 net@14 a 0.385
+Rres@1 net@11 net@14 0.77
+Rres@2 b net@8 0.385
+Rres@3 net@8 net@11 0.77
+.ENDS wire-C_0_011f-66_6-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-403-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-403-R_34_667m
-.ENDS wire90-403-layer_1-width_3
+.SUBCKT wire90-66_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-66_6-R_34_667m
+.ENDS wire90-66_6-layer_1-width_3
*** CELL: oneHotM:sucDri10Pair{sch}
.SUBCKT sucDri10Pair bit[1] out[1][F] out[1][T] when
Xnms2b@0 out[1][T] net@113 net@4 nms2-X_2
Xpms1@0 out[1][T] net@4 pms1-X_10
Xpms2_sy@0 out[1][F] net@105 bit[1] pms2_sy-X_10
-Xwire90@0 net@64 net@4 wire90-403-layer_1-width_3
-Xwire90@1 net@66 net@105 wire90-403-layer_1-width_3
-Xwire90@3 net@113 net@112 wire90-403-layer_1-width_3
-Xwire90@4 net@154 net@92 wire90-403-layer_1-width_3
-Xwire90@5 net@144 net@139 wire90-403-layer_1-width_3
+Xwire90@0 net@64 net@4 wire90-288_3-layer_1-width_3
+Xwire90@1 net@66 net@105 wire90-255_4-layer_1-width_3
+Xwire90@3 net@113 net@112 wire90-120_2-layer_1-width_3
+Xwire90@4 net@154 net@92 wire90-112_1-layer_1-width_3
+Xwire90@5 net@144 net@139 wire90-66_6-layer_1-width_3
.ENDS sucDri10Pair
*** CELL: oneHotM:sucDri10Pairx6{sch}
Xnor2n_sy@0 m1cate[1][T] m1cate[1][F] ready nor2n_sy-X_5
.ENDS sucDri10Pairx6
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-425_8-R_34_667m a b
+Ccap@0 gnd net@14 1.561f
+Ccap@1 gnd net@8 1.561f
+Ccap@2 gnd net@11 1.561f
+Rres@0 net@14 a 2.46
+Rres@1 net@11 net@14 4.92
+Rres@2 b net@8 2.46
+Rres@3 net@8 net@11 4.92
+.ENDS wire-C_0_011f-425_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-425_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-425_8-R_34_667m
+.ENDS wire90-425_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-257_3-R_34_667m a b
+Ccap@0 gnd net@14 0.943f
+Ccap@1 gnd net@8 0.943f
+Ccap@2 gnd net@11 0.943f
+Rres@0 net@14 a 1.487
+Rres@1 net@11 net@14 2.973
+Rres@2 b net@8 1.487
+Rres@3 net@8 net@11 2.973
+.ENDS wire-C_0_011f-257_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-257_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-257_3-R_34_667m
+.ENDS wire90-257_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-692_7-R_34_667m a b
+Ccap@0 gnd net@14 2.54f
+Ccap@1 gnd net@8 2.54f
+Ccap@2 gnd net@11 2.54f
+Rres@0 net@14 a 4.002
+Rres@1 net@11 net@14 8.005
+Rres@2 b net@8 4.002
+Rres@3 net@8 net@11 8.005
+.ENDS wire-C_0_011f-692_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-692_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-692_7-R_34_667m
+.ENDS wire90-692_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-399_3-R_34_667m a b
+Ccap@0 gnd net@14 1.464f
+Ccap@1 gnd net@8 1.464f
+Ccap@2 gnd net@11 1.464f
+Rres@0 net@14 a 2.307
+Rres@1 net@11 net@14 4.614
+Rres@2 b net@8 2.307
+Rres@3 net@8 net@11 4.614
+.ENDS wire-C_0_011f-399_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-399_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-399_3-R_34_667m
+.ENDS wire90-399_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-489_2-R_34_667m a b
+Ccap@0 gnd net@14 1.794f
+Ccap@1 gnd net@8 1.794f
+Ccap@2 gnd net@11 1.794f
+Rres@0 net@14 a 2.826
+Rres@1 net@11 net@14 5.653
+Rres@2 b net@8 2.826
+Rres@3 net@8 net@11 5.653
+.ENDS wire-C_0_011f-489_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-489_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-489_2-R_34_667m
+.ENDS wire90-489_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1763-R_34_667m a b
+Ccap@0 gnd net@14 6.464f
+Ccap@1 gnd net@8 6.464f
+Ccap@2 gnd net@11 6.464f
+Rres@0 net@14 a 10.186
+Rres@1 net@11 net@14 20.372
+Rres@2 b net@8 10.186
+Rres@3 net@8 net@11 20.372
+.ENDS wire-C_0_011f-1763-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1763-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1763-R_34_667m
+.ENDS wire90-1763-layer_1-width_3
+
*** CELL: oneHotM:minusOne{sch}
.SUBCKT minusOne bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] fire[m1] headBit
+m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T]
+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] net@435
+net@421 sucDri10Pairx6
XsucDri20@1 net@407 succ[m1] sucDri20
-Xwire90@10 fire[m1] net@407 wire90-403-layer_1-width_3
-Xwire90@11 net@313 net@235 wire90-403-layer_1-width_3
-Xwire90@12 net@414 net@435 wire90-403-layer_1-width_3
-Xwire90@13 net@411 net@391 wire90-403-layer_1-width_3
-Xwire90@14 net@398 net@405 wire90-403-layer_1-width_3
-Xwire90@15 net@406 net@421 wire90-403-layer_1-width_3
+Xwire90@10 fire[m1] net@407 wire90-425_8-layer_1-width_3
+Xwire90@11 net@313 net@235 wire90-257_3-layer_1-width_3
+Xwire90@12 net@414 net@435 wire90-692_7-layer_1-width_3
+Xwire90@13 net@411 net@391 wire90-399_3-layer_1-width_3
+Xwire90@14 net@398 net@405 wire90-489_2-layer_1-width_3
+Xwire90@15 net@406 net@421 wire90-1763-layer_1-width_3
.ENDS minusOne
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-793_6-R_34_667m a b
+Ccap@0 gnd net@14 2.91f
+Ccap@1 gnd net@8 2.91f
+Ccap@2 gnd net@11 2.91f
+Rres@0 net@14 a 4.585
+Rres@1 net@11 net@14 9.17
+Rres@2 b net@8 4.585
+Rres@3 net@8 net@11 9.17
+.ENDS wire-C_0_011f-793_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-793_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-793_6-R_34_667m
+.ENDS wire90-793_6-layer_1-width_3
+
*** CELL: stagesM:mOneDockStage{sch}
.SUBCKT mOneDockStage m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
+m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23]
+m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33]
+m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ins1in20Bx36
-XlatchDri@0 fire[1] take[m1] latchDriver60
+XlatchDri@1 fire[1] take[m1] latchDriver60
XminusOne@0 ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] net@11
+ring[30] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F]
+m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F]
Xtc[17] tranCap
Xtc[18] tranCap
Xtc[19] tranCap
-Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3
+Xwire90@1 net@11 fire[1] wire90-793_6-layer_1-width_3
.ENDS mOneDockStage
*** CELL: loopCountM:mux10/2{sch}
Xwire90@1 net@1 sF wire90-704_3-layer_1-width_3
.ENDS muxForPS
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4446_4-R_34_667m a b
+Ccap@0 gnd net@14 16.303f
+Ccap@1 gnd net@8 16.303f
+Ccap@2 gnd net@11 16.303f
+Rres@0 net@14 a 25.69
+Rres@1 net@11 net@14 51.381
+Rres@2 b net@8 25.69
+Rres@3 net@8 net@11 51.381
+.ENDS wire-C_0_011f-4446_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4446_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4446_4-R_34_667m
+.ENDS wire90-4446_4-layer_1-width_3
+
*** CELL: registersM:dockPSreg{sch}
-.SUBCKT dockPSreg fire[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16]
+.SUBCKT dockPSreg do[ins] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16]
+m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26]
-+m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36]
-+m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] outLO[1] outLO[2] outLO[3] outLO[4]
-+outLO[5] outLO[6] outLO[7] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16]
-+ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26]
-+ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36]
-+ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[1]
-Xins1in20@0 take[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
-+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
-+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
-+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25]
-+ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35]
-+ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ins1in20Bx36
-XlatchDri@0 fire[1] net@0 latchDriver60
++m1[27] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] outLO[1] outLO[2]
++outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[10] ps[11] ps[12] ps[13]
++ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23]
++ps[24] ps[25] ps[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9]
+Xinv@0 do[ins] net@1 inv-X_40
+Xlx[1] hold[1] m1[1] ps[1] latch1in20B
+Xlx[2] hold[1] m1[2] ps[2] latch1in20B
+Xlx[3] hold[1] m1[3] ps[3] latch1in20B
+Xlx[4] hold[1] m1[4] ps[4] latch1in20B
+Xlx[5] hold[1] m1[5] ps[5] latch1in20B
+Xlx[6] hold[1] m1[6] ps[6] latch1in20B
+Xlx[7] hold[1] m1[7] ps[7] latch1in20B
+Xlx[8] hold[1] m1[8] ps[8] latch1in20B
+Xlx[9] hold[1] m1[9] ps[9] latch1in20B
+Xlx[10] hold[1] m1[10] ps[10] latch1in20B
+Xlx[11] hold[1] m1[11] ps[11] latch1in20B
+Xlx[12] hold[1] m1[12] ps[12] latch1in20B
+Xlx[13] hold[1] m1[13] ps[13] latch1in20B
+Xlx[14] hold[1] m1[14] ps[14] latch1in20B
+Xlx[15] hold[1] m1[15] ps[15] latch1in20B
+Xlx[16] hold[1] m1[16] ps[16] latch1in20B
+Xlx[17] hold[1] m1[17] ps[17] latch1in20B
+Xlx[18] hold[1] m1[18] ps[18] latch1in20B
+Xlx[19] hold[1] m1[19] ps[19] latch1in20B
+Xlx[20] hold[1] m1[20] ps[20] latch1in20B
+Xlx[21] hold[1] m1[21] ps[21] latch1in20B
+Xlx[22] hold[1] m1[22] ps[22] latch1in20B
+Xlx[23] hold[1] m1[23] ps[23] latch1in20B
+Xlx[24] hold[1] m1[24] ps[24] latch1in20B
+Xlx[25] hold[1] m1[25] ps[25] latch1in20B
+Xlx[26] hold[1] m1[26] ps[26] latch1in20B
+Xlx[27] hold[1] m1[27] ps[27] latch1in20B
XmuxForOD@0 ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[8] outLO[1] outLO[2]
+outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForPS
Xtc[1] tranCap
Xtc[2] tranCap
Xtc[3] tranCap
-Xwire90@0 net@0 take[1] wire90-544_2-layer_1-width_3
+Xwire90@0 net@1 hold[1] wire90-4446_4-layer_1-width_3
.ENDS dockPSreg
*** CELL: redFive:nand2n{sch}
Xwire90@43 net@426 do[7] wire90-1019_7-layer_1-width_3
.ENDS ilc
-*** CELL: driversL:predORdri20wMC{sch}
-.SUBCKT predORdri20wMC inA inB mc pred
-XNMOSx@0 pred inA gnd NMOSx-X_20
-XNMOSx@1 pred mc gnd NMOSx-X_4
-XNMOSx@2 pred inB gnd NMOSx-X_20
-XPMOSx@1 pred net@217 net@203 PMOSx-X_4
-XPMOSx@2 net@203 inB net@204 PMOSx-X_4
-XPMOSx@3 net@204 inA net@205 PMOSx-X_4
-XPMOSx@4 net@205 mc vdd PMOSx-X_4
-Xinv@0 pred net@145 inv-X_4
-Xwire90@0 net@217 net@145 wire90-243_6-layer_1-width_3
-.ENDS predORdri20wMC
-
*** CELL: redFive:nand2n{sch}
.SUBCKT nand2n-X_20 ina inb out
Xnand2@0 ina inb out nand2-X_20
.ENDS wire90-392_9-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-174_7-R_34_667m a b
-Ccap@0 gnd net@14 0.641f
-Ccap@1 gnd net@8 0.641f
-Ccap@2 gnd net@11 0.641f
-Rres@0 net@14 a 1.009
-Rres@1 net@11 net@14 2.019
-Rres@2 b net@8 1.009
-Rres@3 net@8 net@11 2.019
-.ENDS wire-C_0_011f-174_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-174_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-174_7-R_34_667m
-.ENDS wire90-174_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-1154_9-R_34_667m a b
Ccap@0 gnd net@14 4.235f
Ccap@1 gnd net@8 4.235f
Xwire@0 a b wire-C_0_011f-590_5-R_34_667m
.ENDS wire90-590_5-layer_1-width_3
-*** CELL: moveM:races{sch}
-.SUBCKT races bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] in[D] in[T] succ torp
-+winLO[M]
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-174_7-R_34_667m a b
+Ccap@0 gnd net@14 0.641f
+Ccap@1 gnd net@8 0.641f
+Ccap@2 gnd net@11 0.641f
+Rres@0 net@14 a 1.009
+Rres@1 net@11 net@14 2.019
+Rres@2 b net@8 1.009
+Rres@3 net@8 net@11 2.019
+.ENDS wire-C_0_011f-174_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-174_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-174_7-R_34_667m
+.ENDS wire90-174_7-layer_1-width_3
+
+*** CELL: moveM:moveRepeat{sch}
+.SUBCKT moveRepeat do[ins] fire[T] in[D] in[T] sel[Di] sel[Mv] sel[Ti]
++sel[Tp] succ[sf] torp winLO[M]
Xarbiter2@0 net@131 net@128 torp in[D] arbiter2
Xarbiter2@1 net@130 net@129 torp in[T] arbiter2
-Xinv@0 winLO[M] net@192 inv-X_5
XinvI@0 net@150 fire[T] inv-X_20
-XinvI@1 net@187 net@186 inv-X_5
-XinvI@3 net@187 invI@3_out inv-X_10
-Xnand2@0 bit[Di] do[Tp] net@35 nand2-X_10
-Xnand2@1 bit[Ti] do[Tp] net@42 nand2-X_10
-Xnand2@2 net@94 do[Mv] net@86 nand2-X_10
-Xnand2n@0 bit[Di] net@11 net@57 nand2n-X_20
-Xnand2n@1 bit[Ti] net@53 net@60 nand2n-X_20
-Xnand3in4@0 net@159 net@123 net@98 winLO[M] nand3in44s
-Xnor2_sy@0 net@48 net@45 net@151 nor2_sy-X_20
-Xnor2n@0 net@39 net@12 net@44 nor2n-X_20
-Xnor2n@1 net@36 net@32 net@43 nor2n-X_20
-Xnor2n@2 succ net@153 net@152 nor2n-X_20
+XinvI@6 net@271 net@217 inv-X_5
+XinvI@7 net@224 invI@7_out inv-X_10
+Xnand2@2 net@224 do[ins] net@86 nand2-X_10
+Xnand2@5 winLO[M] sel[Mv] net@221 nand2-X_5
+Xnand2@6 sel[Tp] do[ins] net@254 nand2-X_10
+Xnand2n@0 sel[Di] net@11 net@57 nand2n-X_20
+Xnand2n@1 sel[Ti] net@53 net@60 nand2n-X_20
+Xnand3in4@0 net@159 net@127 net@98 winLO[M] nand3in44s
+Xnor2_sy@0 net@48 net@45 net@151 nor2_sy-X_10
+Xnor2n@0 net@38 net@12 net@44 nor2n-X_10
+Xnor2n@1 net@38 net@32 net@43 nor2n-X_10
+Xnor2n@2 succ[sf] net@153 net@152 nor2n-X_20
Xwire90@0 net@131 net@12 wire90-321_9-layer_1-width_3
Xwire90@1 net@130 net@32 wire90-321_9-layer_1-width_3
Xwire90@2 net@129 net@53 wire90-294-layer_1-width_3
Xwire90@3 net@128 net@11 wire90-294-layer_1-width_3
-Xwire90@4 net@35 net@39 wire90-572_3-layer_1-width_3
-Xwire90@5 net@42 net@36 wire90-572_3-layer_1-width_3
+Xwire90@4 net@254 net@38 wire90-572_3-layer_1-width_3
Xwire90@6 net@44 net@45 wire90-741_5-layer_1-width_3
Xwire90@7 net@43 net@48 wire90-783-layer_1-width_3
-Xwire90@8 net@60 net@123 wire90-1254_1-layer_1-width_3
+Xwire90@8 net@60 net@127 wire90-1254_1-layer_1-width_3
Xwire90@9 net@57 net@159 wire90-1300_1-layer_1-width_3
Xwire90@11 net@86 net@153 wire90-392_9-layer_1-width_3
-Xwire90@12 net@94 net@186 wire90-174_7-layer_1-width_3
Xwire90@13 net@152 net@98 wire90-1154_9-layer_1-width_3
Xwire90@15 net@151 net@150 wire90-590_5-layer_1-width_3
-Xwire90@16 net@187 net@192 wire90-174_7-layer_1-width_3
-.ENDS races
+Xwire90@19 net@224 net@217 wire90-174_7-layer_1-width_3
+Xwire90@20 net@271 net@221 wire90-174_7-layer_1-width_3
+.ENDS moveRepeat
*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-362_9-R_34_667m a b
.ENDS wire90-709_6-layer_1-width_3
*** CELL: moveM:moveOut{sch}
-.SUBCKT moveOut bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M]
-+flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4] s[5]
+.SUBCKT moveOut do[ins] doneLO[M] epi[torp] fire[M] flag[D][set] ilc[do]
++ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] sel[Di] sel[Mv] sel[Ti] sel[Tp]
+succ[sf] winLO[M]
-Xinv@0 net@28 s[4] inv-X_10
-Xinv@1 net@29 s[3] inv-X_10
-Xinv@2 net@50 s[5] inv-X_10
-Xinv@9 fire[T] net@186 inv-X_5
-Xinv@10 ilc[do] net@221 inv-X_5
-Xinv@11 net@227 s[2] inv-X_10
-Xinv@12 net@194 s[1] inv-X_10
-XinvI@0 do[Tp] net@28 inv-X_5
-XinvI@1 epi[torp] net@29 inv-X_5
-XinvI@2 do[Mv] net@50 inv-X_5
-XinvI@7 pred[D] net@227 inv-X_5
-XinvI@8 pred[T] net@194 inv-X_5
-Xnand2@2 ilc[do] bit[Di] net@208 nand2-X_5
-Xnand2@3 ilc[do] bit[Ti] net@207 nand2-X_5
+Xinv@9 fire[T] net@326 inv-X_5
+Xinv@10 ilc[do] net@221 inv-X_10
+Xinv@13 pred[T] net@194 inv-X_5
+Xinv@14 pred[D] net@227 inv-X_5
+Xinv@15 epi[torp] net@29 inv-X_5
+Xinv@16 net@250 doneLO[M] inv-X_20
+XinvI@9 net@194 s[1] inv-X_10
+XinvI@10 net@227 s[2] inv-X_10
+XinvI@11 net@29 s[3] inv-X_10
+XmoveRepe@0 do[ins] fire[T] pred[D] pred[T] sel[Di] sel[Mv] sel[Ti] sel[Tp]
++succ[sf] epi[torp] winLO[M] moveRepeat
+Xnand2@2 ilc[do] sel[Di] net@208 nand2-X_5
+Xnand2@3 ilc[do] sel[Ti] net@207 nand2-X_5
Xnor2n@1 ilc[mo] winLO[M] net@250 nor2n-X_10
Xnor2n@5 net@206 winLO[M] net@203 nor2n-X_10
Xnor2n@6 net@205 winLO[M] net@204 nor2n-X_10
Xnor2n@7 net@220 winLO[M] fire[M] nor2n-X_20
-Xpms1@0 flag[D][set] net@186 pms1-X_20
+Xpms1@0 flag[D][set] net@327 pms1-X_20
XpredDri2@0 fire[T] mc epi[torp] predDri20wMC
XpredDri2@3 net@201 mc pred[D] predDri20wMC
XpredDri2@4 net@200 mc pred[T] predDri20wMC
-XpredORdr@0 fire[T] done[M] mc do[Tp] predORdri20wMC
-XpredORdr@1 fire[T] done[M] mc do[Mv] predORdri20wMC
-Xraces@0 bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] pred[D] pred[T] succ[sf]
-+epi[torp] winLO[M] races
-XsucDri20@0 done[M] do[reD] sucDri20
+XpredDri4@0 net@345 do[ins] predDri40
+XpredDri4@1 net@340 do[ins] predDri40
Xwire90@9 net@206 net@208 wire90-362_9-layer_1-width_3
Xwire90@10 net@220 net@221 wire90-602_7-layer_1-width_3
Xwire90@11 net@200 net@204 wire90-269_9-layer_1-width_3
Xwire90@12 net@201 net@203 wire90-269_9-layer_1-width_3
Xwire90@13 net@205 net@207 wire90-362_9-layer_1-width_3
-Xwire90@15 done[M] net@250 wire90-709_6-layer_1-width_3
+Xwire90@15 net@345 net@250 wire90-709_6-layer_1-width_3
+Xwire90@16 net@340 fire[T] wire90-269_9-layer_1-width_3
+Xwire90@17 net@326 net@327 wire90-269_9-layer_1-width_3
.ENDS moveOut
+*** CELL: scanM:scanEx1h{sch}
+.SUBCKT scanEx1h dIn[1] mc p1p p2p rd sin sout
+XscanCell@10 dIn[1] p1p p2p rd sin sout scanCellE
+.ENDS scanEx1h
+
*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-297_9-R_34_667m a b
Ccap@0 gnd net@14 1.092f
.ENDS wire90-1831_6-layer_1-width_3
*** CELL: moveM:ilcMoveOut{sch}
-.SUBCKT ilcMoveOut bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M]
-+flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6]
-+inLO[8] mc p1p p2p pred[D] pred[T] rd sin sout succ[sf]
+.SUBCKT ilcMoveOut do[ins] doneLO[M] epi[torp] fire[M] flag[D][set] ilc[load]
++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] mc p1p p2p pred[D]
++pred[T] rd sel[Di] sel[Mv] sel[Ti] sel[Tp] sin sout succ[sf]
Xilc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8]
+ilc[decLO] ilc[do] ilc[load] ilc[mo] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
+inLO[6] inLO[8] ilc
-XoutDockM@0 bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M]
-+flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4] s[5]
-+succ[sf] net@72 moveOut
-XscanEx2h@0 s[1] s[5] mc p1p p2p rd net@51 net@58 scanEx2h
-XscanEx3h@0 s[4] s[3] s[2] mc p1p p2p rd net@58 sout scanEx3h
+XoutDockM@0 do[ins] doneLO[M] epi[torp] fire[M] flag[D][set] ilc[do] ilc[mo]
++mc pred[D] pred[T] s[1] s[2] s[3] sel[Di] sel[Mv] sel[Ti] sel[Tp] succ[sf]
++net@72 moveOut
+XscanEx1h@0 s[3] mc p1p p2p rd net@84 sout scanEx1h
+XscanEx2h@0 s[1] s[2] mc p1p p2p rd net@85 net@84 scanEx2h
XscanEx4h@0 bitt[1] bitt[3] bitt[5] bitt[7] mc p1p p2p rd sin net@50 scanEx4h
-XscanEx4h@1 bitt[2] bitt[4] bitt[6] bitt[8] mc p1p p2p rd net@50 net@51
+XscanEx4h@1 bitt[2] bitt[4] bitt[6] bitt[8] mc p1p p2p rd net@50 net@85
+scanEx4h
Xwire90@0 net@72 ilc[decLO] wire90-4243_4-layer_1-width_3
Xwire90@1 wire90@1_a ilc[mo] wire90-467_9-layer_1-width_3
Xwire90@1 net@1 sT wire90-704_3-layer_1-width_3
.ENDS muxForD
-*** CELL: wiresL:bitAssignments{sch}
-.SUBCKT bitAssignments
-.ENDS bitAssignments
-
*** CELL: redFive:nand2_sy{sch}
.SUBCKT nand2_sy-X_30 ina inb out
XPMOS@0 out inb vdd PMOSx-X_30
Xpms1@3 out resetLO pms1-X_20
.ENDS nand3in20sr
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_5_5 d g s
-MNMOSf@0 d g s gnd nch W='16.5*(1+ABN/sqrt(16.5*2))' L='2'
-+DELVTO='AVT0N/sqrt(16.5*2)'
-.ENDS NMOSx-X_5_5
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_5_5 d g s
-MPMOSf@0 d g s vdd pch W='33*(1+ABP/sqrt(33*2))' L='2'
-+DELVTO='AVT0P/sqrt(33*2)'
-.ENDS PMOSx-X_5_5
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_2_75 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_5_5
-XPMOS@1 d g2 net@2 PMOSx-X_5_5
-.ENDS pms2-X_2_75
-
-*** CELL: redFive:pms2_sy{sch}
-.SUBCKT pms2_sy-X_5_5 d g g2
-Xpms2@0 d g g2 pms2-X_2_75
-Xpms2@1 d g2 g pms2-X_2_75
-.ENDS pms2_sy-X_5_5
-
-*** CELL: redFive:nor2_sy{sch}
-.SUBCKT nor2_sy-X_5_5 ina inb out
-XNMOS@0 out inb gnd NMOSx-X_5_5
-XNMOS@1 out ina gnd NMOSx-X_5_5
-Xpms2_sy@0 out ina inb pms2_sy-X_5_5
-.ENDS nor2_sy-X_5_5
-
-*** CELL: redFive:nor2n_sy{sch}
-.SUBCKT nor2n_sy-X_5_5 ina inb out
-Xnor2@0 ina inb out nor2_sy-X_5_5
-.ENDS nor2n_sy-X_5_5
-
-*** CELL: driversL:sucDri20plain{sch}
-.SUBCKT sucDri20plain in succ
-XPMOSx@0 succ in vdd PMOSx-X_20
-Xinv@1 succ net@94 inv-X_4
-Xnms2@0 succ net@127 in nms2-X_2
-Xwire90@0 net@127 net@94 wire90-124_7-layer_1-width_3
-.ENDS sucDri20plain
-
-*** CELL: predicateM:predSucDri{sch}
-.SUBCKT predSucDri do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] sel[Co]
-+sel[Ld] sel[Lt] sel[Mv] sel[Tp]
-Xna[1] sel[Ld] fire[do] w[1] nand2-X_10
-Xna[2] sel[Co] fire[do] w[2] nand2-X_10
-Xna[3] sel[Mv] fire[do] w[3] nand2-X_10
-Xna[4] sel[Tp] fire[do] w[4] nand2-X_10
-Xna[5] sel[Lt] fire[do] w[5] nand2-X_10
-Xsd[1] w[1] do[Ld] sucDri20plain
-Xsd[2] w[2] do[Co] sucDri20plain
-Xsd[3] w[3] do[Mv] sucDri20plain
-Xsd[4] w[4] do[Tp] sucDri20plain
-Xsd[5] w[5] do[Lt] sucDri20plain
-Xwire90@0 w[1] wire90@0_b wire90-503_4-layer_1-width_3
-Xwire90@1 w[2] wire90@1_b wire90-503_4-layer_1-width_3
-Xwire90@2 w[3] wire90@2_b wire90-503_4-layer_1-width_3
-Xwire90@3 w[4] wire90@3_b wire90-503_4-layer_1-width_3
-Xwire90@4 w[5] wire90@4_b wire90-503_4-layer_1-width_3
-.ENDS predSucDri
-
*** CELL: redFive:pms2{sch}
.SUBCKT pms2-X_1_5 d g g2
XPMOS@0 net@2 g vdd PMOSx-X_3
Xwire@0 a b wire-C_0_011f-60_2-R_34_667m
.ENDS wire90-60_2-layer_1-width_3
-*** CELL: driversL:predCond20wMC{sch}
+*** CELL: driversM:predCond20wMC{sch}
.SUBCKT predCond20wMC cond in mc pred
XNMOSx@1 pred mc gnd NMOSx-X_10
XPMOSx@0 pred in net@217 PMOSx-X_3
Xwire@0 a b wire-C_0_011f-219_5-R_34_667m
.ENDS wire90-219_5-layer_1-width_3
-*** CELL: driversL:predCond20wMS{sch}
+*** CELL: driversM:predCond20wMS{sch}
.SUBCKT predCond20wMS cond in mc pred
XPMOSx@0 pred cond net@210 PMOSx-X_3
XPMOSx@1 pred in net@217 PMOSx-X_3
XpredCond@1 sel[rD] fire[do] mc flag[D][set] predCond20wMS
.ENDS predFlagDri
+*** CELL: redFive:nms1{sch}
+.SUBCKT nms1-X_10 d g
+XNMOS@1 d g gnd NMOSx-X_10
+.ENDS nms1-X_10
+
+*** CELL: redFive:pms1{sch}
+.SUBCKT pms1-X_4 d g
+XPMOS@0 d g vdd PMOSx-X_4
+.ENDS pms1-X_4
+
+*** CELL: redFive:pms2{sch}
+.SUBCKT pms2-X_40 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_80
+XPMOS@1 d g2 net@2 PMOSx-X_80
+.ENDS pms2-X_40
+
+*** CELL: driversM:sucNANDdri40keep{sch}
+.SUBCKT sucNANDdri40keep in inB mc succ
+MNMOS4fwk@0 gnd net@164 succ NMOS4fwk@0_b nch W='3*(1+ABN/sqrt(3*2))' L='2'
++DELVTO='AVT0N/sqrt(3*2)'
+MPMOS4fwk@1 net@174 net@164 succ PMOS4fwk@1_b pch W='3*(1+ABP/sqrt(3*2))'
++L='2' DELVTO='AVT0P/sqrt(3*2)'
+Xinv@3 succ net@167 inv-X_4
+XinvI@0 in net@144 inv-X_20
+Xnms1@0 succ mc nms1-X_10
+Xpms1@0 net@174 mc pms1-X_4
+Xpms2a@0 succ inB net@145 pms2-X_40
+Xwire90@1 net@144 net@145 wire90-503_4-layer_1-width_3
+Xwire90@2 net@167 net@164 wire90-124_7-layer_1-width_3
+.ENDS sucNANDdri40keep
+
*** CELL: predicateM:ohPredDo{sch}
-.SUBCKT ohPredDo do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] fire[skip]
-+flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set]
-+mc ps[do] ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD]
+.SUBCKT ohPredDo do[ins] fire[do] fire[skip] flag[A][clr] flag[A][set]
++flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[do]
++ps[skip]
XbitAssig@0 bitAssignments
-Xinv@1 fire[do] net@125 inv-X_20
-Xinv@2 net@125 net@57 inv-X_20
-XohPredDo@3 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] net@57 sel[Co] sel[Ld] sel[Lt]
-+sel[Mv] sel[Tp] predSucDri
-XpredFlag@1 net@57 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
-+flag[D][clr] flag[D][set] mc sel[Fl] sel[rD] predFlagDri
+XpredFlag@1 fire[do] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
++flag[D][clr] flag[D][set] mc m1[Fl] m1[rD] predFlagDri
XsucDri20@0 net@55 ps[skip] sucDri20
-XsucDri20@1 net@57 ps[do] sucDri20
+XsucDri20@1 fire[do] ps[do] sucDri20
+XsucNANDd@0 fire[do] m1[Fl] mc do[ins] sucNANDdri40keep
Xwire90@2 fire[skip] net@55 wire90-309-layer_1-width_3
.ENDS ohPredDo
Xwire@0 a b wire-C_0_011f-2516_8-R_34_667m
.ENDS wire90-2516_8-layer_1-width_3
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-247_4-R_34_667m a b
-Ccap@0 gnd net@14 0.907f
-Ccap@1 gnd net@8 0.907f
-Ccap@2 gnd net@11 0.907f
-Rres@0 net@14 a 1.429
-Rres@1 net@11 net@14 2.859
-Rres@2 b net@8 1.429
-Rres@3 net@8 net@11 2.859
-.ENDS wire-C_0_011f-247_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-247_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-247_4-R_34_667m
-.ENDS wire90-247_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-249_4-R_34_667m a b
-Ccap@0 gnd net@14 0.914f
-Ccap@1 gnd net@8 0.914f
-Ccap@2 gnd net@11 0.914f
-Rres@0 net@14 a 1.441
-Rres@1 net@11 net@14 2.882
-Rres@2 b net@8 1.441
-Rres@3 net@8 net@11 2.882
-.ENDS wire-C_0_011f-249_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-249_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-249_4-R_34_667m
-.ENDS wire90-249_4-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-244_3-R_34_667m a b
-Ccap@0 gnd net@14 0.896f
-Ccap@1 gnd net@8 0.896f
-Ccap@2 gnd net@11 0.896f
-Rres@0 net@14 a 1.412
-Rres@1 net@11 net@14 2.823
-Rres@2 b net@8 1.412
-Rres@3 net@8 net@11 2.823
-.ENDS wire-C_0_011f-244_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-244_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-244_3-R_34_667m
-.ENDS wire90-244_3-layer_1-width_3
-
*** CELL: predicateM:ohPredAll{sch}
-.SUBCKT ohPredAll do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr]
-+flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p
-+ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD]
-+sin sout
+.SUBCKT ohPredAll do[ins] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
++flag[D][clr] flag[D][set] m1[Fl] m1[rD] m1cate[1][F] m1cate[1][T]
++m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T]
++m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p ps[do]
++ps[skip] rd sin sout
XbitAssig@0 bitAssignments
-XinvI@0 net@82 fire[do] inv-X_40
-XinvI@1 net@63 fire[skip] inv-X_10
-XinvI@2 net@183 net@186 inv-X_10
+Xinv@1 do[ins] net@206 inv-X_5
+XinvI@0 net@82 net@166 inv-X_40
+XinvI@1 net@63 net@144 inv-X_10
+XinvI@2 do[ins] net@193 inv-X_10
+XinvI@3 net@200 s[3] inv-X_10
Xnand2_sy@0 net@94 net@11 net@63 nand2_sy-X_10
-Xnand2_sy@1 net@177 net@174 net@182 nand2_sy-X_6
Xnand2n_s@0 net@147 net@84 fire[both] nand2n_sy-X_30
Xnand3in2@1 net@46 net@41 net@11 net@82 net@21 nand3in20sr
Xnor2n_sy@0 ps[skip] ps[do] net@39 nor2n_sy-X_10
-Xnor2n_sy@2 do[Mv] do[Lt] net@173 nor2n_sy-X_5_5
-Xnor2n_sy@3 do[Ld] do[Co] net@180 nor2n_sy-X_5_5
-XohPredDo@1 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] net@149 flag[A][clr]
-+flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] mc ps[do]
-+ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] ohPredDo
+XohPredDo@1 do[ins] fire[do] fire[skip] flag[A][clr] flag[A][set]
++flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[do]
++ps[skip] ohPredDo
XohPredPr@1 net@92 net@139 net@160 flag[A][clr] flag[A][set] flag[B][clr]
+flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F]
+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
+m1cate[5][T] m1cate[6][F] m1cate[6][T] mc net@19 s[1] s[2] ohPredPred
-XscanEx2h@0 s[1] s[2] mc p1p p2p rd sin sout scanEx2h
+XscanEx3h@0 s[1] s[2] s[3] mc p1p p2p rd sin sout scanEx3h
Xwire90@0 net@39 net@11 wire90-1000_9-layer_1-width_3
-Xwire90@1 net@186 net@41 wire90-544-layer_1-width_3
+Xwire90@1 net@193 net@41 wire90-544-layer_1-width_3
Xwire90@2 net@46 net@139 wire90-863_3-layer_1-width_3
Xwire90@3 net@21 net@19 wire90-355_3-layer_1-width_3
Xwire90@4 net@82 net@84 wire90-1035_5-layer_1-width_3
Xwire90@5 net@147 net@63 wire90-602_8-layer_1-width_3
Xwire90@6 net@92 net@94 wire90-613_9-layer_1-width_3
-Xwire90@7 net@149 fire[skip] wire90-782-layer_1-width_3
+Xwire90@7 fire[skip] net@144 wire90-782-layer_1-width_3
Xwire90@9 fire[both] net@160 wire90-2516_8-layer_1-width_3
-Xwire90@10 net@173 net@174 wire90-247_4-layer_1-width_3
-Xwire90@11 net@180 net@177 wire90-249_4-layer_1-width_3
-Xwire90@12 net@182 net@183 wire90-244_3-layer_1-width_3
+Xwire90@10 net@206 net@200 wire90-215_4-layer_1-width_3
+Xwire90@11 net@166 fire[do] wire90-782-layer_1-width_3
.ENDS ohPredAll
+*** CELL: centersJ:ctrAND2in100{sch}
+.SUBCKT ctrAND2in100 inA inB out
+Xinv@9 net@163 net@161 inv-X_30
+XinvI@1 net@162 out inv-X_100
+Xnor2n_sy@0 inA inB net@158 nor2n_sy-X_10
+Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3
+Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3
+.ENDS ctrAND2in100
+
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b
-Ccap@0 gnd net@14 6.469f
-Ccap@1 gnd net@8 6.469f
-Ccap@2 gnd net@11 6.469f
-Rres@0 net@14 a 10.194
-Rres@1 net@11 net@14 20.389
-Rres@2 b net@8 10.194
-Rres@3 net@8 net@11 20.389
-.ENDS wire-C_0_011f-1764_4-R_34_667m
+.SUBCKT wire-C_0_011f-431_3-R_34_667m a b
+Ccap@0 gnd net@14 1.581f
+Ccap@1 gnd net@8 1.581f
+Ccap@2 gnd net@11 1.581f
+Rres@0 net@14 a 2.492
+Rres@1 net@11 net@14 4.984
+Rres@2 b net@8 2.492
+Rres@3 net@8 net@11 4.984
+.ENDS wire-C_0_011f-431_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1764_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m
-.ENDS wire90-1764_4-layer_1-width_3
+.SUBCKT wire90-431_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-431_3-R_34_667m
+.ENDS wire90-431_3-layer_1-width_3
+
+*** CELL: loopCountM:ilcLoad{sch}
+.SUBCKT ilcLoad do[ins] ilc[load] sel[Ld] sel[rD]
+XctrAND2i@0 sel[rD] net@12 ilc[load] ctrAND2in100
+Xnand2@0 sel[Ld] do[ins] net@23 nand2-X_5
+XpredDri4@0 ilc[load] do[ins] predDri40
+Xwire90@0 net@23 net@12 wire90-431_3-layer_1-width_3
+.ENDS ilcLoad
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_3_999 d g s
+MNMOSf@0 d g s gnd nch W='11.997*(1+ABN/sqrt(11.997*2))' L='2'
++DELVTO='AVT0N/sqrt(11.997*2)'
+.ENDS NMOSx-X_3_999
+
+*** CELL: redFive:nms3{sch}
+.SUBCKT nms3-X_1_333 d g g2 g3
+XNMOS@0 d g3 net@6 NMOSx-X_3_999
+XNMOS@1 net@7 g gnd NMOSx-X_3_999
+XNMOS@2 net@6 g2 net@7 NMOSx-X_3_999
+.ENDS nms3-X_1_333
+
+*** CELL: driversM:sucDri20or{sch}
+.SUBCKT sucDri20or inA inB succ
+Xinv@1 succ net@94 inv-X_4
+Xnms3b@0 succ net@142 inB inA nms3-X_1_333
+Xpms1@0 succ inA pms1-X_20
+Xpms1@1 succ inB pms1-X_20
+Xwire90@0 net@142 net@94 wire90-124_7-layer_1-width_3
+.ENDS sucDri20or
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b
-Ccap@0 gnd net@14 5.036f
-Ccap@1 gnd net@8 5.036f
-Ccap@2 gnd net@11 5.036f
-Rres@0 net@14 a 7.935
-Rres@1 net@11 net@14 15.87
-Rres@2 b net@8 7.935
-Rres@3 net@8 net@11 15.87
-.ENDS wire-C_0_011f-1373_4-R_34_667m
+.SUBCKT wire-C_0_011f-406_2-R_34_667m a b
+Ccap@0 gnd net@14 1.489f
+Ccap@1 gnd net@8 1.489f
+Ccap@2 gnd net@11 1.489f
+Rres@0 net@14 a 2.347
+Rres@1 net@11 net@14 4.694
+Rres@2 b net@8 2.347
+Rres@3 net@8 net@11 4.694
+.ENDS wire-C_0_011f-406_2-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1373_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m
-.ENDS wire90-1373_4-layer_1-width_3
+.SUBCKT wire90-406_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-406_2-R_34_667m
+.ENDS wire90-406_2-layer_1-width_3
-*** CELL: loopCountM:olcEven{sch}
-.SUBCKT olcEven bit[2] bit[4] bit[6] count[T] do[2] do[4] do[6] inLO[2]
-+inLO[4] inLO[6] load[T]
-Xinv@2 count[T] net@210 inv-X_30
-Xinv@3 load[T] net@211 inv-X_30
-XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
-XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
-XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
-Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3
-Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-488_9-R_34_667m a b
+Ccap@0 gnd net@14 1.793f
+Ccap@1 gnd net@8 1.793f
+Ccap@2 gnd net@11 1.793f
+Rres@0 net@14 a 2.825
+Rres@1 net@11 net@14 5.65
+Rres@2 b net@8 2.825
+Rres@3 net@8 net@11 5.65
+.ENDS wire-C_0_011f-488_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-488_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-488_9-R_34_667m
+.ENDS wire90-488_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-348_7-R_34_667m a b
+Ccap@0 gnd net@14 1.279f
+Ccap@1 gnd net@8 1.279f
+Ccap@2 gnd net@11 1.279f
+Rres@0 net@14 a 2.015
+Rres@1 net@11 net@14 4.029
+Rres@2 b net@8 2.015
+Rres@3 net@8 net@11 4.029
+.ENDS wire-C_0_011f-348_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-348_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-348_7-R_34_667m
+.ENDS wire90-348_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-411_6-R_34_667m a b
+Ccap@0 gnd net@14 1.509f
+Ccap@1 gnd net@8 1.509f
+Ccap@2 gnd net@11 1.509f
+Rres@0 net@14 a 2.378
+Rres@1 net@11 net@14 4.756
+Rres@2 b net@8 2.378
+Rres@3 net@8 net@11 4.756
+.ENDS wire-C_0_011f-411_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-411_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-411_6-R_34_667m
+.ENDS wire90-411_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-147_3-R_34_667m a b
+Ccap@0 gnd net@14 0.54f
+Ccap@1 gnd net@8 0.54f
+Ccap@2 gnd net@11 0.54f
+Rres@0 net@14 a 0.851
+Rres@1 net@11 net@14 1.702
+Rres@2 b net@8 0.851
+Rres@3 net@8 net@11 1.702
+.ENDS wire-C_0_011f-147_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-147_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-147_3-R_34_667m
+.ENDS wire90-147_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-143_2-R_34_667m a b
+Ccap@0 gnd net@14 0.525f
+Ccap@1 gnd net@8 0.525f
+Ccap@2 gnd net@11 0.525f
+Rres@0 net@14 a 0.827
+Rres@1 net@11 net@14 1.655
+Rres@2 b net@8 0.827
+Rres@3 net@8 net@11 1.655
+.ENDS wire-C_0_011f-143_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-143_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-143_2-R_34_667m
+.ENDS wire90-143_2-layer_1-width_3
+
+*** CELL: loopCountM:olcControlD{sch}
+.SUBCKT olcControlD fire[Co] fire[zz] flag[D][clr] flag[D][set] olc[zero]
++olc[zoo] s[1] s[2]
+Xinv@6 olc[zoo] net@180 inv-X_5
+Xinv@7 olc[zero] net@184 inv-X_5
+Xinv@18 flag[D][set] net@550 inv-X_5
+Xinv@19 flag[D][clr] net@545 inv-X_5
+XinvI@0 net@544 s[2] inv-X_10
+XinvI@1 net@549 s[1] inv-X_10
+Xnand2@0 net@288 fire[Co] net@286 nand2-X_5
+Xnand2@1 net@289 fire[zz] net@284 nand2-X_5
+Xnand2@2 olc[zoo] fire[Co] net@279 nand2-X_5
+Xnand2@3 olc[zero] fire[zz] net@281 nand2-X_5
+XsucDri20@3 net@428 net@424 flag[D][clr] sucDri20or
+XsucDri20@4 net@426 net@422 flag[D][set] sucDri20or
+Xwire90@9 net@281 net@422 wire90-406_2-layer_1-width_3
+Xwire90@10 net@279 net@426 wire90-488_9-layer_1-width_3
+Xwire90@11 net@286 net@428 wire90-348_7-layer_1-width_3
+Xwire90@12 net@284 net@424 wire90-411_6-layer_1-width_3
+Xwire90@13 net@180 net@288 wire90-147_3-layer_1-width_3
+Xwire90@14 net@184 net@289 wire90-143_2-layer_1-width_3
+Xwire90@21 net@550 net@549 wire90-142_6-layer_1-width_3
+Xwire90@22 net@545 net@544 wire90-142_6-layer_1-width_3
+.ENDS olcControlD
+
+*** CELL: loopCountM:olcCount{sch}
+.SUBCKT olcCount do[ins] fire[Co] olc[dec] olc[zero] sel[Co]
+XctrAND1i@0 net@12 fire[Co] ctrAND1in30
+XctrAND2i@0 olc[zero] net@12 olc[dec] ctrAND2in100
+Xnand2@0 sel[Co] do[ins] net@23 nand2-X_10
+XpredDri4@0 fire[Co] do[ins] predDri40
+Xwire90@0 net@23 net@12 wire90-431_3-layer_1-width_3
+.ENDS olcCount
+
+*** CELL: redFive:nand2n_sy{sch}
+.SUBCKT nand2n_sy-X_6 ina inb out
+Xnand2_sy@0 ina inb out nand2_sy-X_6
+.ENDS nand2n_sy-X_6
+
+*** CELL: redFive:invLT{sch}
+.SUBCKT invLT-X_3 in out
+XNMOS@0 out in gnd NMOSx-X_6
+XPMOS@0 out in vdd PMOSx-X_3
+.ENDS invLT-X_3
+
+*** CELL: driversM:predDri10wMC{sch}
+.SUBCKT predDri10wMC in mc pred
+XNMOSx@0 pred in gnd NMOSx-X_10
+XNMOSx@1 pred mc gnd NMOSx-X_4
+XinvLT@0 pred net@145 invLT-X_3
+Xpms3@0 pred in net@180 mc pms3-X_1
+Xwire90@0 net@180 net@145 wire90-106_7-layer_1-width_3
+.ENDS predDri10wMC
+
+*** CELL: driversM:sucDri10{sch}
+.SUBCKT sucDri10 in succ
+Xinv@1 succ net@94 inv-X_4
+Xinv@2 in net@110 inv-X_4
+Xnms2@0 succ net@117 net@109 nms2-X_2
+Xpms1@0 succ net@109 pms1-X_10
+Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3
+Xwire90@1 net@110 net@109 wire90-503_4-layer_1-width_3
+.ENDS sucDri10
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-140_6-R_34_667m a b
+Ccap@0 gnd net@14 0.516f
+Ccap@1 gnd net@8 0.516f
+Ccap@2 gnd net@11 0.516f
+Rres@0 net@14 a 0.812
+Rres@1 net@11 net@14 1.625
+Rres@2 b net@8 0.812
+Rres@3 net@8 net@11 1.625
+.ENDS wire-C_0_011f-140_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-140_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-140_6-R_34_667m
+.ENDS wire90-140_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-144_3-R_34_667m a b
+Ccap@0 gnd net@14 0.529f
+Ccap@1 gnd net@8 0.529f
+Ccap@2 gnd net@11 0.529f
+Rres@0 net@14 a 0.834
+Rres@1 net@11 net@14 1.667
+Rres@2 b net@8 0.834
+Rres@3 net@8 net@11 1.667
+.ENDS wire-C_0_011f-144_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-144_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-144_3-R_34_667m
+.ENDS wire90-144_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-215_9-R_34_667m a b
+Ccap@0 gnd net@14 0.792f
+Ccap@1 gnd net@8 0.792f
+Ccap@2 gnd net@11 0.792f
+Rres@0 net@14 a 1.247
+Rres@1 net@11 net@14 2.495
+Rres@2 b net@8 1.247
+Rres@3 net@8 net@11 2.495
+.ENDS wire-C_0_011f-215_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-215_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-215_9-R_34_667m
+.ENDS wire90-215_9-layer_1-width_3
+
+*** CELL: loopCountM:olcLoad{sch}
+.SUBCKT olcLoad do[ins] doneLO[M] fire[zz] mc olc[load] sel[Ld] sel[rD]
+XctrAND3i@2 net@983 net@981 net@979 olc[load] ctrAND3in100A
+Xinv@28 net@905 net@908 inv-X_5
+Xinv@30 sel[rD] net@976 inv-X_5
+Xinv@32 net@1032 net@1057 inv-X_5
+Xinv@34 net@913 inv@34_out inv-X_10
+XinvI@7 net@929 net@913 inv-X_5
+XinvI@8 net@1046 net@937 inv-X_10
+XinvI@11 net@908 invI@11_out inv-X_10
+Xnand2@5 sel[Ld] do[ins] net@956 nand2-X_5
+Xnand2@7 net@1035 do[2] net@1033 nand2-X_5
+Xnand2n_s@1 doneLO[M] net@908 fire[zz] nand2n_sy-X_6
+XpredDri1@0 net@979 mc do[2] predDri10wMC
+XpredDri4@0 net@1032 do[ins] predDri40
+XsucDri10@1 olc[load] do[2] sucDri10
+Xwire90@17 net@1033 net@929 wire90-431_3-layer_1-width_3
+Xwire90@25 net@956 net@979 wire90-140_6-layer_1-width_3
+Xwire90@39 net@1032 net@937 wire90-144_3-layer_1-width_3
+Xwire90@42 net@913 net@905 wire90-215_9-layer_1-width_3
+Xwire90@48 net@976 net@981 wire90-431_3-layer_1-width_3
+Xwire90@50 net@983 do[2] wire90-431_3-layer_1-width_3
+Xwire90@51 net@1035 net@1057 wire90-431_3-layer_1-width_3
+Xwire90@52 net@908 net@1046 wire90-215_9-layer_1-width_3
+.ENDS olcLoad
+
+*** CELL: loopCountM:loadORcount{sch}
+.SUBCKT loadORcount do[ins] doneLO[M] flag[D][clr] flag[D][set] ilc[load] mc
++olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] sel[Co] sel[Ld] sel[rD]
+XilcLoad@0 do[ins] ilc[load] sel[Ld] sel[rD] ilcLoad
+XolcContr@1 net@885 net@880 flag[D][clr] flag[D][set] olc[zero] olc[zoo] s[1]
++s[2] olcControlD
+XolcCount@0 do[ins] net@883 olc[dec] olc[zero] sel[Co] olcCount
+XolcLoad@0 do[ins] doneLO[M] net@882 mc olc[load] sel[Ld] sel[rD] olcLoad
+Xwire90@0 net@882 net@880 wire90-431_3-layer_1-width_3
+Xwire90@1 net@885 net@883 wire90-431_3-layer_1-width_3
+.ENDS loadORcount
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b
+Ccap@0 gnd net@14 6.469f
+Ccap@1 gnd net@8 6.469f
+Ccap@2 gnd net@11 6.469f
+Rres@0 net@14 a 10.194
+Rres@1 net@11 net@14 20.389
+Rres@2 b net@8 10.194
+Rres@3 net@8 net@11 20.389
+.ENDS wire-C_0_011f-1764_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1764_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m
+.ENDS wire90-1764_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b
+Ccap@0 gnd net@14 5.036f
+Ccap@1 gnd net@8 5.036f
+Ccap@2 gnd net@11 5.036f
+Rres@0 net@14 a 7.935
+Rres@1 net@11 net@14 15.87
+Rres@2 b net@8 7.935
+Rres@3 net@8 net@11 15.87
+.ENDS wire-C_0_011f-1373_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1373_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m
+.ENDS wire90-1373_4-layer_1-width_3
+
+*** CELL: loopCountM:olcEven{sch}
+.SUBCKT olcEven bit[2] bit[4] bit[6] count[T] do[2] do[4] do[6] inLO[2]
++inLO[4] inLO[6] load[T]
+Xinv@2 count[T] net@210 inv-X_30
+Xinv@3 load[T] net@211 inv-X_30
+XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
+XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
+XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
+Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3
+Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3
.ENDS olcEven
*** CELL: loopCountM:olcOdd{sch}
Xwire90@5 wire90@5_a do[6] wire90-463_3-layer_1-width_3
.ENDS olc
-*** CELL: centersJ:ctrAND2in100{sch}
-.SUBCKT ctrAND2in100 inA inB out
-Xinv@9 net@163 net@161 inv-X_30
-XinvI@1 net@162 out inv-X_100
-Xnor2n_sy@0 inA inB net@158 nor2n_sy-X_10
-Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3
-Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3
-.ENDS ctrAND2in100
-
-*** CELL: centersJ:ctrAND3in30B{sch}
-.SUBCKT ctrAND3in30B inA inB inC out
-Xinv@4 inC net@30 inv-X_5
-Xinv@5 net@9 out inv-X_30
-Xnand2LT_@0 net@15 net@19 net@27 nand2LT_sy-X_10
-Xnor2n_sy@0 inA inB net@6 nor2n_sy-X_5
-Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
-Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
-Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
-.ENDS ctrAND3in30B
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_1 d g s
-MPMOSf@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2'
-+DELVTO='AVT0P/sqrt(6*2)'
-.ENDS PMOSx-X_1
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_1 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_2
-XNMOS@1 net@0 g gnd NMOSx-X_2
-.ENDS nms2-X_1
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_1 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_1
-XPMOS@1 out inb vdd PMOSx-X_1
-Xnms2@0 out ina inb nms2-X_1
-.ENDS nand2-X_1
-
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_2_5 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_5
-XNMOS@1 net@0 g gnd NMOSx-X_5
-.ENDS nms2-X_2_5
-
-*** CELL: redFive:nms2_sy{sch}
-.SUBCKT nms2_sy-X_5 d g g2
-Xnms2@0 d g g2 nms2-X_2_5
-Xnms2@1 d g2 g nms2-X_2_5
-.ENDS nms2_sy-X_5
-
-*** CELL: redFive:nand2_sy{sch}
-.SUBCKT nand2_sy-X_5 ina inb out
-XPMOS@0 out inb vdd PMOSx-X_5
-XPMOS@1 out ina vdd PMOSx-X_5
-Xnms2_sy@0 out ina inb nms2_sy-X_5
-.ENDS nand2_sy-X_5
-
-*** CELL: redFive:nand2n_sy{sch}
-.SUBCKT nand2n_sy-X_5 ina inb out
-Xnand2_sy@0 ina inb out nand2_sy-X_5
-.ENDS nand2n_sy-X_5
-
-*** CELL: redFive:invLT{sch}
-.SUBCKT invLT-X_3 in out
-XNMOS@0 out in gnd NMOSx-X_6
-XPMOS@0 out in vdd PMOSx-X_3
-.ENDS invLT-X_3
-
-*** CELL: driversL:predDri10wMC{sch}
-.SUBCKT predDri10wMC in mc pred
-XNMOSx@0 pred in gnd NMOSx-X_10
-XNMOSx@1 pred mc gnd NMOSx-X_4
-XinvLT@0 pred net@145 invLT-X_3
-Xpms3@0 pred in net@180 mc pms3-X_1
-Xwire90@0 net@180 net@145 wire90-106_7-layer_1-width_3
-.ENDS predDri10wMC
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_2_5 d g s
-MPMOSf@0 d g s vdd pch W='15*(1+ABP/sqrt(15*2))' L='2'
-+DELVTO='AVT0P/sqrt(15*2)'
-.ENDS PMOSx-X_2_5
-
-*** CELL: redFive:nand2{sch}
-.SUBCKT nand2-X_2_5 ina inb out
-XPMOS@0 out ina vdd PMOSx-X_2_5
-XPMOS@1 out inb vdd PMOSx-X_2_5
-Xnms2@0 out ina inb nms2-X_2_5
-.ENDS nand2-X_2_5
-
-*** CELL: driversL:sucANDdri10{sch}
-.SUBCKT sucANDdri10 inA inB succ
-XPMOSx@0 succ net@51 vdd PMOSx-X_10
-Xinv@0 succ net@71 inv-X_4
-Xnand2@0 inA inB net@67 nand2-X_2_5
-Xnms2@0 succ net@75 net@51 nms2-X_2
-Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3
-Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3
-.ENDS sucANDdri10
-
-*** CELL: driversL:sucDri10{sch}
-.SUBCKT sucDri10 in succ
-Xinv@1 succ net@94 inv-X_4
-Xinv@2 in net@110 inv-X_4
-Xnms2@0 succ net@117 net@109 nms2-X_2
-Xpms1@0 succ net@109 pms1-X_10
-Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3
-Xwire90@1 net@110 net@109 wire90-503_4-layer_1-width_3
-.ENDS sucDri10
-
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_3_999 d g s
-MNMOSf@0 d g s gnd nch W='11.997*(1+ABN/sqrt(11.997*2))' L='2'
-+DELVTO='AVT0N/sqrt(11.997*2)'
-.ENDS NMOSx-X_3_999
-
-*** CELL: redFive:nms3{sch}
-.SUBCKT nms3-X_1_333 d g g2 g3
-XNMOS@0 d g3 net@6 NMOSx-X_3_999
-XNMOS@1 net@7 g gnd NMOSx-X_3_999
-XNMOS@2 net@6 g2 net@7 NMOSx-X_3_999
-.ENDS nms3-X_1_333
-
-*** CELL: driversL:sucDri20or{sch}
-.SUBCKT sucDri20or inA inB succ
-Xinv@1 succ net@94 inv-X_4
-Xnms3b@0 succ net@142 inB inA nms3-X_1_333
-Xpms1@0 succ inA pms1-X_20
-Xpms1@1 succ inB pms1-X_20
-Xwire90@0 net@142 net@94 wire90-124_7-layer_1-width_3
-.ENDS sucDri20or
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-405-R_34_667m a b
-Ccap@0 gnd net@14 1.485f
-Ccap@1 gnd net@8 1.485f
-Ccap@2 gnd net@11 1.485f
-Rres@0 net@14 a 2.34
-Rres@1 net@11 net@14 4.68
-Rres@2 b net@8 2.34
-Rres@3 net@8 net@11 4.68
-.ENDS wire-C_0_011f-405-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-405-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-405-R_34_667m
-.ENDS wire90-405-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-472_9-R_34_667m a b
-Ccap@0 gnd net@14 1.734f
-Ccap@1 gnd net@8 1.734f
-Ccap@2 gnd net@11 1.734f
-Rres@0 net@14 a 2.732
-Rres@1 net@11 net@14 5.465
-Rres@2 b net@8 2.732
-Rres@3 net@8 net@11 5.465
-.ENDS wire-C_0_011f-472_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-472_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-472_9-R_34_667m
-.ENDS wire90-472_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-346_7-R_34_667m a b
-Ccap@0 gnd net@14 1.271f
-Ccap@1 gnd net@8 1.271f
-Ccap@2 gnd net@11 1.271f
-Rres@0 net@14 a 2.003
-Rres@1 net@11 net@14 4.006
-Rres@2 b net@8 2.003
-Rres@3 net@8 net@11 4.006
-.ENDS wire-C_0_011f-346_7-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-346_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-346_7-R_34_667m
-.ENDS wire90-346_7-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-438_9-R_34_667m a b
-Ccap@0 gnd net@14 1.609f
-Ccap@1 gnd net@8 1.609f
-Ccap@2 gnd net@11 1.609f
-Rres@0 net@14 a 2.536
-Rres@1 net@11 net@14 5.072
-Rres@2 b net@8 2.536
-Rres@3 net@8 net@11 5.072
-.ENDS wire-C_0_011f-438_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-438_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-438_9-R_34_667m
-.ENDS wire90-438_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-143_2-R_34_667m a b
-Ccap@0 gnd net@14 0.525f
-Ccap@1 gnd net@8 0.525f
-Ccap@2 gnd net@11 0.525f
-Rres@0 net@14 a 0.827
-Rres@1 net@11 net@14 1.655
-Rres@2 b net@8 0.827
-Rres@3 net@8 net@11 1.655
-.ENDS wire-C_0_011f-143_2-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-143_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-143_2-R_34_667m
-.ENDS wire90-143_2-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-144_3-R_34_667m a b
-Ccap@0 gnd net@14 0.529f
-Ccap@1 gnd net@8 0.529f
-Ccap@2 gnd net@11 0.529f
-Rres@0 net@14 a 0.834
-Rres@1 net@11 net@14 1.667
-Rres@2 b net@8 0.834
-Rres@3 net@8 net@11 1.667
-.ENDS wire-C_0_011f-144_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-144_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-144_3-R_34_667m
-.ENDS wire90-144_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-431_3-R_34_667m a b
-Ccap@0 gnd net@14 1.581f
-Ccap@1 gnd net@8 1.581f
-Ccap@2 gnd net@11 1.581f
-Rres@0 net@14 a 2.492
-Rres@1 net@11 net@14 4.984
-Rres@2 b net@8 2.492
-Rres@3 net@8 net@11 4.984
-.ENDS wire-C_0_011f-431_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-431_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-431_3-R_34_667m
-.ENDS wire90-431_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-485_9-R_34_667m a b
-Ccap@0 gnd net@14 1.782f
-Ccap@1 gnd net@8 1.782f
-Ccap@2 gnd net@11 1.782f
-Rres@0 net@14 a 2.807
-Rres@1 net@11 net@14 5.615
-Rres@2 b net@8 2.807
-Rres@3 net@8 net@11 5.615
-.ENDS wire-C_0_011f-485_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-485_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-485_9-R_34_667m
-.ENDS wire90-485_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-215_9-R_34_667m a b
-Ccap@0 gnd net@14 0.792f
-Ccap@1 gnd net@8 0.792f
-Ccap@2 gnd net@11 0.792f
-Rres@0 net@14 a 1.247
-Rres@1 net@11 net@14 2.495
-Rres@2 b net@8 1.247
-Rres@3 net@8 net@11 2.495
-.ENDS wire-C_0_011f-215_9-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-215_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-215_9-R_34_667m
-.ENDS wire90-215_9-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-140_6-R_34_667m a b
-Ccap@0 gnd net@14 0.516f
-Ccap@1 gnd net@8 0.516f
-Ccap@2 gnd net@11 0.516f
-Rres@0 net@14 a 0.812
-Rres@1 net@11 net@14 1.625
-Rres@2 b net@8 0.812
-Rres@3 net@8 net@11 1.625
-.ENDS wire-C_0_011f-140_6-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-140_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-140_6-R_34_667m
-.ENDS wire90-140_6-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-127_4-R_34_667m a b
-Ccap@0 gnd net@14 0.467f
-Ccap@1 gnd net@8 0.467f
-Ccap@2 gnd net@11 0.467f
-Rres@0 net@14 a 0.736
-Rres@1 net@11 net@14 1.472
-Rres@2 b net@8 0.736
-Rres@3 net@8 net@11 1.472
-.ENDS wire-C_0_011f-127_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-127_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-127_4-R_34_667m
-.ENDS wire90-127_4-layer_1-width_3
-
-*** CELL: loopCountM:olcControl{sch}
-.SUBCKT olcControl Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set]
-+ilc[load] mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3]
-XctrAND1i@4 net@547 fire[Co] ctrAND1in30
-XctrAND2i@5 olc[zero] net@547 olc[dec] ctrAND2in100
-XctrAND2i@9 net@348 net@340 olc[load] ctrAND2in100
-XctrAND2i@10 not[Ld] net@634 ilc[load] ctrAND2in100
-XctrAND3i@0 net@821 net@823 not[Ld] net@612 ctrAND3in30B
-Xinv@6 olc[zoo] net@180 inv-X_5
-Xinv@7 olc[zero] net@184 inv-X_5
-Xinv@14 do[Co] net@386 inv-X_10
-Xinv@18 flag[D][set] net@535 inv-X_5
-Xinv@19 flag[D][clr] net@539 inv-X_5
-Xinv@20 do[Ld] net@576 inv-X_10
-Xinv@21 Dvoid net@605 inv-X_5
-Xinv@22 net@632 net@635 inv-X_5
-Xinv@25 do[zz] net@783 inv-X_5
-Xinv@26 net@887 net@893 inv-X_10
-Xinv@27 do[reD] net@885 inv-X_5
-Xinv@28 net@905 net@907 inv-X_10
-XinvI@2 net@538 s[3] inv-X_10
-XinvI@3 net@534 s[2] inv-X_10
-XinvI@4 not[Ld] s[1] inv-X_10
-XinvI@6 net@940 net@889 inv-X_5
-XinvI@7 net@929 net@913 inv-X_5
-XinvI@8 net@907 net@936 inv-X_10
-XinvI@9 net@893 net@938 inv-X_10
-Xnand2@0 net@288 fire[Co] net@286 nand2-X_5
-Xnand2@1 net@289 fire[zz] net@284 nand2-X_5
-Xnand2@2 olc[zoo] net@728 net@279 nand2-X_5
-Xnand2@3 olc[zero] net@926 net@281 nand2-X_5
-Xnand2@4 do[Ld] do[2] net@944 nand2-X_1
-Xnand2n_s@1 net@891 net@909 fire[zz] nand2n_sy-X_5
-XpredDri1@0 net@340 mc do[2] predDri10wMC
-XpredDri1@1 not[Ld] mc net@632 predDri10wMC
-XpredDri1@2 not[Ld] mc do[zz] predDri10wMC
-XpredDri2@2 fire[Co] mc do[Co] predDri20wMC
-XpredDri2@3 net@946 mc do[reD] predDri20wMC
-XpredORdr@1 ilc[load] net@924 mc do[Ld] predORdri20wMC
-XsucANDdr@2 Dvoid net@612 do[zz] sucANDdri10
-XsucANDdr@3 net@653 net@638 net@632 sucANDdri10
-XsucDri10@0 olc[load] do[2] sucDri10
-XsucDri20@3 net@428 net@424 flag[D][clr] sucDri20or
-XsucDri20@4 net@426 net@422 flag[D][set] sucDri20or
-Xwire90@9 net@281 net@422 wire90-405-layer_1-width_3
-Xwire90@10 net@279 net@426 wire90-472_9-layer_1-width_3
-Xwire90@11 net@286 net@428 wire90-346_7-layer_1-width_3
-Xwire90@12 net@284 net@424 wire90-438_9-layer_1-width_3
-Xwire90@13 net@180 net@288 wire90-143_2-layer_1-width_3
-Xwire90@14 net@184 net@289 wire90-144_3-layer_1-width_3
-Xwire90@17 net@783 net@340 wire90-431_3-layer_1-width_3
-Xwire90@19 net@386 net@547 wire90-485_9-layer_1-width_3
-Xwire90@22 net@885 net@940 wire90-215_9-layer_1-width_3
-Xwire90@23 net@535 net@534 wire90-140_6-layer_1-width_3
-Xwire90@24 net@539 net@538 wire90-140_6-layer_1-width_3
-Xwire90@25 net@576 not[Ld] wire90-140_6-layer_1-width_3
-Xwire90@26 net@638 net@612 wire90-127_4-layer_1-width_3
-Xwire90@27 net@653 net@605 wire90-127_4-layer_1-width_3
-Xwire90@28 net@634 net@635 wire90-127_4-layer_1-width_3
-Xwire90@31 net@823 net@632 wire90-140_6-layer_1-width_3
-Xwire90@32 net@821 do[zz] wire90-140_6-layer_1-width_3
-Xwire90@36 net@348 do[2] wire90-431_3-layer_1-width_3
-Xwire90@37 fire[Co] net@728 wire90-472_9-layer_1-width_3
-Xwire90@39 net@924 net@936 wire90-144_3-layer_1-width_3
-Xwire90@40 net@889 net@887 wire90-215_9-layer_1-width_3
-Xwire90@41 net@891 net@893 wire90-215_9-layer_1-width_3
-Xwire90@42 net@913 net@905 wire90-215_9-layer_1-width_3
-Xwire90@43 net@909 net@907 wire90-215_9-layer_1-width_3
-Xwire90@45 net@926 fire[zz] wire90-215_9-layer_1-width_3
-Xwire90@46 net@929 net@944 wire90-215_9-layer_1-width_3
-Xwire90@47 net@938 net@946 wire90-215_9-layer_1-width_3
-.ENDS olcControl
-
*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-1022_9-R_34_667m a b
Ccap@0 gnd net@14 3.751f
.ENDS wire90-1638_1-layer_1-width_3
*** CELL: loopCountM:olcWcont{sch}
-.SUBCKT olcWcont Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set]
-+ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sin
-+sout
+.SUBCKT olcWcont do[ins] doneLO[M] flag[D][clr] flag[D][set] ilc[load]
++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sel[Co] sel[Ld]
++sel[rD] sin sout
+XloadORco@0 do[ins] doneLO[M] flag[D][clr] flag[D][set] ilc[load] mc olc[dec]
++olc[load] olc[zero] olc[zoo] s[1] s[2] sel[Co] sel[Ld] sel[rD] loadORcount
Xolc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2]
+inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo] olc
-XolcContr@0 Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] ilc[load]
-+mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3] olcControl
+XscanEx2h@0 s[1] s[2] mc p1p p2p rd net@81 sout scanEx2h
XscanEx3h@1 bitt[1] bitt[3] bitt[5] mc p1p p2p rd sin net@46 scanEx3h
-XscanEx3h@2 bitt[2] bitt[4] bitt[6] mc p1p p2p rd net@46 net@48 scanEx3h
-XscanEx3h@3 s[3] s[2] s[1] mc p1p p2p rd net@48 sout scanEx3h
+XscanEx3h@2 bitt[2] bitt[4] bitt[6] mc p1p p2p rd net@46 net@81 scanEx3h
Xwire90@1 olc[zero] wire90@1_b wire90-1022_9-layer_1-width_3
Xwire90@2 olc[zoo] wire90@2_b wire90-810_8-layer_1-width_3
Xwire90@3 olc[load] wire90@3_b wire90-4437_9-layer_1-width_3
.ENDS wire90-867_8-layer_1-width_3
*** CELL: stagesM:outDockCenter{sch}
-.SUBCKT outDockCenter bit[18] bit[19] bit[20] do[Lt] epi[torp] fire[M]
-+fire[do] flag[A][clr] flag[A][set] flag[C][T] flag[D][clr] flag[D][set]
-+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] in[1] in[2] in[3]
-+in[4] in[5] in[6] m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6]
-+m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T]
-+m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T]
-+m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[do] ps[skip] sel[Co] sel[Fl]
-+sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] sor[1] succ[sf]
+.SUBCKT outDockCenter do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set]
++flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
++inLO[6] inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] m1[11] m1[12]
++m1[1] m1[21] m1[22] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9]
++m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T]
++m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T]
++pred[D] pred[T] ps[18] ps[19] ps[20] ps[21] ps[23] ps[24] ps[25] ps[26]
++ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
++sir[9] sor[1] succ[sf]
+XbitAssig@0 bitAssignments
Xflags@0 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T]
+m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9]
+sir[9] sir[3] sir[2] sir[5] sir[1] net@279 flags
-XilcMoveO@0 bit[18] bit[19] do[Mv] do[Tp] do[reD] epi[torp] fire[M]
-+flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6]
-+inLO[8] sir[9] sir[3] sir[2] pred[D] pred[T] sir[5] net@249 sor[1] succ[sf]
-+ilcMoveOut
+XilcMoveO@0 do[ins] net@293 epi[torp] fire[M] flag[D][set] ilc[load] inLO[1]
++inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] sir[9] sir[3] sir[2] pred[D]
++pred[T] sir[5] ps[18] ps[25] ps[19] ps[26] net@249 sor[1] succ[sf] ilcMoveOut
XmuxForD@0 in[1] in[2] in[3] in[4] in[5] in[6] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[8] bit[20] muxForD
-XohPredAl@0 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr]
-+flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F]
-+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
-+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9]
-+sir[3] sir[2] ps[do] ps[skip] sir[5] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv]
-+sel[Tp] sel[rD] net@244 net@249 ohPredAll
-XolcWcont@0 sel[rD] do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] net@165
-+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] sir[9] sir[3] sir[2] sir[5]
-+net@279 net@244 olcWcont
++inLO[4] inLO[5] inLO[6] inLO[8] ps[20] muxForD
+XohPredAl@0 do[ins] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
++flag[D][clr] flag[D][set] m1[22] m1[21] m1cate[1][F] m1cate[1][T]
++m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T]
++m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] sir[3] sir[2]
++ps[do] ps[skip] sir[5] net@244 net@249 ohPredAll
+XolcWcont@0 do[ins] doneLO[M] flag[D][clr] flag[D][set] net@165 inLO[1]
++inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] sir[9] sir[3] sir[2] sir[5] ps[24]
++ps[23] ps[21] net@279 net@244 olcWcont
Xtc[1] tranCap
Xtc[2] tranCap
Xtc[3] tranCap
Xwire90@9 wire90@9_a flag[D][set] wire90-1850-layer_1-width_3
Xwire90@10 wire90@10_a flag[D][clr] wire90-1852-layer_1-width_3
Xwire90@24 net@165 ilc[load] wire90-867_8-layer_1-width_3
+Xwire90@25 net@293 doneLO[M] wire90-867_8-layer_1-width_3
.ENDS outDockCenter
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3405_8-R_34_667m a b
-Ccap@0 gnd net@14 12.488f
-Ccap@1 gnd net@8 12.488f
-Ccap@2 gnd net@11 12.488f
-Rres@0 net@14 a 19.678
-Rres@1 net@11 net@14 39.356
-Rres@2 b net@8 19.678
-Rres@3 net@8 net@11 39.356
-.ENDS wire-C_0_011f-3405_8-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3405_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3405_8-R_34_667m
-.ENDS wire90-3405_8-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-5146_2-R_34_667m a b
Ccap@0 gnd net@14 18.869f
Ccap@1 gnd net@8 18.869f
.ENDS wire90-3136_9-layer_1-width_3
*** CELL: stagesM:outDockPredStage{sch}
-.SUBCKT outDockPredStage do[Lt] epi[torp] fire[M] flag[A][clr] flag[A][set]
+.SUBCKT outDockPredStage do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set]
+flag[C][T] flag[D][clr] flag[D][set] in[1] in[2] in[3] in[4] in[5] in[6]
+m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1]
-+m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2]
-+m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6]
-+m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T]
-+m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T]
-+m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14]
-+ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6]
-+ps[7] ps[8] ps[9] ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] sor[1] succ[sf]
-XdockPSre@0 net@39 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
++m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[2] m1[3] m1[4]
++m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F]
++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F]
++m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12]
++ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2]
++ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] sir[1] sir[2]
++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[sf]
+XdockPSre@0 do[ins] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27]
-+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3]
-+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5]
-+inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17]
-+ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27]
-+ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3]
-+ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] dockPSre@0_take[1] dockPSreg
-XoutDockC@0 ps[18] ps[19] ps[20] do[Lt] epi[torp] fire[M] net@6 flag[A][clr]
-+flag[A][set] flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3]
-+inLO[4] inLO[5] inLO[6] inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10]
-+m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9]
-+m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T]
-+m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T]
-+pred[D] pred[T] ps[do] ps[skip] m1[24] m1[22] m1[23] m1[27] m1[25] m1[26]
-+m1[21] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1]
-+succ[sf] outDockCenter
-Xwire90@0 net@6 net@39 wire90-3405_8-layer_1-width_3
++m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] inLO[1] inLO[2] inLO[3]
++inLO[4] inLO[5] inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15]
++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25]
++ps[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] dockPSreg
+XoutDockC@0 net@101 epi[torp] fire[M] flag[A][clr] flag[A][set] flag[C][T]
++flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6]
++inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] m1[11] m1[12] m1[1] m1[21]
++m1[22] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F]
++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F]
++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D]
++pred[T] ps[18] ps[19] ps[20] ps[21] ps[23] ps[24] ps[25] ps[26] ps[do]
++ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
++sor[1] succ[sf] outDockCenter
Xwire90@1 wire90@1_a inLO[1] wire90-5146_2-layer_1-width_3
Xwire90@2 wire90@2_a inLO[2] wire90-5054_2-layer_1-width_3
Xwire90@3 wire90@3_a inLO[3] wire90-4771_5-layer_1-width_3
Xwire90@5 wire90@5_a inLO[5] wire90-4475_8-layer_1-width_3
Xwire90@6 wire90@6_a inLO[6] wire90-4496_1-layer_1-width_3
Xwire90@7 wire90@7_a inLO[8] wire90-3136_9-layer_1-width_3
+Xwire90@8 net@101 do[ins] wire90-5146_2-layer_1-width_3
.ENDS outDockPredStage
*** CELL: orangeTSMC090nm:wire{sch}
.ENDS wire90-3539_8-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1810_5-R_34_667m a b
-Ccap@0 gnd net@14 6.639f
-Ccap@1 gnd net@8 6.639f
-Ccap@2 gnd net@11 6.639f
-Rres@0 net@14 a 10.461
-Rres@1 net@11 net@14 20.921
-Rres@2 b net@8 10.461
-Rres@3 net@8 net@11 20.921
-.ENDS wire-C_0_011f-1810_5-R_34_667m
+.SUBCKT wire-C_0_011f-6608_3-R_34_667m a b
+Ccap@0 gnd net@14 24.23f
+Ccap@1 gnd net@8 24.23f
+Ccap@2 gnd net@11 24.23f
+Rres@0 net@14 a 38.181
+Rres@1 net@11 net@14 76.363
+Rres@2 b net@8 38.181
+Rres@3 net@8 net@11 76.363
+.ENDS wire-C_0_011f-6608_3-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1810_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1810_5-R_34_667m
-.ENDS wire90-1810_5-layer_1-width_3
+.SUBCKT wire90-6608_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-6608_3-R_34_667m
+.ENDS wire90-6608_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1466_1-R_34_667m a b
+Ccap@0 gnd net@14 5.376f
+Ccap@1 gnd net@8 5.376f
+Ccap@2 gnd net@11 5.376f
+Rres@0 net@14 a 8.471
+Rres@1 net@11 net@14 16.942
+Rres@2 b net@8 8.471
+Rres@3 net@8 net@11 16.942
+.ENDS wire-C_0_011f-1466_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1466_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1466_1-R_34_667m
+.ENDS wire90-1466_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1632_5-R_34_667m a b
+Ccap@0 gnd net@14 5.986f
+Ccap@1 gnd net@8 5.986f
+Ccap@2 gnd net@11 5.986f
+Rres@0 net@14 a 9.432
+Rres@1 net@11 net@14 18.864
+Rres@2 b net@8 9.432
+Rres@3 net@8 net@11 18.864
+.ENDS wire-C_0_011f-1632_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1632_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1632_5-R_34_667m
+.ENDS wire90-1632_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1066_4-R_34_667m a b
+Ccap@0 gnd net@14 3.91f
+Ccap@1 gnd net@8 3.91f
+Ccap@2 gnd net@11 3.91f
+Rres@0 net@14 a 6.161
+Rres@1 net@11 net@14 12.323
+Rres@2 b net@8 6.161
+Rres@3 net@8 net@11 12.323
+.ENDS wire-C_0_011f-1066_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1066_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1066_4-R_34_667m
+.ENDS wire90-1066_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1232_5-R_34_667m a b
+Ccap@0 gnd net@14 4.519f
+Ccap@1 gnd net@8 4.519f
+Ccap@2 gnd net@11 4.519f
+Rres@0 net@14 a 7.121
+Rres@1 net@11 net@14 14.242
+Rres@2 b net@8 7.121
+Rres@3 net@8 net@11 14.242
+.ENDS wire-C_0_011f-1232_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1232_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1232_5-R_34_667m
+.ENDS wire90-1232_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1106_7-R_34_667m a b
+Ccap@0 gnd net@14 4.058f
+Ccap@1 gnd net@8 4.058f
+Ccap@2 gnd net@11 4.058f
+Rres@0 net@14 a 6.394
+Rres@1 net@11 net@14 12.789
+Rres@2 b net@8 6.394
+Rres@3 net@8 net@11 12.789
+.ENDS wire-C_0_011f-1106_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1106_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1106_7-R_34_667m
+.ENDS wire90-1106_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1242_8-R_34_667m a b
+Ccap@0 gnd net@14 4.557f
+Ccap@1 gnd net@8 4.557f
+Ccap@2 gnd net@11 4.557f
+Rres@0 net@14 a 7.181
+Rres@1 net@11 net@14 14.361
+Rres@2 b net@8 7.181
+Rres@3 net@8 net@11 14.361
+.ENDS wire-C_0_011f-1242_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1242_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1242_8-R_34_667m
+.ENDS wire90-1242_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1260_9-R_34_667m a b
+Ccap@0 gnd net@14 4.623f
+Ccap@1 gnd net@8 4.623f
+Ccap@2 gnd net@11 4.623f
+Rres@0 net@14 a 7.285
+Rres@1 net@11 net@14 14.57
+Rres@2 b net@8 7.285
+Rres@3 net@8 net@11 14.57
+.ENDS wire-C_0_011f-1260_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1260_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1260_9-R_34_667m
+.ENDS wire90-1260_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1327_2-R_34_667m a b
+Ccap@0 gnd net@14 4.866f
+Ccap@1 gnd net@8 4.866f
+Ccap@2 gnd net@11 4.866f
+Rres@0 net@14 a 7.668
+Rres@1 net@11 net@14 15.337
+Rres@2 b net@8 7.668
+Rres@3 net@8 net@11 15.337
+.ENDS wire-C_0_011f-1327_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1327_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1327_2-R_34_667m
+.ENDS wire90-1327_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1283_7-R_34_667m a b
+Ccap@0 gnd net@14 4.707f
+Ccap@1 gnd net@8 4.707f
+Ccap@2 gnd net@11 4.707f
+Rres@0 net@14 a 7.417
+Rres@1 net@11 net@14 14.834
+Rres@2 b net@8 7.417
+Rres@3 net@8 net@11 14.834
+.ENDS wire-C_0_011f-1283_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1283_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1283_7-R_34_667m
+.ENDS wire90-1283_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1456_1-R_34_667m a b
+Ccap@0 gnd net@14 5.339f
+Ccap@1 gnd net@8 5.339f
+Ccap@2 gnd net@11 5.339f
+Rres@0 net@14 a 8.413
+Rres@1 net@11 net@14 16.826
+Rres@2 b net@8 8.413
+Rres@3 net@8 net@11 16.826
+.ENDS wire-C_0_011f-1456_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1456_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1456_1-R_34_667m
+.ENDS wire90-1456_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1427_2-R_34_667m a b
+Ccap@0 gnd net@14 5.233f
+Ccap@1 gnd net@8 5.233f
+Ccap@2 gnd net@11 5.233f
+Rres@0 net@14 a 8.246
+Rres@1 net@11 net@14 16.492
+Rres@2 b net@8 8.246
+Rres@3 net@8 net@11 16.492
+.ENDS wire-C_0_011f-1427_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1427_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1427_2-R_34_667m
+.ENDS wire90-1427_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1544_9-R_34_667m a b
+Ccap@0 gnd net@14 5.665f
+Ccap@1 gnd net@8 5.665f
+Ccap@2 gnd net@11 5.665f
+Rres@0 net@14 a 8.926
+Rres@1 net@11 net@14 17.852
+Rres@2 b net@8 8.926
+Rres@3 net@8 net@11 17.852
+.ENDS wire-C_0_011f-1544_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1544_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1544_9-R_34_667m
+.ENDS wire90-1544_9-layer_1-width_3
*** CELL: stageGroupsM:outM1PredLit{sch}
.SUBCKT outM1PredLit dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17]
+dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24]
+dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32]
+dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7]
-+dsD[8] dsD[9] net@90 net@79 ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16]
-+ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8]
-+ps[9] signalBitFromInboundSwitchFabric net@48[8] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] litDandP
++dsD[8] dsD[9] net@90 flag[C] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16]
++ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7]
++ps[8] ps[9] signalBitFromInboundSwitchFabric succ[D] succ[T] litDandP
XmOneDock@0 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18]
+m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28]
+m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4]
+ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9]
+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@47[8]
+succ[m1] take[m1] mOneDockStage
-XoutDockP@0 net@91 epi[torp] fire[M] flag[A][clr] flag[A][set] net@82
+XoutDockP@0 do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set] net@82
+flag[D][clr] flag[D][set] dsD[1] dsD[2] dsD[3] dsD[4] dsD[5] dsD[6] m1[10]
+m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20]
-+m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30]
-+m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8]
-+m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F]
-+m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F]
-+m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16]
-+ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8]
-+ps[9] ps[do] ps[skip] net@47[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sir[9] net@48[8] succ[D] outDockPredStage
-Xwire90@0 net@79 net@82 wire90-2993_2-layer_1-width_3
++m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[2] m1[3] m1[4] m1[5]
++m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T]
++m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T]
++m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14]
++ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ps[3] ps[4]
++ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] net@47[8] sir[2] sir[3] sir[4]
++sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] outDockPredStage
+Xwire90@0 flag[C] net@82 wire90-2993_2-layer_1-width_3
Xwire90@1 net@90 fire[M] wire90-3539_8-layer_1-width_3
-Xwire90@2 net@89 net@91 wire90-1810_5-layer_1-width_3
+Xwire90@2 net@89 do[ins] wire90-6608_3-layer_1-width_3
+Xwire90@3 wire90@3_a m1cate[1][T] wire90-1466_1-layer_1-width_3
+Xwire90@4 wire90@4_a m1cate[1][F] wire90-1632_5-layer_1-width_3
+Xwire90@5 wire90@5_a m1cate[2][T] wire90-1066_4-layer_1-width_3
+Xwire90@6 wire90@6_a m1cate[2][F] wire90-1232_5-layer_1-width_3
+Xwire90@7 wire90@7_a m1cate[3][T] wire90-1106_7-layer_1-width_3
+Xwire90@8 wire90@8_a m1cate[3][F] wire90-1242_8-layer_1-width_3
+Xwire90@9 wire90@9_a m1cate[4][T] wire90-1260_9-layer_1-width_3
+Xwire90@10 wire90@10_a m1cate[4][F] wire90-1327_2-layer_1-width_3
+Xwire90@11 wire90@11_a m1cate[5][T] wire90-1283_7-layer_1-width_3
+Xwire90@12 wire90@12_a m1cate[5][F] wire90-1456_1-layer_1-width_3
+Xwire90@13 wire90@13_a m1cate[6][T] wire90-1427_2-layer_1-width_3
+Xwire90@14 wire90@14_a m1cate[6][F] wire90-1544_9-layer_1-width_3
.ENDS outM1PredLit
*** CELL: orangeTSMC090nm:wire{sch}
XdataDriv@0 tok fire take dataDriver60
Xinv@0 pred net@240 inv-X_10
XinvI@0 net@240 s[1] inv-X_10
-XpredDri6@0 fire mc pred driversJ__predDri60wMC
+XpredDri6@1 fire mc pred predDri60wMC
XsucANDdr@2 to[A] fire succ[A] sucANDdri60
XsucANDdr@3 to[B] fire succ[B] sucANDdri60
Xtc[1] tranCap
/* Verilog for cell 'marinaOut{sch}' from library 'aMarinaM' */
/* Created on Mon Nov 17, 2008 08:47:24 */
/* Last revised on Mon Mar 30, 2009 06:59:15 */
-/* Written on Wed Apr 29, 2009 17:24:11 by Electric VLSI Design System, version 8.08k */
+/* Written on Thu Apr 30, 2009 17:07:05 by Electric VLSI Design System, version 8.08k */
module orangeTSMC090nm__wire(a);
input a;
endmodule /* moveM__moveRepeat */
module moveM__moveOut(do_ins_, epi_torp_, ilc_do_, ilc_mo_, mc, pred_D_,
- pred_T_, sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, succ_sf_, do_reD_, fire_M_,
- flag_D__set_, s, winLO_M_);
+ pred_T_, sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, succ_sf_, doneLO_M_,
+ fire_M_, flag_D__set_, s, winLO_M_);
input do_ins_;
input epi_torp_;
input ilc_do_;
input sel_Ti_;
input sel_Tp_;
input succ_sf_;
- output do_reD_;
+ output doneLO_M_;
output fire_M_;
output flag_D__set_;
output [1:3] s;
supply1 vdd;
supply0 gnd;
- wire done_M_, fire_T_, net_194, net_200, net_201, net_205, net_206, net_220;
- wire net_227, net_29, net_326;
+ wire fire_T_, net_194, net_200, net_201, net_205, net_206, net_220, net_227;
+ wire net_250, net_29, net_326;
/* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) inv_9 (net_326, fire_T_);
not (strong0, strong1) #(100) inv_15 (net_29, epi_torp_);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
+ not (strong0, strong1) #(100) inv_16 (doneLO_M_, net_250);
+ // end Verilog_template
+ /* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) invI_9 (s[1], net_194);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
/* begin Verilog_template for redFive:nand2{sch}*/
nand (strong0, strong1) #(100) nand2_3 (net_205, ilc_do_, sel_Ti_);
// end Verilog_template
- redFive__nor2n nor2n_1(.ina(ilc_mo_), .inb(winLO_M_), .out(done_M_));
+ redFive__nor2n nor2n_1(.ina(ilc_mo_), .inb(winLO_M_), .out(net_250));
redFive__nor2n nor2n_5(.ina(net_206), .inb(winLO_M_), .out(net_201));
redFive__nor2n nor2n_6(.ina(net_205), .inb(winLO_M_), .out(net_200));
redFive__nor2n nor2n_7(.ina(net_220), .inb(winLO_M_), .out(fire_M_));
driversM__predDri20wMC predDri2_0(.in(fire_T_), .mc(mc), .pred(epi_torp_));
driversM__predDri20wMC predDri2_3(.in(net_201), .mc(mc), .pred(pred_D_));
driversM__predDri20wMC predDri2_4(.in(net_200), .mc(mc), .pred(pred_T_));
- driversM__predDri40 predDri4_0(.in(done_M_), .pred(do_ins_));
+ driversM__predDri40 predDri4_0(.in(net_250), .pred(do_ins_));
driversM__predDri40 predDri4_1(.in(fire_T_), .pred(do_ins_));
- driversM__sucDri20 sucDri20_0(.in(done_M_), .succ(do_reD_));
orangeTSMC090nm__wire90 wire90_9(.a(net_206));
orangeTSMC090nm__wire90 wire90_10(.a(net_220));
orangeTSMC090nm__wire90 wire90_11(.a(net_200));
orangeTSMC090nm__wire90 wire90_12(.a(net_201));
orangeTSMC090nm__wire90 wire90_13(.a(net_205));
- orangeTSMC090nm__wire90 wire90_15(.a(done_M_));
+ orangeTSMC090nm__wire90 wire90_15(.a(net_250));
orangeTSMC090nm__wire90 wire90_16(.a(fire_T_));
orangeTSMC090nm__wire90 wire90_17(.a(net_326));
endmodule /* moveM__moveOut */
module moveM__ilcMoveOut(do_ins_, epi_torp_, ilc_load_, \inLO[1] , \inLO[2] ,
\inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8] , pred_D_, pred_T_,
- sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, sin, succ_sf_, do_reD_, fire_M_,
+ sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, sin, succ_sf_, doneLO_M_, fire_M_,
flag_D__set_, sout, mc, p1p, p2p, rd);
input do_ins_;
input epi_torp_;
input sel_Tp_;
input sin;
input succ_sf_;
- output do_reD_;
+ output doneLO_M_;
output fire_M_;
output flag_D__set_;
output sout;
.ilc_do_(ilc_do_), .ilc_mo_(ilc_mo_), .mc(mc), .pred_D_(pred_D_),
.pred_T_(pred_T_), .sel_Di_(sel_Di_), .sel_Mv_(sel_Mv_),
.sel_Ti_(sel_Ti_), .sel_Tp_(sel_Tp_), .succ_sf_(succ_sf_),
- .do_reD_(do_reD_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_),
+ .doneLO_M_(doneLO_M_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_),
.s(s[1:3]), .winLO_M_(ilc_decLO_));
scanM__scanEx1h scanEx1h_0(.dIn({s[3]}), .sin(net_84), .mc(mc), .sout(sout),
.p1p(p1p), .p2p(p2p), .rd(rd));
supply1 vdd;
supply0 gnd;
- wire fire_both_, fire_skip_, net_11, net_151, net_19, net_200, net_41, net_46;
- wire net_63, net_82, net_92;
+ wire fire_both_, fire_do_, fire_skip_, net_11, net_19, net_200, net_41;
+ wire net_46, net_63, net_82, net_92;
wire [1:3] s;
wiresL__bitAssignments bitAssig_0();
not (strong0, strong1) #(100) inv_1 (net_200, do_ins_);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_0 (net_151, net_82);
+ not (strong0, strong1) #(100) invI_0 (fire_do_, net_82);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) invI_1 (fire_skip_, net_63);
predicateM__nand3in20sr nand3in2_1(.inA(net_46), .inB(net_41), .inC(net_11),
.resetLO(net_19), .out(net_82));
redFive__nor2n_sy nor2n_sy_0(.ina(ps_skip_), .inb(ps_do_), .out(net_11));
- predicateM__ohPredDo ohPredDo_1(.fire_do_(net_151), .fire_skip_(fire_skip_),
+ predicateM__ohPredDo ohPredDo_1(.fire_do_(fire_do_), .fire_skip_(fire_skip_),
.flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_),
.flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_),
.flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
orangeTSMC090nm__wire90 wire90_7(.a(fire_skip_));
orangeTSMC090nm__wire90 wire90_9(.a(fire_both_));
orangeTSMC090nm__wire90 wire90_10(.a(net_200));
- orangeTSMC090nm__wire90 wire90_11(.a(net_151));
+ orangeTSMC090nm__wire90 wire90_11(.a(fire_do_));
endmodule /* predicateM__ohPredAll */
module centersJ__ctrAND2in100(inA, inB, out);
orangeTSMC090nm__wire90 wire90_1(.a(net_109));
endmodule /* driversM__sucDri10 */
-module loopCountM__olcLoad(do_ins_, do_reD_, mc, sel_Ld_, sel_rD_, fire_zz_,
+module loopCountM__olcLoad(do_ins_, doneLO_M_, mc, sel_Ld_, sel_rD_, fire_zz_,
olc_load_);
input do_ins_;
- input do_reD_;
+ input doneLO_M_;
input mc;
input sel_Ld_;
input sel_rD_;
supply1 vdd;
supply0 gnd;
- wire invI_10_out, invI_11_out, inv_33_out, inv_34_out, net_1035, net_885;
- wire net_887, net_891, net_905, net_908, net_929, net_937, net_938, net_956;
- wire net_976;
+ wire invI_11_out, inv_34_out, net_1035, net_905, net_908, net_929, net_937;
+ wire net_956, net_976;
wire [2:2] do;
centersJ__ctrAND3in100A ctrAND3i_2(.inA(do[2]), .inB(net_976), .inC(net_956),
.out(olc_load_));
/* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_26 (net_891, net_887);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_27 (net_885, do_reD_);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) inv_28 (net_908, net_905);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) inv_32 (net_1035, net_937);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_33 (inv_33_out, net_887);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) inv_34 (inv_34_out, net_905);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_6 (net_887, net_885);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) invI_7 (net_905, net_929);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) invI_8 (net_937, net_908);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_9 (net_938, net_891);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) invI_10 (invI_10_out, net_891);
- // end Verilog_template
- /* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) invI_11 (invI_11_out, net_908);
// end Verilog_template
/* begin Verilog_template for redFive:nand2{sch}*/
/* begin Verilog_template for redFive:nand2{sch}*/
nand (strong0, strong1) #(100) nand2_7 (net_929, net_1035, do[2]);
// end Verilog_template
- redFive__nand2n_sy nand2n_s_1(.ina(net_891), .inb(net_908), .out(fire_zz_));
+ redFive__nand2n_sy nand2n_s_1(.ina(doneLO_M_), .inb(net_908),
+ .out(fire_zz_));
driversM__predDri10wMC predDri1_0(.in(net_956), .mc(mc), .pred(do[2]));
- driversM__predDri20wMC predDri2_3(.in(net_938), .mc(mc), .pred(do_reD_));
driversM__predDri40 predDri4_0(.in(net_937), .pred(do_ins_));
driversM__sucDri10 sucDri10_1(.in(olc_load_), .succ(do[2]));
orangeTSMC090nm__wire90 wire90_17(.a(net_929));
- orangeTSMC090nm__wire90 wire90_22(.a(net_885));
orangeTSMC090nm__wire90 wire90_25(.a(net_956));
orangeTSMC090nm__wire90 wire90_39(.a(net_937));
- orangeTSMC090nm__wire90 wire90_40(.a(net_887));
- orangeTSMC090nm__wire90 wire90_41(.a(net_891));
orangeTSMC090nm__wire90 wire90_42(.a(net_905));
- orangeTSMC090nm__wire90 wire90_47(.a(net_938));
orangeTSMC090nm__wire90 wire90_48(.a(net_976));
orangeTSMC090nm__wire90 wire90_50(.a(do[2]));
orangeTSMC090nm__wire90 wire90_51(.a(net_1035));
orangeTSMC090nm__wire90 wire90_52(.a(net_908));
endmodule /* loopCountM__olcLoad */
-module loopCountM__loadORcount(do_ins_, do_reD_, mc, olc_zero_, olc_zoo_,
+module loopCountM__loadORcount(do_ins_, doneLO_M_, mc, olc_zero_, olc_zoo_,
sel_Co_, sel_Ld_, sel_rD_, flag_D__clr_, flag_D__set_, ilc_load_,
olc_dec_, olc_load_, s);
input do_ins_;
- input do_reD_;
+ input doneLO_M_;
input mc;
input olc_zero_;
input olc_zoo_;
.flag_D__set_(flag_D__set_), .s(s[1:2]));
loopCountM__olcCount olcCount_0(.do_ins_(do_ins_), .olc_zero_(olc_zero_),
.sel_Co_(sel_Co_), .fire_Co_(net_883), .olc_dec_(olc_dec_));
- loopCountM__olcLoad olcLoad_0(.do_ins_(do_ins_), .do_reD_(do_reD_), .mc(mc),
- .sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .fire_zz_(net_880),
+ loopCountM__olcLoad olcLoad_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_),
+ .mc(mc), .sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .fire_zz_(net_880),
.olc_load_(olc_load_));
orangeTSMC090nm__wire90 wire90_0(.a(net_880));
orangeTSMC090nm__wire90 wire90_1(.a(net_883));
orangeTSMC090nm__wire90 wire90_5(.a(do[6]));
endmodule /* loopCountM__olc */
-module loopCountM__olcWcont(do_ins_, do_reD_, inLO, sel_Co_, sel_Ld_, sel_rD_,
- sin, flag_D__clr_, flag_D__set_, ilc_load_, sout, mc, p1p, p2p, rd);
+module loopCountM__olcWcont(do_ins_, doneLO_M_, inLO, sel_Co_, sel_Ld_,
+ sel_rD_, sin, flag_D__clr_, flag_D__set_, ilc_load_, sout, mc, p1p, p2p,
+ rd);
input do_ins_;
- input do_reD_;
+ input doneLO_M_;
input [1:6] inLO;
input sel_Co_;
input sel_Ld_;
wire [1:6] bitt;
wire [1:2] s;
- loopCountM__loadORcount loadORco_0(.do_ins_(do_ins_), .do_reD_(do_reD_),
+ loopCountM__loadORcount loadORco_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_),
.mc(mc), .olc_zero_(olc_zero_), .olc_zoo_(olc_zoo_), .sel_Co_(sel_Co_),
.sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .flag_D__clr_(flag_D__clr_),
.flag_D__set_(flag_D__set_), .ilc_load_(ilc_load_), .olc_dec_(olc_dec_),
supply1 vdd;
supply0 gnd;
- wire do_reD_, flag_B__clr_, flag_B__set_, ilc_load_, net_244, net_249;
+ wire doneLO_M_, flag_B__clr_, flag_B__set_, ilc_load_, net_244, net_249;
wire net_279;
wiresL__bitAssignments bitAssig_0();
.\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8] ), .pred_D_(pred_D_),
.pred_T_(pred_T_), .sel_Di_( \ps[18] ), .sel_Mv_( \ps[25] ), .sel_Ti_(
\ps[19] ), .sel_Tp_( \ps[26] ), .sin(net_249), .succ_sf_(succ_sf_),
- .do_reD_(do_reD_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_),
+ .doneLO_M_(doneLO_M_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_),
.sout(sor[1]), .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
loopCountM__muxForD muxForD_0(.in(in[1:6]), .sel( \ps[20] ), .outLO({
\inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] ,
.m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_), .sin(net_244),
.do_ins_(do_ins_), .ps_do_(ps_do_), .ps_skip_(ps_skip_), .sout(net_249),
.mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
- loopCountM__olcWcont olcWcont_0(.do_ins_(do_ins_), .do_reD_(do_reD_), .inLO({
- \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] }),
- .sel_Co_( \ps[24] ), .sel_Ld_( \ps[23] ), .sel_rD_( \ps[21] ),
- .sin(net_279), .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_),
- .ilc_load_(ilc_load_), .sout(net_244), .mc(sir[9]), .p1p(sir[3]),
- .p2p(sir[2]), .rd(sir[5]));
+ loopCountM__olcWcont olcWcont_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_),
+ .inLO({ \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] ,
+ \inLO[6] }), .sel_Co_( \ps[24] ), .sel_Ld_( \ps[23] ), .sel_rD_( \ps[21]
+ ), .sin(net_279), .flag_D__clr_(flag_D__clr_),
+ .flag_D__set_(flag_D__set_), .ilc_load_(ilc_load_), .sout(net_244),
+ .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
wiresL__tranCap tc_1_();
wiresL__tranCap tc_2_();
wiresL__tranCap tc_3_();
orangeTSMC090nm__wire90 wire90_9(.a(flag_D__set_));
orangeTSMC090nm__wire90 wire90_10(.a(flag_D__clr_));
orangeTSMC090nm__wire90 wire90_24(.a(ilc_load_));
- orangeTSMC090nm__wire90 wire90_25(.a(do_reD_));
+ orangeTSMC090nm__wire90 wire90_25(.a(doneLO_M_));
endmodule /* stagesM__outDockCenter */
module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_,
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