removed files that should not be revision controlled

diff --git a/src/edu/berkeley/fleet/slipway/alu1.v b/src/edu/berkeley/fleet/slipway/alu1.v
deleted file mode 100644 (file)
index ac813d0..0000000
--- a/src/edu/berkeley/fleet/slipway/alu1.v
+++ /dev/null
@@ -1,45 +0,0 @@
-`include "macros.v"
-
-module alu1 (clk, 
-             a_r,    a_a_,  a_d,
-             op_r,   op_a_, op_d,
-             out_r_, out_a, out_d_);
-
-  input  clk;
-  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
-  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
-  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
-  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
-
-  reg                    have_a;
-  reg [(`DATAWIDTH-1):0] reg_a;
-  reg                    have_op;
-  reg [(`DATAWIDTH-1):0] reg_op;
-
-  always @(posedge clk) begin
-    if (!have_a) begin
-      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
-      end
-    if (!have_op) begin
-      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
-      end
-  
-    if (have_a && have_op) begin
-      case (reg_op)
-        0: out_d = -reg_a;
-        1: out_d = reg_a+1;
-        2: out_d = reg_a-1;
-        3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
-        default: out_d = 0;
-      endcase        
-      `onwrite(out_r, out_a)
-        have_a  = 0;
-        have_op = 0;
-      end
-    end
-  end
-
-endmodule
-
-
-

diff --git a/src/edu/berkeley/fleet/slipway/alu2.v b/src/edu/berkeley/fleet/slipway/alu2.v
deleted file mode 100644 (file)
index 57b11d2..0000000
--- a/src/edu/berkeley/fleet/slipway/alu2.v
+++ /dev/null
@@ -1,55 +0,0 @@
-`include "macros.v"
-
-module alu2 (clk, 
-             a_r,    a_a_,  a_d,
-             b_r,    b_a_,  b_d,
-             op_r,   op_a_, op_d,
-             out_r_, out_a, out_d_);
-
-  input  clk;
-  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
-  `input(b_r,    b_a,    b_a_,  [(`DATAWIDTH-1):0], b_d)
-  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
-  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
-  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
-
-  reg                    have_a;
-  reg [(`DATAWIDTH-1):0] reg_a;
-  reg                    have_b;
-  reg [(`DATAWIDTH-1):0] reg_b;
-  reg                    have_op;
-  reg [(`DATAWIDTH-1):0] reg_op;
-
-  always @(posedge clk) begin
-    if (!have_a) begin
-      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
-      end
-    if (!have_b) begin
-      `onread(b_r, b_a) have_b = 1; reg_b = b_d; end
-      end
-    if (!have_op) begin
-      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
-      end
-  
-    if (have_a && have_b && have_op) begin
-      case (reg_op)
-        0: out_d = reg_a + reg_b;
-        1: out_d = reg_a - reg_b;
-        //2: out_d = reg_a * reg_b; // will not synthesize --AM
-        //3: out_d = reg_a / reg_b; // will not synthesize --AM
-        //4: out_d = reg_a % reg_b; // will not synthesize --AM
-        default: out_d = 0;
-      endcase        
-      `onwrite(out_r, out_a)
-        have_a  = 0;
-        have_b  = 0;
-        have_op = 0;
-      end
-    end
-  end
-
-endmodule
-
-
-
-

diff --git a/src/edu/berkeley/fleet/slipway/debug.v b/src/edu/berkeley/fleet/slipway/debug.v
deleted file mode 100644 (file)
index 30a6474..0000000
--- a/src/edu/berkeley/fleet/slipway/debug.v
+++ /dev/null
@@ -1,21 +0,0 @@
-`include "macros.v"
-
-module debug (clk, data_debug_data_r, data_debug_data_a, data_debug_data,
-                   data_debug_out_r, data_debug_out_a, data_debug_out );
-  input clk;
-
-  input  data_debug_data_r;
-  output data_debug_data_a;
-  input  [`DATAWIDTH:0] data_debug_data;
-
-  output  data_debug_out_r;
-  input   data_debug_out_a;
-  output  [`DATAWIDTH:0] data_debug_out;
-
-  assign  data_debug_out_r  = data_debug_data_r;
-  assign  data_debug_data_a = data_debug_out_a;
-  assign  data_debug_out    = data_debug_data;
-
-endmodule
-
-

diff --git a/src/edu/berkeley/fleet/slipway/execute.v b/src/edu/berkeley/fleet/slipway/execute.v
deleted file mode 100644 (file)
index d8486dc..0000000
--- a/src/edu/berkeley/fleet/slipway/execute.v
+++ /dev/null
@@ -1,50 +0,0 @@
-`include "macros.v"
-
-module execute (clk, command_r,   command_a_, command_d,
-                     ihorn_r_, ihorn_a, ihorn_d_,
-                     dhorn_r_, dhorn_a, dhorn_d_
-               );
-  input clk;
-
-  `input(command_r,   command_a,   command_a_, [(`DATAWIDTH-1):0], command_d)
-  `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
-  `defreg(ihorn_d_,                   [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
-  `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
-  `defreg(dhorn_d_,                   [(`PACKET_WIDTH-1):0], dhorn_d)
-
-  reg ihorn_full;
-  reg dhorn_full;
-
-  always @(posedge clk) begin
-    if (ihorn_full) begin
-      `onwrite(ihorn_r, ihorn_a)
-        ihorn_full = 0;
-      end
-    end else if (dhorn_full) begin
-      `onwrite(dhorn_r, dhorn_a)
-        dhorn_full = 0;
-      end
-    end else begin
-      `onread(command_r, command_a)
-        case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
-          0: begin
-              ihorn_full  = 1;
-              ihorn_d = command_d;
-              end
-          //01:
-          2: begin
-              dhorn_full  = 1;
-              `packet_data(dhorn_d) = command_d[23:0];
-              `packet_dest(dhorn_d) = command_d[34:24];
-              end
-          //11:
-        endcase
-      end
-    end
-  end
-
-
-endmodule
-
-
-

diff --git a/src/edu/berkeley/fleet/slipway/fifo.v b/src/edu/berkeley/fleet/slipway/fifo.v
deleted file mode 100644 (file)
index 6bff619..0000000
--- a/src/edu/berkeley/fleet/slipway/fifo.v
+++ /dev/null
@@ -1,27 +0,0 @@
-`include "macros.v"
-
-// fifo *ship*: a 16-deep word-wide fifo
-module fifo (clk, 
-             in_r,  in_a, in_d,
-             out_r, out_a, out_d);
-
-  input  clk;
-  input  in_r;
-  input  out_a;
-  output in_a;
-  output out_r;
-  input  [(`DATAWIDTH-1):0] in_d;
-  output [(`DATAWIDTH-1):0] out_d;
-
-  wire   [(`DATAWIDTH-1):0] d12;
-  wire   [(`DATAWIDTH-1):0] d23;
-  wire   [(`DATAWIDTH-1):0] d34;
-
-  fifo4 s1(clk, in_r, in_a, in_d, r12, a12,     d12);
-  fifo4 s2(clk, r12,  a12,  d12,  r23, a23,     d23);
-  fifo4 s3(clk, r23,  a23,  d23,  r34, a34,     d34);
-  fifo4 s4(clk, r34,  a34,  d34,  out_r, out_a, out_d);
-
-endmodule
-
-