end
== Test ==============================================================================
-#skip
+// expected output
+#expect 10
+#expect 8
+#expect 9
+#expect -9
+#expect 9
+
+#ship debug : Debug
+#ship alu1 : Alu1
+
+debug.in: [*] take, deliver;
+9: sendto alu1.in;
+9: sendto alu1.in;
+9: sendto alu1.in;
+9: sendto alu1.in;
+
+1: sendto alu1.inOp;
+2: sendto alu1.inOp;
+3: sendto alu1.inOp;
+0: sendto alu1.inOp;
+0: sendto alu1.inOp;
+
+alu1.in: [*] take, deliver;
+alu1.inOp: [*] take, deliver;
+alu1.out:
+ [3] take, sendto debug.in;
+ take;
+ sendto debug.in;
+ sendto alu1.in;
+ [*] take, sendto debug.in;
== Contributors =========================================================
end
== Test ==============================================================================
-#skip
+// expected output
+#ship debug : Debug
+#ship alu : Alu2
+
+#expect 17
+#expect 1
+#expect 8
+#expect 9
+
+debug.in: [*] take, deliver;
+9: sendto alu.in1;
+9: sendto alu.in1;
+9: sendto alu.in1;
+9: sendto alu.in1;
+8: sendto alu.in2;
+8: sendto alu.in2;
+8: sendto alu.in2;
+8: sendto alu.in2;
+
+Alu2.ADD: sendto alu.inOp;
+Alu2.SUB: sendto alu.inOp;
+Alu2.MIN: sendto alu.inOp;
+Alu2.MAX: sendto alu.inOp;
+
+alu.in1: [*] take, deliver;
+alu.in2: [*] take, deliver;
+alu.inOp: [*] take, deliver;
+alu.out: [*] take, sendto debug.in;
== Test ==============================================================================
#skip
+#ship debug : Debug
+#expect 0
+0: sendto debug.in;
== Contributors =========================================================
0: sendto bitfifo.inEnqueue;
bitfifo.inEnqueue: [*] take, deliver;
bitfifo.outDequeue: [*] wait, take, sendto lut3.in2;
-lut3.in2: [2] notify bitfifo.outDequeue;
+lut3.in2: [5] notify bitfifo.outDequeue;
[74] take, deliver, notify bitfifo.outDequeue;
// mux on second input
== Test ==============================================================================
#skip
+#ship debug : Debug
+#expect 0
+0: sendto debug.in;
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
== Test ==============================================================================
#skip
+#ship debug : Debug
+#expect 0
+0: sendto debug.in;
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
}
== FleetSim ==============================================================
-== FPGA ==============================================================
-`include "macros.v"
-
-// fifo *ship*: a 16-deep word-wide fifo
-module fifo (clk,
- in_r, in_a, in_d,
- out_r, out_a, out_d);
-
- input clk;
- input in_r;
- input out_a;
- output in_a;
- output out_r;
- input [(`DATAWIDTH-1):0] in_d;
- output [(`DATAWIDTH-1):0] out_d;
-
- wire [(`DATAWIDTH-1):0] d12;
- wire [(`DATAWIDTH-1):0] d23;
- wire [(`DATAWIDTH-1):0] d34;
-
- fifo4 s1(clk, in_r, in_a, in_d, r12, a12, d12);
- fifo4 s2(clk, r12, a12, d12, r23, a23, d23);
- fifo4 s3(clk, r23, a23, d23, r34, a34, d34);
- fifo4 s4(clk, r34, a34, d34, out_r, out_a, out_d);
-
-endmodule
== Test =================================================================
// expected output
debug.in: [*] take, deliver;
9: sendto fifo.in;
fifo.in:
- take;
- [100] deliver;
+ [100] take, deliver;
fifo.out:
- (99) take, sendto fifo.in;
- (1) take, sendto debug.in;
+ [99] take, sendto fifo.in;
+ [1] take, sendto debug.in;
== Test ==============================================================================
#skip
+#ship debug : Debug
+#expect 0
+0: sendto debug.in;
+
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
[*] nop;
(*) wait, take, sendto lut.inLut;
(*) sendto alu.in;
- kill;
+ kill*;
// acks from debug ship trigger new truth tables
debug.in: [*] take, deliver, notify alu.out;