icache bug fixes (was emitting extraneous instructions)
authoradam <adam@megacz.com>
Thu, 8 Feb 2007 03:49:11 +0000 (04:49 +0100)
committeradam <adam@megacz.com>
Thu, 8 Feb 2007 03:49:11 +0000 (04:49 +0100)
src/edu/berkeley/fleet/slipway/icache.v

index 637157d..280ded8 100644 (file)
@@ -28,8 +28,11 @@ module icache (clk,
   `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)
 
   reg ihorn_full;
+  initial ihorn_full = 0;
   reg dhorn_full;
+  initial dhorn_full = 0;
   reg command_valid;
+  initial command_valid = 0;
 
   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
@@ -55,6 +58,7 @@ module icache (clk,
   wire [(`BRAM_DATA_WIDTH-1):0]   ramread;
 
   reg command_valid_read;
+  initial command_valid_read = 0;
 
   reg launched;
   initial launched = 0;
@@ -85,7 +89,7 @@ module icache (clk,
       write_addr        <= write_addr_d;
       write_data        <= write_data_d;
 
-    end else if (ihorn_full) begin
+    end else if (ihorn_full && launched) begin
       `onwrite(ihorn_r, ihorn_a)
         ihorn_full <= 0;
       end
@@ -159,12 +163,6 @@ module icache (clk,
         end
       end
     end
-/*
-    if (write_flag) begin
-      write_flag = 0;
-      ram[write_addr]  <= write_data;
-    end
-*/
   end
 endmodule