genvar i;
generate
for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
- assign out[i] = inLut_d[{in3_d[i], in2_d[i], in1_d[i]}];
+ assign out[i] = reg_inLut[{reg_in3[i], reg_in2[i], reg_in1[i]}];
end
endgenerate
always @(posedge clk) begin
if (!have_in1) begin
`onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
- end
+ end else
if (!have_in2) begin
`onread(in2_r, in2_a) have_in2 = 1; reg_in2 = in2_d; end
- end
+ end else
if (!have_in3) begin
`onread(in3_r, in3_a) have_in3 = 1; reg_in3 = in3_d; end
- end
+ end else
if (!have_inLut) begin
`onread(inLut_r, inLut_a) have_inLut = 1; reg_inLut = inLut_d; end
- end
+ end else
if (have_in1 && have_in2 && have_in3 && have_inLut) begin
out_d = out;