#remote_xilinx = /opt/ISE81/
#remote_dir = fleet/
-host = mm2.millennium.berkeley.edu
+host = intel2950-4.eecs.berkeley.edu
remote_xilinx = /scratch/megacz/xilinx/
remote_dir = /scratch/megacz/fleet/
+#host = mm2.millennium.berkeley.edu
+#remote_xilinx = /scratch/megacz/xilinx/
+#remote_dir = /scratch/megacz/fleet/
+
xilinx = cd build;
xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin
xilinx += XILINX=$(XILINX)
do java -cp build/class edu.berkeley.fleet.Main target=fpga expand $$A;\
done
rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir}
- ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_xilinx}'
+ time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_xilinx}'
scp ${host}:${remote_dir}/build/main.bit build/
synth:
cd build; mkdir -p tmp
cd build; mkdir -p xst
rm -rf build/_ngo
- $(xilinx)xst -intstyle ise -ifn main.xst -ofn main.syr < main.xst
- $(xilinx)ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
- $(xilinx)map -intstyle ise -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
- $(xilinx)par -w -intstyle ise -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
- $(xilinx)bitgen -intstyle ise -d -f main.ut main.ncd
-# $(xilinx)trce -intstyle ise -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf
+ $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
+ $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
+ $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
+ $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
+ $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd
+# $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf
manual: fleet.jar
test: fleet.jar; $(java) -jar fleet.jar test tests/
testfpga: fleet.jar; $(java) -jar fleet.jar target=fpga test tests/
+generate: fleet.jar
+ $(java) -cp fleet.jar edu.berkeley.fleet.slipway.Generator
+
## API docs ####################################################################################
javadoc:
== FleetSim ==============================================================
== FPGA ==============================================================
- reg have_a;
+ reg have_a;
reg [(`PACKET_WIDTH-1):0] reg_a;
- reg have_op;
+ reg have_op;
reg [(`PACKET_WIDTH-1):0] reg_op;
reg [(`PACKET_WIDTH-1):0] extrabits;
== Constants ========================================================
== TeX ==============================================================
+\begin{verbatim}
+
+TODO: have some way to log multiple separate streams; use sibling
+ ports to deliver an opcode
+
+TODO: have a way to programmatically read back the output of the debug
+ ship?
+
+\end{verbatim}
== Fleeterpreter ====================================================
public void service() {
== Constants ========================================================
== TeX ==============================================================
+\begin{verbatim}
+TODO: count/stride
+TODO: multiple interfaces to a single memory
+\end{verbatim}
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
== FleetSim ==============================================================
== FPGA ==============================================================
-
+/* FIXME: inefficient */
reg [(`DATAWIDTH-1):0] mem [4:0];
reg [5:0] depth;
reg skip;
--- /dev/null
+// note: got rid of funnel "fairness" code
+package edu.berkeley.fleet.slipway;
+import edu.berkeley.fleet.slipway.*;
+import edu.berkeley.fleet.doc.*;
+import edu.berkeley.fleet.api.*;
+import edu.berkeley.fleet.ies44.*;
+import edu.berkeley.fleet.*;
+import java.lang.reflect.*;
+import edu.berkeley.sbp.chr.*;
+import edu.berkeley.sbp.misc.*;
+import edu.berkeley.sbp.meta.*;
+import edu.berkeley.sbp.util.*;
+import java.util.*;
+import java.io.*;
+
+public class Generator {
+
+
+ public static class Module {
+ private int id = 0;
+ private HashSet<InstantiatedModule> instantiatedModules =
+ new HashSet<InstantiatedModule>();
+ private final String name;
+ public String getName() { return name; }
+
+ private final HashSet<Action> actions = new HashSet<Action>();
+
+ // FIXME: always-alphabetical convention?
+ private final HashMap<String,Port> ports = new HashMap<String,Port>();
+ private final ArrayList<String> portorder = new ArrayList<String>();
+
+ public Module(String name) {
+ this.name = name;
+ }
+
+ public SourcePort getInputPort(String name, int width) {
+ SourcePort ret = (SourcePort)ports.get(name);
+ if (ret==null) ret = new SourcePort(name, width, true);
+ return ret;
+ }
+ public SinkPort getOutputPort(String name, int width, String resetBehavior) {
+ SinkPort ret = (SinkPort)ports.get(name);
+ if (ret==null) ret = new SinkPort(name, width, true, resetBehavior);
+ return ret;
+ }
+ private abstract class Port {
+ public final String name;
+ public final int width;
+ public boolean hasLatch = false;
+ public boolean external;
+ public Port(String name, int width, boolean external) {
+ this.width = width;
+ this.name = name;
+ this.external = external;
+ ports.put(name, this);
+ if (external)
+ portorder.add(name);
+ }
+ public String getAck() { return name+"_a"; }
+ public String getReq() { return name+"_r"; }
+ public abstract String getInterface();
+ public abstract String getSimpleInterface();
+ public abstract String getDeclaration();
+ public abstract String getAssignments();
+ }
+
+ private class InstantiatedModule {
+ public final Module module;
+ public final int id;
+ public String getName() { return module.getName()+"_"+id; }
+ public InstantiatedModule(Module module) {
+ this.module = module;
+ this.id = Module.this.id++;
+ instantiatedModules.add(this);
+ }
+ public void dump(PrintWriter pw) {
+ pw.println(" " + module.getName() + " " + getName() + "(clk");
+ for(String s : module.portorder)
+ pw.println(", " + getPort(s, module.ports.get(s).width).getSimpleInterface());
+ pw.println(" );");
+ }
+ public Port getPort(String name, int width) {
+ if (module.ports.get(name) instanceof SinkPort)
+ return getInputPort(name, width);
+ return getOutputPort(name, width, "");
+ }
+ public SinkPort getInputPort(String name, int width) {
+ // FIXME: should not re-instantiate, but so what
+ return new SinkPort(getName()+"_"+name, width, false, "");
+ }
+ public SourcePort getOutputPort(String name, int width, String resetBehavior) {
+ // FIXME: should not re-instantiate, but so what
+ return new SourcePort(getName()+"_"+name, width, false);
+ }
+ }
+
+ private class SourcePort extends Port {
+ private SinkPort driven = null;
+ public SourcePort(String name, int width, boolean external) {
+ super(name, width, external); }
+ public String getInterface() { return getReq()+", "+getAck()+"_, "+name+""; }
+ public String getSimpleInterface() { return getReq()+", "+getAck()+", "+name+""; }
+ public String getDeclaration() {
+ StringBuffer sb = new StringBuffer();
+ if (external) {
+ sb.append("input " + name +"_r;\n");
+ sb.append("output " + name +"_a_;\n");
+ sb.append("input ["+(width-1)+":0]" + name +";\n");
+ } else {
+ sb.append("wire " + name +"_r;\n");
+ sb.append("wire ["+(width-1)+":0]" + name +";\n");
+ }
+ if (!hasLatch) {
+ sb.append("wire " + name +"_a;\n");
+ } else {
+ sb.append("reg " + name +"_a;\n");
+ sb.append("initial " + name +"_a = 0;\n");
+ }
+ return sb.toString();
+ }
+ public String getAssignments() {
+ StringBuffer sb = new StringBuffer();
+ if (external) {
+ sb.append("assign " + name +"_a_ = " + name + "_a;\n");
+ }
+ if (driven != null) {
+ sb.append("assign " + driven.name +"_r = " + name + "_r;\n");
+ sb.append("assign " + name +"_a = " + driven.name + "_a;\n");
+ sb.append("assign " + driven.name +" = " + name + ";\n");
+ }
+ return sb.toString();
+ }
+ public void connect(SinkPort driven) {
+ this.driven = driven;
+ }
+ }
+ private class SinkPort extends Port {
+ public final String resetBehavior;
+ public SinkPort(String name, int width, boolean external, String resetBehavior) {
+ super(name, width, external); this.resetBehavior=resetBehavior; }
+ public String getResetBehavior() { return resetBehavior; }
+ public String getInterface() { return name+"_r_, "+name+"_a, "+name+"_"; }
+ public String getSimpleInterface() { return name+"_r, "+name+"_a, "+name; }
+ public String getDeclaration() {
+ StringBuffer sb = new StringBuffer();
+ if (external) {
+ sb.append("output " + name +"_r_;\n");
+ sb.append("input " + name +"_a;\n");
+ sb.append("output ["+(width-1)+":0]" + name +"_;\n");
+ } else {
+ sb.append("wire " + name +"_a;\n");
+ }
+ if (!hasLatch) {
+ sb.append("wire " + name +"_r;\n");
+ sb.append("wire ["+(width-1)+":0]" + name +";\n");
+ } else {
+ sb.append("reg " + name +"_r;\n");
+ sb.append("initial " + name +"_r = 0;\n");
+ sb.append("reg ["+(width-1)+":0]" + name +";\n");
+ sb.append("initial " + name +" = 0;\n");
+ }
+ return sb.toString();
+ }
+ public String getAssignments() {
+ StringBuffer sb = new StringBuffer();
+ if (external) {
+ sb.append("assign " + name +"_r_ = " + name + "_r;\n");
+ sb.append("assign " + name +"_ = " + name + ";\n");
+ }
+ return sb.toString();
+ }
+ }
+
+ public void dump(PrintWriter pw) {
+ pw.println("module "+name+"(clk");
+ for(String name : portorder) {
+ Port p = ports.get(name);
+ pw.println(" , " + p.getInterface());
+ }
+ pw.println(" );");
+ pw.println();
+ pw.println(" input clk;");
+ for(String name : ports.keySet()) {
+ Port p = ports.get(name);
+ pw.println(" " + p.getDeclaration());
+ }
+ for(String name : ports.keySet()) {
+ Port p = ports.get(name);
+ pw.println(" " + p.getAssignments());
+ }
+ for(InstantiatedModule m : instantiatedModules) {
+ m.dump(pw);
+ }
+ pw.println("always @(posedge clk) begin");
+ for(String name : portorder) {
+ Port p = ports.get(name);
+ if (p instanceof SourcePort) {
+ SourcePort ip = (SourcePort)p;
+ if (ip.hasLatch)
+ pw.println("if (!"+ip.getReq()+" && "+ip.getAck()+") "+ip.getAck()+"<=0;");
+ } else {
+ SinkPort op = (SinkPort)p;
+ if (op.hasLatch)
+ pw.println("if ("+op.getReq()+" && "+op.getAck()+") begin "+
+ op.getReq()+"<=0; "+
+ op.getResetBehavior()+" end");
+ }
+ }
+
+ for(Action a : actions) a.dump(pw);
+ pw.println(" begin end");
+ pw.println("end");
+ pw.println("endmodule");
+ }
+
+ private class Action {
+ private String[] triggers;
+ private SourcePort[] inports;
+ private SinkPort[] outports;
+ private Object[] actions;
+ public Action(Object[] triggers, String action) { this(triggers, new Object[] { action }); }
+ public Action(Object[] triggers, Object[] actions) {
+ int numtriggers = 0;
+ int numinports = 0;
+ int numoutports = 0;
+ Module.this.actions.add(this);
+ for(int i=0; i<triggers.length; i++)
+ if (triggers[i] instanceof String) numtriggers++;
+ else if (triggers[i] instanceof SourcePort) {
+ numinports++;
+ ((Port)triggers[i]).hasLatch = true;
+ } else if (triggers[i] instanceof SinkPort) {
+ numoutports++;
+ ((Port)triggers[i]).hasLatch = true;
+ }
+ this.triggers = new String[numtriggers];
+ this.inports = new SourcePort[numinports];
+ this.outports = new SinkPort[numoutports];
+ for(int i=0; i<triggers.length; i++)
+ if (triggers[i] instanceof String) this.triggers[--numtriggers] = (String)triggers[i];
+ else if (triggers[i] instanceof SourcePort) this.inports[--numinports] = (SourcePort)triggers[i];
+ else if (triggers[i] instanceof SinkPort) this.outports[--numoutports] = (SinkPort)triggers[i];
+ this.actions = actions;
+ for(Object o : actions)
+ if (o instanceof SourcePort) ((Port)o).hasLatch = true;
+ else if (o instanceof SinkPort) ((Port)o).hasLatch = true;
+ }
+ public void dump(PrintWriter pw) {
+ pw.print("if (1");
+ for(String s : triggers) pw.print(" && " + s);
+ for(SourcePort ip : inports) pw.print(" && " + ip.getReq() + " && !"+ip.getAck());
+ for(SinkPort op : outports) pw.print(" && !" + op.getReq() + " && !"+op.getAck());
+ pw.println(") begin ");
+ for(Object s : this.actions) {
+ if (s instanceof String) pw.println(s);
+ else if (s instanceof SourcePort) pw.println(((SourcePort)s).getAck() + " <= 1;");
+ else if (s instanceof SinkPort) pw.println(((SinkPort)s).getReq() + " <= 1;");
+ }
+ pw.println("end else ");
+ }
+ }
+ }
+
+ public static final int WORD_WIDTH = 37;
+ public static final int DESTINATION_WIDTH = 11;
+ public static final int PACKET_WIDTH = WORD_WIDTH + DESTINATION_WIDTH;
+
+ public static void main(String[] s) throws Exception {
+ String prefix = "src/edu/berkeley/fleet/slipway/";
+ PrintWriter pw;
+
+ Module funnel = new Module("funnel");
+ Module.SinkPort out = funnel.getOutputPort("out", PACKET_WIDTH, "");
+ Module.SourcePort in1 = funnel.getInputPort("in1", PACKET_WIDTH);
+ Module.SourcePort in2 = funnel.getInputPort("in2", PACKET_WIDTH);
+ funnel.new Action(new Object[] { in1, out }, new Object[] { in1, out, "out = in1;" });
+ funnel.new Action(new Object[] { in2, out }, new Object[] { in2, out, "out = in2;" });
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/funnel.v")));
+ funnel.dump(pw);
+ pw.flush();
+
+ mkhorn( "horn", prefix, PACKET_WIDTH-1, DESTINATION_WIDTH-1, 0, 0);
+ mkhorn("ihorn", prefix, PACKET_WIDTH-1, 34, 24, 0);
+
+ Module fifostage = new Module("fifostage");
+ Module.SourcePort in = fifostage.getInputPort("in", PACKET_WIDTH);
+ Module.SinkPort outf = fifostage.getOutputPort("out", PACKET_WIDTH, "");
+ fifostage.new Action(new Object[] { in, outf }, new Object[] { in, outf, "out = in;" });
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/fifostage.v")));
+ fifostage.dump(pw);
+ pw.flush();
+
+ Module fifo4 = new Module("fifo4");
+ Module.SourcePort inx = fifo4.getInputPort("in", PACKET_WIDTH);
+ Module.SinkPort outx = fifo4.getOutputPort("out", PACKET_WIDTH, "");
+ int len = 4;
+ Module.InstantiatedModule[] stages = new Module.InstantiatedModule[len];
+ for(int i=0; i<=len; i++) {
+ if (i<len) stages[i] = fifo4.new InstantiatedModule(fifostage);
+ Module.SourcePort driver = i==0 ? inx : stages[i-1].getOutputPort("out", PACKET_WIDTH, "");
+ Module.SinkPort driven = i==len ? outx : stages[i].getInputPort("in", PACKET_WIDTH);
+ driver.connect(driven);
+ }
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/fifo4.v")));
+ fifo4.dump(pw);
+ pw.flush();
+ }
+
+ public static void mkhorn(String name,
+ String prefix,
+ int top,
+ int top_of_addr_field,
+ int bot_of_addr_field,
+ int bot) throws Exception {
+ Module horn = new Module(name);
+ Module.SourcePort in = horn.getInputPort("in", PACKET_WIDTH);
+ Module.SinkPort out0 = horn.getOutputPort("out0", PACKET_WIDTH, "");
+ Module.SinkPort out1 = horn.getOutputPort("out1", PACKET_WIDTH, "");
+ String shifted_packet = "{ ";
+ if (top_of_addr_field+1 < top) shifted_packet += " in["+top+":"+(top_of_addr_field+1)+"], ";
+ shifted_packet += " (in["+(top_of_addr_field)+":"+bot_of_addr_field+"] >> 1) ";
+ if (bot_of_addr_field > 0) shifted_packet += ", in["+(bot_of_addr_field-1)+":0] ";
+ shifted_packet += " }";
+ // same behavior as FLEET -- wait for both
+ horn.new Action(new Object[] { in, out0, out1, "(in["+bot_of_addr_field+"]==0)" },
+ new Object[] { in, out0, "out0 = " + shifted_packet + ";" });
+ horn.new Action(new Object[] { in, out0, out1, "(in["+bot_of_addr_field+"]==1)" },
+ new Object[] { in, out1, "out1 = " + shifted_packet + ";" });
+
+ PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v")));
+ horn.dump(pw);
+ pw.flush();
+ }
+
+}
+
+
+
+
public Slipway(String bitfile) {
this.bitfile = bitfile;
createShip("Debug", "debug");
+ createShip("Alu1", "alu1");
+ createShip("Fifo", "fifo1");
+ createShip("Execute", "execute");
+ createShip("Memory", "Memory");
createShip("Alu2", "alu2a");
createShip("Alu2", "alu2b");
createShip("Alu2", "alu2c");
createShip("Alu2", "alu2d");
- createShip("Fifo", "fifo1");
createShip("Fifo", "fifo2");
createShip("Fifo", "fifo3");
createShip("Fifo", "fifo4");
- createShip("Execute", "execute");
- createShip("Memory", "Memory");
createShip("Memory", "Memory");
createShip("Lut3", "lut3");
- createShip("Alu1", "alu1");
- createShip("Alu3", "alu3");
createShip("Choice", "Choice");
createShip("Choice", "Choice");
createShip("Choice", "Choice");
createShip("Choice", "Choice");
createShip("Stack", "Stack");
+ createShip("Alu3", "alu3");
dumpFabric(true);
}
FileOutputStream out = new FileOutputStream(outf);
PrintWriter pw = new PrintWriter(out);
- boolean auto = filename.equals("alu2") || filename.equals("alu1") || filename.equals("alu2b") || filename.equals("lut3") || filename.equals("choice") || filename.equals("alu3") || filename.equals("stack") || filename.equals("mul");
+ boolean auto =
+ !"debug".equals(filename) &&
+ !"execute".equals(filename) &&
+ !"memory".equals(filename) &&
+ !"fifo".equals(filename);
if (auto) {
pw.println("`include \"macros.v\"");
pw.println();
-`include "macros.v"
+module fifo4(clk
+ , in_r, in_a_, in
+ , out_r_, out_a, out_
+ );
-module fifo4 (clk,
- in_r, in_a, in_d,
- out_r, out_a, out_d);
+ input clk;
+ wire fifostage_3_in_a;
+wire fifostage_3_in_r;
+wire [47:0]fifostage_3_in;
- input clk;
- input in_r;
- input out_a;
- output in_a;
- output out_r;
- input [(`PACKET_WIDTH-1):0] in_d;
- output [(`PACKET_WIDTH-1):0] out_d;
+ output out_r_;
+input out_a;
+output [47:0]out_;
+wire out_r;
+wire [47:0]out;
- wire [(`PACKET_WIDTH-1):0] d12;
- wire [(`PACKET_WIDTH-1):0] d23;
- wire [(`PACKET_WIDTH-1):0] d34;
+ wire fifostage_0_out_r;
+wire [47:0]fifostage_0_out;
+wire fifostage_0_out_a;
- fifostage s1(clk, in_r, in_a, in_d, r12, a12, d12);
- fifostage s2(clk, r12, a12, d12, r23, a23, d23);
- fifostage s3(clk, r23, a23, d23, r34, a34, d34);
- fifostage s4(clk, r34, a34, d34, out_r, out_a, out_d);
+ wire fifostage_2_out_r;
+wire [47:0]fifostage_2_out;
+wire fifostage_2_out_a;
+ wire fifostage_1_in_a;
+wire fifostage_1_in_r;
+wire [47:0]fifostage_1_in;
+
+ wire fifostage_0_in_a;
+wire fifostage_0_in_r;
+wire [47:0]fifostage_0_in;
+
+ wire fifostage_1_out_r;
+wire [47:0]fifostage_1_out;
+wire fifostage_1_out_a;
+
+ wire fifostage_3_out_r;
+wire [47:0]fifostage_3_out;
+wire fifostage_3_out_a;
+
+ input in_r;
+output in_a_;
+input [47:0]in;
+wire in_a;
+
+ wire fifostage_2_in_a;
+wire fifostage_2_in_r;
+wire [47:0]fifostage_2_in;
+
+
+ assign out_r_ = out_r;
+assign out_ = out;
+
+ assign fifostage_1_in_r = fifostage_0_out_r;
+assign fifostage_0_out_a = fifostage_1_in_a;
+assign fifostage_1_in = fifostage_0_out;
+
+ assign fifostage_3_in_r = fifostage_2_out_r;
+assign fifostage_2_out_a = fifostage_3_in_a;
+assign fifostage_3_in = fifostage_2_out;
+
+
+
+ assign fifostage_2_in_r = fifostage_1_out_r;
+assign fifostage_1_out_a = fifostage_2_in_a;
+assign fifostage_2_in = fifostage_1_out;
+
+ assign out_r = fifostage_3_out_r;
+assign fifostage_3_out_a = out_a;
+assign out = fifostage_3_out;
+
+ assign in_a_ = in_a;
+assign fifostage_0_in_r = in_r;
+assign in_a = fifostage_0_in_a;
+assign fifostage_0_in = in;
+
+
+ fifostage fifostage_1(clk
+, fifostage_1_in_r, fifostage_1_in_a, fifostage_1_in
+, fifostage_1_out_r, fifostage_1_out_a, fifostage_1_out
+ );
+ fifostage fifostage_2(clk
+, fifostage_2_in_r, fifostage_2_in_a, fifostage_2_in
+, fifostage_2_out_r, fifostage_2_out_a, fifostage_2_out
+ );
+ fifostage fifostage_0(clk
+, fifostage_0_in_r, fifostage_0_in_a, fifostage_0_in
+, fifostage_0_out_r, fifostage_0_out_a, fifostage_0_out
+ );
+ fifostage fifostage_3(clk
+, fifostage_3_in_r, fifostage_3_in_a, fifostage_3_in
+, fifostage_3_out_r, fifostage_3_out_a, fifostage_3_out
+ );
+always @(posedge clk) begin
+ begin end
+end
endmodule
-`include "macros.v"
+module fifostage(clk
+ , in_r, in_a_, in
+ , out_r_, out_a, out_
+ );
-module fifostage (clk,
- in_r, in_a_, in_d,
- out_r_, out_a, out_d_);
+ input clk;
+ output out_r_;
+input out_a;
+output [47:0]out_;
+reg out_r;
+initial out_r = 0;
+reg [47:0]out;
+initial out = 0;
- input clk;
- `input( in_r, in_a, in_a_, [(`PACKET_WIDTH-1):0], in_d)
- `output(out_r, out_r_, out_a, [(`PACKET_WIDTH-1):0], out_d_)
- `defreg(out_d_, [(`PACKET_WIDTH-1):0], out_d)
+ input in_r;
+output in_a_;
+input [47:0]in;
+reg in_a;
+initial in_a = 0;
- reg full;
+ assign out_r_ = out_r;
+assign out_ = out;
- always @(posedge clk) begin
- if (!full) begin
- `onread(in_r, in_a)
- out_d = in_d;
- full = 1;
- end
- end else begin
- `onwrite(out_r, out_a)
- full = 0;
- end
- end
- end
+ assign in_a_ = in_a;
+always @(posedge clk) begin
+if (!in_r && in_a) in_a<=0;
+if (out_r && out_a) begin out_r<=0; end
+if (1 && in_r && !in_a && !out_r && !out_a) begin
+in_a <= 1;
+out_r <= 1;
+out = in;
+end else
+ begin end
+end
endmodule
-`include "macros.v"
+module funnel(clk
+ , out_r_, out_a, out_
+ , in1_r, in1_a_, in1
+ , in2_r, in2_a_, in2
+ );
-module funnel(clk,
- out_r_, out_a, out_d_,
- in1_r, in1_a_, in1_d,
- in2_r, in2_a_, in2_d
- );
+ input clk;
+ output out_r_;
+input out_a;
+output [47:0]out_;
+reg out_r;
+initial out_r = 0;
+reg [47:0]out;
+initial out = 0;
- input clk;
- reg last;
- initial last=0;
- reg full;
- initial full=0;
+ input in2_r;
+output in2_a_;
+input [47:0]in2;
+reg in2_a;
+initial in2_a = 0;
- `input(in1_r, in1_a, in1_a_, [(`PACKET_WIDTH-1):0], in1_d)
- `input(in2_r, in2_a, in2_a_, [(`PACKET_WIDTH-1):0], in2_d)
- `output(out_r, out_r_, out_a, [(`PACKET_WIDTH-1):0], out_d_)
- `defreg(out_d_, [(`PACKET_WIDTH-1):0], out_d)
+ input in1_r;
+output in1_a_;
+input [47:0]in1;
+reg in1_a;
+initial in1_a = 0;
- always @(posedge clk) begin
- if (full) begin
- `onwrite(out_r, out_a)
- full = 0;
- end
- end else begin
- last = ~last;
- if (last) begin
- `onread(in1_r, in1_a)
- full = 1;
- out_d = in1_d;
- end
- end else begin
- `onread(in2_r, in2_a)
- full = 1;
- out_d = in2_d;
- end
- end
- end
- end
-
+ assign out_r_ = out_r;
+assign out_ = out;
+
+ assign in2_a_ = in2_a;
+
+ assign in1_a_ = in1_a;
+
+always @(posedge clk) begin
+if (out_r && out_a) begin out_r<=0; end
+if (!in1_r && in1_a) in1_a<=0;
+if (!in2_r && in2_a) in2_a<=0;
+if (1 && in2_r && !in2_a && !out_r && !out_a) begin
+in2_a <= 1;
+out_r <= 1;
+out = in2;
+end else
+if (1 && in1_r && !in1_a && !out_r && !out_a) begin
+in1_a <= 1;
+out_r <= 1;
+out = in1;
+end else
+ begin end
+end
endmodule
+++ /dev/null
-(clk,
- in_r, in_a_, in_d,
- out0_r_, out0_a, out0_d_,
- out1_r_, out1_a, out1_d_);
-
- input clk;
- reg full;
- reg dir;
- initial full=0;
-
- `input(in_r, in_a, in_a_, [`XWIDTH:0], in_d)
- `output(out0_r, out0_r_, out0_a, [`XWIDTH:0], out0_d_)
- `output(out1_r, out1_r_, out1_a, [`XWIDTH:0], out1_d_)
- `defreg(dat_, [`XWIDTH:0], dat)
-
- assign out0_d_ = dat_;
- assign out1_d_ = dat_;
-
- always @(posedge clk) begin
- if (full) begin
- if (dir==0) begin
- `onwrite(out0_r, out0_a)
- full = 0;
- end
- end else begin
- `onwrite(out1_r, out1_a)
- full = 0;
- end
- end
- end else begin
- `onread(in_r, in_a)
- full = 1;
- dat = in_d;
- dir = `dest_steer(dat);
- `dest(dat) = `dest(dat) >> 1;
- end
- end
- end
-
-endmodule
-`include "macros.v"
-`define XWIDTH (`PACKET_WIDTH-1)
-`define dest(p) `packet_dest(p)
-`define dest_steer(p) `packet_dest_steer(p)
-module horn
-`include "horn.inc"
+module horn(clk
+ , in_r, in_a_, in
+ , out0_r_, out0_a, out0_
+ , out1_r_, out1_a, out1_
+ );
+ input clk;
+ output out1_r_;
+input out1_a;
+output [47:0]out1_;
+reg out1_r;
+initial out1_r = 0;
+reg [47:0]out1;
+initial out1 = 0;
+
+ input in_r;
+output in_a_;
+input [47:0]in;
+reg in_a;
+initial in_a = 0;
+
+ output out0_r_;
+input out0_a;
+output [47:0]out0_;
+reg out0_r;
+initial out0_r = 0;
+reg [47:0]out0;
+initial out0 = 0;
+
+ assign out1_r_ = out1_r;
+assign out1_ = out1;
+
+ assign in_a_ = in_a;
+
+ assign out0_r_ = out0_r;
+assign out0_ = out0;
+
+always @(posedge clk) begin
+if (!in_r && in_a) in_a<=0;
+if (out0_r && out0_a) begin out0_r<=0; end
+if (out1_r && out1_a) begin out1_r<=0; end
+if (1 && (in[0]==1) && in_r && !in_a && !out1_r && !out1_a && !out0_r && !out0_a) begin
+in_a <= 1;
+out1_r <= 1;
+out1 = { in[47:11], (in[10:0] >> 1) };
+end else
+if (1 && (in[0]==0) && in_r && !in_a && !out1_r && !out1_a && !out0_r && !out0_a) begin
+in_a <= 1;
+out0_r <= 1;
+out0 = { in[47:11], (in[10:0] >> 1) };
+end else
+ begin end
+end
+endmodule
-`include "macros.v"
-`define XWIDTH (`INSTRUCTION_WIDTH-1)
-`define dest(p) `instruction_dest(p)
-`define dest_steer(p) `instruction_dest_steer(p)
-module ihorn
-`include "horn.inc"
+module ihorn(clk
+ , in_r, in_a_, in
+ , out0_r_, out0_a, out0_
+ , out1_r_, out1_a, out1_
+ );
+ input clk;
+ output out1_r_;
+input out1_a;
+output [47:0]out1_;
+reg out1_r;
+initial out1_r = 0;
+reg [47:0]out1;
+initial out1 = 0;
+
+ input in_r;
+output in_a_;
+input [47:0]in;
+reg in_a;
+initial in_a = 0;
+
+ output out0_r_;
+input out0_a;
+output [47:0]out0_;
+reg out0_r;
+initial out0_r = 0;
+reg [47:0]out0;
+initial out0 = 0;
+
+ assign out1_r_ = out1_r;
+assign out1_ = out1;
+
+ assign in_a_ = in_a;
+
+ assign out0_r_ = out0_r;
+assign out0_ = out0;
+
+always @(posedge clk) begin
+if (!in_r && in_a) in_a<=0;
+if (out0_r && out0_a) begin out0_r<=0; end
+if (out1_r && out1_a) begin out1_r<=0; end
+if (1 && (in[24]==0) && in_r && !in_a && !out1_r && !out1_a && !out0_r && !out0_a) begin
+in_a <= 1;
+out0_r <= 1;
+out0 = { in[47:35], (in[34:24] >> 1) , in[23:0] };
+end else
+if (1 && (in[24]==1) && in_r && !in_a && !out1_r && !out1_a && !out0_r && !out0_a) begin
+in_a <= 1;
+out1_r <= 1;
+out1 = { in[47:35], (in[34:24] >> 1) , in[23:0] };
+end else
+ begin end
+end
+endmodule
`define instruction_count(instruction) instruction[(1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS-1):(1+`DESTINATION_ADDRESS_BITS)]
`define defreg(signame,width,regname) reg width regname; wire width signame; assign signame = regname; initial regname = 0;
-`define input(r, a, a_, w, d) input r; output a_; reg a; assign a_=a; input w d;
-`define output(r, r_, a, w, d) output r_; input a; reg r; assign r_=r; output w d;
+`define input(r, a, a_, w, d) input r; output a_; reg a; assign a_=a; input w d; initial a=0;
+`define output(r, r_, a, w, d) output r_; input a; reg r; assign r_=r; output w d; initial r=0;
`define onread(req, ack) if (!req && ack) ack=0; else if (req && !ack) begin ack=1;
`define onwrite(req, ack) if (!req && !ack) req = 1; else if (req && ack) begin req = 0;
+//`define onread2(req, ack) if (!req && ack) ack<=0; else if (req && !ack) begin ack<=1;
+
+//`define onwrite2(req, ack) if (req && ack) begin req <= 0;
+
+`define onread2(req, ack) if (req && !ack) begin ack = 1;
+`define onwrite2(req, ack) if (!req && !ack) req = 1;
+++ /dev/null
-`include "macros.v"
-
-module stupidinbox(clk,
- instr_r, instr_a_, instr_d,
- fabric_in_r, fabric_in_a_, fabric_in_d,
- fabric_out_r_, fabric_out_a, fabric_out_d_,
- ship_r_, ship_a, ship_d_);
- input clk;
-
- `input(instr_r, instr_a, instr_a_, [(`INSTRUCTION_WIDTH-1):0], instr_d)
-// `input(fabric_in_r, fabric_in_a, fabric_in_a_, [`DATAWIDTH:0], fabric_in_d)
- `output(fabric_out_r, fabric_out_r_, fabric_out_a, [(`PACKET_WIDTH-1):0], fabric_out_d_)
-
- input fabric_in_r;
- output fabric_in_a_;
- input [(`PACKET_WIDTH-1):0] fabric_in_d;
-
- output ship_r_;
- input ship_a;
- output [(`DATAWIDTH-1):0] ship_d_;
-
- assign ship_r_ = fabric_in_r;
- assign fabric_in_a_ = ship_a;
- assign ship_d_ = `packet_data(fabric_in_d);
-
-endmodule
+++ /dev/null
-#include<stdio.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <stdint.h>
-
-#define uint32 uint32_t
-#define uint64 uint64_t
-static uint32 fd;
-
-void sendc(char c) {
- uint32 rv = write(fd, &c, 1);
- if (rv != 1) {
- printf("write ret: %d\n", rv);
- }
- printf("send: %x\n", c);
-}
-
-void send(int dest, uint64 i) {
- sendc((dest >> 8) & 0xff);
- sendc((dest >> 0) & 0xff);
- sendc((i >>32) & 0xff);
- sendc((i >>24) & 0xff);
- sendc((i >>16) & 0xff);
- sendc((i >> 8) & 0xff);
- sendc((i >> 0) & 0xff);
-}
-
-char recvc() {
- char c;
- uint32 rv = read(fd, &c, 1);
- if (rv != 1) {
- printf("read ret: %d\n", rv);
- }
- return c;
-}
-
-uint64 recv() {
- uint64 ret = 0
- | (((uint64)recvc()) << 32)
- | (((uint64)recvc()) << 24)
- | (((uint64)recvc()) << 16)
- | (((uint64)recvc()) << 8)
- | (((uint64)recvc()) << 0)
- ;
- return ret;
-}
-
-void sendbits(int num, int dat) {
- sendc(num);
- while(num > 0) {
- sendc((dat>>(num>=8 ? (num-8):0)) & 0xff);
- num -= 8;
- }
-}
-
-uint64_t inst(int boxname, int tokenin, int datain, int latch, int dataout, int tokenout, int count, int dest) {
- uint64_t ret = 0;
- ret |= dest; ret <<= 7;
- ret |= count; ret <<= 1;
- ret |= tokenout; ret <<= 1;
- ret |= dataout; ret <<= 1;
- ret |= latch; ret <<= 1;
- ret |= datain; ret <<= 1;
- ret |= tokenin; ret <<= 11;
- ret |= boxname;
- return ret;
-}
-
-int main(int argc, char** argv) {
- char c;
- uint32 i,j;
- int64_t result;
- int64_t temp;
- printf("hello.\n");
- fd = open(argv[1], O_RDWR);
- printf("open %s = %d\n", argv[1], fd);
-
- if (argc > 2) {
- int fd2 = open(argv[2], O_RDWR);
- printf("open %s = %d\n", argv[2], fd2);
- while(1) {
- i = read(fd2, &c, 1);
- if (i!=1) break;
- sendc(c);
- }
- }
-
- printf("\n===================================================================\n\n");
- while(1) {
- result = 0;
- for(j=0; j<6; j++) {
- temp = recvc();
- temp = temp << (j * 8);
- result = result | temp;
- }
- printf("%lld = 0x%llx\n", result, result);
- fflush(stdout);
- }
- return 0;
-}
projects / fleet.git / commitdiff