add Value.getBits(Mask)

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index 06e474c..711f107 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -1,12 +1,9 @@
 package edu.berkeley.fleet.fpga.verilog;
 import edu.berkeley.fleet.api.*;
 import edu.berkeley.fleet.two.*;
+import edu.berkeley.fleet.util.*;
 import edu.berkeley.fleet.*;
 import java.lang.reflect.*;
-import edu.berkeley.sbp.chr.*;
-import edu.berkeley.sbp.misc.*;
-import edu.berkeley.sbp.meta.*;
-import edu.berkeley.sbp.util.*;
 import java.util.*;
 import java.io.*;
 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
@@ -18,6 +15,7 @@ public class Verilog {
         public SimpleValue(String s) { this.s = s; }
         public SimpleValue(String s, int high, int low) { this.s = s+"["+high+":"+low+"]"; }
         public Value getBits(int high, int low) { return new SimpleValue(s, high, low); }
+        public Value getBits(Mask mask) { return getBits(mask.valmaskmax, mask.valmaskmin); }
         public Assignable getAssignableBits(int high, int low) { return new SimpleValue(s, high, low); }
         public String getVerilogName() { return s; }
         public String toString() { return s; }
@@ -26,6 +24,7 @@ public class Verilog {
     public static class CatValue implements Value {
         private final Value[] values;
         public CatValue(Value[] values) { this.values = values; }
+        public Value getBits(Mask mask) { return getBits(mask.valmaskmax, mask.valmaskmin); }
         public Value getBits(int high, int low) {
             throw new RuntimeException();
         }
@@ -72,6 +71,7 @@ public class Verilog {
     public static interface Value extends Assignable {
         public String getVerilogName();
         public Value getBits(int high, int low);
+        public Value getBits(Mask mask);
     }
 
     public static class ConditionalAction implements Action {
@@ -222,6 +222,7 @@ public class Verilog {
             }
             public String getVerilogName() { return name; }
             public Value getBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
+            public Value getBits(Mask mask) { return getBits(mask.valmaskmax, mask.valmaskmin); }
             public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
             public String doReset() { return name+"<="+initial+";"; }
             public void dump(PrintWriter pw) {
@@ -344,6 +345,7 @@ public class Verilog {
             public SourcePort(String name, int width, boolean external) { 
                 super(name, width, external); }
             public Value getBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
+            public Value getBits(Mask mask) { return getBits(mask.valmaskmax, mask.valmaskmin); }
             public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
             public String getVerilogTrigger() { return " && " + getReq() + " && !"+getAck(); }
             public String getVerilogAction() { return getAck() + " <= 1;"; }