temporarily set capacitances in loopCountL:inMux to zero in order to allow load ILC...

diff --git a/electric/loopCountL.jelib b/electric/loopCountL.jelib
index 9eb8d7b..fd3735a 100755 (executable)
--- a/electric/loopCountL.jelib
+++ b/electric/loopCountL.jelib
@@ -2302,7 +2302,7 @@ Evdd_29||D5G2;|pinsVddG@10|vdd_1|P
 X
 
 # Cell inMux;2{sch}
-CinMux;2{sch}||schematic|1216238895693|1225902098462|
+CinMux;2{sch}||schematic|1216238895693|1225909014458|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-5.5|-7.5||||
 NOff-Page|conn@1||-6.5|8||||
@@ -2348,7 +2348,7 @@ Ngeneric:Invisible-Pin|pin@47||-51|27.5|||||ART_message(D3G2;)S["out[7]=HI if ou
 NWire_Pin|pin@53||-12.5|6||||
 IorangeTSMC090nm:wire90;1{ic}|wire90@0||-0.5|15.5|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1400.8999999999996|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@1||15|15.5|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1400.8999999999996|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
-IorangeTSMC090nm:wire90;1{ic}|wire90@2||-41.5|6|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1400.8999999999996|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@2||-41.5|6|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)S1.4009|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@3||-30.5|6|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)S1.4009|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 Abus|inA[1:6],xx|D5G2;|-0.5|IJ900|pin@3||-3|6|pin@4||-3|2
 Abus|inB[1:6,8]|D5G2;|-0.5|IJ2700|pin@5||-3|-6|pin@6||-3|-2

diff --git a/testCode/isolatedInDock.spi b/testCode/isolatedInDock.spi
index 852658d..27fbb4c 100644 (file)
--- a/testCode/isolatedInDock.spi
+++ b/testCode/isolatedInDock.spi
@@ -1,7 +1,7 @@
 *** SPICE deck for cell isolatedInDock{sch} from library marina
 *** Created on Fri Sep 05, 2008 15:05:59
 *** Last revised on Tue Nov 04, 2008 12:48:55
-*** Written on Wed Nov 05, 2008 08:52:50 by Electric VLSI Design System, 
+*** Written on Wed Nov 05, 2008 10:17:53 by Electric VLSI Design System, 
 *version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -8800,7 +8800,7 @@ Xnand3@2 out[3] out[4] out[6] net@24 nand3-X_6_667
 Xnor2n_sy@0 net@18 net@20 out[7] nor2n_sy-X_10
 Xwire90@0 net@10 s[F] wire90-1400_9-layer_1-width_3
 Xwire90@1 net@12 s[T] wire90-1400_9-layer_1-width_3
-Xwire90@2 net@24 net@20 wire90-1400_9-layer_1-width_3
+Xwire90@2 net@24 net@20 wire90-1_4009-layer_1-width_3
 Xwire90@3 net@18 net@25 wire90-1_4009-layer_1-width_3
 .ENDS inMux