use getReq()/getAck() in isFull()

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index cd0deea..1393c55 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -460,7 +460,7 @@ public class Verilog {
             public String getVerilog() { return name; }
             String getAck() { return name+"_a"; }
             String getReq() { return name+"_r"; }
-            public String isFull() { return "("+name+"_r"+" && !"+name+"_a)"; }
+            public String isFull() { return "("+getReq()+" && !"+getAck()+")"; }
             public abstract String getResetCode();
             public abstract String getInterface();
             public abstract String getSimpleInterface();