package com.sun.vlsi.chips.marina.test;
/* -*- tab-width: 4 -*- */
+import com.sun.async.test.BitVector;
import com.sun.async.test.ChainControl;
import com.sun.async.test.ChipModel;
import com.sun.async.test.JtagTester;
private static final String DATA_CHAIN = "marina.isolatedInDock_data";
private static final String CONTROL_CHAIN = "marina.isolatedInDock_control";
private static final String REPORT_CHAIN = "marina.isolatedInDock_report";
+
+ private static final String OLC_PATH = "inDock.ringSkip@1.skipCoun@0.scanKx6@0";
+ private static final String ILC_PATH = "inDock.ringSkip@1.skipCoun@0.scanKx7@0";
+ private static final String FLAGS_PATH = "inDock.ringSkip@1.skipCoun@0.scanKx3@0";
// The name of the scan chain
// The instance path, from the top cell of the netlist, of the instance of infinityWithCover
private final ChipModel model;
public final ProperStopper datIn, tokOut, instrIn, shipOut;
+ /** Shift the report scan chain */
+ private void shiftReport(boolean readEnable, boolean writeEnable) {
+ cc.shift(REPORT_CHAIN, readEnable, writeEnable);
+ }
+
public IsolatedInDock(ChainControl cc, ChipModel model, Indenter indenter) {
this.cc = cc;
this.model = model;
instrIn.resetAfterMasterClear();
shipOut.resetAfterMasterClear();
}
+ public int getOLC() {
+ shiftReport(true, false);
+ return (int) cc.getOutBits(REPORT_CHAIN+"."+OLC_PATH).bitReverse().not().toLong();
+ }
+ public int getILC() {
+ shiftReport(true, false);
+ return (int) cc.getOutBits(REPORT_CHAIN+"."+ILC_PATH).bitReverse().not().toLong();
+ }
+ public boolean getFlagA() {
+ shiftReport(true, false);
+ return cc.getOutBits(REPORT_CHAIN+"."+FLAGS_PATH).get(2);
+ }
+ public boolean getFlagB() {
+ shiftReport(true, false);
+ return cc.getOutBits(REPORT_CHAIN+"."+FLAGS_PATH).get(1);
+ }
+ public boolean getFlagC() {
+ shiftReport(true, false);
+ return cc.getOutBits(REPORT_CHAIN+"."+FLAGS_PATH).get(0);
+ }
// /** Shift the data scan chain. */
// public void shiftData(boolean readEnable, boolean writeEnable) {
// // Get current data of all stoppers
// public void shiftControl(boolean readEnable, boolean writeEnable) {
// cc.shift(CONTROL_CHAIN, readEnable, writeEnable);
// }
-// /** Shift the report scan chain */
-// public void shiftReport(boolean readEnable, boolean writeEnable) {
-// cc.shift(REPORT_CHAIN, readEnable, writeEnable);
-// }
}
adjustIndent(-2);
prln("End sendToken");
}
+ private void getCtrsFlags(IsolatedInDock inDock) {
+ int olc = inDock.getOLC();
+ prln("OLC="+olc);
+
+ int ilc = inDock.getILC();
+ prln("ILC="+ilc);
+
+ boolean a = inDock.getFlagA();
+ prln("flagA="+a);
+
+ boolean b = inDock.getFlagB();
+ prln("flagB="+b);
+
+ boolean c = inDock.getFlagC();
+ prln("flagC="+c);
+ }
private void doOneTest(int testNum) {
prln("MarinaTest: performing test: "+testNum);
design.masterClear(tester);
switch (testNum) {
- case 0: stopToStopOneItem((IsolatedInDock)design); break;
- case 1: stopToStopThreeItems((IsolatedInDock)design); break;
- case 2: sendInstructions((IsolatedInDock)design); break;
- case 3: sendToken((IsolatedInDock)design); break;
+ case 0: stopToStopOneItem((IsolatedInDock)design); break;
+ case 1: stopToStopThreeItems((IsolatedInDock)design); break;
+ case 2: sendInstructions((IsolatedInDock)design); break;
+ case 3: sendToken((IsolatedInDock)design); break;
+ case 4: getCtrsFlags((IsolatedInDock)design); break;
default:
fatal(true, "Test number: "+testNum+" doesn't exist.");
break;
*** SPICE deck for cell isolatedInDock{sch} from library marina
*** Created on Fri Sep 05, 2008 15:05:59
*** Last revised on Fri Oct 31, 2008 09:20:32
-*** Written on Mon Nov 03, 2008 11:49:04 by Electric VLSI Design System,
+*** Written on Mon Nov 03, 2008 14:43:36 by Electric VLSI Design System,
*version 8.08k
*** Layout tech: cmos90, foundry TSMC
*** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
.OPTIONS NOMOD NOPAGE
* Model cards are described in this file:
-.include '../../testCode/header.hsp'
+.include '../testCode/header.hsp'
*** CELL: orangeTSMC090nm:NMOSx{sch}
.SUBCKT NMOSx-X_70 d g s
.ENDS wire90-426-layer_1-width_3
*** CELL: loopCountL:olc{sch}
-.SUBCKT olc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] doLO[7] inLO[1]
+.SUBCKT olc bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] doLO[7] gnd inLO[1]
+inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] olc[dec][1] olc[dec][2] olc[load][1]
+olc[load][2]
Xinv@6 net@270 doLO[7] inv-X_20
-XolcCente@1 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4]
+XolcCente@1 gnd bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4]
+do[5] do[6] net@271 countLogic
XolcEven@0 bitt[2] bitt[4] bitt[6] olc[dec][2] do[2] do[4] do[6] inLO[2]
+inLO[4] inLO[6] olc[load][2] olcEven
-XolcOdd@1 bitt[1] bitt[3] bitt[5] olc[dec][1] do[3] do[5] inLO[1] inLO[3]
-+inLO[5] olc[load][1] olcOdd
+XolcOdd@1 gnd bitt[3] bitt[5] olc[dec][1] do[3] do[5] inLO[1] inLO[3] inLO[5]
++olc[load][1] olcOdd
Xwire90@1 wire90@1_a do[2] wire90-374_2-layer_1-width_3
Xwire90@2 wire90@2_a do[3] wire90-538_8-layer_1-width_3
Xwire90@3 wire90@3_a do[4] wire90-472_8-layer_1-width_3
Xwire90@4 wire90@4_a do[5] wire90-548_8-layer_1-width_3
Xwire90@5 wire90@5_a do[6] wire90-457_8-layer_1-width_3
-Xwire90@7 wire90@7_a bitt[1] wire90-1049_7-layer_1-width_3
+Xwire90@7 wire90@7_a gnd wire90-1049_7-layer_1-width_3
Xwire90@8 wire90@8_a bitt[2] wire90-1049_4-layer_1-width_3
Xwire90@9 wire90@9_a bitt[3] wire90-979_8-layer_1-width_3
Xwire90@10 wire90@10_a bitt[4] wire90-786_3-layer_1-width_3
XinMux@0 inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inB[1] inB[2] inB[3]
+inB[4] inB[5] inB[6] inB[8] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6]
+inLO[7] inLO[8] sel[A] inMux
-Xolc@0 net@130[5] net@130[4] net@130[3] net@130[2] net@130[1] net@130[0]
-+net@10 inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] olc[dec][1]
-+olc[dec][2] olc[load][1] olc[load][2] olc
+Xolc@0 net@130[4] net@130[3] net@130[2] net@130[1] net@130[0] net@10 gnd
++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] olc[dec][1] olc[dec][2]
++olc[load][1] olc[load][2] olc
XscanKx3@0 clS[F] clS[T] cl[F] cl[T] flag[C] flag[B] flag[A] mc rd[F] rd[T]
+net@104 sout scanKx3
-XscanKx6@0 clS[F] clS[T] cl[F] cl[T] net@130[5] net@130[4] net@130[3]
-+net@130[2] net@130[1] net@130[0] mc rd[F] rd[T] net@103 net@104 scanKx6
+XscanKx6@0 clS[F] clS[T] cl[F] cl[T] gnd net@130[4] net@130[3] net@130[2]
++net@130[1] net@130[0] mc rd[F] rd[T] net@103 net@104 scanKx6
XscanKx7@0 clS[F] clS[T] cl[F] cl[T] net@129[6] net@129[5] net@129[4]
+net@129[3] net@129[2] net@129[1] net@129[0] mc rd[F] rd[T] sin net@103
+scanKx7
Xwire90@70 kill fire[T] wire90-2416_4-layer_1-width_4
.ENDS ringSkipMoveLit
-*** CELL: marina:scanConverter{sch}
+*** CELL: scanConverter{sch}
.SUBCKT scanConverter clS[F] clS[T] cl[F] cl[T] mc oldScan[2] oldScan[3]
+oldScan[4] oldScan[5] oldScan[6] oldScan[7] oldScan[8] oldScan[9] rd[F] rd[T]
Xinv@0 oldScan[2] cl[F] inv-X_5
Xinv@7 net@3 mc inv-X_5
.ENDS scanConverter
-*** CELL: marina:inputDock{sch}
+*** CELL: inputDock{sch}
.SUBCKT inputDock datIn[10] datIn[11] datIn[12] datIn[13] datIn[14] datIn[15]
+datIn[16] datIn[17] datIn[18] datIn[19] datIn[1] datIn[20] datIn[21]
+datIn[22] datIn[23] datIn[24] datIn[25] datIn[26] datIn[27] datIn[28]
.global gnd vdd
-*** TOP LEVEL CELL: marina:isolatedInDock{sch}
+*** TOP LEVEL CELL: isolatedInDock{sch}
XdatIn net@6[4] net@6[3] net@6[2] net@6[1] net@6[0] net@6[13] net@6[12]
+net@6[11] net@6[10] net@6[9] net@6[8] net@6[7] net@6[6] net@6[5] net@6[14]
+datIn[47] datIn[48] datIn[49] datIn[50] datIn[51] datIn[38] datIn[39]
<datanet name="inDock.ringSkip@1.skipCoun@0.scanKx7@0.scanCell@8" net="xinDock.xringSkip@1.xskipCoun@0.net@129[2](R)" />
<datanet name="inDock.ringSkip@1.skipCoun@0.scanKx7@0.scanCell@9" net="xinDock.xringSkip@1.xskipCoun@0.net@129[1](R)" />
<datanet name="inDock.ringSkip@1.skipCoun@0.scanKx7@0.scanCell@10" net="xinDock.xringSkip@1.xskipCoun@0.net@129[0](R)" />
- <datanet name="inDock.ringSkip@1.skipCoun@0.scanKx6@0.scanCell@4" net="xinDock.xringSkip@1.xskipCoun@0.net@130[5](R)" />
+ <datanet name="inDock.ringSkip@1.skipCoun@0.scanKx6@0.scanCell@4" net="gnd(R)" />
<datanet name="inDock.ringSkip@1.skipCoun@0.scanKx6@0.scanCell@5" net="xinDock.xringSkip@1.xskipCoun@0.net@130[4](R)" />
<datanet name="inDock.ringSkip@1.skipCoun@0.scanKx6@0.scanCell@6" net="xinDock.xringSkip@1.xskipCoun@0.net@130[3](R)" />
<datanet name="inDock.ringSkip@1.skipCoun@0.scanKx6@0.scanCell@7" net="xinDock.xringSkip@1.xskipCoun@0.net@130[2](R)" />
projects / fleet.git / commitdiff