enable clockHack for VerilogModel

diff --git a/testCode/com/sun/vlsi/chips/marina/test/ProperStopper.java b/testCode/com/sun/vlsi/chips/marina/test/ProperStopper.java
index db4e0ee..5adeee8 100644 (file)
--- a/testCode/com/sun/vlsi/chips/marina/test/ProperStopper.java
+++ b/testCode/com/sun/vlsi/chips/marina/test/ProperStopper.java
@@ -7,6 +7,7 @@ import com.sun.async.test.ChainControl;
 import com.sun.async.test.ChipModel;
 import com.sun.async.test.Infrastructure;
 import com.sun.async.test.NanosimModel;
+import com.sun.async.test.VerilogModel;
 import com.sun.vlsi.chips.marina.test.MarinaUtils.StateWireState;
 
 public class ProperStopper {
@@ -50,6 +51,7 @@ public class ProperStopper {
      * Each instance name in the path must begin with the character 'x'.
      * Return a path with the added X's. */
     private String prefixInstNamesInPathWithX(String path) {
+        if (!(model instanceof NanosimModel)) return path;
         StringBuffer sb = new StringBuffer();
         sb.append('x');
         for (int i=0; i<path.length(); i++) {
@@ -71,6 +73,11 @@ public class ProperStopper {
                 nanoModel.setNodeState(captureClock, 1);
                 nanoModel.waitNS(1);
                 nanoModel.setNodeState(captureClock, 0);
+            } else if (clockHack && model instanceof VerilogModel) {
+                VerilogModel nanoModel = (VerilogModel) model;
+                nanoModel.setNodeState(captureClock, 1);
+                nanoModel.waitNS(1);
+                nanoModel.setNodeState(captureClock, 0);
             }
         }
     }