Module.InstantiatedModule dfifo = new Module.InstantiatedModule(this, dfifo_m);
fabric_in.hasLatch = false;
- addPreCrap("assign "+dfifo.getInputPort("in").getName()+"_r = fabric_in_r;\n");
- addPreCrap("assign fabric_in_a = "+dfifo.getInputPort("in").getName()+"_a;\n");
+ fabric_in.connect(dfifo.getInputPort("in"));
+ dfifo.getInputPort("in").noDriveLatches = true;
if (inbox)
addPreCrap("assign "+dfifo.getInputPort("in").getName()+
" = { "+fpga.PACKET_SIGNAL.verilogVal("fabric_in")+
public boolean forceNoLatch = false;
public SinkPort driven = null;
public Latch latchDriver = null;
+ public boolean noDriveLatches = false;
public final String resetBehavior;
public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
public String getVerilogAction() { return getReq() + " <= 1;"; }
if (driver != null) {
sb.append("assign " + name +"_r = " + driver.name + "_r;\n");
sb.append("assign " + driver.name +"_a = " + name + "_a;\n");
- if (width>0)
+ if (width>0 && !noDriveLatches)
sb.append("assign " + name +" = " + driver.name + ";\n");
}
if (latchDriver != null) {