Checking in header and cfg files

diff --git a/testCode/cfg b/testCode/cfg
index 48ee78a..302522c 100644 (file)
--- a/testCode/cfg
+++ b/testCode/cfg
@@ -1,5 +1,5 @@
 set_sim_tres 10ps
-set_sim_eou sim=3 model=3 net=3
+set_sim_eou sim=6 model=6 net=6
 set_elem_acc *XhalfBit* *xcontRx* *xclockedrx* *xclk_regen* *xsimpleRx* *xrxc_offs* *xdutyrestore*
 print_node_v *
 free_ckt_db 99999999

diff --git a/testCode/header.hsp b/testCode/header.hsp
index 5fa130f..bd242d6 100644 (file)
--- a/testCode/header.hsp
+++ b/testCode/header.hsp
@@ -3,18 +3,23 @@
 ******************************************************************
 * Set Process, Voltage and Temperature corner
 ******************************************************************
+
+.protect
 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT
 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_RES
 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_18
 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_na18
 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_esd
 .lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_18
-.param sup=1.0    * Supply voltage
-.temp 40          * Temperature
+.unprotect
+
+.param sup=0.9    * Supply voltage
+.temp 80          * Temperature
 
 ******************************************************************
 * Standard Parameters and Options
 ******************************************************************
+
 .param vsupply=sup
 .param vhi=sup
 .param vlo=0
@@ -30,4 +35,3 @@ vvdd vdd gnd 'sup'
 .param AVT0P = AGAUSS(0.0,  '0.01 / 0.1' , 1)
 .param ABN = AGAUSS(0.0,  '0.02 / 0.1' , 1)
 .param ABP = AGAUSS(0.0,  '0.02 / 0.1' , 1)
-