Evdd_3||D5G2;|pinsVddG@3|vdd_1|P
X
+# Cell nand5B;1{lay}
+Cnand5B;1{lay}||cmos90|1191015378230|1240141720428||DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1240142457739
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NX-Metal-1-Metal-2-Con|contact@9||-1|-50||6.2||
+NX-Metal-1-Metal-2-Con|contact@10||-7|50||6.2||
+NX-Metal-1-Metal-2-Con|contact@11||-7|0||6.2||
+NMetal-1-Polysilicon-Con|contact@12||-5.5|-22||5.2|RR|
+NMetal-1-P-Active-Con|contact@14||-1|-48||20.8||
+NMetal-1-N-Active-Con|contact@15||-7|0||20.8||
+NMetal-1-P-Active-Con|contact@16||7|-48||20.8||
+NMetal-1-N-Active-Con|contact@17||7|0||20.8||
+NMetal-1-P-Active-Con|contact@18||-7|48||20.8||
+NMetal-1-P-Active-Con|contact@19||1|48||20.8||
+NMetal-1-Polysilicon-Con|contact@20||-1|28||5.2|R|
+NN-Transistor|nmos@5||3|0||26||
+NN-Transistor|nmos@6||-3|0||26||
+NMetal-1-Pin|pin@10||7|-8.1||||
+NMetal-1-Pin|pin@16||0|29||||
+NMetal-1-Pin|pin@17||-6|-25||||
+NPolysilicon-Pin|pin@29||-3|-19.4||||
+NMetal-1-Pin|pin@30||-6|-24.6||||
+NPolysilicon-Pin|pin@31||-3.9|-30||||
+NPolysilicon-Pin|pin@32||-3.9|-24.6||||
+NMetal-1-Pin|pin@33||7|37.6||||
+NPolysilicon-Pin|pin@34||3|28||||
+NMetal-1-Pin|pin@35||-3.6|29||||
+IwiresL:pinsVddGnd;1{lay}|pinsVddG@2||-11.5|0|||D5G4;
+IwiresL:pinsVddGnd;1{lay}|pinsVddG@3||11.5|0|||D5G4;
+NP-Select-Node|plnode@18||0|50|25|52||A
+NP-Select-Node|plnode@19||0|-50|25|52||A
+NP-Well-Node|plnode@20||0|0|28|48||A
+NN-Select-Node|plnode@21||0|0|25|48||A
+NN-Well-Node|plnode@22||0|50|28|52||A
+NN-Well-Node|plnode@23||0|-50|28|52||A
+NP-Transistor|pmos@2||3|-48||26||
+NP-Transistor|pmos@4||-3|48||26||
+Ametal-2|net@17||6.2|S1800|contact@11||-7|0|pinsVddG@3|gnd|11.5|0
+Ametal-2|net@18||6.2|S0|pinsVddG@3|vdd|11.5|50|contact@10||-7|50
+Ametal-2|net@19||6.2|S0|pinsVddG@3|vdd_1|11.5|-50|contact@9||-1|-50
+Ametal-2|net@20||6.2|S0|contact@9||-1|-50|pinsVddG@2|vdd_1|-11.5|-50
+Ametal-2|net@26||6.2|S0|contact@10||-7|50|pinsVddG@2|vdd|-11.5|50
+Ametal-2|net@28||6.2|S1800|pinsVddG@2|gnd|-11.5|0|contact@11||-7|0
+AN-Active|net@48|||RS0|contact@17||7|0|nmos@5|diff-right|5.8|0
+AN-Active|net@49|||RS1800|contact@15||-7|0|nmos@6|diff-left|-5.8|0
+AP-Active|net@50|||RS1800|contact@14||-1|-48|pmos@2|diff-left|0.2|-48
+AP-Active|net@51|||RS0|contact@16||7|-48|pmos@2|diff-right|5.8|-48
+AN-Active|net@52|||RS0|nmos@5|diff-left|0.2|0|nmos@6|diff-right|-0.2|0
+AP-Active|net@53|||RS1800|contact@18||-7|48|pmos@4|diff-left|-5.8|48
+AP-Active|net@54|||RS0|contact@19||1|48|pmos@4|diff-right|-0.2|48
+Ametal-1|net@58|||S1800|contact@11||-7|0|contact@15||-7|0
+Ametal-1|net@59|||S900|contact@10||-7|49|contact@18||-7|49
+Ametal-1|net@60|||S900|contact@9||-1|-49|contact@14||-1|-49
+Ametal-1|net@78|||S900|pin@10||7|-8.1|contact@17||7|-8.1
+Ametal-1|net@96|||S900|contact@17||7|0|contact@16||7|-38.6
+APolysilicon|net@97|||S900|nmos@6|poly-bottom|-3|-18|pin@29||-3|-19.4
+APolysilicon|net@98|||S0|pin@29||-3|-19.4|contact@12||-5.5|-19.4
+Ametal-1|net@99|||S2700|pin@17||-6|-25|pin@30||-6|-24.6
+Ametal-1|net@100|||S1800|pin@30||-6|-24.6|contact@12||-5.5|-24.6
+APolysilicon|net@101|||S0|pmos@2|poly-top|3|-30|pin@31||-3.9|-30
+APolysilicon|net@102|||S2700|pin@31||-3.9|-30|pin@32||-3.9|-24.6
+APolysilicon|net@103|||S0|pin@32||-3.9|-24.6|contact@12||-5.5|-24.6
+Ametal-1|net@105|||S2700|contact@17||7|10.4|pin@33||7|37.6
+Ametal-1|net@106|||S0|pin@33||7|37.6|contact@19||1|37.6
+APolysilicon|net@107|||S2700|nmos@5|poly-top|3|18|pin@34||3|28
+APolysilicon|net@108|||S0|pin@34||3|28|contact@20||1.6|28
+APolysilicon|net@109|||S900|pmos@4|poly-bottom|-3|30|contact@20||-3|28
+Ametal-1|net@110|||S0|pin@16||0|29|pin@35||-3.6|29
+Ametal-1|net@111|||S900|pin@35||-3.6|29|contact@20||-3.6|28
+Egnd||D5G2;|pinsVddG@2|gnd|G
+Egnd_1||D5G2;|pinsVddG@3|gnd|G
+Eina||D5G2;|pin@17||I
+Einb||D5G2;|pin@16||I
+Eout||D5G2;|pin@10||O
+Evdd||D5G2;|pinsVddG@2|vdd|P
+Evdd_1||D5G2;|pinsVddG@2|vdd_1|P
+Evdd_2||D5G2;|pinsVddG@3|vdd|P
+Evdd_3||D5G2;|pinsVddG@3|vdd_1|P
+X
+
# Cell nand6sym;1{lay}
Cnand6sym;1{lay}||cmos90|1188767772815|1239549868233||ATTR_NCC(D5G3;NTY69.5;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1239553775974
Ngeneric:Facet-Center|art@0||0|0||||AV
X
# Cell nor05;1{lay}
-Cnor05;1{lay}||cmos90|1188767772815|1238257435226||ATTR_NCC(D5G3;NTX5.5;Y70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]
+Cnor05;1{lay}||cmos90|1188767772815|1238257435226||ATTR_NCC(D5G3;NTX5.5;Y70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1239929915613
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-P-Active-Con|contact@123||-8|-48||20.8||
NMetal-1-P-Active-Con|contact@124||6|-48||20.8||
X
# Cell xor5;1{lay}
-Cxor5;1{lay}||cmos90|1188767772815|1238257435226||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent inB[T] xt","exportsConnectedByParent inB[F] xf"]
+Cxor5;1{lay}||cmos90|1188767772815|1240182444042||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent inB[T] xt","exportsConnectedByParent inB[F] xf"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1240183479594
Ngeneric:Facet-Center|art@0||0|0||||AV
NMetal-1-N-Active-Con|contact@59||14|0||20.8||
NMetal-1-N-Active-Con|contact@91||0|0||20.8||
NN-Transistor|nmos@25||-4|0||26||
NPolysilicon-Pin|pin@231||4|25.2||||
NPolysilicon-Pin|pin@232||-4|-25.2||||
-NMetal-1-Pin|pin@233||-8|-25.5||||
+NMetal-1-Pin|pin@233||-7|-25.5||||
NMetal-1-Pin|pin@238||0|7||||
NMetal-1-Pin|pin@239||7|25||||
NMetal-1-Pin|pin@242||-7|25||||
APolysilicon|net@1328|||S900|nmos@23|poly-bottom|10|-18|contact@247||10|-25.2
APolysilicon|net@1329|||S2700|pin@232||-4|-25.2|nmos@25|poly-bottom|-4|-18
APolysilicon|net@1330|||S1800|contact@237||-6.9|-25.2|pin@232||-4|-25.2
-Ametal-1|net@1343|||S900|contact@237||-8|-25.2|pin@233||-8|-25.5
+Ametal-1|net@1343|||S900|contact@237||-7|-25.2|pin@233||-7|-25.5
Ametal-1|net@1354|||S900|contact@91||0|10.4|pin@238||0|7
Ametal-1|net@1355|||S2700|pin@239||7|25|contact@212||7|25.2
Ametal-1|net@1358|||S2700|pin@242||-7|25|contact@205||-7|25.2
X
# Cell mlat2in10i;1{sch}
-Cmlat2in10i;1{sch}||schematic|1204973663598|1219458201107|
+Cmlat2in10i;1{sch}||schematic|1204973663598|1240160023316|
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||18|-18|||YRRR|
NOff-Page|conn@1||-34|0|||X|
X
# Cell ilcEven;6{sch}
-CilcEven;6{sch}||schematic|1216766649341|1236908967051|I
+CilcEven;6{sch}||schematic|1216766649341|1240273053366|
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||45|12|||XY|
NOff-Page|conn@1||14.5|12|||XY|
NOff-Page|conn@5||-36|0|||RR|
NOff-Page|conn@6||50|-6|||XY|
NOff-Page|conn@9||-70.5|-25|||Y|
-NOff-Page|conn@14||48|-24|||XY|
+NOff-Page|conn@14||48|-23|||XY|
NWire_Con|conn@22||-2.5|-23||||
NOff-Page|conn@23||-2.5|-29|||RRR|
NOff-Page|conn@24||-69.5|0|||RR|
NOff-Page|conn@25||-66|-16|||YR|
IilcEven;1{ic}|ilcEven@0||51|30.5|||D5G4;
IredFive:inv;1{ic}|inv@7||-40|-24|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFive:inv;1{ic}|inv@8||37|-24|X||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@8||37|-23|X||D0G4;|ATTR_Delay(D5G1;NPX4;Y-4;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IlatchesK:mlat1in10;1{ic}|mlat1in1@1||-60|0|X||D5G4;
IredFive:nor2n;1{ic}|nor2n@0||-60|-24|Y||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S15|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Ngeneric:Invisible-Pin|pin@0||-1|46|||||ART_message(D5G6;)SilcEven
Ngeneric:Invisible-Pin|pin@126||-69.5|32.5|||||ART_message(D3G2;)S["bit[8] is the infinity bit.",It is LO active. A LO output,means keep working even,if counter runs out.]
NWire_Pin|pin@138||-28|-24||||
NWire_Pin|pin@139||-28|-20||||
-NWire_Pin|pin@142||26|-24|||X|
+NWire_Pin|pin@142||26|-23|||X|
NWire_Pin|pin@143||26|-20|||X|
NBus_Pin|pin@145||-9|-12|-1|-1||
NBus_Pin|pin@146||-9|-16|-1|-1||
IringB;1{ic}|ringB@4||0|0|X||D5G4;
IringB;1{ic}|ringB@5||30|0|X||D5G4;
IorangeTSMC090nm:wire90;1{ic}|wire90@8||-33.5|-24|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1588.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
-IorangeTSMC090nm:wire90;1{ic}|wire90@9||30.5|-24|X||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1317.0999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@9||30.5|-23|X||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1317.0999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
IorangeTSMC090nm:wire90;1{ic}|wire90@10||-51|-24|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1283.3|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
Abus|bit[2,4,6,8]|D5G2;|-0.5|IJ2700|conn@22||-2.5|-23|pin@168||-2.5|-18
Awire|count[F]|D5G2;||2700|pin@138||-28|-24|pin@139||-28|-20
Awire|inLO[4]|D5G2;||900|pin@27||12|-2|pin@28||12|-6
Awire|inLO[6]|D5G2;||900|pin@61||-18|-2|pin@62||-18|-6
Awire|inLO[8]|D5G2;||900|pin@157||-54|0|pin@158||-54|-5.5
-Awire|load[F]|D5G2;||2700|pin@142||26|-24|pin@143||26|-20
+Awire|load[F]|D5G2;||2700|pin@142||26|-23|pin@143||26|-20
Abus|load[T,F]|D5G2;|-0.5|IJ900|pin@145||-9|-12|pin@146||-9|-16
Abus|net@5||-0.5|IJ1800|pin@63||-25|-12|pin@145||-9|-12
Awire|net@104|||0|conn@0|y|43|12|ringB@5|do[1]|40|12
Abus|net@244||-0.5|IJ2700|ringB@5|count[T,F]|34.5|10|pin@125||34.5|24
Awire|net@273|||0|wire90@8|a|-36|-24|inv@7|out|-37.5|-24
Awire|net@274|||0|pin@138||-28|-24|wire90@8|b|-31|-24
-Awire|net@275|||1800|wire90@9|a|33|-24|inv@8|out|34.5|-24
-Awire|net@277|||1800|pin@142||26|-24|wire90@9|b|28|-24
-Awire|net@279|||1800|inv@8|in|39.5|-24|conn@14|y|46|-24
+Awire|net@275|||1800|wire90@9|a|33|-23|inv@8|out|34.5|-23
+Awire|net@277|||1800|pin@142||26|-23|wire90@9|b|28|-23
+Awire|net@279|||1800|inv@8|in|39.5|-23|conn@14|y|46|-23
Abus|net@280||-0.5|IJ0|pin@6||35|-12|pin@7||5|-12
Abus|net@281||-0.5|IJ1800|pin@145||-9|-12|pin@7||5|-12
Abus|net@283||-0.5|IJ0|pin@125||34.5|24|pin@124||4.5|24
X
# Cell ilcOdd;6{sch}
-CilcOdd;6{sch}||schematic|1216766649341|1236908967051|I
+CilcOdd;6{sch}||schematic|1216766649341|1240273024047|
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@1||15|12|||XY|
NOff-Page|conn@2||-15|12|||XY|
NGround|gnd@0||-48|-7||||
IilcOdd;1{ic}|ilcOdd@0||39|37|||D5G4;
IredFive:inv;1{ic}|inv@5||-45|-30|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFive:inv;1{ic}|inv@6||29|-30|X||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@6||30|-30|X||D0G4;|ATTR_Delay(D5G1;NPX5;Y-3;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredFive:inv;1{ic}|inv@7||-54|-18|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IlatchesK:mlat2in10i;1{ic}|mlat2in1@1||-55|0|X||D5G4;
IredFive:nor2n;1{ic}|nor2n@0||-66|-30|Y||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)S15|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Abus|net@267||-0.5|IJ2700|ringB@5|count[T,F]|34.5|10|pin@124||34.5|18
Awire|net@273|||0|wire90@4|a|-41|-30|inv@5|out|-42.5|-30
Awire|net@274|||0|pin@126||-33|-30|wire90@4|b|-36|-30
-Awire|net@275|||1800|wire90@5|a|25|-30|inv@6|out|26.5|-30
+Awire|net@275|||1800|wire90@5|a|25|-30|inv@6|out|27.5|-30
Awire|net@277|||1800|pin@130||18|-30|wire90@5|b|20|-30
-Awire|net@278|||0|conn@7|y|36|-30|inv@6|in|31.5|-30
+Awire|net@278|||0|conn@7|y|36|-30|inv@6|in|32.5|-30
Abus|net@280||-0.5|IJ0|pin@67||35|-12|pin@68||5|-12
Abus|net@281||-0.5|IJ0|pin@124||34.5|18|pin@123||4.5|18
Abus|net@282||-0.5|IJ1800|pin@122||-25.5|18|pin@133||-12|18
X
# Cell muxForD;1{sch}
-CmuxForD;1{sch}||schematic|1237123409146|1237643719230|
+CmuxForD;1{sch}||schematic|1237123409146|1240273072038|
Ngeneric:Facet-Center|art@0||0|0||||AV
-NOff-Page|conn@0||-23|12||||
+NOff-Page|conn@0||-23|13||||
NOff-Page|conn@1||-14.5|5||||
NOff-Page|conn@2||7|0||||
NWire_Con|conn@3||-29|5||||
NGround|gnd@0||-29|-1||||
-IredFive:inv;1{ic}|inv@0||-15|12|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFive:inv;1{ic}|inv@1||0|12|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@0||-15|13|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@1||0|13|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Imux10/2x7;1{ic}|mux10/2x@0||0|0|||D5G4;
ImuxForD;1{ic}|muxForD@0||22|19|||D5G4;
Ngeneric:Invisible-Pin|pin@0||0|28|||||ART_message(D5G4;)Shalf mux times 7 for D register
Ngeneric:Invisible-Pin|pin@1||0|33|||||ART_message(D5G6;)SmuxForD
Ngeneric:Invisible-Pin|pin@2||0|22|||||ART_message(D5G3;)Sies 15 March 2009
-NWire_Pin|pin@3||-4|12||||
+NWire_Pin|pin@3||-4|13||||
NWire_Pin|pin@4||-4|9||||
-NWire_Pin|pin@5||12|12||||
+NWire_Pin|pin@5||12|13||||
NWire_Pin|pin@6||12|9||||
NBus_Pin|pin@8||0|7|-1|-1||
NBus_Pin|pin@10||-7|2|-1|-1||
NBus_Pin|pin@11||-7|-1.5|-1|-1||
NWire_Pin|pin@12||-29|10||||
-IorangeTSMC090nm:wire90;1{ic}|wire90@0||-8|12|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D704.3000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
-IorangeTSMC090nm:wire90;1{ic}|wire90@1||8|12|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D704.3000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||-8|13|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D704.3000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||8|13|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D704.3000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
Abus|in[1:6],xx|D5G2;|-0.5|IJ900|pin@10||-7|2|pin@11||-7|-1.5
-Awire|net@0|||1800|inv@0|out|-12.5|12|wire90@0|a|-10.5|12
-Awire|net@1|||1800|inv@1|out|2.5|12|wire90@1|a|5.5|12
-Awire|net@2|||1800|pin@3||-4|12|inv@1|in|-2.5|12
-Awire|net@3|||1800|wire90@0|b|-5.5|12|pin@3||-4|12
-Awire|net@5|||1800|wire90@1|b|10.5|12|pin@5||12|12
-Awire|net@13|||0|inv@0|in|-17.5|12|conn@0|y|-21|12
+Awire|net@0|||1800|inv@0|out|-12.5|13|wire90@0|a|-10.5|13
+Awire|net@1|||1800|inv@1|out|2.5|13|wire90@1|a|5.5|13
+Awire|net@2|||1800|pin@3||-4|13|inv@1|in|-2.5|13
+Awire|net@3|||1800|wire90@0|b|-5.5|13|pin@3||-4|13
+Awire|net@5|||1800|wire90@1|b|10.5|13|pin@5||12|13
+Awire|net@13|||0|inv@0|in|-17.5|13|conn@0|y|-21|13
Abus|net@14||-0.5|IJ0|conn@2|a|5|0|mux10/2x@0|out[1]|2|0
Abus|net@15||-0.5|IJ0|mux10/2x@0|in[1]|-2|2|pin@10||-7|2
Awire|net@17|||2700|gnd@0||-29|1|conn@3||-29|5
-Awire|sF|D5G2;||900|pin@3||-4|12|pin@4||-4|9
-Awire|sT|D5G2;||900|pin@5||12|12|pin@6||12|9
+Awire|sF|D5G2;||900|pin@3||-4|13|pin@4||-4|9
+Awire|sT|D5G2;||900|pin@5||12|13|pin@6||12|9
Abus|sT,sF|D5G2;|-0.5|IJ2700|mux10/2x@0|sT,sF|0|4|pin@8||0|7
Awire|xx|D5G2;||2700|conn@3||-29|5|pin@12||-29|10
Ein[1:7]@152727257|in[1:6]|D4G2;|conn@1|a|I
X
# Cell muxForPS;1{sch}
-CmuxForPS;1{sch}||schematic|1237123409146|1237311332472|
+CmuxForPS;1{sch}||schematic|1237123409146|1240273090344|
Ngeneric:Facet-Center|art@0||0|0||||AV
-NOff-Page|conn@0||-23|12||||
+NOff-Page|conn@0||-23|13||||
NOff-Page|conn@1||-8|2||||
NOff-Page|conn@2||7|0||||
-IredFive:inv;1{ic}|inv@0||-15|12|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFive:inv;1{ic}|inv@1||0|12|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@0||-15|13|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@1||0|13|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)S0|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Imux10/2x7;1{ic}|mux10/2x@0||0|0|||D5G4;
ImuxForPS;1{ic}|muxForOD@0||21.5|17|||D5G4;
Ngeneric:Invisible-Pin|pin@0||0|28|||||ART_message(D5G4;)Shalf mux times 7 for the OD instruction register
Ngeneric:Invisible-Pin|pin@1||0|33|||||ART_message(D5G6;)SmuxForPS
Ngeneric:Invisible-Pin|pin@2||0|22|||||ART_message(D5G3;)Sies 15 March 2009
-NWire_Pin|pin@3||-4|12||||
+NWire_Pin|pin@3||-4|13||||
NWire_Pin|pin@4||-4|9||||
-NWire_Pin|pin@5||12|12||||
+NWire_Pin|pin@5||12|13||||
NWire_Pin|pin@6||12|9||||
NBus_Pin|pin@8||0|7|-1|-1||
-IorangeTSMC090nm:wire90;1{ic}|wire90@0||-8|12|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D704.3000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
-IorangeTSMC090nm:wire90;1{ic}|wire90@1||8|12|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D704.3000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
-Awire|net@0|||1800|inv@0|out|-12.5|12|wire90@0|a|-10.5|12
-Awire|net@1|||1800|inv@1|out|2.5|12|wire90@1|a|5.5|12
-Awire|net@2|||1800|pin@3||-4|12|inv@1|in|-2.5|12
-Awire|net@3|||1800|wire90@0|b|-5.5|12|pin@3||-4|12
-Awire|net@5|||1800|wire90@1|b|10.5|12|pin@5||12|12
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||-8|13|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D704.3000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||8|13|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D704.3000000000001|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+Awire|net@0|||1800|inv@0|out|-12.5|13|wire90@0|a|-10.5|13
+Awire|net@1|||1800|inv@1|out|2.5|13|wire90@1|a|5.5|13
+Awire|net@2|||1800|pin@3||-4|13|inv@1|in|-2.5|13
+Awire|net@3|||1800|wire90@0|b|-5.5|13|pin@3||-4|13
+Awire|net@5|||1800|wire90@1|b|10.5|13|pin@5||12|13
Abus|net@10||-0.5|IJ1800|conn@1|y|-6|2|mux10/2x@0|in[1]|-2|2
-Awire|net@13|||0|inv@0|in|-17.5|12|conn@0|y|-21|12
+Awire|net@13|||0|inv@0|in|-17.5|13|conn@0|y|-21|13
Abus|net@14||-0.5|IJ0|conn@2|a|5|0|mux10/2x@0|out[1]|2|0
-Awire|sF|D5G2;||900|pin@5||12|12|pin@6||12|9
-Awire|sT|D5G2;||900|pin@3||-4|12|pin@4||-4|9
+Awire|sF|D5G2;||900|pin@5||12|13|pin@6||12|9
+Awire|sT|D5G2;||900|pin@3||-4|13|pin@4||-4|9
Abus|sT,sF|D5G2;|-0.5|IJ2700|mux10/2x@0|sT,sF|0|4|pin@8||0|7
Ein[1:7]||D4G2;|conn@1|a|I
Eout[1:7]||D6G2;|conn@2|y|O
X
# Cell programA;1{sch}
-CprogramA;1{sch}||schematic|1219331355301|1237325202795|
+CprogramA;1{sch}||schematic|1219331355301|1239928658221|
Ngeneric:Facet-Center|art@0||0|0||||AV
IwiresL:bitAssignments;1{ic}|bitAssig@0||22|11.5||V|D5G4;
NOff-Page|conn@0||-24|18|||X|
NOff-Page|conn@1||-19|24|||X|
NOff-Page|conn@3||-42|40|||XYRRR|
-IprogramPartsM:flBgets-B;1{ic}|flBgets-@0||0|-42|||D5G4;
+IprogramPartsM:flBgets-B;1{ic}|flBgets-@0||0|-18|||D5G4;
IinsDecrementOLC;1{ic}|insDecre@3||-18|-54|||D5G4;
-IinsLoadILC;2{ic}|insLoadI@1||-18|-18|||D5G4;
+IinsLoadILC;2{ic}|insLoadI@1||-18|-30|||D5G4;
IinsLoadOLC;1{ic}|insLoadO@5||-18|-6|||D5G4;
-IinsMove;2{ic}|insMove@4||-18|-30|||D5G4;
+IinsMove;2{ic}|insMove@4||-18|-42|||D5G4;
IinsSetFlags;1{ic}|insSetFl@7||-18|6|||D5G4;
-IinsSetFlags;1{ic}|insSetFl@11||-18|-42|||D5G4;
+IinsSetFlags;1{ic}|insSetFl@11||-18|-18|||D5G4;
IlatchesK:mlat1in10;1{ic}|lat[1:36]|D5G3;Y5;|-30|36|X||D5G4;
-IprogramPartsM:mvBitsCapDat;1{ic}|mvBitsCa@2||0|-30|||D5G4;
+IprogramPartsM:mvBitsCapDat;1{ic}|mvBitsCa@2||0|-42|||D5G4;
IprogramPartsM:number3;1{ic}|number3@2||0|-6|||D5G4;
-IprogramPartsM:number4;1{ic}|number4@1||0|-18|||D5G4;
+IprogramPartsM:number4;1{ic}|number4@1||0|-30|||D5G4;
IprogramPartsM:numberXX;1{ic}|numberXX@1||0|-54|||D5G4;
Ngeneric:Invisible-Pin|pin@0||-8|57|||||ART_message(D5G6;)SprogramA
Ngeneric:Invisible-Pin|pin@1||-8|47|||||ART_message(D5G3;)Sies 14 January 2009
IprogramPartsM:flClrAB;1{ic}|skClrAB@1||0|6|||D5G4;
IskipNever;1{ic}|skipNeve@7||-36|6|||D5G4;
IskipNever;1{ic}|skipNeve@8||-36|-6|||D5G4;
-IskipNever;1{ic}|skipNeve@12||-36|-30|||D5G4;
-IskipNever;1{ic}|skipNeve@14||-36|-42|||D5G4;
+IskipNever;1{ic}|skipNeve@12||-36|-42|||D5G4;
+IskipNever;1{ic}|skipNeve@14||-36|-18|||D5G4;
IskipWhenD;1{ic}|skipWhen@9||-36|-54|||D5G4;
-IskipWhenD;1{ic}|skipWhen@10||-36|-18|||D5G4;
+IskipWhenD;1{ic}|skipWhen@10||-36|-30|||D5G4;
IprogramPartsM:srDrive;1{ic}|srDrive@7||-30|24|X||D5G4;
IprogramPartsM:srFirst;1{ic}|srFirst@1||-49|6|||D5G4;
IprogramPartsM:srLoop;1{ic}|srLoop@1||-49|-18|||D5G4;
Awire|net@729|||0|conn@0|y|-26|18|pin@399||-28|18
Abus|net@905||-0.5|IJ1800|pin@365||-42|36|lat[1:36]|out[1]|-32|36
Abus|net@906||-0.5|IJ900|skipNeve@7|intD[31:36]|-36|8|skipNeve@8|intD[31:36]|-36|-4
-Abus|net@907||-0.5|IJ2700|skipNeve@12|intD[31:36]|-36|-28|skipWhen@10|intD[31:36]|-36|-16
-Abus|net@908||-0.5|IJ2700|skipWhen@9|intD[31:36]|-36|-52|skipNeve@14|intD[31:36]|-36|-40
-Abus|net@909||-0.5|IJ2700|skipNeve@14|intD[31:36]|-36|-40|skipNeve@12|intD[31:36]|-36|-28
-Abus|net@910||-0.5|IJ900|skipNeve@8|intD[31:36]|-36|-4|skipWhen@10|intD[31:36]|-36|-16
Abus|net@925||-0.5|IJ1800|srFirst@1|out[T,F]|-45|6|skipNeve@7|s[T,F]|-40|6
Abus|net@928||-0.5|IJ1800|skipNeve@7|s[T,F]|-40|6|insSetFl@7|s[T,F]|-24|6
Abus|net@929||-0.5|IJ1800|insSetFl@7|s[T,F]|-24|6|skClrAB@1|s[T,F]|-6|6
Abus|net@934||-0.5|IJ0|insLoadO@5|s[T,F]|-24|-6|skipNeve@8|s[T,F]|-40|-6
Abus|net@935||-0.5|IJ2700|insLoadO@5|outD[19:30]|-18|-4|insSetFl@7|outD[19:30]|-18|8
Abus|net@936||-0.5|IJ2700|number3@2|intD[1:18]|0|-4|skClrAB@1|intD[1:18]|0|8
-Abus|net@937||-0.5|IJ900|insLoadO@5|outD[19:30]|-18|-4|insLoadI@1|outD[19:30]|-18|-16
-Abus|net@938||-0.5|IJ900|insLoadI@1|outD[19:30]|-18|-16|insMove@4|outD[19:30]|-18|-28
-Abus|net@939||-0.5|IJ900|insMove@4|outD[19:30]|-18|-28|insSetFl@11|outD[19:30]|-18|-40
-Abus|net@940||-0.5|IJ900|insSetFl@11|outD[19:30]|-18|-40|insDecre@3|outD[19:30]|-18|-52
-Abus|net@941||-0.5|IJ1800|srLoop@1|out[T,F]|-45|-18|skipWhen@10|s[T,F]|-40|-18
-Abus|net@942||-0.5|IJ1800|skipWhen@10|s[T,F]|-40|-18|insLoadI@1|s[T,F]|-24|-18
-Abus|net@943||-0.5|IJ1800|srThru@5|out[T,F]|-45|-30|skipNeve@12|s[T,F]|-40|-30
-Abus|net@944||-0.5|IJ1800|skipNeve@12|s[T,F]|-40|-30|insMove@4|s[T,F]|-24|-30
-Abus|net@945||-0.5|IJ1800|srThru@6|out[T,F]|-45|-42|skipNeve@14|s[T,F]|-40|-42
-Abus|net@946||-0.5|IJ1800|skipNeve@14|s[T,F]|-40|-42|insSetFl@11|s[T,F]|-24|-42
+Abus|net@942||-0.5|IJ1800|skipWhen@10|s[T,F]|-40|-30|insLoadI@1|s[T,F]|-24|-30
+Abus|net@944||-0.5|IJ1800|skipNeve@12|s[T,F]|-40|-42|insMove@4|s[T,F]|-24|-42
+Abus|net@946||-0.5|IJ1800|skipNeve@14|s[T,F]|-40|-18|insSetFl@11|s[T,F]|-24|-18
Abus|net@947||-0.5|IJ1800|srThru@7|out[T,F]|-45|-54|skipWhen@9|s[T,F]|-40|-54
Abus|net@948||-0.5|IJ1800|skipWhen@9|s[T,F]|-40|-54|insDecre@3|in[T,F]|-24|-54
-Abus|net@949||-0.5|IJ900|number3@2|intD[1:18]|0|-4|number4@1|intD[1:18]|0|-16
-Abus|net@950||-0.5|IJ900|number4@1|intD[1:18]|0|-16|mvBitsCa@2|intD[1:18]|0|-28
-Abus|net@951||-0.5|IJ900|mvBitsCa@2|intD[1:18]|0|-28|flBgets-@0|intD[1:18]|0|-40
Abus|net@958||-0.5|IJ1800|insDecre@3|in[T,F]|-24|-54|numberXX@1|s[T,F]|-6|-54
-Abus|net@959||-0.5|IJ900|flBgets-@0|intD[1:18]|0|-40|numberXX@1|intD[1:18]|0|-52
Abus|net@960||-0.5|IJ1800|lat[1:36]|in[1]|-28|36|pin@538||-20|36
-Abus|net@962||-0.5|IJ1800|insLoadI@1|s[T,F]|-24|-18|number4@1|s[T,F]|-6|-18
-Abus|net@963||-0.5|IJ1800|insMove@4|s[T,F]|-24|-30|mvBitsCa@2|s[T,F]|-6|-30
-Abus|net@964||-0.5|IJ1800|insSetFl@11|s[T,F]|-24|-42|flBgets-@0|s[T,F]|-6|-42
+Abus|net@962||-0.5|IJ1800|insLoadI@1|s[T,F]|-24|-30|number4@1|s[T,F]|-6|-30
+Abus|net@963||-0.5|IJ1800|insMove@4|s[T,F]|-24|-42|mvBitsCa@2|s[T,F]|-6|-42
+Abus|net@964||-0.5|IJ1800|insSetFl@11|s[T,F]|-24|-18|flBgets-@0|s[T,F]|-6|-18
+Abus|net@965||-0.5|IJ0|skipWhen@10|s[T,F]|-40|-30|srThru@5|out[T,F]|-45|-30
+Abus|net@966||-0.5|IJ0|skipNeve@12|s[T,F]|-40|-42|srThru@6|out[T,F]|-45|-42
+Abus|net@967||-0.5|IJ1800|srLoop@1|out[T,F]|-45|-18|skipNeve@14|s[T,F]|-40|-18
+Abus|net@968||-0.5|IJ900|skipNeve@8|intD[31:36]|-36|-4|skipNeve@14|intD[31:36]|-36|-16
+Abus|net@969||-0.5|IJ2700|skipNeve@12|intD[31:36]|-36|-40|skipWhen@10|intD[31:36]|-36|-28
+Abus|net@970||-0.5|IJ2700|skipWhen@9|intD[31:36]|-36|-52|skipNeve@12|intD[31:36]|-36|-40
+Abus|net@971||-0.5|IJ2700|skipWhen@10|intD[31:36]|-36|-28|skipNeve@14|intD[31:36]|-36|-16
+Abus|net@972||-0.5|IJ900|insLoadO@5|outD[19:30]|-18|-4|insSetFl@11|outD[19:30]|-18|-16
+Abus|net@973||-0.5|IJ900|insSetFl@11|outD[19:30]|-18|-16|insLoadI@1|outD[19:30]|-18|-28
+Abus|net@974||-0.5|IJ900|insLoadI@1|outD[19:30]|-18|-28|insMove@4|outD[19:30]|-18|-40
+Abus|net@975||-0.5|IJ900|insMove@4|outD[19:30]|-18|-40|insDecre@3|outD[19:30]|-18|-52
+Abus|net@976||-0.5|IJ2700|numberXX@1|intD[1:18]|0|-52|mvBitsCa@2|intD[1:18]|0|-40
+Abus|net@977||-0.5|IJ2700|mvBitsCa@2|intD[1:18]|0|-40|number4@1|intD[1:18]|0|-28
+Abus|net@978||-0.5|IJ2700|number4@1|intD[1:18]|0|-28|flBgets-@0|intD[1:18]|0|-16
+Abus|net@979||-0.5|IJ2700|flBgets-@0|intD[1:18]|0|-16|number3@2|intD[1:18]|0|-4
Abus|val[1:18]|D5G2;|-0.5|IJ2700|skClrAB@1|intD[1:18]|0|8|pin@534||0|12
Abus|val[1:36]|D5G2;|-0.5|IJ900|pin@538||-20|36|pin@539||-20|30
Abus|val[19:30]|D5G2;|-0.5|IJ2700|insSetFl@7|outD[19:30]|-18|8|pin@533||-18|12
X
# Cell aGallery;1{sch}
-CaGallery;1{sch}||schematic|1044916063000|1238803665323||prototype_center()I[0,0]
+CaGallery;1{sch}||schematic|1044916063000|1239967814977||prototype_center()I[0,0]
ILEsettings;1{ic}|LEsettin@0||-100|6|||D5G4;|ATTR_LESETTINGS(D6G1;NPX-4;Y-3.5;)I1|ATTR_alpha(D5G1;NPX-1.5;Y-1.5;)D0.7|ATTR_epsilon(D6G1;NPX-4;Y1.5;)S0.01|ATTR_gate_cap(D6G1;NPX-4;Y-0.5;)F0.4|ATTR_keeper_ratio(D5G1;NPY-2.5;)F0.1|ATTR_max_iter(D6G1;NPX-4;Y0.5;)I40|ATTR_su(D6G1;NPX-4;Y3.5;)S4.5|ATTR_wire_ratio(D6G1;NPX-4;Y2.5;)S0.22
IorangeTSMC090nm:NMOS4x_io25;1{ic}|NMOS4_io@0||-66|46|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
IorangeTSMC090nm:NMOS4x_io33;1{ic}|NMOS4_io@2||-75|46|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
IredFive:invCTLp;1{ic}|invCTLn@3||40|-27|Y||D0G4;|ATTR_Delay(D5G1;NPX4.25;Y-1.75;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S1|ATTR_sloDelay(D5G1;NPX4.75;Y-3.25;)I175
IredFive:invHT;1{ic}|invHT@0||-72|-27|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IinvHT;1{ic}|invHT@1||-72|-18|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
-IredFive:invHTI;2{ic}|invHTI@0||-72|-36|||D5G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX1.5;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFive:invI;2{ic}|invI@0||-104|-36|||D5G4;|ATTR_Delay(D5G1;NPX1.75;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX1.25;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invHTI;2{ic}|invHTI@0||-72|-36|||D5G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.25;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invI;2{ic}|invI@0||-104|-36|||D5G4;|ATTR_Delay(D5G1;NPX1.75;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.25;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredFive:invK;1{ic}|invK@0||-56|-27|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1|ATTR_su()I-1
IinvK;1{ic}|invK@1||-56|-18|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEKEEPER(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1|ATTR_su(P)I-1
IredFive:invKV;1{ic}|invKV@0||123|5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-4;)I100|ATTR_XN(D5G1.5;NPX1.5;Y-2.25;)I1|ATTR_XP(D5G1.5;NPX1.5;Y1.75;)I1|ATTR_drive0(P)Sweak0|ATTR_drive1(P)Sweak1
IredFive:invLT;1{ic}|invLT@0||-88|-27|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IinvLT;1{ic}|invLT@1||-88|-18|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
-IredFive:invLTI;2{ic}|invLTI@0||-88|-36|||D5G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX1.5;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:invLTI;2{ic}|invLTI@0||-88|-36|||D5G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.25;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredFive:invV;1{ic}|invV@0||137|5|||D0G4;|ATTR_Delay(D5G1;NPX1.5;Y-4;)I100|ATTR_XN(D5G1.5;NPX1.75;Y-2.5;)I1|ATTR_XP(D5G1.5;NPX1.75;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredFive:invVn;1{ic}|invVn@0||95|5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-3;)I100|ATTR_NPdrvR(D5G1;NPX2;Y-2;)I1|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredFive:invVp;1{ic}|invVp@0||109|5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-3;)I100|ATTR_PNdrvR(D5G1;NPX2;Y-2;)I1|ATTR_X(D5G1.5;NPX1.5;Y2;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredFive:nms3a;1{ic}|nms3a@0||-18|75|||D5G4;|ATTR_Delay(D5G1;NPX4.5;Y-0.5;)I100|ATTR_X(D5G1;NOLPX4.5;Y0.5;)S1
IredFive:nms3b;1{ic}|nms3b@0||-6|75|||D5G4;|ATTR_Delay(D5G1;NPX-3.25;Y0.5;)I100|ATTR_X(D5G1;NOLPX-3.25;Y1.5;)S1
IredFive:nms3c;1{ic}|nms3c@0||6|75|||D5G4;|ATTR_Delay(D5G1;NPX-3.5;Y-3;)I100|ATTR_X(D5G1;NOLPX-3.5;Y-2;)S1
-IredFive:nor2;1{ic}|nor2@0||-105|-66|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su()I-1
Inor2;1{ic}|nor2@1||-105|-48|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.25;Y2.25;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
-IredFive:nor2HT_sya;2{ic}|nor2HT_s@0||153|-82|||D5G4;|ATTR_Delay(D5G1;NPX4;Y-1.75;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX3.75;Y2.75;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFive:nor2_sy;1{ic}|nor2_sy@0||-87|-66|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(T)I-1
+IredFive:nor2;1{ic}|nor2@2||-105|-66|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX2.25;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:nor2HT_sya;2{ic}|nor2HT_s@0||153|-82|||D5G4;|ATTR_Delay(D5G1;NPX4;Y-1.75;)I100|ATTR_X(D5FLeave alone;G1.5;NPX2.5;Y2.25;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Inor2_sy;2{ic}|nor2_sy@1||-87|-48|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2.5;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.25;Y2.25;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
+IredFive:nor2_sy;1{ic}|nor2_sy@3||-87|-66|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX2.25;Y2.25;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Inor2en;1{ic}|nor2en@0||72|-48|||D5G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.25;Y2.25;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
IredFive:nor2en;1{ic}|nor2en@1||72|-66|||D5G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Inor2k;1{ic}|nor2k@0||90|-48|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_LEKEEPER(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.25;Y2.25;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
Inor2kresetV;1{ic}|nor2kres@0||162|-60.5|||D5G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_LEGATE(D5G1;NPX-92.75;Y-40.75;)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.25;Y2.25;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
IredFive:nor2n;1{ic}|nor2n@0||-105|-75|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5G1.5;NPX2.25;Y2.25;)I1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Inor2n;1{ic}|nor2n@1||-105|-57|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-3;)I100|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX3.5;Y2.5;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
-IredFive:nor2n_sy;1{ic}|nor2n_sy@1||-87|-75|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.25;Y2.25;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Inor2n_sy;2{ic}|nor2n_sy@3||-87|-57|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-3.5;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.25;Y2.25;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
Inor2n_sy;2{ic}|nor2n_sy@4||162|-72|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-3.5;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX2.25;Y2.25;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
+IredFive:nor2n_sy;1{ic}|nor2n_sy@5||-87|-75|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NPX2.25;Y2.25;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
IredFive:passF;1{ic}|passF@0||121|17|||D5G4;|ATTR_XN(D5G1;NPX-3.25;Y-0.5;)I1|ATTR_XP(D5G1;NPX3.25;Y-0.5;)I1|ATTR_Xinv(D5G1;NPY2.5;)I1
IredFive:passT;1{ic}|passT@0||109|17|||D5G4;|ATTR_XN(D5G1;NPX-3.25;Y-0.5;)I1|ATTR_XP(D5G1;NPX3.25;Y-0.5;)I1|ATTR_Xinv(D5G1;NPY2.5;)I1
IredFive:passTF;1{ic}|passTF@0||134|17|||D5G4;|ATTR_XN(D5G1;NPX-3.25;Y-0.5;)I1|ATTR_XP(D5G1;NPX3.25;Y-0.5;)I1
# header information:
-HredFive|8.08o|USER_electrical_units()I70464
+HredFive|8.09a|USER_electrical_units()I70464
# Views:
Vicon|ic
X
# Cell nor2;1{sch}
-Cnor2;1{sch}||schematic|1021415734000|1231517768916||ATTR_Delay(D5G1;HNPX-18;Y-6;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-18;Y-5;)S1|ATTR_drive0(D5G1;HNPTX-18;Y-7;)Sstrong0|ATTR_drive1(D5G1;HNPTX-18;Y-8;)Sstrong1|ATTR_verilog_template(D5G1;NTX5.5;Y-18.5;)Snor ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
+Cnor2;1{sch}||schematic|1021415734000|1239967786229||ATTR_Delay(D5G1;HNPX-18;Y-6;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-18;Y-5;)S1|ATTR_drive0(D5G1;HNPTX-18;Y-7;)Sstrong0|ATTR_drive1(D5G1;HNPTX-18;Y-8;)Sstrong1|ATTR_verilog_template(D5G1;NTX5.5;Y-18.5;)Snor ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
IorangeTSMC090nm:NMOSx;1{ic}|NMOS@0||-4|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
IorangeTSMC090nm:NMOSx;1{ic}|NMOS@1||4|-8|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@1||14|-8|||RR|
NOff-Page|conn@2||14|0||||
NGround|gnd@0||0|-15||||
-Inor2;1{ic}|nor2@0||24.5|14.5|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.25;Y2.25;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-Inor2nn;1{ic}|nor2nn@0||25|8|||D5G4;|ATTR_Delay(D5G1;NPX-18;Y-6;)I100|ATTR_X(D5FLeave alone;G1;NOLPX-18;Y-5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Inor2;1{ic}|nor2@0||24.5|14.5|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX2.25;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Inor2nn;1{ic}|nor2nn@0||25|8|||D5G4;|ATTR_Delay(D5G1;NPX-18;Y-6;)I100|ATTR_X(D5FLeave alone;G1;NPX-18;Y-5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
NWire_Pin|pin@0||0|-11.5||||
NWire_Pin|pin@1||-4|-11.5||||
NWire_Pin|pin@2||4|-11.5||||
X
# Cell nor2_sy;1{sch}
-Cnor2_sy;1{sch}||schematic|1021415734000|1227395980725||ATTR_Delay(D5G1;HNPX-18;Y-6;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-18;Y-5;)S1|ATTR_drive0(D5G1;HNPTX-18;Y-7;)Sstrong0|ATTR_drive1(D5G1;HNPTX-18;Y-8;)Sstrong1|ATTR_verilog_template(D5G1;NTX5.5;Y-18.5;)Snor ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
+Cnor2_sy;1{sch}||schematic|1021415734000|1239967677870||ATTR_Delay(D5G1;HNPX-18;Y-6;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-18;Y-5;)S1|ATTR_drive0(D5G1;HNPTX-18;Y-7;)Sstrong0|ATTR_drive1(D5G1;HNPTX-18;Y-8;)Sstrong1|ATTR_verilog_template(D5G1;NTX5.5;Y-18.5;)Snor ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
IorangeTSMC090nm:NMOSx;1{ic}|NMOS@0||4|-8|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
IorangeTSMC090nm:NMOSx;1{ic}|NMOS@1||-4|-8|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@1||14|-8|||RR|
NOff-Page|conn@2||-15.5|0||||
NGround|gnd@0||0|-15||||
-Inor2_sy;1{ic}|nor2_sy@0||29.5|17|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.25;Y2.25;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Inor2_sy;1{ic}|nor2_sy@0||29.5|17|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX2.25;Y2.25;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
Ngeneric:Invisible-Pin|pin@0||27|-14|||||ART_message(D5G2;)S[X is drive strength,One pull-down is as strong,as the pull-up]
NWire_Pin|pin@1||-4|0||||
NWire_Pin|pin@2||4|0||||
X
# Cell nor2n_sy;1{sch}
-Cnor2n_sy;1{sch}||schematic|1021415734000|1223674427927||ATTR_Delay(D5G1;HNPX-18;Y-8.5;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-18;Y-7.5;)S1|ATTR_drive0(D5G1;HNPTX-18;Y-9.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-18;Y-10.5;)Sstrong1|prototype_center()I[0,0]
+Cnor2n_sy;1{sch}||schematic|1021415734000|1239967624447||ATTR_Delay(D5G1;HNPX-18;Y-8.5;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-18;Y-7.5;)S1|ATTR_drive0(D5G1;HNPTX-18;Y-9.5;)Sstrong0|ATTR_drive1(D5G1;HNPTX-18;Y-10.5;)Sstrong1|prototype_center()I[0,0]
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@0||10.5|0||||
NOff-Page|conn@1||-15.5|2.5||||
NOff-Page|conn@2||-15.5|-2.5||||
Inor2_sy;1{ic}|nor2@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX2.25;Y2.25;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
-Inor2n_sy;1{ic}|nor2n@0||24|5.5|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.25;Y2.25;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Inor2n_sy;1{ic}|nor2n@0||24|5.5|||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NPX2.25;Y2.25;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
NWire_Pin|pin@0||-7|-2.5||||
NWire_Pin|pin@1||-7|-1||||
NWire_Pin|pin@2||-7|1||||
X
# Cell outM1PredLit;1{sch}
-CoutM1PredLit;1{sch}||schematic|1237229034349|1239536069408|I
+CoutM1PredLit;1{sch}||schematic|1237229034349|1240273138665|I
Ngeneric:Facet-Center|art@0||0|0||||AV
NOff-Page|conn@2||35.5|-10||||
NOff-Page|conn@3||57|3||||
NOff-Page|conn@6||-24|-13|||RRR|
NOff-Page|conn@8||-11.5|5|||Y|
NOff-Page|conn@11||-57|3|||Y|
-NOff-Page|conn@12||-36|-13|||RRR|
+NOff-Page|conn@12||-35|-13|||RRR|
NOff-Page|conn@13||-58|-9||||
NOff-Page|conn@14||-56|8|||Y|
NOff-Page|conn@15||57|8||||
NBus_Pin|pin@3||17|-9|-1|-1||
NBus_Pin|pin@5||17|-12|-1|-1||
NBus_Pin|pin@23||-24|-9|-1|-1||
-NWire_Pin|pin@27||-36|5||||
+NWire_Pin|pin@27||-35|5||||
NBus_Pin|pin@28||-30|3|-1|-1||
NBus_Pin|pin@29||-30|0|-1|-1||
NWire_Pin|pin@34||39.5|3||||
Abus|net@30||-0.5|IJ900|pin@23||-24|-9|conn@6|a|-24|-11
Abus|net@32||-0.5|IJ1800|conn@8|y|-9.5|5|outDockP@0|pred[D,T]|-4|5
Awire|net@36|||0|mOneDock@0|pred|-52|3|conn@11|y|-55|3
-Awire|net@37|||2700|conn@12|a|-36|-11|pin@27||-36|5
-Awire|net@38|||0|pin@27||-36|5|mOneDock@0|succ|-44|5
+Awire|net@37|||2700|conn@12|a|-35|-11|pin@27||-35|5
+Awire|net@38|||0|pin@27||-35|5|mOneDock@0|succ|-44|5
Abus|net@39||-0.5|IJ0|mOneDock@0|in[1:36]|-52|-9|conn@13|y|-56|-9
Abus|net@43||-0.5|IJ1800|mOneDock@0|out[1:36]|-42|-9|pin@23||-24|-9
Abus|net@46||-0.5|IJ0|outDockP@0|m1cate[1:6][T,F]|-5|3|pin@28||-30|3
*** SPICE deck for cell marinaOut{sch} from library aMarinaM
*** Created on Mon Nov 17, 2008 08:47:24
*** Last revised on Mon Mar 30, 2009 06:59:15
-*** Written on Mon Apr 13, 2009 11:37:47 by Electric VLSI Design System,
+*** Written on Mon Apr 20, 2009 18:24:51 by Electric VLSI Design System,
*version 8.08k
*** Layout tech: cmos90, foundry TSMC
*** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
XPMOS@0 out in vdd PMOSx-X_5
.ENDS inv-X_5
-*** CELL: orangeTSMC090nm:NMOSx{sch}
-.SUBCKT NMOSx-X_1_733 d g s
-MNMOSf@0 d g s gnd nch W='5.199*(1+ABN/sqrt(5.199*2))' L='2'
+*** CELL: orangeTSMC090nm:NMOSxwk{sch}
+.SUBCKT NMOSxwk-X_1_733 d g s
+MNMOSfwk@0 d g s gnd nch W='5.199*(1+ABN/sqrt(5.199*2))' L='2'
+DELVTO='AVT0N/sqrt(5.199*2)'
-.ENDS NMOSx-X_1_733
-
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_4 d g s
-MPMOSf@0 d g s vdd pch W='24*(1+ABP/sqrt(24*2))' L='2'
-+DELVTO='AVT0P/sqrt(24*2)'
-.ENDS PMOSx-X_4
+.ENDS NMOSxwk-X_1_733
-*** CELL: orangeTSMC090nm:PMOSx{sch}
-.SUBCKT PMOSx-X_1 d g s
-MPMOSf@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2'
+*** CELL: orangeTSMC090nm:PMOSxwk{sch}
+.SUBCKT PMOSxwk-X_1 d g s
+MPMOSfwk@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2'
+DELVTO='AVT0P/sqrt(6*2)'
-.ENDS PMOSx-X_1
+.ENDS PMOSxwk-X_1
+
+*** CELL: orangeTSMC090nm:PMOSxwk{sch}
+.SUBCKT PMOSxwk-X_4 d g s
+MPMOSfwk@0 d g s vdd pch W='24*(1+ABP/sqrt(24*2))' L='2'
++DELVTO='AVT0P/sqrt(24*2)'
+.ENDS PMOSxwk-X_4
*** CELL: latchPartsK:latchKeep{sch}
.SUBCKT latchKeep out[B] out[s]
-XNMOSx@0 out[B] out[s] gnd NMOSx-X_1_733
-XNMOSx@1 out[s] out[B] gnd NMOSx-X_1_733
-XPMOSx@0 out[B] out[s] vdd PMOSx-X_4
-XPMOSx@1 out[s] out[B] vdd PMOSx-X_1
+XNMOSxwk@0 out[s] out[B] gnd NMOSxwk-X_1_733
+XNMOSxwk@1 out[B] out[s] gnd NMOSxwk-X_1_733
+XPMOSxwk@0 out[s] out[B] vdd PMOSxwk-X_1
+XPMOSxwk@1 out[B] out[s] vdd PMOSxwk-X_4
.ENDS latchKeep
*** CELL: orangeTSMC090nm:NMOSx{sch}
.SUBCKT half2inArb cross grant[B] inA req[B]
XNMOSx@0 vdd req[B] grant[B] PMOSx-X_10
XPMOSx@0 cross inA grant[B] NMOSx-X_10
+XPMOSxwk@0 grant[B] gnd vdd PMOSxwk-X_1
Xnor2n@0 inA req[B] cross nand2-X_25
.ENDS half2inArb
+DELVTO='AVT0N/sqrt(12*2)'
.ENDS NMOSx-X_4
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_4 d g s
+MPMOSf@0 d g s vdd pch W='24*(1+ABP/sqrt(24*2))' L='2'
++DELVTO='AVT0P/sqrt(24*2)'
+.ENDS PMOSx-X_4
+
*** CELL: redFive:inv{sch}
.SUBCKT inv-X_4 in out
XNMOS@0 out in gnd NMOSx-X_4
*** CELL: driversJ:latchDriver60{sch}
.SUBCKT latchDriver60 in out
Xinv@1 in net@16 inv-X_20
-XinvI@0 net@8 out inv-X_60
-Xwire90@0 net@16 net@8 wire90-544_2-layer_1-width_3
+XinvI@2 net@17 out inv-X_60
+Xwire90@0 net@16 net@17 wire90-544_2-layer_1-width_3
.ENDS latchDriver60
*** CELL: driversL:predDri60wMC{sch}
.ENDS gaspFill
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-70-R_34_667m a b
-Ccap@0 gnd net@14 0.257f
-Ccap@1 gnd net@8 0.257f
-Ccap@2 gnd net@11 0.257f
-Rres@0 net@14 a 0.404
-Rres@1 net@11 net@14 0.809
-Rres@2 b net@8 0.404
-Rres@3 net@8 net@11 0.809
-.ENDS wire-C_0_011f-70-R_34_667m
+.SUBCKT wire-C_0_011f-185_4-R_34_667m a b
+Ccap@0 gnd net@14 0.68f
+Ccap@1 gnd net@8 0.68f
+Ccap@2 gnd net@11 0.68f
+Rres@0 net@14 a 1.071
+Rres@1 net@11 net@14 2.142
+Rres@2 b net@8 1.071
+Rres@3 net@8 net@11 2.142
+.ENDS wire-C_0_011f-185_4-R_34_667m
*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-70-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-70-R_34_667m
-.ENDS wire90-70-layer_1-width_3
+.SUBCKT wire90-185_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-185_4-R_34_667m
+.ENDS wire90-185_4-layer_1-width_3
*** CELL: scanM:scanAmp{sch}
.SUBCKT scanAmp in[1] out[1]
-Xinv@0 in[1] net@1 inv-X_10
+Xinv@0 in[1] net@1 inv-X_5
Xinv@1 net@2 out[1] inv-X_20
-Xwire90@0 net@1 net@2 wire90-70-layer_1-width_3
+Xwire90@0 net@1 net@2 wire90-185_4-layer_1-width_3
.ENDS scanAmp
*** CELL: scanM:scanAMPx5{sch}
+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
-+succ
++sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
++sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ
Xaddr1in6@0 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2]
+aout[3] aout[4] aout[5] aout[6] aout[7] net@13 sx[3] sx[2] sx[5] net@61
+net@62 sx[A] addr1in60Cx7scan
+sx[1] sx[2] sx[3] sx[4] sx[5] scanAMPx5
XscanAMPx@3 sz[1] sx[2] sx[3] sx[4] sx[5] sid[6] sid[7] sid[8] sid[9] sod[1]
+sod[2] sod[3] sod[4] sod[5] scanAMPx5
-XscanEx2@0 s[1] s[2] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
-+sir[8] sor[1] scanEx2
-XscanFx3@0 block extra fill sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
-+sic[8] sic[9] soc[1] scanFx3
+XscanAMPx@4 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9]
++net@139[8] soc[2] soc[3] soc[4] soc[5] scanAMPx5
+XscanAMPx@5 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
++net@142[8] sor[2] sor[3] sor[4] sor[5] scanAMPx5
+XscanEx2@0 s[1] s[2] sir[9] net@142[8] sor[2] sor[3] sor[4] sor[5] sir[6]
++sir[7] sir[8] sor[1] scanEx2
+XscanFx3@0 block extra fill net@139[8] soc[2] soc[3] soc[4] soc[5] sic[6]
++sic[7] sic[8] sic[9] soc[1] scanFx3
Xtc[1] tranCap
Xtc[2] tranCap
Xtc[3] tranCap
+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
-+succ
++sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
++sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ
XdrainSta@1 net@65[41] net@65[40] net@65[39] net@65[38] net@65[37] net@65[50]
+net@65[49] net@65[48] net@65[47] net@65[46] net@65[45] net@65[44] net@65[43]
+net@65[42] net@65[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
+out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24]
+out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32]
+out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7]
-+out[8] out[9] net@42 net@3[8] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
-+sic[8] sic[9] net@2[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
++out[8] out[9] net@42 net@3[8] soc[2] soc[3] soc[4] soc[5] sic[6] sic[7]
++sic[8] sic[9] net@2[8] sor[2] sor[3] sor[4] sor[5] sir[6] sir[7] sir[8]
+sir[9] soc[1] sor[1] succ drainStage
XfillStag@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] net@65[41] net@65[40]
+net@65[32] net@65[31] net@65[30] net@65[29] net@65[28] pred sic[1] sic[2]
+sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4]
+sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6]
-+sir[7] sir[8] sir[9] net@3[8] sod[1] sod[2] sod[3] sod[4] sod[5] net@2[8]
-+net@41 fillStage
++sir[7] sir[8] sir[9] net@3[8] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
++sod[3] sod[4] sod[5] net@2[8] sor[2] sor[3] sor[4] sor[5] net@41 fillStage
Xwire90@0 net@41 net@42 wire90-2080_4-layer_1-width_3
.ENDS properStopper
+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
-+succ
++sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
++sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ
Xinstruct@0 net@53 net@48 fin fout net@61[8] sod[2] sod[3] sod[4] sod[5]
+sid[6] sid[7] sid[8] sid[9] sod[1] instructionCount
XproperSt@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] net@61[8] sod[2] sod[3] sod[4] sod[5]
-+sor[1] succ properStopper
++sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] net@61[8]
++sod[2] sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ
++properStopper
Xwire90@1 net@86 net@48 wire90-2080_4-layer_1-width_3
.ENDS fillDrainCount
+outD[25] outD[26] outD[27] outD[28] outD[29] outD[2] outD[30] outD[31]
+outD[32] outD[33] outD[34] outD[35] outD[36] outD[37] outD[3] outD[4] outD[5]
+outD[6] outD[7] outD[8] outD[9] predU sic[1] sic[2] sic[3] sic[4] sic[5]
-+sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9]
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[8] sir[9] succD
++sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7]
++sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
++succD
XfillDrai@1 net@256[41] net@256[40] net@256[39] net@256[38] net@256[37]
+net@256[50] net@256[49] net@256[48] net@256[47] net@256[46] net@256[45]
+net@256[44] net@256[43] net@256[42] net@256[51] net@259[41] net@259[40]
+net@259[12] net@259[11] net@259[10] net@259[9] net@259[8] net@259[35]
+net@259[7] net@259[6] net@259[5] net@259[4] net@259[3] net@259[2] net@259[1]
+net@259[0] net@259[34] net@259[33] net@259[32] net@259[31] net@259[30]
-+net@259[29] net@259[28] net@263 sic[1] sic[2] sic[3] sic[4] sic[5] sic[3]
-+sic[2] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8]
-+sid[9] net@254[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] sir[9]
-+sic[8] sid[8] sid[7] sid[6] net@235[5] net@235[4] sir[8] net@267
-+fillDrainCount
++net@259[29] net@259[28] net@263 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6]
++sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8]
++sid[9] net@254[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
++sic[8] sic[7] sic[6] net@236[5] net@236[4] sid[8] sid[7] sid[6] net@235[5]
++net@235[4] sir[8] sir[7] sir[6] net@262[5] net@262[4] net@267 fillDrainCount
XscanCap@5 sid[8] sid[7] sid[6] net@235[5] net@235[4] sid[9] scanCap
-XscanCap@6 sic[8] sic[2] sic[3] sic[4] sic[5] sic[9] scanCap
-XscanCap@7 sir[8] sir[2] sir[3] sir[4] sir[5] sir[9] scanCap
+XscanCap@6 sic[8] sic[7] sic[6] net@236[5] net@236[4] sic[9] scanCap
+XscanCap@7 sir[8] sir[7] sir[6] net@262[5] net@262[4] sir[9] scanCap
XupDown8w@2 net@259[41] net@259[40] net@259[39] net@259[38] net@259[37]
+net@259[50] net@259[49] net@259[48] net@259[47] net@259[46] net@259[45]
+net@259[44] net@259[43] net@259[42] net@259[51] ainU[10] ainU[11] ainU[12]
+net@256[11] net@256[10] net@256[9] net@256[8] net@256[35] net@256[7]
+net@256[6] net@256[5] net@256[4] net@256[3] net@256[2] net@256[1] net@256[0]
+net@256[34] net@256[33] net@256[32] net@256[31] net@256[30] net@256[29]
-+net@256[28] net@229 predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2]
++net@256[28] net@229 predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
+sir[8] sir[9] net@254[8] succD net@264 upDown8weak
Xwire90@6 net@229 net@267 wire90-1185_9-layer_1-width_3
Xwire90@18 net@264 net@263 wire90-1185_9-layer_1-width_3
*** CELL: centersJ:ctrAND2in30{sch}
.SUBCKT ctrAND2in30 inA inB out
-Xinv@0 net@7 net@8 inv-X_10
-Xinv@1 net@9 out inv-X_30
+Xinv@3 net@9 out inv-X_30
+XinvI@1 net@7 net@8 inv-X_10
Xnor2HT_s@1 inA inB net@6 nor2HT_sy-X_4
Xwire90@0 net@6 net@7 wire90-249_5-layer_1-width_3
Xwire90@1 net@8 net@9 wire90-355_8-layer_1-width_3
*** CELL: centersJ:ctrAND3in30A{sch}
.SUBCKT ctrAND3in30A inA inB inC out outM
-Xinv@1 outM out inv-X_30
+XinvI@1 outM out inv-X_30
Xnand2_sy@0 net@15 inC outM nand2_sy-X_10
Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5
Xwire90@0 net@6 net@15 wire90-414-layer_1-width_3
Xinv@8 pred net@358 inv-X_5
Xinv@9 bits[HEAD] net@441 inv-X_5
Xinv@10 bits[ABORT] net@463 inv-X_5
-XinvI@1 net@368 fire[od] inv-X_30
XinvI@2 net@317 s[2] inv-X_10
-XinvI@3 net@314 s[1] inv-X_10
-Xnand2LT_@0 net@371 net@374 net@367 nand2LT_sy-X_10
-Xnor2_sy@4 flag[A][set] flag[A][clr] net@305 nor2_sy-X_5
-Xnor2_sy@5 flag[D][set] flag[D][clr] net@297 nor2_sy-X_5
+XinvI@5 net@368 fire[od] inv-X_30
+XinvI@6 net@314 s[1] inv-X_10
+Xnand2LT_@2 net@371 net@374 net@367 nand2LT_sy-X_10
+Xnor2_sy@7 flag[A][set] flag[A][clr] net@305 nor2_sy-X_5
+Xnor2_sy@8 flag[D][set] flag[D][clr] net@297 nor2_sy-X_5
Xnor3in3_@2 net@317 net@436 net@314 net@322 nor3in6_6sym
Xnor3in3_@5 od[ABORT] od[OTHER] od[HEAD] net@476 nor3in6_6sym
XpredDri2@2 fire[od] mc pred predDri20wMC
*** CELL: centersJ:ctrAND2in30A{sch}
.SUBCKT ctrAND2in30A inA inB out
-Xinv@1 net@9 out inv-X_30
-Xinv@2 inA net@27 inv-X_5
-Xnand2LT_@0 net@32 inB net@24 nand2LT_sy-X_10
+XinvI@1 inA net@27 inv-X_5
+XinvI@2 net@9 out inv-X_30
+Xnand2LT_@2 net@32 inB net@24 nand2LT_sy-X_10
Xwire90@0 net@27 net@32 wire90-161_8-layer_1-width_3
Xwire90@1 net@24 net@9 wire90-372_8-layer_1-width_3
.ENDS ctrAND2in30A
.ENDS nand3in6_6
*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-3616_3-R_34_667m a b
-Ccap@0 gnd net@14 13.26f
-Ccap@1 gnd net@8 13.26f
-Ccap@2 gnd net@11 13.26f
-Rres@0 net@14 a 20.894
-Rres@1 net@11 net@14 41.788
-Rres@2 b net@8 20.894
-Rres@3 net@8 net@11 41.788
-.ENDS wire-C_0_011f-3616_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-3616_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-3616_3-R_34_667m
-.ENDS wire90-3616_3-layer_1-width_3
-
-*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-3495_7-R_34_667m a b
Ccap@0 gnd net@14 12.818f
Ccap@1 gnd net@8 12.818f
.ENDS wire90-3495_7-layer_1-width_3
*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3616_3-R_34_667m a b
+Ccap@0 gnd net@14 13.26f
+Ccap@1 gnd net@8 13.26f
+Ccap@2 gnd net@11 13.26f
+Rres@0 net@14 a 20.894
+Rres@1 net@11 net@14 41.788
+Rres@2 b net@8 20.894
+Rres@3 net@8 net@11 41.788
+.ENDS wire-C_0_011f-3616_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3616_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3616_3-R_34_667m
+.ENDS wire90-3616_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
.SUBCKT wire-C_0_011f-270-R_34_667m a b
Ccap@0 gnd net@14 0.99f
Ccap@1 gnd net@8 0.99f
Xwire@0 a b wire-C_0_011f-358-R_34_667m
.ENDS wire90-358-layer_1-width_3
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-433_4-R_34_667m a b
+Ccap@0 gnd net@14 1.589f
+Ccap@1 gnd net@8 1.589f
+Ccap@2 gnd net@11 1.589f
+Rres@0 net@14 a 2.504
+Rres@1 net@11 net@14 5.008
+Rres@2 b net@8 2.504
+Rres@3 net@8 net@11 5.008
+.ENDS wire-C_0_011f-433_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-433_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-433_4-R_34_667m
+.ENDS wire90-433_4-layer_1-width_3
+
*** CELL: registersM:newPathReg{sch}
.SUBCKT newPathReg aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT]
+aout[7] aout[8] aout[9] aout[TT] take[dp] take[ps] addr2in60Cx15
Xinv@1 ps[13] net@46 inv-X_10
Xinv@2 ps[14] net@47 inv-X_10
-Xinv@3 ps[15] ps[15not] inv-X_10
+Xinv@3 ps[15] net@52 inv-X_10
XinvI@0 net@19 net@40 inv-X_30
XlatchAnd@0 ps[14] fire[M] net@43 latchAndDriver30
Xnand3in6@1 net@25 net@28 fire[M] net@19 nand3in6_6
-Xwire90@0 net@43 take[ps] wire90-3616_3-layer_1-width_3
-Xwire90@1 net@40 take[dp] wire90-3495_7-layer_1-width_3
+Xwire90@0 net@43 take[ps] wire90-3495_7-layer_1-width_3
+Xwire90@1 net@40 take[dp] wire90-3616_3-layer_1-width_3
Xwire90@3 net@46 net@28 wire90-270-layer_1-width_3
Xwire90@4 net@47 net@25 wire90-358-layer_1-width_3
+Xwire90@5 net@52 ps[15not] wire90-433_4-layer_1-width_3
.ENDS newPathReg
*** CELL: redFive:nor2_sy{sch}
Xinv@0 net@51 resetLO inv-X_10
Xinv@2 fire[both] net@54 inv-X_10
XinvI@0 net@18 net@49 inv-X_5
-XinvI@1 net@66 s[1] inv-X_10
-XinvI@2 net@71 s[2] inv-X_10
-Xnor2_sy@2 m1cate[1][F] m1cate[1][T] net@62 nor2_sy-X_5
-Xnor2_sy@3 flag[A][clr] flag[A][set] net@67 nor2_sy-X_5
+XinvI@4 net@66 s[1] inv-X_10
+XinvI@5 net@71 s[2] inv-X_10
+Xnor2_sy@5 flag[A][clr] flag[A][set] net@67 nor2_sy-X_5
+Xnor2_sy@6 m1cate[1][F] m1cate[1][T] net@62 nor2_sy-X_5
XohSRxor6@1 do any flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
+flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T]
+m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T]
Xwire90@24 net@165 ilc[load] wire90-867_8-layer_1-width_3
.ENDS outDockCenter
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3405_8-R_34_667m a b
+Ccap@0 gnd net@14 12.488f
+Ccap@1 gnd net@8 12.488f
+Ccap@2 gnd net@11 12.488f
+Rres@0 net@14 a 19.678
+Rres@1 net@11 net@14 39.356
+Rres@2 b net@8 19.678
+Rres@3 net@8 net@11 39.356
+.ENDS wire-C_0_011f-3405_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3405_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3405_8-R_34_667m
+.ENDS wire90-3405_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5146_2-R_34_667m a b
+Ccap@0 gnd net@14 18.869f
+Ccap@1 gnd net@8 18.869f
+Ccap@2 gnd net@11 18.869f
+Rres@0 net@14 a 29.734
+Rres@1 net@11 net@14 59.467
+Rres@2 b net@8 29.734
+Rres@3 net@8 net@11 59.467
+.ENDS wire-C_0_011f-5146_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5146_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-5146_2-R_34_667m
+.ENDS wire90-5146_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5054_2-R_34_667m a b
+Ccap@0 gnd net@14 18.532f
+Ccap@1 gnd net@8 18.532f
+Ccap@2 gnd net@11 18.532f
+Rres@0 net@14 a 29.202
+Rres@1 net@11 net@14 58.404
+Rres@2 b net@8 29.202
+Rres@3 net@8 net@11 58.404
+.ENDS wire-C_0_011f-5054_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5054_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-5054_2-R_34_667m
+.ENDS wire90-5054_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4771_5-R_34_667m a b
+Ccap@0 gnd net@14 17.496f
+Ccap@1 gnd net@8 17.496f
+Ccap@2 gnd net@11 17.496f
+Rres@0 net@14 a 27.569
+Rres@1 net@11 net@14 55.137
+Rres@2 b net@8 27.569
+Rres@3 net@8 net@11 55.137
+.ENDS wire-C_0_011f-4771_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4771_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4771_5-R_34_667m
+.ENDS wire90-4771_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4764_9-R_34_667m a b
+Ccap@0 gnd net@14 17.471f
+Ccap@1 gnd net@8 17.471f
+Ccap@2 gnd net@11 17.471f
+Rres@0 net@14 a 27.531
+Rres@1 net@11 net@14 55.061
+Rres@2 b net@8 27.531
+Rres@3 net@8 net@11 55.061
+.ENDS wire-C_0_011f-4764_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4764_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4764_9-R_34_667m
+.ENDS wire90-4764_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4475_8-R_34_667m a b
+Ccap@0 gnd net@14 16.411f
+Ccap@1 gnd net@8 16.411f
+Ccap@2 gnd net@11 16.411f
+Rres@0 net@14 a 25.86
+Rres@1 net@11 net@14 51.72
+Rres@2 b net@8 25.86
+Rres@3 net@8 net@11 51.72
+.ENDS wire-C_0_011f-4475_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4475_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4475_8-R_34_667m
+.ENDS wire90-4475_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4496_1-R_34_667m a b
+Ccap@0 gnd net@14 16.486f
+Ccap@1 gnd net@8 16.486f
+Ccap@2 gnd net@11 16.486f
+Rres@0 net@14 a 25.977
+Rres@1 net@11 net@14 51.955
+Rres@2 b net@8 25.977
+Rres@3 net@8 net@11 51.955
+.ENDS wire-C_0_011f-4496_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4496_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4496_1-R_34_667m
+.ENDS wire90-4496_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3136_9-R_34_667m a b
+Ccap@0 gnd net@14 11.502f
+Ccap@1 gnd net@8 11.502f
+Ccap@2 gnd net@11 11.502f
+Rres@0 net@14 a 18.124
+Rres@1 net@11 net@14 36.249
+Rres@2 b net@8 18.124
+Rres@3 net@8 net@11 36.249
+.ENDS wire-C_0_011f-3136_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3136_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3136_9-R_34_667m
+.ENDS wire90-3136_9-layer_1-width_3
+
*** CELL: stagesM:outDockPredStage{sch}
.SUBCKT outDockPredStage do[Lt] epi[torp] fire[M] flag[A][clr] flag[A][set]
+flag[C][T] flag[D][clr] flag[D][set] in[1] in[2] in[3] in[4] in[5] in[6]
+pred[D] pred[T] ps[do] ps[skip] m1[24] m1[22] m1[23] m1[27] m1[25] m1[26]
+m1[21] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1]
+succ[sf] outDockCenter
-Xwire90@0 net@6 net@39 wire90-791_7-layer_1-width_3
+Xwire90@0 net@6 net@39 wire90-3405_8-layer_1-width_3
+Xwire90@1 wire90@1_a inLO[1] wire90-5146_2-layer_1-width_3
+Xwire90@2 wire90@2_a inLO[2] wire90-5054_2-layer_1-width_3
+Xwire90@3 wire90@3_a inLO[3] wire90-4771_5-layer_1-width_3
+Xwire90@4 wire90@4_a inLO[4] wire90-4764_9-layer_1-width_3
+Xwire90@5 wire90@5_a inLO[5] wire90-4475_8-layer_1-width_3
+Xwire90@6 wire90@6_a inLO[6] wire90-4496_1-layer_1-width_3
+Xwire90@7 wire90@7_a inLO[8] wire90-3136_9-layer_1-width_3
.ENDS outDockPredStage
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2993_2-R_34_667m a b
+Ccap@0 gnd net@14 10.975f
+Ccap@1 gnd net@8 10.975f
+Ccap@2 gnd net@11 10.975f
+Rres@0 net@14 a 17.294
+Rres@1 net@11 net@14 34.588
+Rres@2 b net@8 17.294
+Rres@3 net@8 net@11 34.588
+.ENDS wire-C_0_011f-2993_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2993_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2993_2-R_34_667m
+.ENDS wire90-2993_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3539_8-R_34_667m a b
+Ccap@0 gnd net@14 12.979f
+Ccap@1 gnd net@8 12.979f
+Ccap@2 gnd net@11 12.979f
+Rres@0 net@14 a 20.452
+Rres@1 net@11 net@14 40.904
+Rres@2 b net@8 20.452
+Rres@3 net@8 net@11 40.904
+.ENDS wire-C_0_011f-3539_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3539_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3539_8-R_34_667m
+.ENDS wire90-3539_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1810_5-R_34_667m a b
+Ccap@0 gnd net@14 6.639f
+Ccap@1 gnd net@8 6.639f
+Ccap@2 gnd net@11 6.639f
+Rres@0 net@14 a 10.461
+Rres@1 net@11 net@14 20.921
+Rres@2 b net@8 10.461
+Rres@3 net@8 net@11 20.921
+.ENDS wire-C_0_011f-1810_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1810_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1810_5-R_34_667m
+.ENDS wire90-1810_5-layer_1-width_3
+
*** CELL: stageGroupsM:outM1PredLit{sch}
.SUBCKT outM1PredLit dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17]
+dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27]
+ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8]
+ps[9] ps[do] ps[skip] net@47[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
+sir[8] sir[9] net@48[8] succ[D] outDockPredStage
-Xwire90@0 net@79 net@82 wire90-4175_4-layer_1-width_3
-Xwire90@1 net@90 fire[M] wire90-4175_4-layer_1-width_3
-Xwire90@2 net@89 net@91 wire90-4175_4-layer_1-width_3
+Xwire90@0 net@79 net@82 wire90-2993_2-layer_1-width_3
+Xwire90@1 net@90 fire[M] wire90-3539_8-layer_1-width_3
+Xwire90@2 net@89 net@91 wire90-1810_5-layer_1-width_3
.ENDS outM1PredLit
*** CELL: orangeTSMC090nm:wire{sch}
+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1]
+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
-+succ[A] succ[B]
++sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2]
++sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5] succ[A] succ[B]
Xinstruct@0 cin net@91 fin fout net@105[8] sod[2] sod[3] sod[4] sod[5] sid[6]
+sid[7] sid[8] sid[9] sod[1] instructionCount
XproperSt@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3]
+net@107[32] net@107[31] net@107[30] net@107[29] net@107[28] pred sic[1]
+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3]
+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5]
-+sir[6] sir[7] sir[8] sir[9] net@100[8] net@105[8] sod[2] sod[3] sod[4] sod[5]
-+net@101[8] net@98 properStopper
++sir[6] sir[7] sir[8] sir[9] net@100[8] soc[2] soc[3] soc[4] soc[5] net@105[8]
++sod[2] sod[3] sod[4] sod[5] net@101[8] sor[2] sor[3] sor[4] sor[5] net@98
++properStopper
XtapStage@2 net@107[41] net@107[40] net@107[39] net@107[38] net@107[37]
+net@107[50] net@107[49] net@107[48] net@107[47] net@107[46] net@107[45]
+net@107[44] net@107[43] net@107[42] net@107[51] aout[10] aout[11] aout[12]
+out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23]
+out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31]
+out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6]
-+out[7] out[8] out[9] net@85 net@100[8] sic[2] sic[3] sic[4] sic[5] sic[6]
-+sic[7] sic[8] sic[9] net@101[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
++out[7] out[8] out[9] net@85 net@100[8] soc[2] soc[3] soc[4] soc[5] sic[6]
++sic[7] sic[8] sic[9] net@101[8] sor[2] sor[3] sor[4] sor[5] sir[6] sir[7]
+sir[8] sir[9] soc[1] sor[1] succ[A] succ[B] tapStage
Xwire90@2 net@98 net@85 wire90-2080_4-layer_1-width_3
.ENDS tapPropStop
+out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8]
+out[9] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1]
+sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3]
-+sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4]
-+sod[5] sor[1] succ[tap]
++sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] soc[2] soc[3] soc[4] soc[5]
++sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] sor[2] sor[3] sor[4] sor[5]
++succ[tap]
XtapPropS@1 net@79[41] net@79[40] net@79[39] net@79[38] net@79[37] net@79[50]
+net@79[49] net@79[48] net@79[47] net@79[46] net@79[45] net@79[44] net@79[43]
+net@79[42] net@79[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1]
+out[6] out[7] out[8] out[9] net@61 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6]
+sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8]
+sid[9] net@64[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9]
-+soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] net@53 succ[tap] tapPropStop
++soc[1] soc[2] soc[3] soc[4] soc[5] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1]
++sor[2] sor[3] sor[4] sor[5] net@53 succ[tap] tapPropStop
XupDown8w@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] net@77[41]
+net@77[40] net@77[39] net@77[38] net@77[37] net@77[50] net@77[49] net@77[48]
+din[17] din[18] din[19] din[1] din[20] din[21] din[22] din[23] din[24]
+din[25] din[26] din[27] din[28] din[29] din[2] din[30] din[31] din[32]
+din[33] din[34] din[35] din[36] din[37] din[3] din[4] din[5] din[6] din[7]
-+din[8] din[9] dockSucc[D] net@116[8] sic[2] sic[3] sic[4] sic[5] sic[8]
-+sic[9] net@117[8] net@117[7] net@117[6] net@117[5] net@117[4] sid[6] sid[7]
-+sid[8] sid[9] net@109[8] sir[2] sir[3] sir[4] sir[5] sir[8] sir[9]
-+dockPred[D] northFifo
++din[8] din[9] dockSucc[D] net@116[8] net@116[7] net@116[6] net@116[5]
++net@116[4] sic[6] sic[7] sic[8] sic[9] net@117[8] net@117[7] net@117[6]
++net@117[5] net@117[4] sid[6] sid[7] sid[8] sid[9] net@109[8] net@109[7]
++net@109[6] net@109[5] net@109[4] sir[6] sir[7] sir[8] sir[9] dockPred[D]
++northFifo
XoutputDo@0 net@14 din[10] din[11] din[12] din[13] din[14] din[15] din[16]
+din[17] din[18] din[19] din[1] din[20] din[21] din[22] din[23] din[24]
+din[25] din[26] din[27] din[28] din[29] din[2] din[30] din[31] din[32]
+iout[20] iout[1] iout[21] iout[22] iout[23] iout[24] iout[25] iout[26]
+iout[27] iout[28] iout[29] iout[30] iout[2] iout[31] iout[32] iout[33]
+iout[34] iout[35] iout[36] iout[37] iout[3] iout[4] iout[5] iout[6] iout[7]
-+iout[8] iout[9] aout[T] dockPred[D] dockPred[T] ain[14] net@119[8] sir[2]
-+sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] sir[9] net@120[8] dockSucc[D]
-+dockSucc[T] outputDock
++iout[8] iout[9] aout[T] dockPred[D] dockPred[T] ain[14] net@119[8] net@109[7]
++net@109[6] net@109[5] net@109[4] sir[6] sir[7] sir[8] sir[9] net@120[8]
++dockSucc[D] dockSucc[T] outputDock
XsouthFif@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@44 fin
+net@38 iout[10] iout[11] iout[12] iout[13] iout[14] iout[15] iout[16]
+iout[24] iout[25] iout[26] iout[27] iout[28] iout[29] iout[2] iout[30]
+iout[31] iout[32] iout[33] iout[34] iout[35] iout[36] iout[37] iout[3]
+iout[4] iout[5] iout[6] iout[7] iout[8] iout[9] sic[1] sic[2] sic[3] sic[4]
-+sic[5] sic[3] sic[2] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
-+sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8]
-+sir[9] net@116[8] net@117[8] net@117[7] net@117[6] net@117[5] net@117[4]
-+net@119[8] net@14 southFifo
-XtokenFIF@1 dockSucc[T] net@120[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2]
-+sir[8] sir[9] net@109[8] dockPred[T] tokenFIFO
++sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6]
++sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8]
++sir[9] net@116[8] net@116[7] net@116[6] net@116[5] net@116[4] net@117[8]
++net@117[7] net@117[6] net@117[5] net@117[4] net@119[8] net@109[7] net@109[6]
++net@109[5] net@109[4] net@14 southFifo
+XtokenFIF@1 dockSucc[T] net@120[8] net@109[7] net@109[6] net@109[5]
++net@109[4] sir[6] sir[7] sir[8] sir[9] net@109[8] dockPred[T] tokenFIFO
.END
/* Verilog for cell 'marinaOut{sch}' from library 'aMarinaM' */
/* Created on Mon Nov 17, 2008 08:47:24 */
/* Last revised on Mon Mar 30, 2009 06:59:15 */
-/* Written on Sat Apr 18, 2009 16:47:30 by Electric VLSI Design System, version 8.08k */
+/* Written on Mon Apr 20, 2009 17:38:34 by Electric VLSI Design System, version 8.08k */
module orangeTSMC090nm__wire(a);
input a;
not (strong0, strong1) #(100) inv_0 (sT, sel);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (sF, sT);
+ not (strong0, strong1) #(0) inv_1 (sF, sT);
// end Verilog_template
loopCountM__mux10_2x7 mux10_2x_0(.in(in[1:7]), .sF(sF), .sT(sT),
.out(out[1:7]));
not (strong0, strong1) #(100) inv_7 (count_F_, count_T_);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_8 (load_F_, load_T_);
+ not (strong0, strong1) #(0) inv_8 (load_F_, load_T_);
// end Verilog_template
latchesK__mlat1in10 mlat1in1_1(.cl_F_(load_F_), .cl_T_(load_T_), .in({
\inLO[8] }), .out({ \bitt[8] }));
not (strong0, strong1) #(100) inv_5 (count_F_, count_T_);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_6 (load_F_, load_T_);
+ not (strong0, strong1) #(0) inv_6 (load_F_, load_T_);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
not (strong0, strong1) #(100) inv_7 (check_T_, ilc_decLO_);
not (strong0, strong1) #(100) inv_0 (sF, sel);
// end Verilog_template
/* begin Verilog_template for redFive:inv{sch}*/
- not (strong0, strong1) #(100) inv_1 (sT, sF);
+ not (strong0, strong1) #(0) inv_1 (sT, sF);
// end Verilog_template
loopCountM__mux10_2x7 mux10_2x_0(.in({in[1], in[2], in[3], in[4], in[5],
in[6], gnd}), .sF(sF), .sT(sT), .out(outLO[1:7]));
projects / fleet.git / commitdiff