pcore = ${remote_edk}/hw/XilinxProcessorIPLib/pcores
synth:
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
- cd build/fpga; echo work > main.lso
- cd build/fpga; for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
+ cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
+ rm -f build/fpga/main.lso
+ echo work >> build/fpga/main.lso
+ rm -f build/fpga/main.prj
+ cd build/fpga; for A in *.v; do echo verilog work \""$$A"\"; done >> main.prj
+ cd build/fpga; for A in *.vhd; do echo vhdl work \""$$A"\"; done >> main.prj
cd build/fpga; mkdir -p tmp
cd build/fpga; mkdir -p xst
rm -rf build/fpga/_ngo