+++ /dev/null
-############################################################################
-##
-## Xilinx, Inc. 2006 www.xilinx.com
-## Sat Feb 28 21:05:46 2009
-## Generated by MIG Version 2.3
-##
-############################################################################
-## File name : ddr2_sdram.ucf
-##
-## Details : Constraints file
-## FPGA family: virtex5
-## FPGA: xc5vlx110t-ff1136
-## Speedgrade: -1
-## Design Entry: VERILOG
-## Frequency: 200 MHz
-## Design: without Test bench
-## DCM Used: Enable
-## Two Bytes per Bank:Disable
-## No.Of Controllers: 1
-##
-############################################################################
-
-############################################################################
-# Clock constraints #
-############################################################################
-
-NET "ddr2_0/ddr2_sdram/u_ddr2_infrastructure/sys_clk_ibufg" TNM_NET = "SYS_CLK";
-TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5 ns HIGH 50 %;
-
-NET "ddr2_0/ddr2_sdram/u_ddr2_infrastructure/clk200_ibufg" TNM_NET = "SYS_CLK_200";
-TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;
-
-############################################################################
-########################################################################
-# Controller 0
-# Memory Device: DDR2_SDRAM->SODIMMs->MT8HTF3264HY-53E #
-# Data Width: 64 #
-# Data Mask: 1 #
-########################################################################
-
-################################################################################
-# I/O STANDARDS
-################################################################################
-
-NET "ddr2_dq[*]" IOSTANDARD = SSTL18_II_DCI;
-NET "ddr2_a[*]" IOSTANDARD = SSTL18_II;
-NET "ddr2_ba[*]" IOSTANDARD = SSTL18_II;
-NET "ddr2_ras_n" IOSTANDARD = SSTL18_II;
-NET "ddr2_cas_n" IOSTANDARD = SSTL18_II;
-NET "ddr2_we_n" IOSTANDARD = SSTL18_II;
-NET "ddr2_cs_n[*]" IOSTANDARD = SSTL18_II;
-NET "ddr2_odt[*]" IOSTANDARD = SSTL18_II;
-NET "ddr2_cke[*]" IOSTANDARD = SSTL18_II;
-NET "ddr2_dm[*]" IOSTANDARD = SSTL18_II;
-NET "sys_clk_p" IOSTANDARD = LVPECL_25;
-NET "sys_clk_n" IOSTANDARD = LVPECL_25;
-NET "clk200_p" IOSTANDARD = LVPECL_25;
-NET "clk200_n" IOSTANDARD = LVPECL_25;
-NET "sys_rst_n" IOSTANDARD = LVCMOS18;
-NET "phy_init_done" IOSTANDARD = LVCMOS18;
-NET "ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
-NET "ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
-NET "ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_II;
-NET "ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_II;
-
-################################################################################
-# Location Constraints
-################################################################################
-
-NET "ddr2_dq[0]" LOC = "C20" ; #Bank 23
-NET "ddr2_dq[1]" LOC = "B20" ; #Bank 23
-NET "ddr2_dq[2]" LOC = "B21" ; #Bank 23
-NET "ddr2_dq[3]" LOC = "A21" ; #Bank 23
-NET "ddr2_dq[4]" LOC = "C18" ; #Bank 23
-NET "ddr2_dq[5]" LOC = "C22" ; #Bank 23
-NET "ddr2_dq[6]" LOC = "B22" ; #Bank 23
-NET "ddr2_dq[7]" LOC = "B18" ; #Bank 23
-NET "ddr2_dq[8]" LOC = "C23" ; #Bank 23
-NET "ddr2_dq[9]" LOC = "B23" ; #Bank 23
-NET "ddr2_dq[10]" LOC = "A19" ; #Bank 23
-NET "ddr2_dq[11]" LOC = "A20" ; #Bank 23
-NET "ddr2_dq[12]" LOC = "A24" ; #Bank 23
-NET "ddr2_dq[13]" LOC = "D26" ; #Bank 23
-NET "ddr2_dq[14]" LOC = "C27" ; #Bank 23
-NET "ddr2_dq[15]" LOC = "A29" ; #Bank 23
-NET "ddr2_dq[16]" LOC = "C28" ; #Bank 23
-NET "ddr2_dq[17]" LOC = "D27" ; #Bank 23
-NET "ddr2_dq[18]" LOC = "B31" ; #Bank 23
-NET "ddr2_dq[19]" LOC = "A31" ; #Bank 23
-NET "ddr2_dq[20]" LOC = "D29" ; #Bank 23
-NET "ddr2_dq[21]" LOC = "D31" ; #Bank 23
-NET "ddr2_dq[22]" LOC = "D30" ; #Bank 23
-NET "ddr2_dq[23]" LOC = "A30" ; #Bank 23
-NET "ddr2_dq[24]" LOC = "K24" ; #Bank 19
-NET "ddr2_dq[25]" LOC = "L24" ; #Bank 19
-NET "ddr2_dq[26]" LOC = "L25" ; #Bank 19
-NET "ddr2_dq[27]" LOC = "L26" ; #Bank 19
-NET "ddr2_dq[28]" LOC = "J25" ; #Bank 19
-NET "ddr2_dq[29]" LOC = "M25" ; #Bank 19
-NET "ddr2_dq[30]" LOC = "M26" ; #Bank 19
-NET "ddr2_dq[31]" LOC = "J27" ; #Bank 19
-NET "ddr2_dq[32]" LOC = "G25" ; #Bank 19
-NET "ddr2_dq[33]" LOC = "G26" ; #Bank 19
-NET "ddr2_dq[34]" LOC = "H25" ; #Bank 19
-NET "ddr2_dq[35]" LOC = "H24" ; #Bank 19
-NET "ddr2_dq[36]" LOC = "F26" ; #Bank 19
-NET "ddr2_dq[37]" LOC = "K28" ; #Bank 19
-NET "ddr2_dq[38]" LOC = "L28" ; #Bank 19
-NET "ddr2_dq[39]" LOC = "K27" ; #Bank 19
-NET "ddr2_dq[40]" LOC = "M28" ; #Bank 19
-NET "ddr2_dq[41]" LOC = "N28" ; #Bank 19
-NET "ddr2_dq[42]" LOC = "P26" ; #Bank 19
-NET "ddr2_dq[43]" LOC = "P27" ; #Bank 19
-NET "ddr2_dq[44]" LOC = "P24" ; #Bank 19
-NET "ddr2_dq[45]" LOC = "P25" ; #Bank 19
-NET "ddr2_dq[46]" LOC = "N25" ; #Bank 19
-NET "ddr2_dq[47]" LOC = "R24" ; #Bank 19
-NET "ddr2_dq[48]" LOC = "E29" ; #Bank 15
-NET "ddr2_dq[49]" LOC = "F29" ; #Bank 15
-NET "ddr2_dq[50]" LOC = "G30" ; #Bank 15
-NET "ddr2_dq[51]" LOC = "F30" ; #Bank 15
-NET "ddr2_dq[52]" LOC = "J29" ; #Bank 15
-NET "ddr2_dq[53]" LOC = "F31" ; #Bank 15
-NET "ddr2_dq[54]" LOC = "E31" ; #Bank 15
-NET "ddr2_dq[55]" LOC = "L29" ; #Bank 15
-NET "ddr2_dq[56]" LOC = "H30" ; #Bank 15
-NET "ddr2_dq[57]" LOC = "G31" ; #Bank 15
-NET "ddr2_dq[58]" LOC = "J30" ; #Bank 15
-NET "ddr2_dq[59]" LOC = "J31" ; #Bank 15
-NET "ddr2_dq[60]" LOC = "M30" ; #Bank 15
-NET "ddr2_dq[61]" LOC = "T31" ; #Bank 15
-NET "ddr2_dq[62]" LOC = "R31" ; #Bank 15
-NET "ddr2_dq[63]" LOC = "U30" ; #Bank 15
-NET "ddr2_a[12]" LOC = "B30" ; #Bank 23
-NET "ddr2_a[11]" LOC = "T24" ; #Bank 19
-NET "ddr2_a[10]" LOC = "P31" ; #Bank 15
-NET "ddr2_a[9]" LOC = "P30" ; #Bank 15
-NET "ddr2_a[8]" LOC = "M31" ; #Bank 15
-NET "ddr2_a[7]" LOC = "N30" ; #Bank 15
-NET "ddr2_a[6]" LOC = "T28" ; #Bank 15
-NET "ddr2_a[5]" LOC = "T29" ; #Bank 15
-NET "ddr2_a[4]" LOC = "U27" ; #Bank 15
-NET "ddr2_a[3]" LOC = "U28" ; #Bank 15
-NET "ddr2_a[2]" LOC = "R26" ; #Bank 15
-NET "ddr2_a[1]" LOC = "R27" ; #Bank 15
-NET "ddr2_a[0]" LOC = "U26" ; #Bank 15
-NET "ddr2_ba[1]" LOC = "T26" ; #Bank 15
-NET "ddr2_ba[0]" LOC = "U25" ; #Bank 15
-NET "ddr2_ras_n" LOC = "T25" ; #Bank 15
-NET "ddr2_cas_n" LOC = "B32" ; #Bank 11
-NET "ddr2_we_n" LOC = "A33" ; #Bank 11
-NET "ddr2_cs_n[0]" LOC = "B33" ; #Bank 11
-NET "ddr2_odt[0]" LOC = "C33" ; #Bank 11
-NET "ddr2_cke[0]" LOC = "C32" ; #Bank 11
-NET "ddr2_dm[0]" LOC = "C19" ; #Bank 23
-NET "ddr2_dm[1]" LOC = "A23" ; #Bank 23
-NET "ddr2_dm[2]" LOC = "C30" ; #Bank 23
-NET "ddr2_dm[3]" LOC = "J24" ; #Bank 19
-NET "ddr2_dm[4]" LOC = "F25" ; #Bank 19
-NET "ddr2_dm[5]" LOC = "N24" ; #Bank 19
-NET "ddr2_dm[6]" LOC = "H29" ; #Bank 15
-NET "ddr2_dm[7]" LOC = "L30" ; #Bank 15
-NET "sys_clk_p" LOC = "H17" ; #Bank 3
-NET "sys_clk_n" LOC = "H18" ; #Bank 3
-NET "clk200_p" LOC = "K17" ; #Bank 3
-NET "clk200_n" LOC = "L18" ; #Bank 3
-NET "sys_rst_n" LOC = "D32" ; #Bank 11
-NET "phy_init_done" LOC = "C34" ; #Bank 11
-NET "ddr2_dqs[0]" LOC = "C24" ; #Bank 23
-NET "ddr2_dqs_n[0]" LOC = "D25" ; #Bank 23
-NET "ddr2_dqs[1]" LOC = "B26" ; #Bank 23
-NET "ddr2_dqs_n[1]" LOC = "A25" ; #Bank 23
-NET "ddr2_dqs[2]" LOC = "B27" ; #Bank 23
-NET "ddr2_dqs_n[2]" LOC = "A26" ; #Bank 23
-NET "ddr2_dqs[3]" LOC = "G27" ; #Bank 19
-NET "ddr2_dqs_n[3]" LOC = "H27" ; #Bank 19
-NET "ddr2_dqs[4]" LOC = "H28" ; #Bank 19
-NET "ddr2_dqs_n[4]" LOC = "G28" ; #Bank 19
-NET "ddr2_dqs[5]" LOC = "E28" ; #Bank 19
-NET "ddr2_dqs_n[5]" LOC = "F28" ; #Bank 19
-NET "ddr2_dqs[6]" LOC = "N29" ; #Bank 15
-NET "ddr2_dqs_n[6]" LOC = "P29" ; #Bank 15
-NET "ddr2_dqs[7]" LOC = "K31" ; #Bank 15
-NET "ddr2_dqs_n[7]" LOC = "L31" ; #Bank 15
-NET "ddr2_ck[0]" LOC = "B25" ; #Bank 23
-NET "ddr2_ck_n[0]" LOC = "C25" ; #Bank 23
-NET "ddr2_ck[1]" LOC = "E26" ; #Bank 19
-NET "ddr2_ck_n[1]" LOC = "E27" ; #Bank 19
-
-################################################################################
-#IDELAYCTRL Location Constraints
-################################################################################
-INST "*/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y7;
-INST "*/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y6;
-INST "*/IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X0Y5;
-
-###############################################################################
-# Define multicycle paths - these paths may take longer because additional
-# time allowed for logic to settle in calibration/initialization FSM
-###############################################################################
-
-# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
-# multicycle paths from originating flip-flop to ANY destination
-# flip-flop (or in some cases, it can also be a BRAM)
-# MUX Select for either rising/falling CLK0 for 2nd stage read capture
-INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
-TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
-"TS_SYS_CLK" * 4;
-
-# Commented out -- AM
-# MUX select for read data - optional delay on data to account for byte skews
-#INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
-#TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
-#"TS_SYS_CLK" * 4;
-
-# Calibration/Initialization complete status flag (for PHY logic only) - can
-# be used to drive both flip-flops and BRAMs
-INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
-TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
-"TS_SYS_CLK" * 4;
-TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
-"TS_SYS_CLK" * 4;
-# Select (address) bits for SRL32 shift registers used in stage3/stage4
-# calibration
-INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
-TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_CLK" * 4;
-
-# Commented out -- AM
-#INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
-#TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;
-
-INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
- TNM = "TNM_CAL_RDEN_DLY";
-TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
- "TS_SYS_CLK" * 4;
-
-###############################################################################
-# DQS Read Post amble Glitch Squelch circuit related constraints
-###############################################################################
-
-###############################################################################
-# LOC placement of DQS-squelch related IDDR and IDELAY elements
-# Each circuit can be located at any of the following locations:
-# 1. Unused "N"-side of DQS differential pair I/O
-# 2. DM data mask (output only, input side is free for use)
-# 3. Any output-only site
-###############################################################################
-
-INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y302";
-INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y302";
-INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y300";
-INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y300";
-INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y298";
-INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y298";
-INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";
-INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";
-INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";
-INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";
-INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y258";
-INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y258";
-INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y222";
-INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y222";
-INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y220";
-INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y220";
-
-###############################################################################
-# LOC and timing constraints for flop driving DQS CE enable signal
-# from fabric logic. Even though the absolute delay on this path is
-# calibrated out (when synchronizing this output to DQS), the delay
-# should still be kept as low as possible to reduce post-calibration
-# voltage/temp variations - these are roughly proportional to the
-# absolute delay of the path
-###############################################################################
-
-INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y151;
-INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y150;
-INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y149;
-INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y131;
-INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y130;
-INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y129;
-INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y111;
-INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y110;
-
-# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
-# two parts to this path: (1) from fabric flop to IDELAY, (2) from
-# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
-# This can be relaxed by the user for lower frequencies:
-# 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
-# In general PAR should be able to route this
-# within 900ps over all speed grades.
-NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
-NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;
-
-###############################################################################
-# "Half-cycle" path constraint from IDDR to CE pin for all DQ IDDR's
-# for DQS Read Post amble Glitch Squelch circuit
-###############################################################################
-
-# Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
-# where slack account for rise-time of DQS on board. For now assume slack =
-# 0.400ns (based on initial SPICE simulations, assumes use of ODT), so
-# time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
-INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
-INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
-TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 2.4 ns;
-
-###############################################################################
-# MIG 2.2: Prevent unrelated logic from being packed into any slices used
-# by read data capture RPM's - if unrelated logic gets packed into
-# these slices, it could cause the DIRT strings that define the
-# IDDR -> fabric flop routing to become unroutable during PAR stage
-# (unrelated logic may require routing resources required by the
-# DIRT strings - MAP does not currently take into account DIRT
-# strings when placing logic
-###############################################################################
-
-AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
-
-###############################################################################
-# Location constraints for DQ read-data capture flops in fabric (for 2nd
-# stage capture)
-###############################################################################
-
-INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y159;
-INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y159;
-INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y158;
-INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y158;
-INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y157;
-INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y156;
-INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y156;
-INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y155;
-INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y154;
-INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y154;
-INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y153;
-INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y153;
-INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y152;
-INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y146;
-INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y146;
-INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y145;
-INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y144;
-INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y144;
-INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y143;
-INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y143;
-INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y142;
-INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y141;
-INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y141;
-INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y140;
-INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139;
-INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139;
-INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
-INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
-INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y137;
-INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
-INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
-INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y135;
-INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
-INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
-INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
-INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
-INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y132;
-INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
-INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
-INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y125;
-INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
-INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
-INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
-INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
-INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y122;
-INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
-INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
-INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120;
-INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y119;
-INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y119;
-INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y118;
-INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y118;
-INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y117;
-INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y116;
-INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y116;
-INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y115;
-INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y114;
-INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y114;
-INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y113;
-INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y113;
-INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y112;
-INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y106;
-INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y106;
-INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y105;
-
projects / fleet.git / commitdiff