Regressions run based upon 11 Nov 2008 design.

diff --git a/testCode/com/sun/vlsi/chips/marina/test/Marina.java b/testCode/com/sun/vlsi/chips/marina/test/Marina.java
index f701e4d..44e391a 100644 (file)
--- a/testCode/com/sun/vlsi/chips/marina/test/Marina.java
+++ b/testCode/com/sun/vlsi/chips/marina/test/Marina.java
@@ -1,94 +1,142 @@
 package com.sun.vlsi.chips.marina.test;
 /* -*- tab-width: 4 -*- */
+import com.sun.async.test.BitVector;
 import com.sun.async.test.ChainControl;
 import com.sun.async.test.ChipModel;
-import com.sun.async.test.JtagLogicLevel;
 import com.sun.async.test.JtagTester;
 import com.sun.async.test.NanosimModel;
 
 /** The Marina object will eventually represent the Marina test chip.  
  * Right now, it doesn't do much of anything. It just helps me exercise
  * my test infrastructure. */
-public class Marina implements Design {
-    private static final String DATA_CHAIN =    "marina.jtag_dockTest_data";      
-    private static final String CONTROL_CHAIN = "marina.jtag_dockTest_control";
-       private static final String REPORT_CHAIN =  "marina.jtag_dockTest_report";
+public class Marina {
+    private static final String DATA_CHAIN =    "marina.marina_data";      
+    private static final String CONTROL_CHAIN = "marina.marina_control";
+       private static final String REPORT_CHAIN =  "marina.marina_report";
+       
+       private static final String OLC_PATH = "ringSkip@0.skipCoun@0.scanKx6@0";
+       private static final String ILC_PATH = "ringSkip@0.skipCoun@0.scanKx7@0";
+       private static final String FLAGS_PATH = "ringSkip@0.skipCoun@0.scanKx3@0";
+       private static final String SEND_INSTR_PATH = "instrIn.tapPropS@0.tapStage@1";
+       
+       private final Indenter indenter;
 
        // The name of the scan chain
        // The instance path, from the top cell of the netlist, of the instance of infinityWithCover 
     private final ChainControl cc;           // specifies the scan chain
     private final ChipModel model;
-    public final ProperStopper stopper1, stopper2;
-    public final Counter counter;
+    public final ProperStopper data, tokOut;
+    public final InstructionStopper instrIn;
+    
+       private void prln(String msg) {indenter.prln(msg);}
+       private void pr(String msg) {indenter.pr(msg);}
+    
+    /** Shift the report scan chain */
+       private void shiftReport(boolean readEnable, boolean writeEnable) {
+         cc.shift(REPORT_CHAIN, readEnable, writeEnable);
+       }
+    
+    /** Shift the report scan chain */
+       private void shiftControl(boolean readEnable, boolean writeEnable) {
+         cc.shift(CONTROL_CHAIN, readEnable, writeEnable);
+       }
 
-    public Marina(ChainControl cc, ChipModel model, boolean wholeChipNetlist, Indenter indenter) {
+       public Marina(ChainControl cc, ChipModel model, Indenter indenter) {
         this.cc = cc;
         this.model = model;
-        stopper1 = new ProperStopper("ps1",
-                                            CONTROL_CHAIN, 
-                                            DATA_CHAIN,  
-                                            REPORT_CHAIN,
-                                            cc, model, indenter);
-        stopper2 = new ProperStopper("ps2", 
-                                                    CONTROL_CHAIN,
-                                                    DATA_CHAIN,
-                                                    REPORT_CHAIN,
-                                                    cc, model, indenter);
-        counter = new Counter("??", DATA_CHAIN, cc);
+        this.indenter = indenter;
+        data = new ProperStopper("data.fillDrai@0.properSt@0",
+                                         CONTROL_CHAIN, 
+                                         DATA_CHAIN,  
+                                         REPORT_CHAIN,
+                                         cc, model, indenter);
+        tokOut = new ProperStopper("tokOut", 
+                                                  CONTROL_CHAIN,
+                                                  DATA_CHAIN,
+                                                  REPORT_CHAIN,
+                                                  cc, model, indenter);
+        instrIn = new InstructionStopper("instrIn.tapPropS@0.properSt@0", 
+                                     CONTROL_CHAIN,
+                                     DATA_CHAIN,
+                                     REPORT_CHAIN,
+                                     cc, model, indenter);
     }
     public void masterClear(JtagTester tester) {
-       final double WIDTH = 10;
-       if (model instanceof NanosimModel) {
-               NanosimModel nModel = (NanosimModel) model;
-               System.out.println("master clear");
-               // Put a low going pulse on the chip's master clear pin. This clears
-               // the master clear register. The master clear register's output is
-               // inverted. This inverse drivers the chip's internal master clear 
-               // signal.
-            nModel.setNodeVoltage("mc",0.0);
-               nModel.waitNS(WIDTH);
-            nModel.setNodeVoltage("mc",1.0);
-       } else {
-               JtagLogicLevel jll = new JtagLogicLevel(tester, 0);
-               jll.setLogicState(false);
-               model.wait(0.100f);
-               jll.setLogicState(true);
-            
-            // Set the master clear register. This resets the chip's internal
-            // master clear.
-            cc.setInBits("Infinity.jtag_mc", "1");
-            cc.shift("Infinity.jtag_mc", false, true);
-       }
-       resetAfterMasterClear();
+       final double WIDTH = 10; // ns
+       NanosimModel nModel = (NanosimModel) model;
+               // Put a high going pulse on the internal chip master clear signal
+        nModel.setNodeVoltage("scanInD[9]",1.0);
+        nModel.setNodeVoltage("scanInC[9]",1.0);
+        nModel.setNodeVoltage("scanInR[9]",1.0);
+        nModel.waitNS(WIDTH);
+        nModel.setNodeVoltage("scanInD[9]",0.0);
+        nModel.setNodeVoltage("scanInC[9]",0.0);
+        nModel.setNodeVoltage("scanInR[9]",0.0);
+        nModel.waitNS(1);
+        resetAfterMasterClear();
     }
-    
-
     private void resetAfterMasterClear() {
-       // For reset, I want to simultaneously clear all the stoppers 
-       stopper1.clear();
-       stopper2.clear();
+       // The following call to ChainControl.resetInBits() is vital!
+       // If you forget, then the inBits member initializes 
+       // with random data. Then when you do your first write,
+       // some bits are written randomly.
+       cc.resetInBits();
+
+       // For reset, I want to clear all the stoppers simultaneously
+       data.clear();
+       tokOut.clear();
+       instrIn.clear();
        
-       stopper1.stop();
-       stopper2.stop();
+       data.stop();
+       tokOut.stop();
+       instrIn.stop();
        
-       stopper1.resetAfterMasterClear();
-       stopper2.resetAfterMasterClear();
+       data.resetAfterMasterClear();
+       tokOut.resetAfterMasterClear();
+       instrIn.resetAfterMasterClear();
+    }
+    /** Get the 6 bit outer loop counter. */
+    public int getOLC() {
+       shiftReport(true, false);
+       return (int) cc.getOutBits(REPORT_CHAIN+"."+OLC_PATH).bitReverse().not().toLong();
+    }
+    /** Get the 7 bit inner loop counter. The MSB is the zero bit.
+     * The low order 6 bits are the count */
+    public int getILC() {
+       shiftReport(true, false);
+       return (int) cc.getOutBits(REPORT_CHAIN+"."+ILC_PATH).bitReverse().not().toLong();
+    }
+    /** Get the inner loop counter zero bit. If the zero bit is true
+     * then the hardware considers the inner loop counter to be zero
+     * regardless of the state of the count bits */
+       public boolean getIlcZero() {
+               return (getILC() & 0x40) != 0;
+       }
+       /** Get the 6 bits of count of the inner loop counter */
+       public int getIlcCount() {
+               return getILC() & 0x3f;
+       }
+       /** Get the A flag */
+    public boolean getFlagA() {
+       shiftReport(true, false);
+       return cc.getOutBits(REPORT_CHAIN+"."+FLAGS_PATH).get(2);
+    }
+    /** Get the B flag */
+    public boolean getFlagB() {
+       shiftReport(true, false);
+       return cc.getOutBits(REPORT_CHAIN+"."+FLAGS_PATH).get(1);
+    }
+    /** Get the C flag */
+    public boolean getFlagC() {
+       shiftReport(true, false);
+       return cc.getOutBits(REPORT_CHAIN+"."+FLAGS_PATH).get(0);
     }
-//    /** Shift the data scan chain. */
-//    public void shiftData(boolean readEnable, boolean writeEnable) {
-//     // Get current data of all stoppers
-//     cc.shift(DATA_CHAIN, readEnable, writeEnable);
-//    }
-//    /** Shift the control scan chain */
-//    public void shiftControl(boolean readEnable, boolean writeEnable) {
-//     cc.shift(CONTROL_CHAIN, readEnable, writeEnable);
-//    }
-//    /** Shift the report scan chain */
-//    public void shiftReport(boolean readEnable, boolean writeEnable) {
-//     cc.shift(REPORT_CHAIN, readEnable, writeEnable);
-//    }
-    public void initCounterScanBits(boolean val) {
-        cc.setInBits(DATA_CHAIN+".infinity@1.infinity@0.cnt", val);
-        cc.setInBits(DATA_CHAIN+".infinity@1.infinity@5.cnt", val);
+    /** Enable the transmission of instructions from the instruction
+     * ring test structure to the EPI FIFO. */
+    public void enableInstructionSend(boolean b) {
+       BitVector bv = new BitVector(1, "send flag");
+       bv.setFromLong(b?1:0);
+       cc.setInBits(CONTROL_CHAIN+"."+SEND_INSTR_PATH, bv); 
+       shiftControl(true, false);
     }
 }

diff --git a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
index 6a3a8b1..890565d 100644 (file)
--- a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
+++ b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
@@ -65,7 +65,7 @@ public class MarinaTest {
        private static long startTime;
 
        private Indenter indenter = new Indenter();
-       private Design design;
+       private Marina marina;
        private ChipModel model;
        private ChainControl cc;
        private JtagTester tester;
@@ -97,12 +97,6 @@ public class MarinaTest {
        private static void reportTask(CmdArgs args) {
                System.out.println("Begin testing Marina");
         switch (args.mode) {
-        case ISOLATED_IN_DOCK:
-               System.out.println("  Simulate isolated input dock");
-               break;
-        case ISOLATED_OUT_DOCK:
-               System.out.println("  Simulate isolated output dock");
-               break;
         case WHOLE_CHIP_SCHEMATIC_PARASITICS:
                System.out.println("  Simulate whole chip, schematic parasitics");
                break;
@@ -162,30 +156,20 @@ public class MarinaTest {
 
         String netListName;
         switch (cmdArgs.mode) {
-        case ISOLATED_IN_DOCK:
-               netListName = "isolatedInDock.spi";
-            cc = new ChainControl("isolatedInDock.xml", tester, 1.8f, khz);
-            design = new IsolatedInDock(cc, model, indenter);
-               break;
-        case ISOLATED_OUT_DOCK:
-               netListName = "isolatedOutDock.spi";
-            cc = new ChainControl("isolatedOutDock.xml", tester, 1.8f, khz);
-            design = null;
-               break;
         case WHOLE_CHIP_SCHEMATIC_PARASITICS:
-               netListName = "marina_pads_guts.spi"; 
-            cc = new ChainControl("???", tester, 1.8f, khz);
-            design = null;
+               netListName = "marina.spi"; 
+            cc = new ChainControl("marina.xml", tester, 1.8f, khz);
+            marina = new Marina(cc, model, indenter);
                break;
         case WHOLE_CHIP_LAYOUT_PARASITICS:
                netListName = "marina_pads_guts.spi"; 
             cc = new ChainControl("???", tester, 1.8f, khz);
-            design = null;
+            marina = null;
                break;
         case TEST_SILICON:
                netListName = "marina_pads_guts.spi"; 
             cc = new ChainControl("???", tester, 1.8f, khz);
-            design = null;
+            marina = null;
                break;
         default:
                fatal(true, "unrecognized CmdArgs.Mode");
@@ -348,13 +332,13 @@ public class MarinaTest {
 
     //=========================================================================
     // Put top level tests here
-    private void stopToStopOneItem(IsolatedInDock inDock) {
-       stopToStopOne(inDock.datIn, inDock.tokOut, null, -1);
+    private void stopToStopOneItem(Marina marina) {
+       stopToStopOne(marina.data, marina.tokOut, null, -1);
     }
-    private void stopToStopThreeItems(IsolatedInDock inDock) {
-       stopToStopThree(inDock.datIn, inDock.tokOut, null, -1);
+    private void stopToStopThreeItems(Marina marina) {
+       stopToStopThree(marina.data, marina.tokOut, null, -1);
     }
-    private void sendInstructions(IsolatedInDock inDock) {
+    private void sendInstructions(Marina marina) {
        prln("Begin sendInstructions");
        adjustIndent(2);
        
@@ -369,22 +353,24 @@ public class MarinaTest {
                count = count.add(one);
        }
 
-       inDock.instrIn.fillMany(din);
+       marina.instrIn.fillMany(din);
 
        adjustIndent(-2);
        prln("End sendInstructions");
     }
 
-    private void sendToken(IsolatedInDock inDock) {
+    private void sendToken(Marina marina) {
        prln("Begin sendToken");
        adjustIndent(2);
        
-       inDock.instrIn.fill(
+       prln("ILC=1");
+       marina.instrIn.fill(
                new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, 1));
 
-       getCtrsFlags(inDock);
+       getCtrsFlags(marina);
        
-        inDock.instrIn.fill(
+       prln("send token");
+        marina.instrIn.fill(
             new Instruction.Move(DOCK,
                                  false,                 /* requeueing  */
                                  Predicate.IgnoreOLC,   /* predicate   */
@@ -398,9 +384,9 @@ public class MarinaTest {
                                  true                   /* tokenOut    */
                                  ));
         
-        getCtrsFlags(inDock);
+        getCtrsFlags(marina);
         
-        List<BitVector> toks = inDock.tokOut.drainMany();
+        List<BitVector> toks = marina.tokOut.drainMany();
         fatal(toks.size()!=1, "Expected one token to emerge but got: "+toks.size()+" tokens");
         
         prln("Token="+MarinaUtils.formatDataTokAddr(toks.get(0)));
@@ -409,7 +395,7 @@ public class MarinaTest {
        prln("End sendToken");
     }
 
-    private void testFlagZ(IsolatedInDock inDock) {
+    private void testFlagZ(Marina marina) {
        prln("Begin testFlagZ");
        adjustIndent(2);
        
@@ -424,11 +410,11 @@ public class MarinaTest {
                      "olc=="+olc+" and "+
                      "predicate olc"+(predicate_olc_nonzero?"!=0":"==0"));
                 adjustIndent(2);
-                inDock.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, 1));
+                marina.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, 1));
                 if (olc==0)
-                    inDock.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC, SetDest.OuterLoopCounter, SetSource.Decrement));
-                inDock.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, 1));
-                inDock.instrIn.fill(new Instruction.Move(DOCK,
+                    marina.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC, SetDest.OuterLoopCounter, SetSource.Decrement));
+                marina.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, 1));
+                marina.instrIn.fill(new Instruction.Move(DOCK,
                                                          false,                 /* requeueing  */
                                                          predicate_olc_nonzero  /* predicate   */
                                                          ? only_if_olc_nonzero
@@ -443,7 +429,7 @@ public class MarinaTest {
                                                          false,                 /* dataOut     */
                                                          true                   /* tokenOut    */
                                                          ));
-                toks = inDock.tokOut.drainMany();
+                toks = marina.tokOut.drainMany();
                 int expected = (predicate_olc_nonzero == (olc!=0)) ? 1 : 0;
                 fatal(toks.size()!=expected, "Expected "+expected+" token to emerge but got: "+toks.size()+" token(s)");
                 adjustIndent(-2);
@@ -453,23 +439,23 @@ public class MarinaTest {
        prln("End testFlagZ");
     }
 
-    private void testPredicationOnAB(IsolatedInDock inDock) {
+    private void testPredicationOnAB(Marina marina) {
        prln("Begin testPredicationOnAB");
        adjustIndent(2);
        
         List<BitVector> toks;
 
         prln("Setting OLC=63");
-        inDock.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, 63));
+        marina.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, 63));
 
         for(boolean flag_a : new boolean[] { false, true }) {
             for(boolean flag_b : new boolean[] { false, true }) {
                 prln("Setting flags, a="+flag_a+" b="+flag_b);
-                inDock.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,
+                marina.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,
                                                         flag_a ? Instruction.Set.FlagFunction.ONE : Instruction.Set.FlagFunction.ZERO,
                                                         flag_b ? Instruction.Set.FlagFunction.ONE : Instruction.Set.FlagFunction.ZERO
                                                         ));
-               getCtrsFlags(inDock);
+               getCtrsFlags(marina);
 
                 adjustIndent(2);
                 for(Predicate predicate : new Predicate[] {
@@ -482,8 +468,8 @@ public class MarinaTest {
 
                     prln("Attempting send token with a="+flag_a+", b="+flag_b+", predicate="+predicate.getClass().getName());
                     adjustIndent(2);
-                    inDock.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, 1));
-                    inDock.instrIn.fill(new Instruction.Move(DOCK,
+                    marina.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, 1));
+                    marina.instrIn.fill(new Instruction.Move(DOCK,
                                                              false,                 /* requeueing  */
                                                              predicate,             /* predicate   */
                                                              false,                 /* torpedoable */
@@ -496,7 +482,7 @@ public class MarinaTest {
                                                              true                   /* tokenOut    */
                                                              ));
                     adjustIndent(-2);
-                    toks = inDock.tokOut.drainMany();
+                    toks = marina.tokOut.drainMany();
                     int expected = predicate.evaluate(flag_a, flag_b, false, false) ? 1 : 0;
                     fatal(toks.size()!=expected, "Expected "+expected+" token to emerge but got: "+
                           toks.size()+" token(s)");
@@ -508,37 +494,43 @@ public class MarinaTest {
        prln("End testPredicationOnAB");
     }
 
-    private void getCtrsFlags(IsolatedInDock inDock) {
-        int olc = inDock.getOLC();
-        prln("OLC="+olc);
+    private void getCtrsFlags(Marina marina) {
+       prln("begin getCtrsFlags");
+       adjustIndent(2);
+       
+        int olc = marina.getOLC();
+        prln("OLC=="+olc);
         
-       prln("ILC.zero="+inDock.getIlcZero()+
-                " ILC.count="+inDock.getIlcCount());
+       prln("ILC.zero=="+marina.getIlcZero()+
+                " ILC.count=="+marina.getIlcCount());
+       
+       boolean a = marina.getFlagA();
+       prln("flagA=="+a);
        
-       boolean a = inDock.getFlagA();
-       prln("flagA="+a);
+       boolean b = marina.getFlagB();
+       prln("flagB=="+b);
        
-       boolean b = inDock.getFlagB();
-       prln("flagB="+b);
+       boolean c = marina.getFlagC();
+       prln("flagC=="+c);
        
-       boolean c = inDock.getFlagC();
-       prln("flagC="+c);
+       adjustIndent(-2);
+       prln("end getCtrsFlags");
     }
-    private void walkOneOLC(IsolatedInDock inDock) {
+    private void walkOneOLC(Marina marina) {
        prln("Begin walkOneOLC");
        adjustIndent(2);
        for (int i=0; i<7; i++) {
                int inOlc = 0x20 >> i;
                prln("inOlc="+inOlc);
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
                        Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, inOlc));
-               int outOlc = inDock.getOLC();
+               int outOlc = marina.getOLC();
                fatal(outOlc!=inOlc, "walkOneOLC: got="+outOlc+" expected="+inOlc);
        }
        adjustIndent(-2);
        prln("End walkOneOLC");
     }
-    private void walkOneILC(IsolatedInDock inDock) {
+    private void walkOneILC(Marina marina) {
        prln("Begin walkOneILC");
        adjustIndent(2);
        for (int i=0; i<7; i++) {
@@ -546,32 +538,32 @@ public class MarinaTest {
                int inIlc = 0x20 >> i;
                        prln("inIlc="+inIlc);
 
-                       inDock.instrIn.fill(new 
+                       marina.instrIn.fill(new 
                        Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, inIlc));
 
-               int outIlc = inDock.getIlcCount();
+               int outIlc = marina.getIlcCount();
                fatal(outIlc!=inIlc, "bad ILC count: "+outIlc+" expected: "+outIlc);
                
                boolean inZero = inIlc==0;
-               boolean outZero = inDock.getIlcZero();
+               boolean outZero = marina.getIlcZero();
                fatal(outZero!=inZero, "bad ILC zero: "+outZero);
        }
        adjustIndent(-2);
        prln("End walkOneILC");
     }
-    private void countIlc(IsolatedInDock inDock) {
+    private void countIlc(Marina marina) {
        final int maxIlc = 63;
        prln("Begin countIlc");
        adjustIndent(2);
        
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
                        Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, maxIlc));
 
-               int ilc = inDock.getIlcCount();
+               int ilc = marina.getIlcCount();
                fatal(ilc!=maxIlc, "bad ILC count: "+ilc+" expected: "+maxIlc);
                
                // execute a move instruction that does nothing except decrement the ILC to zero
-        inDock.instrIn.fill(
+        marina.instrIn.fill(
             new Instruction.Move(DOCK,
                                     false,                             /* requeueing */
                                  Predicate.IgnoreOLC,   /* predicate   */
@@ -588,25 +580,25 @@ public class MarinaTest {
                // wait for ILC to count from 63 to 0
         model.waitNS(64 * CYCLE_TIME_NS);
 
-               ilc = inDock.getIlcCount();
+               ilc = marina.getIlcCount();
                fatal(ilc!=0, "bad ILC count: "+ilc+" expected: "+0);
        
        adjustIndent(-2);
        prln("End countIlc");
     }
     // Note: countOlc takes 44 minutes to run on nanosim
-    private void countOlc(IsolatedInDock inDock) {
+    private void countOlc(Marina marina) {
        final int maxOlc = 63;
        prln("Begin countOlc");
        adjustIndent(2);
        
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
                        Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, maxOlc));
                for (int i=maxOlc; i>=0; i--) {
                        prln("OLC should be: "+i);
-                       int olc = inDock.getOLC();
+                       int olc = marina.getOLC();
                        fatal(olc!=i, "bad OLC: "+olc+" expected: "+i);
-                       inDock.instrIn.fill(new 
+                       marina.instrIn.fill(new 
                                Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, SetSource.Decrement));
                }
 
@@ -614,12 +606,12 @@ public class MarinaTest {
        prln("End countOlc");
     }
 
-    private void saturateInstructionFifo(IsolatedInDock inDock, Instruction instruction, boolean expect_it_to_jam_up) {
+    private void saturateInstructionFifo(Marina marina, Instruction instruction, boolean expect_it_to_jam_up) {
         prln("Inserting "+(UPPER_BOUND_ON_INSTRUCTION_FIFO_SIZE+1)+" copies of \"" + instruction + "\"");
        adjustIndent(2);
         int i=0;
         for(i=0; i<(UPPER_BOUND_ON_INSTRUCTION_FIFO_SIZE+1); i++) {
-            boolean jammed = (inDock.instrIn.getFillStateWire()==MarinaUtils.StateWireState.FULL);
+            boolean jammed = (marina.instrIn.getFillStateWire()==MarinaUtils.StateWireState.FULL);
             if (jammed && expect_it_to_jam_up) {
                 prln("Stopper remained full after inserting instruction; this was expected; we are happy.");
                 adjustIndent(-2);
@@ -627,7 +619,7 @@ public class MarinaTest {
             }
             fatal(jammed, "Instruction stopper did not drain after inserting " + i + " instructions; not good!");
             prln("Inserting instruction " + (i+1) +"/"+ (UPPER_BOUND_ON_INSTRUCTION_FIFO_SIZE+1));
-                inDock.instrIn.fill(instruction);
+                marina.instrIn.fill(instruction);
         }
         fatal(expect_it_to_jam_up, "Expected instruction stopper to jam up, but it did not");
        adjustIndent(-2);
@@ -648,31 +640,31 @@ public class MarinaTest {
                              false                  /* tokenOut    */
                              );
 
-    private void testRequeueStage0(IsolatedInDock inDock) {
+    private void testRequeueStage0(Marina marina) {
         prln("Begin testRequeueStage0");
        adjustIndent(2);
 
         prln("Executing Set OLC=1");
-        inDock.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter,1));
+        marina.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter,1));
         prln("Executing Set OLC--");
-        inDock.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter,SetSource.Decrement));
-        saturateInstructionFifo(inDock, REQUEUEING_NOP, false);
+        marina.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter,SetSource.Decrement));
+        saturateInstructionFifo(marina, REQUEUEING_NOP, false);
        adjustIndent(-2);
         prln("End testRequeueStage0");
     }
 
-    private void testRequeueStage0to1(IsolatedInDock inDock) {
+    private void testRequeueStage0to1(Marina marina) {
         prln("Begin testRequeueStage0to1");
        adjustIndent(2);
 
         prln("Executing Set OLC=63");
-        inDock.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter,63));
-        saturateInstructionFifo(inDock, REQUEUEING_NOP, true);
+        marina.instrIn.fill(new Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter,63));
+        saturateInstructionFifo(marina, REQUEUEING_NOP, true);
        adjustIndent(-2);
         prln("End testRequeueStage0to1");
     }
 
-    private void testFlagAB(IsolatedInDock inDock) {
+    private void testFlagAB(Marina marina) {
        prln("Begin testFlagAB");
        adjustIndent(2);
 
@@ -695,42 +687,42 @@ public class MarinaTest {
         for(boolean b : new boolean[] { false, true, false }) {
             prln((b?"Setting":"Clearing")+" flags");
 
-            inDock.instrIn.fill(new 
+            marina.instrIn.fill(new 
                                 Instruction.Set(DOCK,false,Predicate.IgnoreOLC,
                                                 b ? one : zero,
                                                 b ? one : zero
                                                 ));
-            fatal(inDock.getFlagA()!=b, "after "+(b?"setting":"clearing")+" FlagA, it was still "+(b?"clear":"set"));
-            fatal(inDock.getFlagB()!=b, "after "+(b?"setting":"clearing")+" FlagB, it was still "+(b?"clear":"set"));
+            fatal(marina.getFlagA()!=b, "after "+(b?"setting":"clearing")+" FlagA, it was still "+(b?"clear":"set"));
+            fatal(marina.getFlagB()!=b, "after "+(b?"setting":"clearing")+" FlagB, it was still "+(b?"clear":"set"));
         }
 
        adjustIndent(-2);
        prln("End testFlagAB");         
     }
-    private void sendTorpedo(IsolatedInDock inDock) {
+    private void sendTorpedo(Marina marina) {
        prln("Begin sendTorpedo");
        adjustIndent(2);
        
        prln("OLC = 63");
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
                        Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, 63));
 
-               int olc = inDock.getOLC();
+               int olc = marina.getOLC();
                fatal(olc!=63, "bad OLC: "+olc+" expected: 63");
 
                prln("A=0, B=0");
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
             Instruction.Set(DOCK,false,Predicate.IgnoreOLC, CLEAR_FLAG, CLEAR_FLAG));
 
-               fatal(inDock.getFlagA(), "bad A flag: true");
-               fatal(inDock.getFlagB(), "bad B flag: true");
+               fatal(marina.getFlagA(), "bad A flag: true");
+               fatal(marina.getFlagB(), "bad B flag: true");
                
                prln("ILC = Infinity");
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
                Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, SetSource.Infinity));
                
                prln("execute a move instruction that does nothing but loops until torpedo arrives"); 
-        inDock.instrIn.fill(
+        marina.instrIn.fill(
             new Instruction.Move(DOCK,
                                     false,                             /* requeueing */
                                  Predicate.IgnoreOLC,   /* predicate   */
@@ -745,73 +737,75 @@ public class MarinaTest {
                                  ));
         
                prln("NOP This instruction can't predicate on OLC because of a hardware bug");
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
             Instruction.Set(DOCK,false,Predicate.Default, A_FLAG, B_FLAG));
 
                prln("A=1, B=1 This instruction should get torpedoed along with the Move");
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
                        Instruction.Set(DOCK,false,Predicate.Default, SET_FLAG, SET_FLAG));
 
                prln("send torpedo. This should clear the OLC");
-               inDock.instrIn.fill(InstructionStopper.TORPEDO);
+               marina.instrIn.fill(InstructionStopper.TORPEDO);
                
-               getCtrsFlags(inDock);
+               getCtrsFlags(marina);
                
                prln("A and B should remain false");
-               fatal(inDock.getFlagA(), "bad A flag: true");
-               fatal(inDock.getFlagB(), "bad B flag: true");
+               fatal(marina.getFlagA(), "bad A flag: true");
+               fatal(marina.getFlagB(), "bad B flag: true");
        
        prln("OLC = 63. Reload OLC after torpedo");
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
                        Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, 63));
 
-               olc = inDock.getOLC();
+               olc = marina.getOLC();
                fatal(olc!=63, "bad OLC: "+olc+" expected: 63");
                
                prln("A=1, B=1 This instruction should execute because OLC!=0");
-               inDock.instrIn.fill(new 
+               marina.instrIn.fill(new 
                        Instruction.Set(DOCK,false,Predicate.Default, SET_FLAG, SET_FLAG));
 
                prln("A and B should be true");
-               fatal(!inDock.getFlagA(), "bad A flag: false");
-               fatal(!inDock.getFlagB(), "bad B flag: false");
+               fatal(!marina.getFlagA(), "bad A flag: false");
+               fatal(!marina.getFlagB(), "bad B flag: false");
                
                adjustIndent(-2);
        prln("End sendTorpedo");        
     }    
        private void doOneTest(int testNum) {
         prln("MarinaTest: performing test: "+testNum);
-        design.masterClear(tester);
+        marina.masterClear(tester);
+        
+        marina.enableInstructionSend(true);
         
                switch (testNum) {
-               case 0:                 stopToStopOneItem((IsolatedInDock)design);      break;
-               case 1:                 stopToStopThreeItems((IsolatedInDock)design);   break;
-               case 2:                 sendInstructions((IsolatedInDock)design);               break;
-               case 3:                 sendToken((IsolatedInDock)design);                              break;
-               case 4:                 getCtrsFlags((IsolatedInDock)design);                   break;
-               case 5:                 walkOneOLC((IsolatedInDock)design);                             break;
+               case 2:                 sendInstructions(marina);               break;
+               case 3:                 sendToken(marina);                              break;
+               case 4:                 getCtrsFlags(marina);                   break;
+               case 5:                 walkOneOLC(marina);                             break;
                
                // Russell's tests begin with 1000
-               case 1000:              walkOneILC((IsolatedInDock)design);                     break;
-               case 1001:              countIlc((IsolatedInDock)design);                               break;
-               case 1002:              countOlc((IsolatedInDock)design);                               break;
-               case 1003:              sendTorpedo((IsolatedInDock)design);                    break;
+               case 1000:              walkOneILC(marina);                     break;
+               case 1001:              countIlc(marina);                               break;
+               case 1002:              countOlc(marina);                               break;
+               case 1003:              sendTorpedo(marina);                    break;
                
                // Bill's tests begin with 2000
                case 2000: break;
                     
                 // Adam's tests begin with 3000
-               case 3000: sendToken((IsolatedInDock)design); break;
-               case 3001: testFlagAB((IsolatedInDock)design); break;
-               case 3002: testRequeueStage0((IsolatedInDock)design); break;
-               case 3003: testRequeueStage0to1((IsolatedInDock)design); break;
-               case 3004: testFlagZ((IsolatedInDock)design); break;
-               case 3005: testPredicationOnAB((IsolatedInDock)design); break;
+               case 3000: sendToken(marina); break;
+               case 3001: testFlagAB(marina); break;
+               case 3002: testRequeueStage0(marina); break;
+               case 3003: testRequeueStage0to1(marina); break;
+               case 3004: testFlagZ(marina); break;
+               case 3005: testPredicationOnAB(marina); break;
 
                default:
                        fatal(true, "Test number: "+testNum+" doesn't exist.");
                        break;
                }
+               // If we get here then test passed
+               prln("Passed");
        }
 
 

diff --git a/testCode/com/sun/vlsi/chips/marina/test/MarinaUtils.java b/testCode/com/sun/vlsi/chips/marina/test/MarinaUtils.java
index 41c0200..495086f 100644 (file)
--- a/testCode/com/sun/vlsi/chips/marina/test/MarinaUtils.java
+++ b/testCode/com/sun/vlsi/chips/marina/test/MarinaUtils.java
@@ -23,21 +23,21 @@ public class MarinaUtils {
         STOPSOURCE ("01000"),//("10000"),
         SINK       ("00110"),//("00011"),
         STOPSINK   ("00010");
-        private String scanBits;
-        RingIfc(String bits) {scanBits = bits;}
-        public String bits() {return scanBits;}
+        private BitVector scanBits;
+        RingIfc(String bits) {scanBits = new BitVector(bits,"RingIfc");}
+        public BitVector bits() {return scanBits;}
     }
     /** StateWireState hides whether the state wire being high means FULL 
      * or whether high means EMPTY */
     public static enum StateWireState {FULL, EMPTY};
 
     public static class CmdArgs {
-               public enum Mode {ISOLATED_IN_DOCK,
-                                                 ISOLATED_OUT_DOCK,
+               public enum Mode {//ISOLATED_IN_DOCK,
+                                                 //ISOLATED_OUT_DOCK,
                           WHOLE_CHIP_SCHEMATIC_PARASITICS,
                           WHOLE_CHIP_LAYOUT_PARASITICS,
                           TEST_SILICON};
-               public Mode mode = Mode.ISOLATED_IN_DOCK;
+               public Mode mode = Mode.WHOLE_CHIP_SCHEMATIC_PARASITICS;
                public int testNum, ringNum, numTokensOther, chipNum=-1;
                public Station station=Station.ONE;
         public float vdd, temp;
@@ -50,8 +50,8 @@ public class MarinaUtils {
                        System.out.println("Options: -testNum <int>            select which test to run");
             System.out.println("         -vdd <float>");
             System.out.println("         -temp <float>");
-            System.out.println("         -isoIn                    simulate netlist of isolated input dock only, parasitics from schematic");
-            System.out.println("         -isoOut                   simulate netlist of isolated output dock only, parasitics from schematic");
+//            System.out.println("         -isoIn                    simulate netlist of isolated input dock only, parasitics from schematic");
+//            System.out.println("         -isoOut                   simulate netlist of isolated output dock only, parasitics from schematic");
                        System.out.println("         -chipSch                  simulate netlist of entire chip, parasitics from schematic");
                        System.out.println("         -chipLay                  simulate netlist of entire chip, parasitics from layout");
                        System.out.println("         -silicon                  test the silicon");
@@ -91,12 +91,10 @@ public class MarinaUtils {
                                        case 2: station = Station.TWO; break;
                                        default: System.out.println("Bad station: "+args[i]); usage();
                                        }
-                               } else if (args[i].equals("-exptSch")) {
-                                       mode = CmdArgs.Mode.ISOLATED_IN_DOCK;
-                               } else if (args[i].equals("-exptLay")) {
-                                       mode = CmdArgs.Mode.ISOLATED_OUT_DOCK;
-                               } else if (args[i].equals("-chipLay")) {
+                               } else if (args[i].equals("-chipSch")) {
                                        mode = CmdArgs.Mode.WHOLE_CHIP_SCHEMATIC_PARASITICS;
+                               } else if (args[i].equals("-chipLay")) {
+                                       mode = CmdArgs.Mode.WHOLE_CHIP_LAYOUT_PARASITICS;
                                } else if (args[i].equals("-silicon")) {
                                        mode = CmdArgs.Mode.TEST_SILICON;
                                } else {

diff --git a/testCode/com/sun/vlsi/chips/marina/test/ProperStopper.java b/testCode/com/sun/vlsi/chips/marina/test/ProperStopper.java
index 6649abf..eb8d00e 100644 (file)
--- a/testCode/com/sun/vlsi/chips/marina/test/ProperStopper.java
+++ b/testCode/com/sun/vlsi/chips/marina/test/ProperStopper.java
@@ -11,7 +11,7 @@ import com.sun.vlsi.chips.marina.test.MarinaUtils.StateWireState;
 
 public class ProperStopper {
        private final String name;
-    private final String captureClockRelPath = "aFillSta@0.all1in52@1.data1in3@0";
+    private final String captureClockRelPath = "fillStag@0.all1in52@1.data1in3@0";
     private final String captureClockName = "wrr";
 
     private boolean traceFill = true;
@@ -71,6 +71,23 @@ public class ProperStopper {
     private StateWireState boolToState(boolean b) {
        return b ? StateWireState.FULL : StateWireState.EMPTY;
     }
+    // The first 5 bits of the control chain control the fill and drain stages
+    private void setFillDrainControl(BitVector fdCtl) {
+       fatal(fdCtl.getNumBits()!=5, "expect 5 proper stopper control bits");
+       BitVector val = cc.getInBits(controlPath);
+       for (int i=0; i<fdCtl.getNumBits(); i++) {
+               val.set(i, fdCtl.get(i));
+       }
+       cc.setInBits(controlPath, val);
+       shiftControl(false, true);
+    }
+    // The last bit of the control chain controls the general purpose
+    // output
+    public void setGeneralPurposeOutput(Boolean b) {
+       BitVector val = cc.getInBits(controlPath);
+       val.set(5,b);
+       shiftControl(false, true);
+    }
     
     //-------------------------- public methods ----------------------------
     
@@ -83,53 +100,43 @@ public class ProperStopper {
 
     /** Put stopper in RUN state */
     public void run() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.RUN.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.RUN.bits());
     }
     /** Put stopper in IDLE state */
     public void idle() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.IDLE.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.IDLE.bits());
     }
     /** Put stopper in FILL state */
     public void fill() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.FILL.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.FILL.bits());
     }
     /** Put stopper in BLOCK state */
     public void block() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.BLOCK.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.BLOCK.bits());
     }
     /** Put stopper in STOP state */
     public void stop() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.STOP.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.STOP.bits());
     }
     /** Put stopper in CLEAR state */
     public void clear() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.CLEAR.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.CLEAR.bits());
     }
     /** Put stopper in SOURCE state */
     public void source() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.SOURCE.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.SOURCE.bits());
     }
     /** Put stopper in STOPSOURCE state */
     public void stopSource() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.STOPSOURCE.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.STOPSOURCE.bits());
     }
     /** Put stopper in SINK state */
     public void sink() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.SINK.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.SINK.bits());
     }
     /** Put stopper in STOPSINK state */
     public void stopSink() {
-       cc.setInBits(controlPath, MarinaUtils.RingIfc.STOPSINK.bits());
-       shiftControl(false, true);
+       setFillDrainControl(MarinaUtils.RingIfc.STOPSINK.bits());
     }
     /** Stop a running stopper in order to add items.  Ensure that we don't
      * lose the item in the fill stage.  Wait long enough for ring to quiesce.

diff --git a/testCode/hardwareBugs.txt b/testCode/hardwareBugs.txt
index 9faf47b..f89de0b 100644 (file)
--- a/testCode/hardwareBugs.txt
+++ b/testCode/hardwareBugs.txt
@@ -35,3 +35,14 @@ but not acknowledged, the alternator will assert succB and overwrite the
 data intended for A. 
 Noted: 12 Nov 2008
 Fixed:
+
+8) Sense of Token bit in EPI FIFO is wrong. The correct sense is "High 
+means not a token". 
+Noted: 14 Nov 2008
+Fixed: 14 Nov 2008
+
+9) EPI FIFO is missing it's data latches.
+Noted: 14 Nov 2008
+Fixed: 14 Nov 2008
+
+10)
\ No newline at end of file

diff --git a/testCode/marina.bsh b/testCode/marina.bsh
index f61e564..05f845d 100644 (file)
--- a/testCode/marina.bsh
+++ b/testCode/marina.bsh
@@ -16,6 +16,7 @@ import com.sun.electric.plugins.menus.ScanChainXML;
   gen.addScanChainElement("scanJ", "scanCellE", "RW", "-", "sin", "sout", "dIn[1](R)", "latch2in@0.dataBar(WI)");
   gen.addScanChainElement("scanJ", "scanCellF", "RW", "L", "sin", "sout", "dout[1](R)", "latch2in@1.dataBar(WI)");
   gen.addScanChainElement("scanK", "scanCellKh", "R", "-", "sin", "sout", "din[1](R)", "");
+  gen.addScanChainElement("countersL", "cntScnOne", "RW", "-", "sin", "out", "out(R)", "latch2in@0.dataBar(WI)");
   //gen.addScanChainElement("latchGroupsK", "latchWscan", "RW", "-", "sin", "sout", "scanCell@2.latch2in@0.dataBar(WI)", "out[1](R)");
   //gen.addScanChainElement("latchGroupsK", "latchWscan", "RW", "-", "sin", "sout", "hi2inLat@1.dataBar(WI)", "out[1](R)");
 
@@ -38,8 +39,8 @@ import com.sun.electric.plugins.menus.ScanChainXML;
 
    // Generate xml for isolatedInDock only. This is for simulations that include only
    // one input dock.
-   gen.setOutput("isolatedInDock.xml");
-   gen.startFromExport("scanInR[1]", "isolatedInDock_report");
-   gen.startFromExport("scanInC[1]", "isolatedInDock_control");
-   gen.startFromExport("scanInD[1]", "isolatedInDock_data");
-   gen.start("marina","isolatedInDock{sch}");
+   gen.setOutput("marina.xml");
+   gen.startFromExport("scanInR[1]", "marina_report");
+   gen.startFromExport("scanInC[1]", "marina_control");
+   gen.startFromExport("scanInD[1]", "marina_data");
+   gen.start("marina","marina{sch}");

diff --git a/testCode/marina.spi b/testCode/marina.spi
new file mode 100644 (file)
index 0000000..56e9f57
--- /dev/null
+++ b/testCode/marina.spi
@@ -0,0 +1,12271 @@
+*** SPICE deck for cell marina{sch} from library marina
+*** Created on Wed Nov 12, 2008 08:21:20
+*** Last revised on Fri Nov 14, 2008 09:00:35
+*** Written on Fri Nov 14, 2008 12:38:06 by Electric VLSI Design System, 
+*version 8.08k
+*** Layout tech: cmos90, foundry TSMC
+*** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
+.OPTIONS NOMOD NOPAGE
+* Model cards are described in this file:
+.include '../testCode/header.hsp'
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_10 d g s
+MNMOSf@0 d g s gnd nch W='30*(1+ABN/sqrt(30*2))' L='2' 
++DELVTO='AVT0N/sqrt(30*2)'
+.ENDS NMOSx-X_10
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_10 d g s
+MPMOSf@0 d g s vdd pch W='60*(1+ABP/sqrt(60*2))' L='2'  
++DELVTO='AVT0P/sqrt(60*2)'
+.ENDS PMOSx-X_10
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_10 in out
+XNMOS@0 out in gnd NMOSx-X_10
+XPMOS@0 out in vdd PMOSx-X_10
+.ENDS inv-X_10
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_20 d g s
+MNMOSf@0 d g s gnd nch W='60*(1+ABN/sqrt(60*2))' L='2' 
++DELVTO='AVT0N/sqrt(60*2)'
+.ENDS NMOSx-X_20
+
+*** CELL: redFour:nms2{sch}
+.SUBCKT nms2-X_10 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_20
+XNMOS@1 net@0 g gnd NMOSx-X_20
+.ENDS nms2-X_10
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_20 d g s
+MPMOSf@0 d g s vdd pch W='120*(1+ABP/sqrt(120*2))' L='2'  
++DELVTO='AVT0P/sqrt(120*2)'
+.ENDS PMOSx-X_20
+
+*** CELL: redFour:pms2{sch}
+.SUBCKT pms2-X_10 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_20
+XPMOS@1 d g2 net@2 PMOSx-X_20
+.ENDS pms2-X_10
+
+*** CELL: redFour:triInv{sch}
+.SUBCKT triInv-X_10 en enB in out
+Xnms2@0 out in en nms2-X_10
+Xpms2@0 out in enB pms2-X_10
+.ENDS triInv-X_10
+
+*** CELL: gatesK:mux10{sch}
+.SUBCKT mux10 inA[1] inB[1] out[1] s[F] s[T]
+XtriInv@0 s[T] s[F] inA[1] out[1] triInv-X_10
+XtriInv@1 s[F] s[T] inB[1] out[1] triInv-X_10
+.ENDS mux10
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-277_3-R_34_667m a b
+Ccap@0 gnd net@14 1.017f
+Ccap@1 gnd net@8 1.017f
+Ccap@2 gnd net@11 1.017f
+Rres@0 net@14 a 1.602
+Rres@1 net@11 net@14 3.204
+Rres@2 b net@8 1.602
+Rres@3 net@8 net@11 3.204
+.ENDS wire-C_0_011f-277_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-277_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-277_3-R_34_667m
+.ENDS wire90-277_3-layer_1-width_3
+
+*** CELL: registersL:dataMux4{sch}
+.SUBCKT dataMux4 lit[16] lit[17] lit[18] lit[19] out[16] out[17] out[18] 
++out[19] s[F] s[T] sign
+Xi[1] lit[16] x[1] inv-X_10
+Xi[2] lit[17] x[2] inv-X_10
+Xi[3] lit[18] x[3] inv-X_10
+Xi[4] lit[19] x[4] inv-X_10
+Xm[1] x[1] sign out[16] s[F] s[T] mux10
+Xm[2] x[2] sign out[17] s[F] s[T] mux10
+Xm[3] x[3] sign out[18] s[F] s[T] mux10
+Xm[4] x[4] sign out[19] s[F] s[T] mux10
+Xwire90@0 x[1] wire90@0_b wire90-277_3-layer_1-width_3
+Xwire90@1 x[2] wire90@1_b wire90-277_3-layer_1-width_3
+Xwire90@2 x[3] wire90@2_b wire90-277_3-layer_1-width_3
+Xwire90@3 x[4] wire90@3_b wire90-277_3-layer_1-width_3
+.ENDS dataMux4
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_80 d g s
+MNMOSf@0 d g s gnd nch W='240*(1+ABN/sqrt(240*2))' L='2' 
++DELVTO='AVT0N/sqrt(240*2)'
+.ENDS NMOSx-X_80
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_80 d g s
+MPMOSf@0 d g s vdd pch W='480*(1+ABP/sqrt(480*2))' L='2'  
++DELVTO='AVT0P/sqrt(480*2)'
+.ENDS PMOSx-X_80
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_80 in out
+XNMOS@0 out in gnd NMOSx-X_80
+XPMOS@0 out in vdd PMOSx-X_80
+.ENDS inv-X_80
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_30 d g s
+MNMOSf@0 d g s gnd nch W='90*(1+ABN/sqrt(90*2))' L='2' 
++DELVTO='AVT0N/sqrt(90*2)'
+.ENDS NMOSx-X_30
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_30 d g s
+MPMOSf@0 d g s vdd pch W='180*(1+ABP/sqrt(180*2))' L='2'  
++DELVTO='AVT0P/sqrt(180*2)'
+.ENDS PMOSx-X_30
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_30 in out
+XNMOS@0 out in gnd NMOSx-X_30
+XPMOS@0 out in vdd PMOSx-X_30
+.ENDS inv-X_30
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_100 d g s
+MNMOSf@0 d g s gnd nch W='300*(1+ABN/sqrt(300*2))' L='2' 
++DELVTO='AVT0N/sqrt(300*2)'
+.ENDS NMOSx-X_100
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_100 d g s
+MPMOSf@0 d g s vdd pch W='600*(1+ABP/sqrt(600*2))' L='2'  
++DELVTO='AVT0P/sqrt(600*2)'
+.ENDS PMOSx-X_100
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_100 in out
+XNMOS@0 out in gnd NMOSx-X_100
+XPMOS@0 out in vdd PMOSx-X_100
+.ENDS inv-X_100
+
+*** CELL: redFour:nms2_sy{sch}
+.SUBCKT nms2_sy-X_20 d g g2
+Xnms2@0 d g g2 nms2-X_10
+Xnms2@1 d g2 g nms2-X_10
+.ENDS nms2_sy-X_20
+
+*** CELL: redFour:nand2_sy{sch}
+.SUBCKT nand2_sy-X_20 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_20
+XPMOS@1 out ina vdd PMOSx-X_20
+Xnms2_sy@0 out ina inb nms2_sy-X_20
+.ENDS nand2_sy-X_20
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-953_9-R_34_667m a b
+Ccap@0 gnd net@14 3.498f
+Ccap@1 gnd net@8 3.498f
+Ccap@2 gnd net@11 3.498f
+Rres@0 net@14 a 5.511
+Rres@1 net@11 net@14 11.023
+Rres@2 b net@8 5.511
+Rres@3 net@8 net@11 11.023
+.ENDS wire-C_0_011f-953_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-953_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-953_9-R_34_667m
+.ENDS wire90-953_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-668_2-R_34_667m a b
+Ccap@0 gnd net@14 2.45f
+Ccap@1 gnd net@8 2.45f
+Ccap@2 gnd net@11 2.45f
+Rres@0 net@14 a 3.861
+Rres@1 net@11 net@14 7.721
+Rres@2 b net@8 3.861
+Rres@3 net@8 net@11 7.721
+.ENDS wire-C_0_011f-668_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-668_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-668_2-R_34_667m
+.ENDS wire90-668_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4189_7-R_34_667m a b
+Ccap@0 gnd net@14 15.362f
+Ccap@1 gnd net@8 15.362f
+Ccap@2 gnd net@11 15.362f
+Rres@0 net@14 a 24.207
+Rres@1 net@11 net@14 48.414
+Rres@2 b net@8 24.207
+Rres@3 net@8 net@11 48.414
+.ENDS wire-C_0_011f-4189_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4189_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4189_7-R_34_667m
+.ENDS wire90-4189_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-6941_5-R_34_667m a b
+Ccap@0 gnd net@14 25.452f
+Ccap@1 gnd net@8 25.452f
+Ccap@2 gnd net@11 25.452f
+Rres@0 net@14 a 40.106
+Rres@1 net@11 net@14 80.213
+Rres@2 b net@8 40.106
+Rres@3 net@8 net@11 80.213
+.ENDS wire-C_0_011f-6941_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-6941_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-6941_5-R_34_667m
+.ENDS wire90-6941_5-layer_1-width_3
+
+*** CELL: registersL:dataMuxAll{sch}
+.SUBCKT dataMuxAll lit[15] lit[16] lit[17] lit[18] lit[19] out[15] out[16] 
++out[17] out[18] out[19] s[F] s[T] sel[long] sign
+XdataMux4@0 lit[16] lit[17] lit[18] lit[19] out[16] out[17] out[18] out[19] 
++s[F] s[T] sign dataMux4
+Xinv@0 net@64 sign inv-X_80
+Xinv@2 lit[15] out[15] inv-X_10
+Xinv@5 sel[long] net@61 inv-X_30
+Xinv@6 net@115 net@111 inv-X_100
+Xinv@7 s[T] net@113 inv-X_80
+Xnand2_sy@0 net@115 lit[15] net@75 nand2_sy-X_20
+Xwire90@8 net@61 net@115 wire90-953_9-layer_1-width_3
+Xwire90@9 net@75 net@64 wire90-668_2-layer_1-width_3
+Xwire90@10 net@113 s[F] wire90-4189_7-layer_1-width_3
+Xwire90@11 net@111 s[T] wire90-6941_5-layer_1-width_3
+.ENDS dataMuxAll
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_70 d g s
+MNMOSf@0 d g s gnd nch W='210*(1+ABN/sqrt(210*2))' L='2' 
++DELVTO='AVT0N/sqrt(210*2)'
+.ENDS NMOSx-X_70
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_70 d g s
+MPMOSf@0 d g s vdd pch W='420*(1+ABP/sqrt(420*2))' L='2'  
++DELVTO='AVT0P/sqrt(420*2)'
+.ENDS PMOSx-X_70
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_70 in out
+XNMOS@0 out in gnd NMOSx-X_70
+XPMOS@0 out in vdd PMOSx-X_70
+.ENDS inv-X_70
+
+*** CELL: redFour:nms2{sch}
+.SUBCKT nms2-X_15 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_30
+XNMOS@1 net@0 g gnd NMOSx-X_30
+.ENDS nms2-X_15
+
+*** CELL: redFour:nms2_sy{sch}
+.SUBCKT nms2_sy-X_30 d g g2
+Xnms2@0 d g g2 nms2-X_15
+Xnms2@1 d g2 g nms2-X_15
+.ENDS nms2_sy-X_30
+
+*** CELL: redFour:nand2_sy{sch}
+.SUBCKT nand2_sy-X_30 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_30
+XPMOS@1 out ina vdd PMOSx-X_30
+Xnms2_sy@0 out ina inb nms2_sy-X_30
+.ENDS nand2_sy-X_30
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-947_7-R_34_667m a b
+Ccap@0 gnd net@14 3.475f
+Ccap@1 gnd net@8 3.475f
+Ccap@2 gnd net@11 3.475f
+Rres@0 net@14 a 5.476
+Rres@1 net@11 net@14 10.951
+Rres@2 b net@8 5.476
+Rres@3 net@8 net@11 10.951
+.ENDS wire-C_0_011f-947_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-947_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-947_7-R_34_667m
+.ENDS wire90-947_7-layer_1-width_3
+
+*** CELL: driversJ:dataDriver70{sch}
+.SUBCKT dataDriver70 inA inB out
+Xinv@0 net@8 out inv-X_70
+Xnand2_sy@0 inA inB net@7 nand2_sy-X_30
+Xwire90@0 net@7 net@8 wire90-947_7-layer_1-width_3
+.ENDS dataDriver70
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_1_733 d g s
+MNMOSf@0 d g s gnd nch W='5.199*(1+ABN/sqrt(5.199*2))' L='2' 
++DELVTO='AVT0N/sqrt(5.199*2)'
+.ENDS NMOSx-X_1_733
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_4 d g s
+MPMOSf@0 d g s vdd pch W='24*(1+ABP/sqrt(24*2))' L='2'  
++DELVTO='AVT0P/sqrt(24*2)'
+.ENDS PMOSx-X_4
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_1 d g s
+MPMOSf@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2'  
++DELVTO='AVT0P/sqrt(6*2)'
+.ENDS PMOSx-X_1
+
+*** CELL: latchPartsK:latchKeep{sch}
+.SUBCKT latchKeep out[B] out[s]
+XNMOSx@0 out[B] out[s] gnd NMOSx-X_1_733
+XNMOSx@1 out[s] out[B] gnd NMOSx-X_1_733
+XPMOSx@0 out[B] out[s] vdd PMOSx-X_4
+XPMOSx@1 out[s] out[B] vdd PMOSx-X_1
+.ENDS latchKeep
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_3 d g s
+MNMOSf@0 d g s gnd nch W='9*(1+ABN/sqrt(9*2))' L='2' DELVTO='AVT0N/sqrt(9*2)'
+.ENDS NMOSx-X_3
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_6 d g s
+MNMOSf@0 d g s gnd nch W='18*(1+ABN/sqrt(18*2))' L='2' 
++DELVTO='AVT0N/sqrt(18*2)'
+.ENDS NMOSx-X_6
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_5 d g s
+MPMOSf@0 d g s vdd pch W='30*(1+ABP/sqrt(30*2))' L='2'  
++DELVTO='AVT0P/sqrt(30*2)'
+.ENDS PMOSx-X_5
+
+*** CELL: redFour:invLT{sch}
+.SUBCKT invLT-X_5 in out
+XNMOS@0 out in gnd NMOSx-X_10
+XPMOS@0 out in vdd PMOSx-X_5
+.ENDS invLT-X_5
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-124_4-R_34_667m a b
+Ccap@0 gnd net@14 0.456f
+Ccap@1 gnd net@8 0.456f
+Ccap@2 gnd net@11 0.456f
+Rres@0 net@14 a 0.719
+Rres@1 net@11 net@14 1.438
+Rres@2 b net@8 0.719
+Rres@3 net@8 net@11 1.438
+.ENDS wire-C_0_011f-124_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-124_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-124_4-R_34_667m
+.ENDS wire90-124_4-layer_1-width_3
+
+*** CELL: latchPartsK:latchPointF{sch}
+.SUBCKT latchPointF hcl in[1] x[F] x[T]
+XPMOSx@0 in[1] hcl x[T] NMOSx-X_3
+XPMOSx@1 net@8 hcl x[F] NMOSx-X_6
+Xinv@0 in[1] net@105 invLT-X_5
+Xwire90@0 net@105 net@8 wire90-124_4-layer_1-width_3
+.ENDS latchPointF
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-145_9-R_34_667m a b
+Ccap@0 gnd net@14 0.535f
+Ccap@1 gnd net@8 0.535f
+Ccap@2 gnd net@11 0.535f
+Rres@0 net@14 a 0.843
+Rres@1 net@11 net@14 1.686
+Rres@2 b net@8 0.843
+Rres@3 net@8 net@11 1.686
+.ENDS wire-C_0_011f-145_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-145_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-145_9-R_34_667m
+.ENDS wire90-145_9-layer_1-width_3
+
+*** CELL: latchesK:raw2inLatchF{sch}
+.SUBCKT raw2inLatchF hcl[A] hcl[B] inA[1] inB[1] out[F]
+XlatchKee@0 out[F] net@63 latchKeep
+XlatchPoi@0 hcl[A] inA[1] out[F] net@45 latchPointF
+XlatchPoi@1 hcl[B] inB[1] out[F] net@45 latchPointF
+Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3
+.ENDS raw2inLatchF
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_20 in out
+XNMOS@0 out in gnd NMOSx-X_20
+XPMOS@0 out in vdd PMOSx-X_20
+.ENDS inv-X_20
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_60 d g s
+MNMOSf@0 d g s gnd nch W='180*(1+ABN/sqrt(180*2))' L='2' 
++DELVTO='AVT0N/sqrt(180*2)'
+.ENDS NMOSx-X_60
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_60 d g s
+MPMOSf@0 d g s vdd pch W='360*(1+ABP/sqrt(360*2))' L='2'  
++DELVTO='AVT0P/sqrt(360*2)'
+.ENDS PMOSx-X_60
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_60 in out
+XNMOS@0 out in gnd NMOSx-X_60
+XPMOS@0 out in vdd PMOSx-X_60
+.ENDS inv-X_60
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-295_8-R_34_667m a b
+Ccap@0 gnd net@14 1.085f
+Ccap@1 gnd net@8 1.085f
+Ccap@2 gnd net@11 1.085f
+Rres@0 net@14 a 1.709
+Rres@1 net@11 net@14 3.418
+Rres@2 b net@8 1.709
+Rres@3 net@8 net@11 3.418
+.ENDS wire-C_0_011f-295_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-295_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-295_8-R_34_667m
+.ENDS wire90-295_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-242_1-R_34_667m a b
+Ccap@0 gnd net@14 0.888f
+Ccap@1 gnd net@8 0.888f
+Ccap@2 gnd net@11 0.888f
+Rres@0 net@14 a 1.399
+Rres@1 net@11 net@14 2.798
+Rres@2 b net@8 1.399
+Rres@3 net@8 net@11 2.798
+.ENDS wire-C_0_011f-242_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-242_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-242_1-R_34_667m
+.ENDS wire90-242_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-555_8-R_34_667m a b
+Ccap@0 gnd net@14 2.038f
+Ccap@1 gnd net@8 2.038f
+Ccap@2 gnd net@11 2.038f
+Rres@0 net@14 a 3.211
+Rres@1 net@11 net@14 6.423
+Rres@2 b net@8 3.211
+Rres@3 net@8 net@11 6.423
+.ENDS wire-C_0_011f-555_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-555_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-555_8-R_34_667m
+.ENDS wire90-555_8-layer_1-width_3
+
+*** CELL: latchesK:latch2in60C{sch}
+.SUBCKT latch2in60C hcl[A] hcl[B] inA[1] inB[1] outS[1]
+Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@14 raw2inLatchF
+XinvLT@0 net@15 net@18 invLT-X_5
+XinvLT@1 net@16 net@19 inv-X_20
+XinvLT@2 net@17 outS[1] inv-X_60
+Xwire90@0 net@14 net@15 wire90-295_8-layer_1-width_3
+Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3
+Xwire90@2 net@19 net@17 wire90-555_8-layer_1-width_3
+.ENDS latch2in60C
+
+*** CELL: registersL:dRegDrive{sch}
+.SUBCKT dRegDrive dcl[A] dcl[B] fire[A] fire[B] inA[1] inA[T] inB[1] inB[T] 
++outS[1] outS[T]
+XdataDriv@0 inB[T] fire[B] dcl[B] dataDriver70
+XdataDriv@1 inA[T] fire[A] dcl[A] dataDriver70
+Xhi2inLat@0 fire[A] fire[B] inA[T] inB[T] outS[T] latch2in60C
+Xlatch2in@0 dcl[A] dcl[B] inA[1] inB[1] outS[1] latch2in60C
+.ENDS dRegDrive
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-146_1-R_34_667m a b
+Ccap@0 gnd net@14 0.536f
+Ccap@1 gnd net@8 0.536f
+Ccap@2 gnd net@11 0.536f
+Rres@0 net@14 a 0.844
+Rres@1 net@11 net@14 1.688
+Rres@2 b net@8 0.844
+Rres@3 net@8 net@11 1.688
+.ENDS wire-C_0_011f-146_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-146_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-146_1-R_34_667m
+.ENDS wire90-146_1-layer_1-width_3
+
+*** CELL: latchesK:raw1inLatchF{sch}
+.SUBCKT raw1inLatchF hcl in[1] out[F]
+XlatchFlo@0 out[F] net@58 latchKeep
+XlatchPoi@0 hcl in[1] out[F] net@45 latchPointF
+Xwire90@0 net@45 net@58 wire90-146_1-layer_1-width_3
+.ENDS raw1inLatchF
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_9_6 d g s
+MNMOSf@0 d g s gnd nch W='28.8*(1+ABN/sqrt(28.8*2))' L='2' 
++DELVTO='AVT0N/sqrt(28.8*2)'
+.ENDS NMOSx-X_9_6
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_9_6 d g s
+MPMOSf@0 d g s vdd pch W='57.6*(1+ABP/sqrt(57.6*2))' L='2'  
++DELVTO='AVT0P/sqrt(57.6*2)'
+.ENDS PMOSx-X_9_6
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_9_6 in out
+XNMOS@0 out in gnd NMOSx-X_9_6
+XPMOS@0 out in vdd PMOSx-X_9_6
+.ENDS inv-X_9_6
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_4 d g s
+MNMOSf@0 d g s gnd nch W='12*(1+ABN/sqrt(12*2))' L='2' 
++DELVTO='AVT0N/sqrt(12*2)'
+.ENDS NMOSx-X_4
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_4 in out
+XNMOS@0 out in gnd NMOSx-X_4
+XPMOS@0 out in vdd PMOSx-X_4
+.ENDS inv-X_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-114_7-R_34_667m a b
+Ccap@0 gnd net@14 0.421f
+Ccap@1 gnd net@8 0.421f
+Ccap@2 gnd net@11 0.421f
+Rres@0 net@14 a 0.663
+Rres@1 net@11 net@14 1.325
+Rres@2 b net@8 0.663
+Rres@3 net@8 net@11 1.325
+.ENDS wire-C_0_011f-114_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-114_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-114_7-R_34_667m
+.ENDS wire90-114_7-layer_1-width_3
+
+*** CELL: latchesK:latch1in09.6Bi{sch}
+.SUBCKT latch1in09_6Bi hcl in[1] out[1]
+Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF
+Xinv@0 net@23 out[1] inv-X_9_6
+XinvLT@0 net@18 net@25 inv-X_4
+Xwire90@0 net@19 net@18 wire90-277_3-layer_1-width_3
+Xwire90@1 net@25 net@23 wire90-114_7-layer_1-width_3
+.ENDS latch1in09_6Bi
+
+*** CELL: redFour:nms2{sch}
+.SUBCKT nms2-X_5 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_10
+XNMOS@1 net@0 g gnd NMOSx-X_10
+.ENDS nms2-X_5
+
+*** CELL: redFour:pms2{sch}
+.SUBCKT pms2-X_5 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_10
+XPMOS@1 d g2 net@2 PMOSx-X_10
+.ENDS pms2-X_5
+
+*** CELL: redFour:triInv{sch}
+.SUBCKT triInv-X_5 en enB in out
+Xnms2@0 out in en nms2-X_5
+Xpms2@0 out in enB pms2-X_5
+.ENDS triInv-X_5
+
+*** CELL: gatesK:mux5{sch}
+.SUBCKT mux5 inA[1] inB[1] out[1] s[F] s[T]
+XtriInv@0 s[T] s[F] inA[1] out[1] triInv-X_5
+XtriInv@1 s[F] s[T] inB[1] out[1] triInv-X_5
+.ENDS mux5
+
+*** CELL: latchGroupsK:dataMux{sch}
+.SUBCKT dataMux hcl inB[1] in[1] out[1] s[F] s[T]
+Xlatch1in@1 hcl in[1] net@5 latch1in09_6Bi
+Xmux5@0 net@6 inB[1] out[1] s[F] s[T] mux5
+Xwire90@0 net@5 net@6 wire90-277_3-layer_1-width_3
+.ENDS dataMux
+
+*** CELL: registersL:dataMux18{sch}
+.SUBCKT dataMux18 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[20] out[21] 
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[30] 
++out[31] out[32] out[33] out[34] out[35] out[36] out[37] s[F] s[T] sign take
+Xdm[1] net@42 sign in[1] out[20] s[F] s[T] dataMux
+Xdm[2] net@42 sign in[2] out[21] s[F] s[T] dataMux
+Xdm[3] net@42 sign in[3] out[22] s[F] s[T] dataMux
+Xdm[4] net@42 sign in[4] out[23] s[F] s[T] dataMux
+Xdm[5] net@42 sign in[5] out[24] s[F] s[T] dataMux
+Xdm[6] net@42 sign in[6] out[25] s[F] s[T] dataMux
+Xdm[7] net@42 sign in[7] out[26] s[F] s[T] dataMux
+Xdm[8] net@42 sign in[8] out[27] s[F] s[T] dataMux
+Xdm[9] net@42 sign in[9] out[28] s[F] s[T] dataMux
+Xdm[10] net@42 sign in[10] out[29] s[F] s[T] dataMux
+Xdm[11] net@42 sign in[11] out[30] s[F] s[T] dataMux
+Xdm[12] net@42 sign in[12] out[31] s[F] s[T] dataMux
+Xdm[13] net@42 sign in[13] out[32] s[F] s[T] dataMux
+Xdm[14] net@42 sign in[14] out[33] s[F] s[T] dataMux
+Xdm[15] net@42 sign in[15] out[34] s[F] s[T] dataMux
+Xdm[16] net@42 sign in[16] out[35] s[F] s[T] dataMux
+Xdm[17] net@42 sign in[17] out[36] s[F] s[T] dataMux
+Xdm[18] net@42 sign in[18] out[37] s[F] s[T] dataMux
+Xinv@0 take net@39 inv-X_30
+Xwire90@0 net@39 net@42 wire90-277_3-layer_1-width_3
+.ENDS dataMux18
+
+*** CELL: registersL:theDregister{sch}
+.SUBCKT theDregister fire[A] fire[B] inA[10] inA[11] inA[12] inA[13] inA[14] 
++inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] 
++inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] 
++inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] inA[5] 
++inA[6] inA[7] inA[8] inA[9] inA[T] inB[10] inB[11] inB[12] inB[13] inB[14] 
++inB[15] inB[16] inB[17] inB[18] inB[19] inB[1] inB[2] inB[3] inB[4] inB[5] 
++inB[6] inB[7] inB[8] inB[9] inB[T] outS[10] outS[11] outS[12] outS[13] 
++outS[14] outS[15] outS[16] outS[17] outS[18] outS[19] outS[1] outS[20] 
++outS[21] outS[22] outS[23] outS[24] outS[25] outS[26] outS[27] outS[28] 
++outS[29] outS[2] outS[30] outS[31] outS[32] outS[33] outS[34] outS[35] 
++outS[36] outS[37] outS[3] outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] 
++outS[T] s[F] s[T] sign
+XdRegDriv@1 dcl[A] dcl[B] fire[A] fire[B] inA[19] inA[T] inB[19] inB[T] 
++outS[19] outS[T] dRegDrive
+XdataMux1@0 outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] outS[16] 
++outS[17] outS[18] outS[1] outS[2] outS[3] outS[4] outS[5] outS[6] outS[7] 
++outS[8] outS[9] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] inB[26] 
++inB[27] inB[28] inB[29] inB[30] inB[31] inB[32] inB[33] inB[34] inB[35] 
++inB[36] inB[37] s[F] s[T] sign dcl[B] dataMux18
+Xlat[1] net@6 net@3 inA[1] inB[1] outS[1] latch2in60C
+Xlat[2] net@6 net@3 inA[2] inB[2] outS[2] latch2in60C
+Xlat[3] net@6 net@3 inA[3] inB[3] outS[3] latch2in60C
+Xlat[4] net@6 net@3 inA[4] inB[4] outS[4] latch2in60C
+Xlat[5] net@6 net@3 inA[5] inB[5] outS[5] latch2in60C
+Xlat[6] net@6 net@3 inA[6] inB[6] outS[6] latch2in60C
+Xlat[7] net@6 net@3 inA[7] inB[7] outS[7] latch2in60C
+Xlat[8] net@6 net@3 inA[8] inB[8] outS[8] latch2in60C
+Xlat[9] net@6 net@3 inA[9] inB[9] outS[9] latch2in60C
+Xlat[10] net@6 net@3 inA[10] inB[10] outS[10] latch2in60C
+Xlat[11] net@6 net@3 inA[11] inB[11] outS[11] latch2in60C
+Xlat[12] net@6 net@3 inA[12] inB[12] outS[12] latch2in60C
+Xlat[13] net@6 net@3 inA[13] inB[13] outS[13] latch2in60C
+Xlat[14] net@6 net@3 inA[14] inB[14] outS[14] latch2in60C
+Xlat[15] net@6 net@3 inA[15] inB[15] outS[15] latch2in60C
+Xlat[16] net@6 net@3 inA[16] inB[16] outS[16] latch2in60C
+Xlat[17] net@6 net@3 inA[17] inB[17] outS[17] latch2in60C
+Xlat[18] net@6 net@3 inA[18] inB[18] outS[18] latch2in60C
+Xlat[20] net@6 net@3 inA[20] inB[20] outS[20] latch2in60C
+Xlat[21] net@6 net@3 inA[21] inB[21] outS[21] latch2in60C
+Xlat[22] net@6 net@3 inA[22] inB[22] outS[22] latch2in60C
+Xlat[23] net@6 net@3 inA[23] inB[23] outS[23] latch2in60C
+Xlat[24] net@6 net@3 inA[24] inB[24] outS[24] latch2in60C
+Xlat[25] net@6 net@3 inA[25] inB[25] outS[25] latch2in60C
+Xlat[26] net@6 net@3 inA[26] inB[26] outS[26] latch2in60C
+Xlat[27] net@6 net@3 inA[27] inB[27] outS[27] latch2in60C
+Xlat[28] net@6 net@3 inA[28] inB[28] outS[28] latch2in60C
+Xlat[29] net@6 net@3 inA[29] inB[29] outS[29] latch2in60C
+Xlat[30] net@6 net@3 inA[30] inB[30] outS[30] latch2in60C
+Xlat[31] net@6 net@3 inA[31] inB[31] outS[31] latch2in60C
+Xlat[32] net@6 net@3 inA[32] inB[32] outS[32] latch2in60C
+Xlat[33] net@6 net@3 inA[33] inB[33] outS[33] latch2in60C
+Xlat[34] net@6 net@3 inA[34] inB[34] outS[34] latch2in60C
+Xlat[35] net@6 net@3 inA[35] inB[35] outS[35] latch2in60C
+Xlat[36] net@6 net@3 inA[36] inB[36] outS[36] latch2in60C
+Xlat[37] net@6 net@3 inA[37] inB[37] outS[37] latch2in60C
+Xwire90@1 dcl[A] net@6 wire90-668_2-layer_1-width_3
+Xwire90@2 dcl[B] net@3 wire90-668_2-layer_1-width_3
+.ENDS theDregister
+
+*** CELL: dockPartOD:dRegAll{sch}
+.SUBCKT dRegAll fire[L] fire[M] inA[10] inA[11] inA[12] inA[13] inA[14] 
++inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] 
++inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] 
++inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] inA[5] 
++inA[6] inA[7] inA[8] inA[9] inA[T] lit[10] lit[11] lit[12] lit[13] lit[14] 
++lit[15] lit[16] lit[17] lit[18] lit[19] lit[1] lit[2] lit[3] lit[4] lit[5] 
++lit[6] lit[7] lit[8] lit[9] lit[T] outS[10] outS[11] outS[12] outS[13] 
++outS[14] outS[15] outS[16] outS[17] outS[18] outS[19] outS[1] outS[20] 
++outS[21] outS[22] outS[23] outS[24] outS[25] outS[26] outS[27] outS[28] 
++outS[29] outS[2] outS[30] outS[31] outS[32] outS[33] outS[34] outS[35] 
++outS[36] outS[37] outS[3] outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] 
++outS[T] sel[long]
+XdataMuxA@0 lit[15] lit[16] lit[17] lit[18] lit[19] bk[15] bk[16] bk[17] 
++bk[18] bk[19] net@42[0] net@42[1] sel[long] net@50 dataMuxAll
+XtheDregi@0 fire[M] fire[L] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] 
++inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] 
++inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] 
++inA[32] inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] inA[5] inA[6] 
++inA[7] inA[8] inA[9] inA[T] lit[10] lit[11] lit[12] lit[13] lit[14] bk[15] 
++bk[16] bk[17] bk[18] bk[19] lit[1] lit[2] lit[3] lit[4] lit[5] lit[6] lit[7] 
++lit[8] lit[9] lit[T] outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] 
++outS[16] outS[17] outS[18] outS[19] outS[1] outS[20] outS[21] outS[22] 
++outS[23] outS[24] outS[25] outS[26] outS[27] outS[28] outS[29] outS[2] 
++outS[30] outS[31] outS[32] outS[33] outS[34] outS[35] outS[36] outS[37] 
++outS[3] outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] outS[T] net@42[0] 
++net@42[1] net@50 theDregister
+.ENDS dRegAll
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_40 d g s
+MNMOSf@0 d g s gnd nch W='120*(1+ABN/sqrt(120*2))' L='2' 
++DELVTO='AVT0N/sqrt(120*2)'
+.ENDS NMOSx-X_40
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_40 d g s
+MPMOSf@0 d g s vdd pch W='240*(1+ABP/sqrt(240*2))' L='2'  
++DELVTO='AVT0P/sqrt(240*2)'
+.ENDS PMOSx-X_40
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_40 in out
+XNMOS@0 out in gnd NMOSx-X_40
+XPMOS@0 out in vdd PMOSx-X_40
+.ENDS inv-X_40
+
+*** CELL: redFour:nand2{sch}
+.SUBCKT nand2-X_10 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_10
+XPMOS@1 out inb vdd PMOSx-X_10
+Xnms2@0 out ina inb nms2-X_10
+.ENDS nand2-X_10
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-506_4-R_34_667m a b
+Ccap@0 gnd net@14 1.857f
+Ccap@1 gnd net@8 1.857f
+Ccap@2 gnd net@11 1.857f
+Rres@0 net@14 a 2.926
+Rres@1 net@11 net@14 5.852
+Rres@2 b net@8 2.926
+Rres@3 net@8 net@11 5.852
+.ENDS wire-C_0_011f-506_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-506_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-506_4-R_34_667m
+.ENDS wire90-506_4-layer_1-width_3
+
+*** CELL: countersL:cntShift{sch}
+.SUBCKT cntShift ctgLO myp1p myp2p sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] 
++sid[7] sid[8] sid[9] sin
+Xinv@0 ctgLO net@17 inv-X_10
+Xinv@3 net@98 myp1p inv-X_40
+Xinv@4 net@100 myp2p inv-X_40
+Xnand2@4 net@95 sid[2] net@99 nand2-X_10
+Xnand2@5 net@95 sid[3] net@97 nand2-X_10
+Xwire90@2 net@17 net@95 wire90-506_4-layer_1-width_3
+Xwire90@9 net@98 net@97 wire90-506_4-layer_1-width_3
+Xwire90@10 net@100 net@99 wire90-506_4-layer_1-width_3
+.ENDS cntShift
+
+*** CELL: redFour:nand2{sch}
+.SUBCKT nand2-X_5 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_5
+XPMOS@1 out inb vdd PMOSx-X_5
+Xnms2@0 out ina inb nms2-X_5
+.ENDS nand2-X_5
+
+*** CELL: countersL:cntFreq{sch}
+.SUBCKT cntFreq count ctgLO fin fout myFin
+Xinv@0 ctgLO net@17 inv-X_10
+Xinv@1 count ctgLO inv-X_40
+Xnand2@0 net@18 myFin net@72 nand2-X_5
+Xnand2@1 ctgLO fin net@33 nand2-X_5
+Xnand2_sy@0 net@34 net@39 fout nand2_sy-X_20
+Xwire90@2 net@17 net@18 wire90-506_4-layer_1-width_3
+Xwire90@4 net@34 net@33 wire90-506_4-layer_1-width_3
+Xwire90@5 net@39 net@72 wire90-506_4-layer_1-width_3
+.ENDS cntFreq
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_5 d g s
+MNMOSf@0 d g s gnd nch W='15*(1+ABN/sqrt(15*2))' L='2' 
++DELVTO='AVT0N/sqrt(15*2)'
+.ENDS NMOSx-X_5
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_5 in out
+XNMOS@0 out in gnd NMOSx-X_5
+XPMOS@0 out in vdd PMOSx-X_5
+.ENDS inv-X_5
+
+*** CELL: latchesK:latch2in10A{sch}
+.SUBCKT latch2in10A hcl[A] hcl[B] inA[1] inB[1] out[1]
+Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF
+XinvLT@1 net@16 out[1] inv-X_10
+Xwire90@1 dataBar net@16 wire90-242_1-layer_1-width_3
+.ENDS latch2in10A
+
+*** CELL: redFour:pms2{sch}
+.SUBCKT pms2-X_2_5 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_5
+XPMOS@1 d g2 net@2 PMOSx-X_5
+.ENDS pms2-X_2_5
+
+*** CELL: redFour:pms2_sy{sch}
+.SUBCKT pms2_sy-X_5 d g g2
+Xpms2@0 d g g2 pms2-X_2_5
+Xpms2@1 d g2 g pms2-X_2_5
+.ENDS pms2_sy-X_5
+
+*** CELL: redFour:nor2_sy{sch}
+.SUBCKT nor2_sy-X_5 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_5
+XNMOS@1 out ina gnd NMOSx-X_5
+Xpms2_sy@0 out ina inb pms2_sy-X_5
+.ENDS nor2_sy-X_5
+
+*** CELL: redFour:nor2n_sy{sch}
+.SUBCKT nor2n_sy-X_5 ina inb out
+Xnor2@0 ina inb out nor2_sy-X_5
+.ENDS nor2n_sy-X_5
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-214_2-R_34_667m a b
+Ccap@0 gnd net@14 0.785f
+Ccap@1 gnd net@8 0.785f
+Ccap@2 gnd net@11 0.785f
+Rres@0 net@14 a 1.238
+Rres@1 net@11 net@14 2.475
+Rres@2 b net@8 1.238
+Rres@3 net@8 net@11 2.475
+.ENDS wire-C_0_011f-214_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-214_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-214_2-R_34_667m
+.ENDS wire90-214_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-413_4-R_34_667m a b
+Ccap@0 gnd net@14 1.516f
+Ccap@1 gnd net@8 1.516f
+Ccap@2 gnd net@11 1.516f
+Rres@0 net@14 a 2.389
+Rres@1 net@11 net@14 4.777
+Rres@2 b net@8 2.389
+Rres@3 net@8 net@11 4.777
+.ENDS wire-C_0_011f-413_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-413_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-413_4-R_34_667m
+.ENDS wire90-413_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-231_2-R_34_667m a b
+Ccap@0 gnd net@14 0.848f
+Ccap@1 gnd net@8 0.848f
+Ccap@2 gnd net@11 0.848f
+Rres@0 net@14 a 1.336
+Rres@1 net@11 net@14 2.672
+Rres@2 b net@8 1.336
+Rres@3 net@8 net@11 2.672
+.ENDS wire-C_0_011f-231_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-231_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-231_2-R_34_667m
+.ENDS wire90-231_2-layer_1-width_3
+
+*** CELL: countersL:cntScnOne{sch}
+.SUBCKT cntScnOne cin ctgLO out p1p p2p sin
+Xinv@0 out net@14 inv-X_5
+Xlatch2in@0 cB p1p net@3 net@3 out latch2in10A
+Xlatch2in@1 cA p2p net@15 sin net@6 latch2in10A
+Xnor2n_sy@0 ctgLO cB net@20 nor2n_sy-X_5
+Xnor2n_sy@2 ctgLO cin net@25 nor2n_sy-X_5
+Xwire90@0 net@15 net@14 wire90-214_2-layer_1-width_3
+Xwire90@1 net@6 net@3 wire90-506_4-layer_1-width_3
+Xwire90@2 net@20 cA wire90-413_4-layer_1-width_3
+Xwire90@3 net@25 cB wire90-231_2-layer_1-width_3
+.ENDS cntScnOne
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-668_5-R_34_667m a b
+Ccap@0 gnd net@14 2.451f
+Ccap@1 gnd net@8 2.451f
+Ccap@2 gnd net@11 2.451f
+Rres@0 net@14 a 3.862
+Rres@1 net@11 net@14 7.725
+Rres@2 b net@8 3.862
+Rres@3 net@8 net@11 7.725
+.ENDS wire-C_0_011f-668_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-668_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-668_5-R_34_667m
+.ENDS wire90-668_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-680_5-R_34_667m a b
+Ccap@0 gnd net@14 2.495f
+Ccap@1 gnd net@8 2.495f
+Ccap@2 gnd net@11 2.495f
+Rres@0 net@14 a 3.932
+Rres@1 net@11 net@14 7.864
+Rres@2 b net@8 3.932
+Rres@3 net@8 net@11 7.864
+.ENDS wire-C_0_011f-680_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-680_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-680_5-R_34_667m
+.ENDS wire90-680_5-layer_1-width_3
+
+*** CELL: countersL:cntScnThree{sch}
+.SUBCKT cntScnThree cin ctgLO out p1p p2p sin
+XcntScnOn@0 net@88 ctgLO out p1p p2p net@88 cntScnOne
+XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne
+XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne
+Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3
+Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3
+.ENDS cntScnThree
+
+*** CELL: countersL:cntScnNine{sch}
+.SUBCKT cntScnNine cin ctgLO out p1p p2p sin
+XcntScnTh@0 net@60 ctgLO out p1p p2p net@60 cntScnThree
+XcntScnTh@1 cin ctgLO net@43 p1p p2p sin cntScnThree
+XcntScnTh@2 net@61 ctgLO net@46 p1p p2p net@61 cntScnThree
+Xwire90@5 net@43 net@61 wire90-668_5-layer_1-width_3
+Xwire90@6 net@46 net@60 wire90-668_5-layer_1-width_3
+.ENDS cntScnNine
+
+*** CELL: countersL:cntScnFour{sch}
+.SUBCKT cntScnFour cin ctgLO out p1p p2p sin
+XcntScnOn@0 net@88 ctgLO net@40 p1p p2p net@88 cntScnOne
+XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne
+XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne
+XcntScnOn@3 net@94 ctgLO out p1p p2p net@94 cntScnOne
+Xwire90@4 net@40 net@94 wire90-668_5-layer_1-width_3
+Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3
+Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3
+.ENDS cntScnFour
+
+*** CELL: countersL:cntScnTwelve{sch}
+.SUBCKT cntScnTwelve cin ctgLO out p1p p2p sin
+XcntScnFo@0 net@60 ctgLO out p1p p2p net@60 cntScnFour
+XcntScnFo@1 cin ctgLO net@43 p1p p2p sin cntScnFour
+XcntScnFo@2 net@61 ctgLO net@46 p1p p2p net@61 cntScnFour
+Xwire90@5 net@43 net@61 wire90-668_5-layer_1-width_3
+Xwire90@6 net@46 net@60 wire90-668_5-layer_1-width_3
+.ENDS cntScnTwelve
+
+*** CELL: countersL:instructionCount{sch}
+.SUBCKT instructionCount cin count fin fout sid[1] sid[2] sid[3] sid[4] 
++sid[5] sid[6] sid[7] sid[8] sid[9] sod[1]
+XcntContr@0 ctgLO myp1p myp2p sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] 
++sid[7] sid[8] sid[9] sod[1] cntShift
+XcntFreq@0 count ctgLO fin fout net@54 cntFreq
+XcntScnNi@2 net@42 ctgLO sod[1] myp1p myp2p net@42 cntScnNine
+XcntScnOn@2 cin ctgLO net@1 myp1p myp2p sid[1] cntScnOne
+XcntScnTw@3 net@2 ctgLO net@3 myp1p myp2p net@2 cntScnTwelve
+XcntScnTw@4 net@54 ctgLO net@78 myp1p myp2p net@54 cntScnTwelve
+Xwire90@0 net@1 net@2 wire90-506_4-layer_1-width_3
+Xwire90@1 net@3 net@54 wire90-506_4-layer_1-width_3
+Xwire90@2 net@78 net@42 wire90-506_4-layer_1-width_3
+.ENDS instructionCount
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-428_5-R_34_667m a b
+Ccap@0 gnd net@14 1.571f
+Ccap@1 gnd net@8 1.571f
+Ccap@2 gnd net@11 1.571f
+Rres@0 net@14 a 2.476
+Rres@1 net@11 net@14 4.952
+Rres@2 b net@8 2.476
+Rres@3 net@8 net@11 4.952
+.ENDS wire-C_0_011f-428_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-428_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-428_5-R_34_667m
+.ENDS wire90-428_5-layer_1-width_3
+
+*** CELL: latchesK:latch1in30A{sch}
+.SUBCKT latch1in30A hcl in[1] out[1]
+Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF
+XinvLT@0 net@18 out[1] inv-X_30
+Xwire90@0 net@19 net@18 wire90-428_5-layer_1-width_3
+.ENDS latch1in30A
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5118_8-R_34_667m a b
+Ccap@0 gnd net@14 18.769f
+Ccap@1 gnd net@8 18.769f
+Ccap@2 gnd net@11 18.769f
+Rres@0 net@14 a 29.575
+Rres@1 net@11 net@14 59.151
+Rres@2 b net@8 29.575
+Rres@3 net@8 net@11 59.151
+.ENDS wire-C_0_011f-5118_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5118_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-5118_8-R_34_667m
+.ENDS wire90-5118_8-layer_1-width_3
+
+*** CELL: registersL:all1in52weak{sch}
+.SUBCKT all1in52weak ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] 
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
++aout[7] aout[8] aout[9] aout[T] fire in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
+XdataDriv@0 ain[T] fire net@81 dataDriver70
+XhiL[1] net@41 in[1] out[1] latch1in30A
+XhiL[2] net@41 in[2] out[2] latch1in30A
+XhiL[3] net@41 in[3] out[3] latch1in30A
+XhiL[4] net@41 in[4] out[4] latch1in30A
+XhiL[5] net@41 in[5] out[5] latch1in30A
+XhiL[6] net@41 in[6] out[6] latch1in30A
+XhiL[7] net@41 in[7] out[7] latch1in30A
+XhiL[8] net@41 in[8] out[8] latch1in30A
+XhiL[9] net@41 in[9] out[9] latch1in30A
+XhiL[10] net@41 in[10] out[10] latch1in30A
+XhiL[11] net@41 in[11] out[11] latch1in30A
+XhiL[12] net@41 in[12] out[12] latch1in30A
+XhiL[13] net@41 in[13] out[13] latch1in30A
+XhiL[14] net@41 in[14] out[14] latch1in30A
+XhiL[15] net@41 in[15] out[15] latch1in30A
+XhiL[16] net@41 in[16] out[16] latch1in30A
+XhiL[17] net@41 in[17] out[17] latch1in30A
+XhiL[18] net@41 in[18] out[18] latch1in30A
+XhiL[19] net@41 in[19] out[19] latch1in30A
+XhiL[20] net@41 in[20] out[20] latch1in30A
+XhiL[21] net@41 in[21] out[21] latch1in30A
+XhiL[22] net@41 in[22] out[22] latch1in30A
+XhiL[23] net@41 in[23] out[23] latch1in30A
+XhiL[24] net@41 in[24] out[24] latch1in30A
+XhiL[25] net@41 in[25] out[25] latch1in30A
+XhiL[26] net@41 in[26] out[26] latch1in30A
+XhiL[27] net@41 in[27] out[27] latch1in30A
+XhiL[28] net@41 in[28] out[28] latch1in30A
+XhiL[29] net@41 in[29] out[29] latch1in30A
+XhiL[30] net@41 in[30] out[30] latch1in30A
+XhiL[31] net@41 in[31] out[31] latch1in30A
+XhiL[32] net@41 in[32] out[32] latch1in30A
+XhiL[33] net@41 in[33] out[33] latch1in30A
+XhiL[34] net@41 in[34] out[34] latch1in30A
+XhiL[35] net@41 in[35] out[35] latch1in30A
+XhiL[36] net@41 in[36] out[36] latch1in30A
+XhiL[37] net@41 in[37] out[37] latch1in30A
+Xlat[1] fire ain[1] aout[1] latch1in30A
+Xlat[2] fire ain[2] aout[2] latch1in30A
+Xlat[3] fire ain[3] aout[3] latch1in30A
+Xlat[4] fire ain[4] aout[4] latch1in30A
+Xlat[5] fire ain[5] aout[5] latch1in30A
+Xlat[6] fire ain[6] aout[6] latch1in30A
+Xlat[7] fire ain[7] aout[7] latch1in30A
+Xlat[8] fire ain[8] aout[8] latch1in30A
+Xlat[9] fire ain[9] aout[9] latch1in30A
+Xlat[10] fire ain[10] aout[10] latch1in30A
+Xlat[11] fire ain[11] aout[11] latch1in30A
+Xlat[12] fire ain[12] aout[12] latch1in30A
+Xlat[13] fire ain[13] aout[13] latch1in30A
+Xlat[14] fire ain[14] aout[14] latch1in30A
+Xlatch1in@0 fire ain[T] aout[T] latch1in30A
+Xwire90@0 net@81 net@41 wire90-5118_8-layer_1-width_3
+.ENDS all1in52weak
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_25 d g s
+MPMOSf@0 d g s vdd pch W='150*(1+ABP/sqrt(150*2))' L='2'  
++DELVTO='AVT0P/sqrt(150*2)'
+.ENDS PMOSx-X_25
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_50 d g s
+MNMOSf@0 d g s gnd nch W='150*(1+ABN/sqrt(150*2))' L='2' 
++DELVTO='AVT0N/sqrt(150*2)'
+.ENDS NMOSx-X_50
+
+*** CELL: redFour:nms2{sch}
+.SUBCKT nms2-X_25 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_50
+XNMOS@1 net@0 g gnd NMOSx-X_50
+.ENDS nms2-X_25
+
+*** CELL: redFour:nand2{sch}
+.SUBCKT nand2-X_25 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_25
+XPMOS@1 out inb vdd PMOSx-X_25
+Xnms2@0 out ina inb nms2-X_25
+.ENDS nand2-X_25
+
+*** CELL: arbiterK:half2inArb{sch}
+.SUBCKT half2inArb cross grant[B] inA req[B]
+XNMOSx@0 vdd req[B] grant[B] PMOSx-X_10
+XPMOSx@0 cross inA grant[B] NMOSx-X_10
+Xnor2n@0 inA req[B] cross nand2-X_25
+.ENDS half2inArb
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-830_7-R_34_667m a b
+Ccap@0 gnd net@14 3.046f
+Ccap@1 gnd net@8 3.046f
+Ccap@2 gnd net@11 3.046f
+Rres@0 net@14 a 4.8
+Rres@1 net@11 net@14 9.599
+Rres@2 b net@8 4.8
+Rres@3 net@8 net@11 9.599
+.ENDS wire-C_0_011f-830_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-830_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-830_7-R_34_667m
+.ENDS wire90-830_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-834_6-R_34_667m a b
+Ccap@0 gnd net@14 3.06f
+Ccap@1 gnd net@8 3.06f
+Ccap@2 gnd net@11 3.06f
+Rres@0 net@14 a 4.822
+Rres@1 net@11 net@14 9.644
+Rres@2 b net@8 4.822
+Rres@3 net@8 net@11 9.644
+.ENDS wire-C_0_011f-834_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-834_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-834_6-R_34_667m
+.ENDS wire90-834_6-layer_1-width_3
+
+*** CELL: arbiterK:arbiter2{sch}
+.SUBCKT arbiter2 grant[A] grant[B] req[A] req[B]
+XhalfArb@2 net@12 grant[A] net@5 req[A] half2inArb
+XhalfArb@3 net@13 grant[B] net@8 req[B] half2inArb
+Xwire90@0 net@12 net@8 wire90-830_7-layer_1-width_3
+Xwire90@1 net@5 net@13 wire90-834_6-layer_1-width_3
+.ENDS arbiter2
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_15 d g s
+MPMOSf@0 d g s vdd pch W='90*(1+ABP/sqrt(90*2))' L='2'  
++DELVTO='AVT0P/sqrt(90*2)'
+.ENDS PMOSx-X_15
+
+*** CELL: redFour:nand2LT_sy{sch}
+.SUBCKT nand2LT_sy-X_30 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_15
+XPMOS@1 out inb vdd PMOSx-X_15
+Xnms2_sy@0 out ina inb nms2_sy-X_30
+.ENDS nand2LT_sy-X_30
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-399_2-R_34_667m a b
+Ccap@0 gnd net@14 1.464f
+Ccap@1 gnd net@8 1.464f
+Ccap@2 gnd net@11 1.464f
+Rres@0 net@14 a 2.306
+Rres@1 net@11 net@14 4.613
+Rres@2 b net@8 2.306
+Rres@3 net@8 net@11 4.613
+.ENDS wire-C_0_011f-399_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-399_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-399_2-R_34_667m
+.ENDS wire90-399_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1013_8-R_34_667m a b
+Ccap@0 gnd net@14 3.717f
+Ccap@1 gnd net@8 3.717f
+Ccap@2 gnd net@11 3.717f
+Rres@0 net@14 a 5.858
+Rres@1 net@11 net@14 11.715
+Rres@2 b net@8 5.858
+Rres@3 net@8 net@11 11.715
+.ENDS wire-C_0_011f-1013_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1013_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1013_8-R_34_667m
+.ENDS wire90-1013_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-468_3-R_34_667m a b
+Ccap@0 gnd net@14 1.717f
+Ccap@1 gnd net@8 1.717f
+Ccap@2 gnd net@11 1.717f
+Rres@0 net@14 a 2.706
+Rres@1 net@11 net@14 5.411
+Rres@2 b net@8 2.706
+Rres@3 net@8 net@11 5.411
+.ENDS wire-C_0_011f-468_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-468_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-468_3-R_34_667m
+.ENDS wire90-468_3-layer_1-width_3
+
+*** CELL: centersJ:ctrAND2in100LT{sch}
+.SUBCKT ctrAND2in100LT inA inB out
+Xinv@8 inB net@135 inv-X_10
+Xinv@9 inA net@139 inv-X_10
+Xinv@10 net@146 out inv-X_100
+Xnand2LT_@0 net@140 net@136 net@144 nand2LT_sy-X_30
+Xwire90@4 net@135 net@136 wire90-399_2-layer_1-width_3
+Xwire90@5 net@144 net@146 wire90-1013_8-layer_1-width_3
+Xwire90@6 net@139 net@140 wire90-468_3-layer_1-width_3
+.ENDS ctrAND2in100LT
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_3_999 d g s
+MPMOSf@0 d g s vdd pch W='23.994*(1+ABP/sqrt(23.994*2))' L='2'  
++DELVTO='AVT0P/sqrt(23.994*2)'
+.ENDS PMOSx-X_3_999
+
+*** CELL: redFour:pms3{sch}
+.SUBCKT pms3-X_1_333 d g g2 g3
+XPMOS@0 d g3 net@2 PMOSx-X_3_999
+XPMOS@1 net@2 g2 net@5 PMOSx-X_3_999
+XPMOS@2 net@5 g vdd PMOSx-X_3_999
+.ENDS pms3-X_1_333
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-243_6-R_34_667m a b
+Ccap@0 gnd net@14 0.893f
+Ccap@1 gnd net@8 0.893f
+Ccap@2 gnd net@11 0.893f
+Rres@0 net@14 a 1.407
+Rres@1 net@11 net@14 2.815
+Rres@2 b net@8 1.407
+Rres@3 net@8 net@11 2.815
+.ENDS wire-C_0_011f-243_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-243_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-243_6-R_34_667m
+.ENDS wire90-243_6-layer_1-width_3
+
+*** CELL: driversL:predDri20wMC{sch}
+.SUBCKT predDri20wMC in mc pred
+XNMOSx@0 pred in gnd NMOSx-X_20
+XNMOSx@1 pred mc gnd NMOSx-X_4
+Xinv@0 pred net@145 inv-X_4
+Xpms3@0 pred net@177 in mc pms3-X_1_333
+Xwire90@0 net@177 net@145 wire90-243_6-layer_1-width_3
+.ENDS predDri20wMC
+
+*** CELL: redFour:invLT{sch}
+.SUBCKT invLT-X_10 in out
+XNMOS@0 out in gnd NMOSx-X_20
+XPMOS@0 out in vdd PMOSx-X_10
+.ENDS invLT-X_10
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-282-R_34_667m a b
+Ccap@0 gnd net@14 1.034f
+Ccap@1 gnd net@8 1.034f
+Ccap@2 gnd net@11 1.034f
+Rres@0 net@14 a 1.629
+Rres@1 net@11 net@14 3.259
+Rres@2 b net@8 1.629
+Rres@3 net@8 net@11 3.259
+.ENDS wire-C_0_011f-282-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-282-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-282-R_34_667m
+.ENDS wire90-282-layer_1-width_3
+
+*** CELL: latchesK:latch1in10A{sch}
+.SUBCKT latch1in10A hcl in[1] out[1]
+Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF
+XinvLT@0 net@18 out[1] invLT-X_10
+Xwire90@0 net@19 net@18 wire90-282-layer_1-width_3
+.ENDS latch1in10A
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-311_7-R_34_667m a b
+Ccap@0 gnd net@14 1.143f
+Ccap@1 gnd net@8 1.143f
+Ccap@2 gnd net@11 1.143f
+Rres@0 net@14 a 1.801
+Rres@1 net@11 net@14 3.602
+Rres@2 b net@8 1.801
+Rres@3 net@8 net@11 3.602
+.ENDS wire-C_0_011f-311_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-311_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-311_7-R_34_667m
+.ENDS wire90-311_7-layer_1-width_3
+
+*** CELL: latchesK:latch2in10Alo{sch}
+.SUBCKT latch2in10Alo hcl[A] hcl[B] inA[1] inB[1] out[1]
+Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF
+XinvLT@0 net@15 out[1] invLT-X_10
+Xwire90@0 dataBar net@15 wire90-311_7-layer_1-width_3
+.ENDS latch2in10Alo
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-218_4-R_34_667m a b
+Ccap@0 gnd net@14 0.801f
+Ccap@1 gnd net@8 0.801f
+Ccap@2 gnd net@11 0.801f
+Rres@0 net@14 a 1.262
+Rres@1 net@11 net@14 2.524
+Rres@2 b net@8 1.262
+Rres@3 net@8 net@11 2.524
+.ENDS wire-C_0_011f-218_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-218_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-218_4-R_34_667m
+.ENDS wire90-218_4-layer_1-width_3
+
+*** CELL: scanJ:scanCellE{sch}
+.SUBCKT scanCellE dIn[1] p1p p2p rd sin sout
+Xlatch1in@0 p2p sin net@2 latch1in10A
+Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo
+Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3
+.ENDS scanCellE
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-297_6-R_34_667m a b
+Ccap@0 gnd net@14 1.091f
+Ccap@1 gnd net@8 1.091f
+Ccap@2 gnd net@11 1.091f
+Rres@0 net@14 a 1.719
+Rres@1 net@11 net@14 3.439
+Rres@2 b net@8 1.719
+Rres@3 net@8 net@11 3.439
+.ENDS wire-C_0_011f-297_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-297_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-297_6-R_34_667m
+.ENDS wire90-297_6-layer_1-width_3
+
+*** CELL: scanJ:scanEx2vert{sch}
+.SUBCKT scanEx2vert dIn[1] dIn[2] mc sir[1] sir[2] sir[3] sir[4] sir[5] 
++sir[6] sir[7] sir[8] sor[1]
+XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanCellE
+XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 sor[1] scanCellE
+Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3
+.ENDS scanEx2vert
+
+*** CELL: latchPartsK:latchPointFmcHI{sch}
+.SUBCKT latchPointFmcHI mc x[F] x[T]
+XPMOSx@0 gnd mc x[T] NMOSx-X_3
+XPMOSx@1 vdd mc x[F] NMOSx-X_6
+.ENDS latchPointFmcHI
+
+*** CELL: latchesK:raw2inLatchFmc{sch}
+.SUBCKT raw2inLatchFmc hcl inA[1] mc out[F]
+XlatchKee@0 out[F] net@63 latchKeep
+XlatchPoi@0 hcl inA[1] out[F] net@45 latchPointF
+XlatchPoi@1 mc out[F] net@45 latchPointFmcHI
+Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3
+.ENDS raw2inLatchFmc
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-283-R_34_667m a b
+Ccap@0 gnd net@14 1.038f
+Ccap@1 gnd net@8 1.038f
+Ccap@2 gnd net@11 1.038f
+Rres@0 net@14 a 1.635
+Rres@1 net@11 net@14 3.27
+Rres@2 b net@8 1.635
+Rres@3 net@8 net@11 3.27
+.ENDS wire-C_0_011f-283-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-283-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-283-R_34_667m
+.ENDS wire90-283-layer_1-width_3
+
+*** CELL: latchesK:latch2in10Alomc{sch}
+.SUBCKT latch2in10Alomc hcl inA[1] mc out[1]
+Xhi2inLat@0 hcl inA[1] mc dataBar raw2inLatchFmc
+XinvLT@0 net@20 out[1] invLT-X_10
+Xwire90@0 dataBar net@20 wire90-283-layer_1-width_3
+.ENDS latch2in10Alomc
+
+*** CELL: scanJ:scanCellF{sch}
+.SUBCKT scanCellF dout[1] mc p1p p2p rd sin sout wr
+Xlatch1in@0 p2p sin net@2 latch1in10A
+Xlatch2in@0 p1p rd net@10 dout[1] sout latch2in10Alo
+Xlatch2in@1 wr sout mc dout[1] latch2in10Alomc
+Xwire90@0 net@2 net@10 wire90-297_6-layer_1-width_3
+.ENDS scanCellF
+
+*** CELL: scanJ:scanFx1vert{sch}
+.SUBCKT scanFx1vert dout[1] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
++sic[8] sic[9] soc[1]
+XscanCell@2 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] soc[1] sic[4] 
++scanCellF
+.ENDS scanFx1vert
+
+*** CELL: scanJ:scanFx3hor{sch}
+.SUBCKT scanFx3hor dout[1] dout[2] dout[3] sic[1] sic[2] sic[3] sic[4] sic[5] 
++sic[6] sic[7] sic[8] sic[9] soc[1]
+XscanCell@1 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 net@31 sic[4] 
++scanCellF
+XscanCell@2 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4] 
++scanCellF
+XscanCell@3 dout[3] sic[9] sic[3] sic[2] sic[5] net@33 soc[1] sic[4] 
++scanCellF
+Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3
+Xwire90@1 net@31 net@33 wire90-297_6-layer_1-width_3
+.ENDS scanFx3hor
+
+*** CELL: redFour:nms2{sch}
+.SUBCKT nms2-X_2 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_4
+XNMOS@1 net@0 g gnd NMOSx-X_4
+.ENDS nms2-X_2
+
+*** CELL: redFour:nms2{sch}
+.SUBCKT nms2-X_2_5 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_5
+XNMOS@1 net@0 g gnd NMOSx-X_5
+.ENDS nms2-X_2_5
+
+*** CELL: redFour:nms2_sy{sch}
+.SUBCKT nms2_sy-X_5 d g g2
+Xnms2@0 d g g2 nms2-X_2_5
+Xnms2@1 d g2 g nms2-X_2_5
+.ENDS nms2_sy-X_5
+
+*** CELL: redFour:nand2_sy{sch}
+.SUBCKT nand2_sy-X_5 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_5
+XPMOS@1 out ina vdd PMOSx-X_5
+Xnms2_sy@0 out ina inb nms2_sy-X_5
+.ENDS nand2_sy-X_5
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-309-R_34_667m a b
+Ccap@0 gnd net@14 1.133f
+Ccap@1 gnd net@8 1.133f
+Ccap@2 gnd net@11 1.133f
+Rres@0 net@14 a 1.785
+Rres@1 net@11 net@14 3.571
+Rres@2 b net@8 1.785
+Rres@3 net@8 net@11 3.571
+.ENDS wire-C_0_011f-309-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-309-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-309-R_34_667m
+.ENDS wire90-309-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-114_9-R_34_667m a b
+Ccap@0 gnd net@14 0.421f
+Ccap@1 gnd net@8 0.421f
+Ccap@2 gnd net@11 0.421f
+Rres@0 net@14 a 0.664
+Rres@1 net@11 net@14 1.328
+Rres@2 b net@8 0.664
+Rres@3 net@8 net@11 1.328
+.ENDS wire-C_0_011f-114_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-114_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-114_9-R_34_667m
+.ENDS wire90-114_9-layer_1-width_3
+
+*** CELL: driversL:sucANDdri20{sch}
+.SUBCKT sucANDdri20 inA inB succ
+XPMOSx@0 succ net@51 vdd PMOSx-X_20
+Xinv@0 succ net@71 inv-X_4
+Xnms2@0 succ net@75 net@51 nms2-X_2
+Xnor2_sy@0 inA inB net@67 nand2_sy-X_5
+Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3
+Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3
+.ENDS sucANDdri20
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-310_8-R_34_667m a b
+Ccap@0 gnd net@14 1.14f
+Ccap@1 gnd net@8 1.14f
+Ccap@2 gnd net@11 1.14f
+Rres@0 net@14 a 1.796
+Rres@1 net@11 net@14 3.591
+Rres@2 b net@8 1.796
+Rres@3 net@8 net@11 3.591
+.ENDS wire-C_0_011f-310_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-310_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-310_8-R_34_667m
+.ENDS wire90-310_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-925_7-R_34_667m a b
+Ccap@0 gnd net@14 3.394f
+Ccap@1 gnd net@8 3.394f
+Ccap@2 gnd net@11 3.394f
+Rres@0 net@14 a 5.348
+Rres@1 net@11 net@14 10.697
+Rres@2 b net@8 5.348
+Rres@3 net@8 net@11 10.697
+.ENDS wire-C_0_011f-925_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-925_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-925_7-R_34_667m
+.ENDS wire90-925_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-602_3-R_34_667m a b
+Ccap@0 gnd net@14 2.208f
+Ccap@1 gnd net@8 2.208f
+Ccap@2 gnd net@11 2.208f
+Rres@0 net@14 a 3.48
+Rres@1 net@11 net@14 6.96
+Rres@2 b net@8 3.48
+Rres@3 net@8 net@11 6.96
+.ENDS wire-C_0_011f-602_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-602_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-602_3-R_34_667m
+.ENDS wire90-602_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-236-R_34_667m a b
+Ccap@0 gnd net@14 0.865f
+Ccap@1 gnd net@8 0.865f
+Ccap@2 gnd net@11 0.865f
+Rres@0 net@14 a 1.364
+Rres@1 net@11 net@14 2.727
+Rres@2 b net@8 1.364
+Rres@3 net@8 net@11 2.727
+.ENDS wire-C_0_011f-236-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-236-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-236-R_34_667m
+.ENDS wire90-236-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-169_4-R_34_667m a b
+Ccap@0 gnd net@14 0.621f
+Ccap@1 gnd net@8 0.621f
+Ccap@2 gnd net@11 0.621f
+Rres@0 net@14 a 0.979
+Rres@1 net@11 net@14 1.958
+Rres@2 b net@8 0.979
+Rres@3 net@8 net@11 1.958
+.ENDS wire-C_0_011f-169_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-169_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-169_4-R_34_667m
+.ENDS wire90-169_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-661_2-R_34_667m a b
+Ccap@0 gnd net@14 2.424f
+Ccap@1 gnd net@8 2.424f
+Ccap@2 gnd net@11 2.424f
+Rres@0 net@14 a 3.82
+Rres@1 net@11 net@14 7.641
+Rres@2 b net@8 3.82
+Rres@3 net@8 net@11 7.641
+.ENDS wire-C_0_011f-661_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-661_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-661_2-R_34_667m
+.ENDS wire90-661_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-611_7-R_34_667m a b
+Ccap@0 gnd net@14 2.243f
+Ccap@1 gnd net@8 2.243f
+Ccap@2 gnd net@11 2.243f
+Rres@0 net@14 a 3.534
+Rres@1 net@11 net@14 7.069
+Rres@2 b net@8 3.534
+Rres@3 net@8 net@11 7.069
+.ENDS wire-C_0_011f-611_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-611_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-611_7-R_34_667m
+.ENDS wire90-611_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-706_1-R_34_667m a b
+Ccap@0 gnd net@14 2.589f
+Ccap@1 gnd net@8 2.589f
+Ccap@2 gnd net@11 2.589f
+Rres@0 net@14 a 4.08
+Rres@1 net@11 net@14 8.159
+Rres@2 b net@8 4.08
+Rres@3 net@8 net@11 8.159
+.ENDS wire-C_0_011f-706_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-706_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-706_1-R_34_667m
+.ENDS wire90-706_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-529_6-R_34_667m a b
+Ccap@0 gnd net@14 1.942f
+Ccap@1 gnd net@8 1.942f
+Ccap@2 gnd net@11 1.942f
+Rres@0 net@14 a 3.06
+Rres@1 net@11 net@14 6.12
+Rres@2 b net@8 3.06
+Rres@3 net@8 net@11 6.12
+.ENDS wire-C_0_011f-529_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-529_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-529_6-R_34_667m
+.ENDS wire90-529_6-layer_1-width_3
+
+*** CELL: gaspL:gaspDrain{sch}
+.SUBCKT gaspDrain dOut fire[A] pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] 
++sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] 
++sir[9] soc[1] sor[1] succ
+Xarbiter2@0 net@374 net@353 pred net@375 arbiter2
+XctrAND2i@2 net@241 succ fire[A] ctrAND2in100LT
+Xinv@0 net@357 net@409 inv-X_10
+Xinv@1 go net@360 inv-X_10
+Xinv@3 silent net@333 inv-X_10
+XpredDri2@0 fire[A] net@364 pred predDri20wMC
+XscanEx2v@1 pred stopped sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sor[1] scanEx2vert
+XscanFx1v@0 dOut net@468[8] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] 
++sic[9] soc[1] scanFx1vert
+XscanFx3h@0 net@467 net@447 net@466 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] 
++sic[7] sic[8] sic[9] net@468[8] scanFx3hor
+XsucANDdr@3 net@338 fire[A] succ sucANDdri20
+Xwire90@1 net@374 net@241 wire90-310_8-layer_1-width_3
+Xwire90@7 net@375 net@360 wire90-925_7-layer_1-width_3
+Xwire90@8 net@364 clear wire90-602_3-layer_1-width_3
+Xwire90@9 net@333 net@338 wire90-236-layer_1-width_3
+Xwire90@10 net@357 net@353 wire90-169_4-layer_1-width_3
+Xwire90@11 stopped net@409 wire90-661_2-layer_1-width_3
+Xwire90@12 net@466 clear wire90-611_7-layer_1-width_3
+Xwire90@13 net@447 silent wire90-706_1-layer_1-width_3
+Xwire90@14 net@467 go wire90-529_6-layer_1-width_3
+.ENDS gaspDrain
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5192-R_34_667m a b
+Ccap@0 gnd net@14 19.037f
+Ccap@1 gnd net@8 19.037f
+Ccap@2 gnd net@11 19.037f
+Rres@0 net@14 a 29.998
+Rres@1 net@11 net@14 59.996
+Rres@2 b net@8 29.998
+Rres@3 net@8 net@11 59.996
+.ENDS wire-C_0_011f-5192-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5192-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-5192-R_34_667m
+.ENDS wire90-5192-layer_1-width_3
+
+*** CELL: stagesL:drainStage{sch}
+.SUBCKT drainStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] 
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
++aout[7] aout[8] aout[9] aout[T] dOut fire in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] 
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] 
++sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ
+Xall1in52@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] 
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] 
++aout[8] aout[9] aout[T] net@2 in[10] in[11] in[12] in[13] in[14] in[15] 
++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] 
++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] 
++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] 
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] 
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] 
++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] 
++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] all1in52weak
+XgaspDrai@0 dOut fire pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
++sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] 
++soc[1] sor[1] succ gaspDrain
+Xwire90@0 fire net@2 wire90-5192-layer_1-width_3
+.ENDS drainStage
+
+*** CELL: latchGroupsK:latchWscan{sch}
+.SUBCKT latchWscan hcl in[1] out[1] p1p p2p rd sin sout wr
+Xhi2inLat@1 hcl wr in[1] sout out[1] latch2in60C
+XscanCell@2 out[1] p1p p2p rd sin sout scanCellE
+.ENDS latchWscan
+
+*** CELL: registersJ:addr1in14scan{sch}
+.SUBCKT addr1in14scan ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] aout[10] aout[11] aout[12] 
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] 
++aout[8] aout[9] fire p1p p2p rd sin sout wrA
+Xls[1] fire ain[1] aout[1] p1p p2p rd sin xin[2] wrA latchWscan
+Xls[2] fire ain[2] aout[2] p1p p2p rd xin[2] xin[3] wrA latchWscan
+Xls[3] fire ain[3] aout[3] p1p p2p rd xin[3] xin[4] wrA latchWscan
+Xls[4] fire ain[4] aout[4] p1p p2p rd xin[4] xin[5] wrA latchWscan
+Xls[5] fire ain[5] aout[5] p1p p2p rd xin[5] xin[6] wrA latchWscan
+Xls[6] fire ain[6] aout[6] p1p p2p rd xin[6] xin[7] wrA latchWscan
+Xls[7] fire ain[7] aout[7] p1p p2p rd xin[7] xin[8] wrA latchWscan
+Xls[8] fire ain[8] aout[8] p1p p2p rd xin[8] xin[9] wrA latchWscan
+Xls[9] fire ain[9] aout[9] p1p p2p rd xin[9] xin[10] wrA latchWscan
+Xls[10] fire ain[10] aout[10] p1p p2p rd xin[10] xin[11] wrA latchWscan
+Xls[11] fire ain[11] aout[11] p1p p2p rd xin[11] xin[12] wrA latchWscan
+Xls[12] fire ain[12] aout[12] p1p p2p rd xin[12] xin[13] wrA latchWscan
+Xls[13] fire ain[13] aout[13] p1p p2p rd xin[13] xin[14] wrA latchWscan
+Xls[14] fire ain[14] aout[14] p1p p2p rd xin[14] sout wrA latchWscan
+.ENDS addr1in14scan
+
+*** CELL: scanJ:scanTwinAmp{sch}
+.SUBCKT scanTwinAmp in[1] outA[1] outB[1]
+Xinv@0 net@2 outA[1] inv-X_20
+Xinv@1 in[1] net@1 inv-X_10
+Xinv@2 net@2 outB[1] inv-X_40
+Xwire90@0 net@1 net@2 wire90-947_7-layer_1-width_3
+.ENDS scanTwinAmp
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2534-R_34_667m a b
+Ccap@0 gnd net@14 9.291f
+Ccap@1 gnd net@8 9.291f
+Ccap@2 gnd net@11 9.291f
+Rres@0 net@14 a 14.641
+Rres@1 net@11 net@14 29.282
+Rres@2 b net@8 14.641
+Rres@3 net@8 net@11 29.282
+.ENDS wire-C_0_011f-2534-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2534-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2534-R_34_667m
+.ENDS wire90-2534-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-918_6-R_34_667m a b
+Ccap@0 gnd net@14 3.368f
+Ccap@1 gnd net@8 3.368f
+Ccap@2 gnd net@11 3.368f
+Rres@0 net@14 a 5.307
+Rres@1 net@11 net@14 10.615
+Rres@2 b net@8 5.307
+Rres@3 net@8 net@11 10.615
+.ENDS wire-C_0_011f-918_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-918_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-918_6-R_34_667m
+.ENDS wire90-918_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1177-R_34_667m a b
+Ccap@0 gnd net@14 4.316f
+Ccap@1 gnd net@8 4.316f
+Ccap@2 gnd net@11 4.316f
+Rres@0 net@14 a 6.8
+Rres@1 net@11 net@14 13.601
+Rres@2 b net@8 6.8
+Rres@3 net@8 net@11 13.601
+.ENDS wire-C_0_011f-1177-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1177-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1177-R_34_667m
+.ENDS wire90-1177-layer_1-width_3
+
+*** CELL: registersJ:data1in38scan{sch}
+.SUBCKT data1in38scan ain[T] aout[T] fire in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] p1p p2p rd 
++scanFromAddress scanToAddr sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] 
++sid[8] sid[9] sod[2] sod[3] sod[4] sod[5] wrA
+XdataDriv@0 ain[T] fire net@120 dataDriver70
+XdataDriv@1 net@115 net@137 wrD dataDriver70
+XdataDriv@2 xin[1] wrr wrA dataDriver70
+XlatchWsc@1 fire ain[T] aout[T] p1p p2p rd xin[38] scanToAddr wrA latchWscan
+Xls[1] net@124 in[1] out[1] p1p p2p rd xin[1] xin[2] wrD latchWscan
+Xls[2] net@124 in[2] out[2] p1p p2p rd xin[2] xin[3] wrD latchWscan
+Xls[3] net@124 in[3] out[3] p1p p2p rd xin[3] xin[4] wrD latchWscan
+Xls[4] net@124 in[4] out[4] p1p p2p rd xin[4] xin[5] wrD latchWscan
+Xls[5] net@124 in[5] out[5] p1p p2p rd xin[5] xin[6] wrD latchWscan
+Xls[6] net@124 in[6] out[6] p1p p2p rd xin[6] xin[7] wrD latchWscan
+Xls[7] net@124 in[7] out[7] p1p p2p rd xin[7] xin[8] wrD latchWscan
+Xls[8] net@124 in[8] out[8] p1p p2p rd xin[8] xin[9] wrD latchWscan
+Xls[9] net@124 in[9] out[9] p1p p2p rd xin[9] xin[10] wrD latchWscan
+Xls[10] net@124 in[10] out[10] p1p p2p rd xin[10] xin[11] wrD latchWscan
+Xls[11] net@124 in[11] out[11] p1p p2p rd xin[11] xin[12] wrD latchWscan
+Xls[12] net@124 in[12] out[12] p1p p2p rd xin[12] xin[13] wrD latchWscan
+Xls[13] net@124 in[13] out[13] p1p p2p rd xin[13] xin[14] wrD latchWscan
+Xls[14] net@124 in[14] out[14] p1p p2p rd xin[14] xin[15] wrD latchWscan
+Xls[15] net@124 in[15] out[15] p1p p2p rd xin[15] xin[16] wrD latchWscan
+Xls[16] net@124 in[16] out[16] p1p p2p rd xin[16] xin[17] wrD latchWscan
+Xls[17] net@124 in[17] out[17] p1p p2p rd xin[17] xin[18] wrD latchWscan
+Xls[18] net@124 in[18] out[18] p1p p2p rd xin[18] xin[19] wrD latchWscan
+Xls[19] net@124 in[19] out[19] p1p p2p rd xin[19] xin[20] wrD latchWscan
+Xls[20] net@124 in[20] out[20] p1p p2p rd xin[20] xin[21] wrD latchWscan
+Xls[21] net@124 in[21] out[21] p1p p2p rd xin[21] xin[22] wrD latchWscan
+Xls[22] net@124 in[22] out[22] p1p p2p rd xin[22] xin[23] wrD latchWscan
+Xls[23] net@124 in[23] out[23] p1p p2p rd xin[23] xin[24] wrD latchWscan
+Xls[24] net@124 in[24] out[24] p1p p2p rd xin[24] xin[25] wrD latchWscan
+Xls[25] net@124 in[25] out[25] p1p p2p rd xin[25] xin[26] wrD latchWscan
+Xls[26] net@124 in[26] out[26] p1p p2p rd xin[26] xin[27] wrD latchWscan
+Xls[27] net@124 in[27] out[27] p1p p2p rd xin[27] xin[28] wrD latchWscan
+Xls[28] net@124 in[28] out[28] p1p p2p rd xin[28] xin[29] wrD latchWscan
+Xls[29] net@124 in[29] out[29] p1p p2p rd xin[29] xin[30] wrD latchWscan
+Xls[30] net@124 in[30] out[30] p1p p2p rd xin[30] xin[31] wrD latchWscan
+Xls[31] net@124 in[31] out[31] p1p p2p rd xin[31] xin[32] wrD latchWscan
+Xls[32] net@124 in[32] out[32] p1p p2p rd xin[32] xin[33] wrD latchWscan
+Xls[33] net@124 in[33] out[33] p1p p2p rd xin[33] xin[34] wrD latchWscan
+Xls[34] net@124 in[34] out[34] p1p p2p rd xin[34] xin[35] wrD latchWscan
+Xls[35] net@124 in[35] out[35] p1p p2p rd xin[35] xin[36] wrD latchWscan
+Xls[36] net@124 in[36] out[36] p1p p2p rd xin[36] xin[37] wrD latchWscan
+Xls[37] net@124 in[37] out[37] p1p p2p rd xin[37] xin[38] wrD latchWscan
+Xsa[1] sid[2] sod[2] p2p scanTwinAmp
+Xsa[2] sid[3] sod[3] p1p scanTwinAmp
+Xsa[3] sid[4] sod[4] wrr scanTwinAmp
+Xsa[4] sid[5] sod[5] rd scanTwinAmp
+XscanCell@0 scanCell@0_dIn[1] p1p p2p rd sid[1] net@130 scanCellE
+XscanCell@1 scanCell@1_dIn[1] p1p p2p rd net@115 xin[1] scanCellE
+Xwire90@0 net@124 net@120 wire90-2534-layer_1-width_3
+Xwire90@2 net@124 net@120 wire90-2534-layer_1-width_3
+Xwire90@3 net@130 net@115 wire90-918_6-layer_1-width_3
+Xwire90@5 net@137 wrr wire90-1177-layer_1-width_3
+.ENDS data1in38scan
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2975_6-R_34_667m a b
+Ccap@0 gnd net@14 10.911f
+Ccap@1 gnd net@8 10.911f
+Ccap@2 gnd net@11 10.911f
+Rres@0 net@14 a 17.192
+Rres@1 net@11 net@14 34.385
+Rres@2 b net@8 17.192
+Rres@3 net@8 net@11 34.385
+.ENDS wire-C_0_011f-2975_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2975_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2975_6-R_34_667m
+.ENDS wire90-2975_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2989_9-R_34_667m a b
+Ccap@0 gnd net@14 10.963f
+Ccap@1 gnd net@8 10.963f
+Ccap@2 gnd net@11 10.963f
+Rres@0 net@14 a 17.275
+Rres@1 net@11 net@14 34.55
+Rres@2 b net@8 17.275
+Rres@3 net@8 net@11 34.55
+.ENDS wire-C_0_011f-2989_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2989_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2989_9-R_34_667m
+.ENDS wire90-2989_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-12168-R_34_667m a b
+Ccap@0 gnd net@14 44.616f
+Ccap@1 gnd net@8 44.616f
+Ccap@2 gnd net@11 44.616f
+Rres@0 net@14 a 70.304
+Rres@1 net@11 net@14 140.608
+Rres@2 b net@8 70.304
+Rres@3 net@8 net@11 140.608
+.ENDS wire-C_0_011f-12168-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-12168-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-12168-R_34_667m
+.ENDS wire90-12168-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-12492-R_34_667m a b
+Ccap@0 gnd net@14 45.804f
+Ccap@1 gnd net@8 45.804f
+Ccap@2 gnd net@11 45.804f
+Rres@0 net@14 a 72.176
+Rres@1 net@11 net@14 144.352
+Rres@2 b net@8 72.176
+Rres@3 net@8 net@11 144.352
+.ENDS wire-C_0_011f-12492-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-12492-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-12492-R_34_667m
+.ENDS wire90-12492-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3927_5-R_34_667m a b
+Ccap@0 gnd net@14 14.401f
+Ccap@1 gnd net@8 14.401f
+Ccap@2 gnd net@11 14.401f
+Rres@0 net@14 a 22.692
+Rres@1 net@11 net@14 45.384
+Rres@2 b net@8 22.692
+Rres@3 net@8 net@11 45.384
+.ENDS wire-C_0_011f-3927_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3927_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3927_5-R_34_667m
+.ENDS wire90-3927_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-11401_6-R_34_667m a b
+Ccap@0 gnd net@14 41.806f
+Ccap@1 gnd net@8 41.806f
+Ccap@2 gnd net@11 41.806f
+Rres@0 net@14 a 65.876
+Rres@1 net@11 net@14 131.752
+Rres@2 b net@8 65.876
+Rres@3 net@8 net@11 131.752
+.ENDS wire-C_0_011f-11401_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-11401_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-11401_6-R_34_667m
+.ENDS wire90-11401_6-layer_1-width_3
+
+*** CELL: registersJ:all1in52scan{sch}
+.SUBCKT all1in52scan ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] 
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
++aout[7] aout[8] aout[9] aout[T] fire in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] sid[1] 
++sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sod[1] sod[2] sod[3] 
++sod[4] sod[5]
+Xaddr1in1@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] aout[10] aout[11] aout[12] aout[13] 
++aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] 
++aout[9] fire p1p p2p rd net@4 net@26 wrA addr1in14scan
+Xdata1in3@0 ain[T] aout[T] fire in[10] in[11] in[12] in[13] in[14] in[15] 
++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] 
++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] 
++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] 
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] 
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] 
++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] 
++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] p1p p2p rd sod[1] 
++net@1 sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sod[2] 
++sod[3] sod[4] sod[5] wrA data1in38scan
+Xwire90@0 net@26 sod[1] wire90-2975_6-layer_1-width_3
+Xwire90@1 net@4 net@1 wire90-2989_9-layer_1-width_3
+Xwire90@2 wire90@2_a p2p wire90-12168-layer_1-width_3
+Xwire90@3 wire90@3_a p1p wire90-12492-layer_1-width_3
+Xwire90@4 wire90@4_a wrA wire90-3927_5-layer_1-width_3
+Xwire90@5 wire90@5_a rd wire90-11401_6-layer_1-width_3
+.ENDS all1in52scan
+
+*** CELL: redFour:pms2_sy{sch}
+.SUBCKT pms2_sy-X_10 d g g2
+Xpms2@0 d g g2 pms2-X_5
+Xpms2@1 d g2 g pms2-X_5
+.ENDS pms2_sy-X_10
+
+*** CELL: redFour:nor2HT_sy{sch}
+.SUBCKT nor2HT_sy-X_10 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_5
+XNMOS@1 out ina gnd NMOSx-X_5
+Xpms2_sy@0 out ina inb pms2_sy-X_10
+.ENDS nor2HT_sy-X_10
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-403-R_34_667m a b
+Ccap@0 gnd net@14 1.478f
+Ccap@1 gnd net@8 1.478f
+Ccap@2 gnd net@11 1.478f
+Rres@0 net@14 a 2.328
+Rres@1 net@11 net@14 4.657
+Rres@2 b net@8 2.328
+Rres@3 net@8 net@11 4.657
+.ENDS wire-C_0_011f-403-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-403-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-403-R_34_667m
+.ENDS wire90-403-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-959-R_34_667m a b
+Ccap@0 gnd net@14 3.516f
+Ccap@1 gnd net@8 3.516f
+Ccap@2 gnd net@11 3.516f
+Rres@0 net@14 a 5.541
+Rres@1 net@11 net@14 11.082
+Rres@2 b net@8 5.541
+Rres@3 net@8 net@11 11.082
+.ENDS wire-C_0_011f-959-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-959-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-959-R_34_667m
+.ENDS wire90-959-layer_1-width_3
+
+*** CELL: centersJ:ctrAND3in100HT{sch}
+.SUBCKT ctrAND3in100HT inA inB inC out
+Xinv@3 net@104 out inv-X_100
+Xinv@4 inC net@143 inv-X_10
+Xnand2_sy@0 net@131 net@137 net@134 nand2_sy-X_30
+Xnor2HT_s@0 inA inB net@130 nor2HT_sy-X_10
+Xwire90@0 net@130 net@131 wire90-403-layer_1-width_3
+Xwire90@4 net@134 net@104 wire90-959-layer_1-width_3
+Xwire90@5 net@143 net@137 wire90-403-layer_1-width_3
+.ENDS ctrAND3in100HT
+
+*** CELL: scanJ:scanFx2vert{sch}
+.SUBCKT scanFx2vert dout[1] dout[2] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] 
++sic[7] sic[8] sic[9] soc[1]
+XscanCell@1 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 soc[1] sic[4] 
++scanCellF
+XscanCell@2 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4] 
++scanCellF
+Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3
+.ENDS scanFx2vert
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1001_8-R_34_667m a b
+Ccap@0 gnd net@14 3.673f
+Ccap@1 gnd net@8 3.673f
+Ccap@2 gnd net@11 3.673f
+Rres@0 net@14 a 5.788
+Rres@1 net@11 net@14 11.576
+Rres@2 b net@8 5.788
+Rres@3 net@8 net@11 11.576
+.ENDS wire-C_0_011f-1001_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1001_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1001_8-R_34_667m
+.ENDS wire90-1001_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-209-R_34_667m a b
+Ccap@0 gnd net@14 0.766f
+Ccap@1 gnd net@8 0.766f
+Ccap@2 gnd net@11 0.766f
+Rres@0 net@14 a 1.208
+Rres@1 net@11 net@14 2.415
+Rres@2 b net@8 1.208
+Rres@3 net@8 net@11 2.415
+.ENDS wire-C_0_011f-209-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-209-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-209-R_34_667m
+.ENDS wire90-209-layer_1-width_3
+
+*** CELL: driversL:sucORdri20{sch}
+.SUBCKT sucORdri20 inA inB succ
+XPMOSx@0 succ net@51 vdd PMOSx-X_20
+Xinv@0 succ net@71 inv-X_4
+Xnms2@0 succ net@73 net@51 nms2-X_2
+Xnor2_sy@0 inA inB net@67 nor2_sy-X_5
+Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3
+Xwire90@1 net@73 net@71 wire90-209-layer_1-width_3
+.ENDS sucORdri20
+
+*** CELL: gaspL:gaspFill{sch}
+.SUBCKT gaspFill fire pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
++sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] 
++soc[1] sor[1] succ
+XctrAND3i@0 net@241 succ fire fire[B] ctrAND3in100HT
+XctrAND3i@1 net@454 succ net@541 fire ctrAND3in100HT
+Xinv@0 pred net@533 inv-X_5
+Xinv@1 net@465 net@537 inv-X_5
+XpredDri2@0 fire sir[9] pred predDri20wMC
+XscanEx2v@2 pred net@465 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sor[1] scanEx2vert
+XscanFx2v@0 block fill sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
++sic[8] sic[9] soc[1] scanFx2vert
+XsucORdri@2 fire net@320 succ sucORdri20
+Xwire90@1 net@537 net@241 wire90-602_3-layer_1-width_3
+Xwire90@10 net@465 fill wire90-602_3-layer_1-width_3
+Xwire90@12 net@533 net@454 wire90-602_3-layer_1-width_3
+Xwire90@14 net@541 block wire90-602_3-layer_1-width_3
+Xwire90@15 fire[B] net@320 wire90-602_3-layer_1-width_3
+.ENDS gaspFill
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5449_9-R_34_667m a b
+Ccap@0 gnd net@14 19.983f
+Ccap@1 gnd net@8 19.983f
+Ccap@2 gnd net@11 19.983f
+Rres@0 net@14 a 31.488
+Rres@1 net@11 net@14 62.977
+Rres@2 b net@8 31.488
+Rres@3 net@8 net@11 62.977
+.ENDS wire-C_0_011f-5449_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5449_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-5449_9-R_34_667m
+.ENDS wire90-5449_9-layer_1-width_3
+
+*** CELL: stagesL:fillStage{sch}
+.SUBCKT fillStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] 
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
++aout[7] aout[8] aout[9] aout[T] in[10] in[11] in[12] in[13] in[14] in[15] 
++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] 
++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] 
++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] 
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] 
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] 
++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] 
++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] sic[2] 
++sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] 
++sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] succ
+Xall1in52@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] 
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] 
++aout[8] aout[9] aout[T] net@2 in[10] in[11] in[12] in[13] in[14] in[15] 
++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] 
++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] 
++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] 
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] 
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] 
++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] 
++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] sid[1] sid[2] sid[3] 
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sod[1] sod[2] sod[3] sod[4] sod[5] 
++all1in52scan
+XgaspFill@0 net@0 pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
++sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] 
++soc[1] sor[1] succ gaspFill
+Xwire90@0 net@0 net@2 wire90-5449_9-layer_1-width_3
+.ENDS fillStage
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2080_4-R_34_667m a b
+Ccap@0 gnd net@14 7.628f
+Ccap@1 gnd net@8 7.628f
+Ccap@2 gnd net@11 7.628f
+Rres@0 net@14 a 12.02
+Rres@1 net@11 net@14 24.04
+Rres@2 b net@8 12.02
+Rres@3 net@8 net@11 24.04
+.ENDS wire-C_0_011f-2080_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2080_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2080_4-R_34_667m
+.ENDS wire90-2080_4-layer_1-width_3
+
+*** CELL: stageGroupsL:properStopper{sch}
+.SUBCKT properStopper ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] 
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
++aout[7] aout[8] aout[9] aout[T] dOut fire in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] 
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] 
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] 
++sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] 
++succ
+XdrainSta@0 net@1[4] net@1[3] net@1[2] net@1[1] net@1[0] net@1[13] net@1[12] 
++net@1[11] net@1[10] net@1[9] net@1[8] net@1[7] net@1[6] net@1[5] net@1[14] 
++aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] 
++aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] dOut fire net@1[42] net@1[41] 
++net@1[40] net@1[39] net@1[38] net@1[37] net@1[36] net@1[35] net@1[34] 
++net@1[33] net@1[51] net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] 
++net@1[27] net@1[26] net@1[25] net@1[24] net@1[23] net@1[50] net@1[22] 
++net@1[21] net@1[20] net@1[19] net@1[18] net@1[17] net@1[16] net@1[15] 
++net@1[49] net@1[48] net@1[47] net@1[46] net@1[45] net@1[44] net@1[43] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@42 
++net@3[8] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] net@2[8] 
++sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ 
++drainStage
+XfillStag@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] net@1[4] net@1[3] net@1[2] 
++net@1[1] net@1[0] net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] 
++net@1[7] net@1[6] net@1[5] net@1[14] in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] net@1[42] 
++net@1[41] net@1[40] net@1[39] net@1[38] net@1[37] net@1[36] net@1[35] 
++net@1[34] net@1[33] net@1[51] net@1[32] net@1[31] net@1[30] net@1[29] 
++net@1[28] net@1[27] net@1[26] net@1[25] net@1[24] net@1[23] net@1[50] 
++net@1[22] net@1[21] net@1[20] net@1[19] net@1[18] net@1[17] net@1[16] 
++net@1[15] net@1[49] net@1[48] net@1[47] net@1[46] net@1[45] net@1[44] 
++net@1[43] pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] 
++sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] 
++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@3[8] sod[1] sod[2] 
++sod[3] sod[4] sod[5] net@2[8] net@41 fillStage
+Xwire90@0 net@41 net@42 wire90-2080_4-layer_1-width_3
+.ENDS properStopper
+
+*** CELL: stageGroupsL:fillDrainCount{sch}
+.SUBCKT fillDrainCount ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] 
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
++aout[7] aout[8] aout[9] aout[T] fin fout in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] 
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] 
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] 
++sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] 
++succ
+Xinstruct@0 net@53 net@48 fin fout net@74[8] sod[2] sod[3] sod[4] sod[5] 
++sid[6] sid[7] sid[8] sid[9] sod[1] instructionCount
+XproperSt@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] 
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] 
++aout[8] aout[9] aout[T] net@87 net@53 in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] 
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] 
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] 
++sir[6] sir[7] sir[8] sir[9] soc[1] net@74[8] sod[2] sod[3] sod[4] sod[5] 
++sor[1] succ properStopper
+Xwire90@1 net@87 net@48 wire90-2080_4-layer_1-width_3
+.ENDS fillDrainCount
+
+*** CELL: scanK:scanEx1vertFup{sch}
+.SUBCKT scanEx1vertFup dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sor[1]
+XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanCellE
+.ENDS scanEx1vertFup
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_6 d g s
+MPMOSf@0 d g s vdd pch W='36*(1+ABP/sqrt(36*2))' L='2'  
++DELVTO='AVT0P/sqrt(36*2)'
+.ENDS PMOSx-X_6
+
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_6 in out
+XNMOS@0 out in gnd NMOSx-X_6
+XPMOS@0 out in vdd PMOSx-X_6
+.ENDS inv-X_6
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-124_7-R_34_667m a b
+Ccap@0 gnd net@14 0.457f
+Ccap@1 gnd net@8 0.457f
+Ccap@2 gnd net@11 0.457f
+Rres@0 net@14 a 0.72
+Rres@1 net@11 net@14 1.441
+Rres@2 b net@8 0.72
+Rres@3 net@8 net@11 1.441
+.ENDS wire-C_0_011f-124_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-124_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-124_7-R_34_667m
+.ENDS wire90-124_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-503_4-R_34_667m a b
+Ccap@0 gnd net@14 1.846f
+Ccap@1 gnd net@8 1.846f
+Ccap@2 gnd net@11 1.846f
+Rres@0 net@14 a 2.909
+Rres@1 net@11 net@14 5.817
+Rres@2 b net@8 2.909
+Rres@3 net@8 net@11 5.817
+.ENDS wire-C_0_011f-503_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-503_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-503_4-R_34_667m
+.ENDS wire90-503_4-layer_1-width_3
+
+*** CELL: driversL:sucDri20{sch}
+.SUBCKT sucDri20 in succ
+XPMOSx@0 succ net@46 vdd PMOSx-X_20
+Xinv@1 succ net@94 inv-X_4
+Xinv@2 in net@110 inv-X_6
+Xnms2@0 succ net@117 net@46 nms2-X_2
+Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3
+Xwire90@1 net@110 net@46 wire90-503_4-layer_1-width_3
+.ENDS sucDri20
+
+*** CELL: gaspL:gaspWeakUp{sch}
+.SUBCKT gaspWeakUp fire pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sir[9] sor[1] succ
+XctrAND2i@0 net@16 succ fire ctrAND2in100LT
+Xinv@1 pred net@9 inv-X_10
+XpredDri2@0 fire net@25 pred predDri20wMC
+XscanEx1v@2 pred sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sor[1] scanEx1vertFup
+XsucDri20@0 fire succ sucDri20
+Xwire90@1 net@9 net@16 wire90-602_3-layer_1-width_3
+Xwire90@2 net@25 sir[9] wire90-602_3-layer_1-width_3
+.ENDS gaspWeakUp
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5130_5-R_34_667m a b
+Ccap@0 gnd net@14 18.812f
+Ccap@1 gnd net@8 18.812f
+Ccap@2 gnd net@11 18.812f
+Rres@0 net@14 a 29.643
+Rres@1 net@11 net@14 59.286
+Rres@2 b net@8 29.643
+Rres@3 net@8 net@11 59.286
+.ENDS wire-C_0_011f-5130_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5130_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-5130_5-R_34_667m
+.ENDS wire90-5130_5-layer_1-width_3
+
+*** CELL: stagesL:weakStageUp{sch}
+.SUBCKT weakStageUp ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] 
++ainU[2] ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[T] 
++aoutU[10] aoutU[11] aoutU[12] aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] 
++aoutU[4] aoutU[5] aoutU[6] aoutU[7] aoutU[8] aoutU[9] aoutU[T] inU[10] 
++inU[11] inU[12] inU[13] inU[14] inU[15] inU[16] inU[17] inU[18] inU[19] 
++inU[1] inU[20] inU[21] inU[22] inU[23] inU[24] inU[25] inU[26] inU[27] 
++inU[28] inU[29] inU[2] inU[30] inU[31] inU[32] inU[33] inU[34] inU[35] 
++inU[36] inU[37] inU[3] inU[4] inU[5] inU[6] inU[7] inU[8] inU[9] outU[10] 
++outU[11] outU[12] outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] 
++outU[19] outU[1] outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] 
++outU[26] outU[27] outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] 
++outU[33] outU[34] outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] 
++outU[7] outU[8] outU[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sir[9] sor[1] succ
+Xall1in52@2 ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] 
++ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[T] aoutU[10] 
++aoutU[11] aoutU[12] aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] 
++aoutU[5] aoutU[6] aoutU[7] aoutU[8] aoutU[9] aoutU[T] net@2 inU[10] inU[11] 
++inU[12] inU[13] inU[14] inU[15] inU[16] inU[17] inU[18] inU[19] inU[1] 
++inU[20] inU[21] inU[22] inU[23] inU[24] inU[25] inU[26] inU[27] inU[28] 
++inU[29] inU[2] inU[30] inU[31] inU[32] inU[33] inU[34] inU[35] inU[36] 
++inU[37] inU[3] inU[4] inU[5] inU[6] inU[7] inU[8] inU[9] outU[10] outU[11] 
++outU[12] outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] 
++outU[1] outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] 
++outU[27] outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] 
++outU[34] outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] 
++outU[8] outU[9] all1in52weak
+XgaspPlai@1 net@0 pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sir[9] sor[1] succ gaspWeakUp
+Xwire90@0 net@0 net@2 wire90-5130_5-layer_1-width_3
+.ENDS weakStageUp
+
+*** CELL: scanK:scanEx1vertFdn{sch}
+.SUBCKT scanEx1vertFdn dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sor[8]
+XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sor[8] sir[8] scanCellE
+.ENDS scanEx1vertFdn
+
+*** CELL: gaspL:gaspWeakDn{sch}
+.SUBCKT gaspWeakDn fire pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sir[9] sor[8] succ
+XctrAND2i@0 net@16 succ fire ctrAND2in100LT
+Xinv@1 pred net@9 inv-X_10
+XpredDri2@0 fire net@25 pred predDri20wMC
+XscanEx1v@1 pred sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sor[8] scanEx1vertFdn
+XsucDri20@0 fire succ sucDri20
+Xwire90@1 net@9 net@16 wire90-602_3-layer_1-width_3
+Xwire90@2 net@25 sir[9] wire90-602_3-layer_1-width_3
+.ENDS gaspWeakDn
+
+*** CELL: stagesL:weakStageDn{sch}
+.SUBCKT weakStageDn ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] 
++ainD[2] ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[T] 
++aoutD[10] aoutD[11] aoutD[12] aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] 
++aoutD[4] aoutD[5] aoutD[6] aoutD[7] aoutD[8] aoutD[9] aoutD[T] inD[10] 
++inD[11] inD[12] inD[13] inD[14] inD[15] inD[16] inD[17] inD[18] inD[19] 
++inD[1] inD[20] inD[21] inD[22] inD[23] inD[24] inD[25] inD[26] inD[27] 
++inD[28] inD[29] inD[2] inD[30] inD[31] inD[32] inD[33] inD[34] inD[35] 
++inD[36] inD[37] inD[3] inD[4] inD[5] inD[6] inD[7] inD[8] inD[9] outD[10] 
++outD[11] outD[12] outD[13] outD[14] outD[15] outD[16] outD[17] outD[18] 
++outD[19] outD[1] outD[20] outD[21] outD[22] outD[23] outD[24] outD[25] 
++outD[26] outD[27] outD[28] outD[29] outD[2] outD[30] outD[31] outD[32] 
++outD[33] outD[34] outD[35] outD[36] outD[37] outD[3] outD[4] outD[5] outD[6] 
++outD[7] outD[8] outD[9] predD sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sir[9] sor[8] succD
+Xall1in52@2 ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] ainD[2] 
++ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[T] aoutD[10] 
++aoutD[11] aoutD[12] aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] 
++aoutD[5] aoutD[6] aoutD[7] aoutD[8] aoutD[9] aoutD[T] net@2 inD[10] inD[11] 
++inD[12] inD[13] inD[14] inD[15] inD[16] inD[17] inD[18] inD[19] inD[1] 
++inD[20] inD[21] inD[22] inD[23] inD[24] inD[25] inD[26] inD[27] inD[28] 
++inD[29] inD[2] inD[30] inD[31] inD[32] inD[33] inD[34] inD[35] inD[36] 
++inD[37] inD[3] inD[4] inD[5] inD[6] inD[7] inD[8] inD[9] outD[10] outD[11] 
++outD[12] outD[13] outD[14] outD[15] outD[16] outD[17] outD[18] outD[19] 
++outD[1] outD[20] outD[21] outD[22] outD[23] outD[24] outD[25] outD[26] 
++outD[27] outD[28] outD[29] outD[2] outD[30] outD[31] outD[32] outD[33] 
++outD[34] outD[35] outD[36] outD[37] outD[3] outD[4] outD[5] outD[6] outD[7] 
++outD[8] outD[9] all1in52weak
+XgaspWeak@0 net@0 predD sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sir[9] sor[8] succD gaspWeakDn
+Xwire90@0 net@0 net@2 wire90-5130_5-layer_1-width_3
+.ENDS weakStageDn
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1243_9-R_34_667m a b
+Ccap@0 gnd net@14 4.561f
+Ccap@1 gnd net@8 4.561f
+Ccap@2 gnd net@11 4.561f
+Rres@0 net@14 a 7.187
+Rres@1 net@11 net@14 14.374
+Rres@2 b net@8 7.187
+Rres@3 net@8 net@11 14.374
+.ENDS wire-C_0_011f-1243_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1243_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1243_9-R_34_667m
+.ENDS wire90-1243_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1185_9-R_34_667m a b
+Ccap@0 gnd net@14 4.348f
+Ccap@1 gnd net@8 4.348f
+Ccap@2 gnd net@11 4.348f
+Rres@0 net@14 a 6.852
+Rres@1 net@11 net@14 13.704
+Rres@2 b net@8 6.852
+Rres@3 net@8 net@11 13.704
+.ENDS wire-C_0_011f-1185_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1185_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1185_9-R_34_667m
+.ENDS wire90-1185_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1249_9-R_34_667m a b
+Ccap@0 gnd net@14 4.583f
+Ccap@1 gnd net@8 4.583f
+Ccap@2 gnd net@11 4.583f
+Rres@0 net@14 a 7.222
+Rres@1 net@11 net@14 14.443
+Rres@2 b net@8 7.222
+Rres@3 net@8 net@11 14.443
+.ENDS wire-C_0_011f-1249_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1249_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1249_9-R_34_667m
+.ENDS wire90-1249_9-layer_1-width_3
+
+*** CELL: stageGroupsL:upDown8weak{sch}
+.SUBCKT upDown8weak ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] 
++ainD[2] ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[T] 
++ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] ainU[3] ainU[4] 
++ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[T] aoutD[10] aoutD[11] aoutD[12] 
++aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5] aoutD[6] 
++aoutD[7] aoutD[8] aoutD[9] aoutD[T] aoutU[10] aoutU[11] aoutU[12] aoutU[13] 
++aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6] aoutU[7] 
++aoutU[8] aoutU[9] aoutU[T] inD[10] inD[11] inD[12] inD[13] inD[14] inD[15] 
++inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] inD[23] 
++inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] inD[31] 
++inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] inD[6] 
++inD[7] inD[8] inD[9] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15] inU[16] 
++inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23] inU[24] 
++inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31] inU[32] 
++inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6] inU[7] 
++inU[8] inU[9] outD[10] outD[11] outD[12] outD[13] outD[14] outD[15] outD[16] 
++outD[17] outD[18] outD[19] outD[1] outD[20] outD[21] outD[22] outD[23] 
++outD[24] outD[25] outD[26] outD[27] outD[28] outD[29] outD[2] outD[30] 
++outD[31] outD[32] outD[33] outD[34] outD[35] outD[36] outD[37] outD[3] 
++outD[4] outD[5] outD[6] outD[7] outD[8] outD[9] outU[10] outU[11] outU[12] 
++outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] outU[1] 
++outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] outU[27] 
++outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] outU[34] 
++outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] outU[8] 
++outU[9] predD predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] 
++sir[9] sor[1] sor[8] succD succU
+XweakStag@10 ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] 
++ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[T] net@111[4] 
++net@111[3] net@111[2] net@111[1] net@111[0] net@111[13] net@111[12] 
++net@111[11] net@111[10] net@111[9] net@111[8] net@111[7] net@111[6] 
++net@111[5] net@111[14] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15] 
++inU[16] inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23] 
++inU[24] inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31] 
++inU[32] inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6] 
++inU[7] inU[8] inU[9] net@111[42] net@111[41] net@111[40] net@111[39] 
++net@111[38] net@111[37] net@111[36] net@111[35] net@111[34] net@111[33] 
++net@111[51] net@111[32] net@111[31] net@111[30] net@111[29] net@111[28] 
++net@111[27] net@111[26] net@111[25] net@111[24] net@111[23] net@111[50] 
++net@111[22] net@111[21] net@111[20] net@111[19] net@111[18] net@111[17] 
++net@111[16] net@111[15] net@111[49] net@111[48] net@111[47] net@111[46] 
++net@111[45] net@111[44] net@111[43] predU sir[1] sir[2] sir[3] sir[4] sir[5] 
++sir[6] sir[7] sir[8] sir[9] net@117[8] net@28 weakStageUp
+XweakStag@11 net@111[4] net@111[3] net@111[2] net@111[1] net@111[0] 
++net@111[13] net@111[12] net@111[11] net@111[10] net@111[9] net@111[8] 
++net@111[7] net@111[6] net@111[5] net@111[14] net@112[4] net@112[3] net@112[2] 
++net@112[1] net@112[0] net@112[13] net@112[12] net@112[11] net@112[10] 
++net@112[9] net@112[8] net@112[7] net@112[6] net@112[5] net@112[14] 
++net@111[42] net@111[41] net@111[40] net@111[39] net@111[38] net@111[37] 
++net@111[36] net@111[35] net@111[34] net@111[33] net@111[51] net@111[32] 
++net@111[31] net@111[30] net@111[29] net@111[28] net@111[27] net@111[26] 
++net@111[25] net@111[24] net@111[23] net@111[50] net@111[22] net@111[21] 
++net@111[20] net@111[19] net@111[18] net@111[17] net@111[16] net@111[15] 
++net@111[49] net@111[48] net@111[47] net@111[46] net@111[45] net@111[44] 
++net@111[43] net@112[42] net@112[41] net@112[40] net@112[39] net@112[38] 
++net@112[37] net@112[36] net@112[35] net@112[34] net@112[33] net@112[51] 
++net@112[32] net@112[31] net@112[30] net@112[29] net@112[28] net@112[27] 
++net@112[26] net@112[25] net@112[24] net@112[23] net@112[50] net@112[22] 
++net@112[21] net@112[20] net@112[19] net@112[18] net@112[17] net@112[16] 
++net@112[15] net@112[49] net@112[48] net@112[47] net@112[46] net@112[45] 
++net@112[44] net@112[43] net@46 net@117[8] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] net@120[1] sir[9] net@123[8] net@62 weakStageUp
+XweakStag@12 net@112[4] net@112[3] net@112[2] net@112[1] net@112[0] 
++net@112[13] net@112[12] net@112[11] net@112[10] net@112[9] net@112[8] 
++net@112[7] net@112[6] net@112[5] net@112[14] net@113[4] net@113[3] net@113[2] 
++net@113[1] net@113[0] net@113[13] net@113[12] net@113[11] net@113[10] 
++net@113[9] net@113[8] net@113[7] net@113[6] net@113[5] net@113[14] 
++net@112[42] net@112[41] net@112[40] net@112[39] net@112[38] net@112[37] 
++net@112[36] net@112[35] net@112[34] net@112[33] net@112[51] net@112[32] 
++net@112[31] net@112[30] net@112[29] net@112[28] net@112[27] net@112[26] 
++net@112[25] net@112[24] net@112[23] net@112[50] net@112[22] net@112[21] 
++net@112[20] net@112[19] net@112[18] net@112[17] net@112[16] net@112[15] 
++net@112[49] net@112[48] net@112[47] net@112[46] net@112[45] net@112[44] 
++net@112[43] net@113[42] net@113[41] net@113[40] net@113[39] net@113[38] 
++net@113[37] net@113[36] net@113[35] net@113[34] net@113[33] net@113[51] 
++net@113[32] net@113[31] net@113[30] net@113[29] net@113[28] net@113[27] 
++net@113[26] net@113[25] net@113[24] net@113[23] net@113[50] net@113[22] 
++net@113[21] net@113[20] net@113[19] net@113[18] net@113[17] net@113[16] 
++net@113[15] net@113[49] net@113[48] net@113[47] net@113[46] net@113[45] 
++net@113[44] net@113[43] net@63 net@123[8] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] net@126[1] sir[9] net@129[8] net@64 weakStageUp
+XweakStag@13 net@113[4] net@113[3] net@113[2] net@113[1] net@113[0] 
++net@113[13] net@113[12] net@113[11] net@113[10] net@113[9] net@113[8] 
++net@113[7] net@113[6] net@113[5] net@113[14] aoutU[10] aoutU[11] aoutU[12] 
++aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6] 
++aoutU[7] aoutU[8] aoutU[9] aoutU[T] net@113[42] net@113[41] net@113[40] 
++net@113[39] net@113[38] net@113[37] net@113[36] net@113[35] net@113[34] 
++net@113[33] net@113[51] net@113[32] net@113[31] net@113[30] net@113[29] 
++net@113[28] net@113[27] net@113[26] net@113[25] net@113[24] net@113[23] 
++net@113[50] net@113[22] net@113[21] net@113[20] net@113[19] net@113[18] 
++net@113[17] net@113[16] net@113[15] net@113[49] net@113[48] net@113[47] 
++net@113[46] net@113[45] net@113[44] net@113[43] outU[10] outU[11] outU[12] 
++outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] outU[1] 
++outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] outU[27] 
++outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] outU[34] 
++outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] outU[8] 
++outU[9] net@65 net@129[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++net@132[1] sir[9] sor[1] succU weakStageUp
+XweakStag@14 net@104[4] net@104[3] net@104[2] net@104[1] net@104[0] 
++net@104[13] net@104[12] net@104[11] net@104[10] net@104[9] net@104[8] 
++net@104[7] net@104[6] net@104[5] net@104[14] aoutD[10] aoutD[11] aoutD[12] 
++aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5] aoutD[6] 
++aoutD[7] aoutD[8] aoutD[9] aoutD[T] net@104[42] net@104[41] net@104[40] 
++net@104[39] net@104[38] net@104[37] net@104[36] net@104[35] net@104[34] 
++net@104[33] net@104[51] net@104[32] net@104[31] net@104[30] net@104[29] 
++net@104[28] net@104[27] net@104[26] net@104[25] net@104[24] net@104[23] 
++net@104[50] net@104[22] net@104[21] net@104[20] net@104[19] net@104[18] 
++net@104[17] net@104[16] net@104[15] net@104[49] net@104[48] net@104[47] 
++net@104[46] net@104[45] net@104[44] net@104[43] outD[10] outD[11] outD[12] 
++outD[13] outD[14] outD[15] outD[16] outD[17] outD[18] outD[19] outD[1] 
++outD[20] outD[21] outD[22] outD[23] outD[24] outD[25] outD[26] outD[27] 
++outD[28] outD[29] outD[2] outD[30] outD[31] outD[32] outD[33] outD[34] 
++outD[35] outD[36] outD[37] outD[3] outD[4] outD[5] outD[6] outD[7] outD[8] 
++outD[9] net@50 net@117[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] 
++sir[9] net@120[1] succD weakStageDn
+XweakStag@15 net@106[4] net@106[3] net@106[2] net@106[1] net@106[0] 
++net@106[13] net@106[12] net@106[11] net@106[10] net@106[9] net@106[8] 
++net@106[7] net@106[6] net@106[5] net@106[14] net@104[4] net@104[3] net@104[2] 
++net@104[1] net@104[0] net@104[13] net@104[12] net@104[11] net@104[10] 
++net@104[9] net@104[8] net@104[7] net@104[6] net@104[5] net@104[14] 
++net@106[42] net@106[41] net@106[40] net@106[39] net@106[38] net@106[37] 
++net@106[36] net@106[35] net@106[34] net@106[33] net@106[51] net@106[32] 
++net@106[31] net@106[30] net@106[29] net@106[28] net@106[27] net@106[26] 
++net@106[25] net@106[24] net@106[23] net@106[50] net@106[22] net@106[21] 
++net@106[20] net@106[19] net@106[18] net@106[17] net@106[16] net@106[15] 
++net@106[49] net@106[48] net@106[47] net@106[46] net@106[45] net@106[44] 
++net@106[43] net@104[42] net@104[41] net@104[40] net@104[39] net@104[38] 
++net@104[37] net@104[36] net@104[35] net@104[34] net@104[33] net@104[51] 
++net@104[32] net@104[31] net@104[30] net@104[29] net@104[28] net@104[27] 
++net@104[26] net@104[25] net@104[24] net@104[23] net@104[50] net@104[22] 
++net@104[21] net@104[20] net@104[19] net@104[18] net@104[17] net@104[16] 
++net@104[15] net@104[49] net@104[48] net@104[47] net@104[46] net@104[45] 
++net@104[44] net@104[43] net@44 net@123[8] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] net@120[1] sir[9] net@126[1] net@51 weakStageDn
+XweakStag@16 net@107[4] net@107[3] net@107[2] net@107[1] net@107[0] 
++net@107[13] net@107[12] net@107[11] net@107[10] net@107[9] net@107[8] 
++net@107[7] net@107[6] net@107[5] net@107[14] net@106[4] net@106[3] net@106[2] 
++net@106[1] net@106[0] net@106[13] net@106[12] net@106[11] net@106[10] 
++net@106[9] net@106[8] net@106[7] net@106[6] net@106[5] net@106[14] 
++net@107[42] net@107[41] net@107[40] net@107[39] net@107[38] net@107[37] 
++net@107[36] net@107[35] net@107[34] net@107[33] net@107[51] net@107[32] 
++net@107[31] net@107[30] net@107[29] net@107[28] net@107[27] net@107[26] 
++net@107[25] net@107[24] net@107[23] net@107[50] net@107[22] net@107[21] 
++net@107[20] net@107[19] net@107[18] net@107[17] net@107[16] net@107[15] 
++net@107[49] net@107[48] net@107[47] net@107[46] net@107[45] net@107[44] 
++net@107[43] net@106[42] net@106[41] net@106[40] net@106[39] net@106[38] 
++net@106[37] net@106[36] net@106[35] net@106[34] net@106[33] net@106[51] 
++net@106[32] net@106[31] net@106[30] net@106[29] net@106[28] net@106[27] 
++net@106[26] net@106[25] net@106[24] net@106[23] net@106[50] net@106[22] 
++net@106[21] net@106[20] net@106[19] net@106[18] net@106[17] net@106[16] 
++net@106[15] net@106[49] net@106[48] net@106[47] net@106[46] net@106[45] 
++net@106[44] net@106[43] net@52 net@129[8] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] net@126[1] sir[9] net@132[1] net@43 weakStageDn
+XweakStag@17 ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] ainD[2] 
++ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[T] net@107[4] 
++net@107[3] net@107[2] net@107[1] net@107[0] net@107[13] net@107[12] 
++net@107[11] net@107[10] net@107[9] net@107[8] net@107[7] net@107[6] 
++net@107[5] net@107[14] inD[10] inD[11] inD[12] inD[13] inD[14] inD[15] 
++inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] inD[23] 
++inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] inD[31] 
++inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] inD[6] 
++inD[7] inD[8] inD[9] net@107[42] net@107[41] net@107[40] net@107[39] 
++net@107[38] net@107[37] net@107[36] net@107[35] net@107[34] net@107[33] 
++net@107[51] net@107[32] net@107[31] net@107[30] net@107[29] net@107[28] 
++net@107[27] net@107[26] net@107[25] net@107[24] net@107[23] net@107[50] 
++net@107[22] net@107[21] net@107[20] net@107[19] net@107[18] net@107[17] 
++net@107[16] net@107[15] net@107[49] net@107[48] net@107[47] net@107[46] 
++net@107[45] net@107[44] net@107[43] predD sor[1] sir[2] sir[3] sir[4] sir[5] 
++sir[6] sir[7] net@132[1] sir[9] sor[8] net@53 weakStageDn
+Xwire90@1 net@44 net@43 wire90-1243_9-layer_1-width_3
+Xwire90@2 net@28 net@46 wire90-1185_9-layer_1-width_3
+Xwire90@3 net@62 net@63 wire90-1185_9-layer_1-width_3
+Xwire90@4 net@64 net@65 wire90-1185_9-layer_1-width_3
+Xwire90@5 net@50 net@51 wire90-1249_9-layer_1-width_3
+Xwire90@6 net@52 net@53 wire90-1249_9-layer_1-width_3
+.ENDS upDown8weak
+
+*** CELL: stageGroupsL:northFifo{sch}
+.SUBCKT northFifo ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] 
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
++aout[7] aout[8] aout[9] aout[T] fin fout in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] 
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] 
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] 
++sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] 
++sor[8] succ
+XfillDrai@0 net@256[4] net@256[3] net@256[2] net@256[1] net@256[0] 
++net@256[13] net@256[12] net@256[11] net@256[10] net@256[9] net@256[8] 
++net@256[7] net@256[6] net@256[5] net@256[14] net@259[4] net@259[3] net@259[2] 
++net@259[1] net@259[0] net@259[13] net@259[12] net@259[11] net@259[10] 
++net@259[9] net@259[8] net@259[7] net@259[6] net@259[5] net@259[14] fin fout 
++net@256[42] net@256[41] net@256[40] net@256[39] net@256[38] net@256[37] 
++net@256[36] net@256[35] net@256[34] net@256[33] net@256[51] net@256[32] 
++net@256[31] net@256[30] net@256[29] net@256[28] net@256[27] net@256[26] 
++net@256[25] net@256[24] net@256[23] net@256[50] net@256[22] net@256[21] 
++net@256[20] net@256[19] net@256[18] net@256[17] net@256[16] net@256[15] 
++net@256[49] net@256[48] net@256[47] net@256[46] net@256[45] net@256[44] 
++net@256[43] net@259[42] net@259[41] net@259[40] net@259[39] net@259[38] 
++net@259[37] net@259[36] net@259[35] net@259[34] net@259[33] net@259[51] 
++net@259[32] net@259[31] net@259[30] net@259[29] net@259[28] net@259[27] 
++net@259[26] net@259[25] net@259[24] net@259[23] net@259[50] net@259[22] 
++net@259[21] net@259[20] net@259[19] net@259[18] net@259[17] net@259[16] 
++net@259[15] net@259[49] net@259[48] net@259[47] net@259[46] net@259[45] 
++net@259[44] net@259[43] net@263 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] 
++sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] 
++sid[9] net@254[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sor[8] sir[9] 
++soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] net@267 fillDrainCount
+XupDown8w@1 net@259[4] net@259[3] net@259[2] net@259[1] net@259[0] 
++net@259[13] net@259[12] net@259[11] net@259[10] net@259[9] net@259[8] 
++net@259[7] net@259[6] net@259[5] net@259[14] ain[10] ain[11] ain[12] ain[13] 
++ain[14] ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] 
++aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] 
++aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@256[4] net@256[3] 
++net@256[2] net@256[1] net@256[0] net@256[13] net@256[12] net@256[11] 
++net@256[10] net@256[9] net@256[8] net@256[7] net@256[6] net@256[5] 
++net@256[14] net@259[42] net@259[41] net@259[40] net@259[39] net@259[38] 
++net@259[37] net@259[36] net@259[35] net@259[34] net@259[33] net@259[51] 
++net@259[32] net@259[31] net@259[30] net@259[29] net@259[28] net@259[27] 
++net@259[26] net@259[25] net@259[24] net@259[23] net@259[50] net@259[22] 
++net@259[21] net@259[20] net@259[19] net@259[18] net@259[17] net@259[16] 
++net@259[15] net@259[49] net@259[48] net@259[47] net@259[46] net@259[45] 
++net@259[44] net@259[43] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] 
++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] 
++in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] 
++out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] 
++out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] 
++out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] 
++out[4] out[5] out[6] out[7] out[8] out[9] net@256[42] net@256[41] net@256[40] 
++net@256[39] net@256[38] net@256[37] net@256[36] net@256[35] net@256[34] 
++net@256[33] net@256[51] net@256[32] net@256[31] net@256[30] net@256[29] 
++net@256[28] net@256[27] net@256[26] net@256[25] net@256[24] net@256[23] 
++net@256[50] net@256[22] net@256[21] net@256[20] net@256[19] net@256[18] 
++net@256[17] net@256[16] net@256[15] net@256[49] net@256[48] net@256[47] 
++net@256[46] net@256[45] net@256[44] net@256[43] net@229 pred sir[1] sir[2] 
++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@254[8] sor[8] succ 
++net@264 upDown8weak
+Xwire90@6 net@229 net@267 wire90-1185_9-layer_1-width_3
+Xwire90@18 net@264 net@263 wire90-1185_9-layer_1-width_3
+.ENDS northFifo
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_2 d g s
+MNMOSf@0 d g s gnd nch W='6*(1+ABN/sqrt(6*2))' L='2' DELVTO='AVT0N/sqrt(6*2)'
+.ENDS NMOSx-X_2
+
+*** CELL: redFour:pms2{sch}
+.SUBCKT pms2-X_2 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_4
+XPMOS@1 d g2 net@2 PMOSx-X_4
+.ENDS pms2-X_2
+
+*** CELL: redFour:pms2_sy{sch}
+.SUBCKT pms2_sy-X_4 d g g2
+Xpms2@0 d g g2 pms2-X_2
+Xpms2@1 d g2 g pms2-X_2
+.ENDS pms2_sy-X_4
+
+*** CELL: redFour:nor2HT_sy{sch}
+.SUBCKT nor2HT_sy-X_4 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_2
+XNMOS@1 out ina gnd NMOSx-X_2
+Xpms2_sy@0 out ina inb pms2_sy-X_4
+.ENDS nor2HT_sy-X_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-249_5-R_34_667m a b
+Ccap@0 gnd net@14 0.915f
+Ccap@1 gnd net@8 0.915f
+Ccap@2 gnd net@11 0.915f
+Rres@0 net@14 a 1.442
+Rres@1 net@11 net@14 2.883
+Rres@2 b net@8 1.442
+Rres@3 net@8 net@11 2.883
+.ENDS wire-C_0_011f-249_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-249_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-249_5-R_34_667m
+.ENDS wire90-249_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-355_8-R_34_667m a b
+Ccap@0 gnd net@14 1.305f
+Ccap@1 gnd net@8 1.305f
+Ccap@2 gnd net@11 1.305f
+Rres@0 net@14 a 2.056
+Rres@1 net@11 net@14 4.111
+Rres@2 b net@8 2.056
+Rres@3 net@8 net@11 4.111
+.ENDS wire-C_0_011f-355_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-355_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-355_8-R_34_667m
+.ENDS wire90-355_8-layer_1-width_3
+
+*** CELL: centersJ:ctrAND2in30{sch}
+.SUBCKT ctrAND2in30 inA inB out
+Xinv@0 net@7 net@8 inv-X_10
+Xinv@1 net@9 out inv-X_30
+Xnor2HT_s@1 inA inB net@6 nor2HT_sy-X_4
+Xwire90@0 net@6 net@7 wire90-249_5-layer_1-width_3
+Xwire90@1 net@8 net@9 wire90-355_8-layer_1-width_3
+.ENDS ctrAND2in30
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-291_8-R_34_667m a b
+Ccap@0 gnd net@14 1.07f
+Ccap@1 gnd net@8 1.07f
+Ccap@2 gnd net@11 1.07f
+Rres@0 net@14 a 1.686
+Rres@1 net@11 net@14 3.372
+Rres@2 b net@8 1.686
+Rres@3 net@8 net@11 3.372
+.ENDS wire-C_0_011f-291_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-291_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-291_8-R_34_667m
+.ENDS wire90-291_8-layer_1-width_3
+
+*** CELL: gaspL:aStage{sch}
+.SUBCKT aStage fire mc pred s[1] succ
+XctrAND2i@4 net@494 succ fire ctrAND2in30
+Xinv@4 net@987 s[1] inv-X_10
+Xinv@5 pred net@987 inv-X_5
+XpredDri2@1 fire mc pred predDri20wMC
+XsucDri20@1 fire succ sucDri20
+Xwire90@0 net@987 net@494 wire90-291_8-layer_1-width_3
+.ENDS aStage
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-544_2-R_34_667m a b
+Ccap@0 gnd net@14 1.995f
+Ccap@1 gnd net@8 1.995f
+Ccap@2 gnd net@11 1.995f
+Rres@0 net@14 a 3.144
+Rres@1 net@11 net@14 6.289
+Rres@2 b net@8 3.144
+Rres@3 net@8 net@11 6.289
+.ENDS wire-C_0_011f-544_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-544_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-544_2-R_34_667m
+.ENDS wire90-544_2-layer_1-width_3
+
+*** CELL: driversJ:latchDriver60{sch}
+.SUBCKT latchDriver60 in out
+Xinv@0 net@8 out inv-X_60
+Xinv@1 in net@16 inv-X_20
+Xwire90@0 net@16 net@8 wire90-544_2-layer_1-width_3
+.ENDS latchDriver60
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_2 d g s
+MPMOSf@0 d g s vdd pch W='12*(1+ABP/sqrt(12*2))' L='2'  
++DELVTO='AVT0P/sqrt(12*2)'
+.ENDS PMOSx-X_2
+
+*** CELL: redFour:pms2{sch}
+.SUBCKT pms2-X_1 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_2
+XPMOS@1 d g2 net@2 PMOSx-X_2
+.ENDS pms2-X_1
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-185-R_34_667m a b
+Ccap@0 gnd net@14 0.678f
+Ccap@1 gnd net@8 0.678f
+Ccap@2 gnd net@11 0.678f
+Rres@0 net@14 a 1.069
+Rres@1 net@11 net@14 2.138
+Rres@2 b net@8 1.069
+Rres@3 net@8 net@11 2.138
+.ENDS wire-C_0_011f-185-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-185-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-185-R_34_667m
+.ENDS wire90-185-layer_1-width_3
+
+*** CELL: latchesK:mlat1in10{sch}
+.SUBCKT mlat1in10 cl[F] cl[T] in[1] out[1]
+Xinv@0 net@26 out[1] inv-X_10
+Xnms2@0 net@4 out[1] cl[F] nms2-X_2
+Xnms2@1 net@4 in[1] cl[T] nms2-X_2
+Xpms2@0 net@4 out[1] cl[T] pms2-X_1
+Xpms2@1 net@4 in[1] cl[F] pms2-X_2
+Xwire90@0 net@4 net@26 wire90-185-layer_1-width_3
+.ENDS mlat1in10
+
+*** CELL: redFour:nms2{sch}
+.SUBCKT nms2-X_3 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_6
+XNMOS@1 net@0 g gnd NMOSx-X_6
+.ENDS nms2-X_3
+
+*** CELL: redFour:nms3{sch}
+.SUBCKT nms3-X_2 d g g2 g3
+XNMOS@0 d g3 net@6 NMOSx-X_6
+XNMOS@1 net@7 g gnd NMOSx-X_6
+XNMOS@2 net@6 g2 net@7 NMOSx-X_6
+.ENDS nms3-X_2
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_3 d g s
+MPMOSf@0 d g s vdd pch W='18*(1+ABP/sqrt(18*2))' L='2'  
++DELVTO='AVT0P/sqrt(18*2)'
+.ENDS PMOSx-X_3
+
+*** CELL: redFour:pms3{sch}
+.SUBCKT pms3-X_1 d g g2 g3
+XPMOS@0 d g3 net@2 PMOSx-X_3
+XPMOS@1 net@2 g2 net@5 PMOSx-X_3
+XPMOS@2 net@5 g vdd PMOSx-X_3
+.ENDS pms3-X_1
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-339_3-R_34_667m a b
+Ccap@0 gnd net@14 1.244f
+Ccap@1 gnd net@8 1.244f
+Ccap@2 gnd net@11 1.244f
+Rres@0 net@14 a 1.96
+Rres@1 net@11 net@14 3.921
+Rres@2 b net@8 1.96
+Rres@3 net@8 net@11 3.921
+.ENDS wire-C_0_011f-339_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-339_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-339_3-R_34_667m
+.ENDS wire90-339_3-layer_1-width_3
+
+*** CELL: latchesK:mlat2in10{sch}
+.SUBCKT mlat2in10 clA[F] clA[T] clB[F] clB[T] inA inB out[1]
+Xinv@0 net@26 out[1] inv-X_10
+Xnms2@0 net@4 inB clB[T] nms2-X_3
+Xnms2@1 net@4 inA clA[T] nms2-X_3
+Xnms3@0 net@4 clA[F] out[1] clB[F] nms3-X_2
+Xpms2@0 net@4 inB clB[F] pms2-X_2_5
+Xpms2@1 net@4 inA clA[F] pms2-X_2_5
+Xpms3@0 net@4 clA[T] out[1] clB[T] pms3-X_1
+Xwire90@0 net@4 net@26 wire90-339_3-layer_1-width_3
+.ENDS mlat2in10
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-271_1-R_34_667m a b
+Ccap@0 gnd net@14 0.994f
+Ccap@1 gnd net@8 0.994f
+Ccap@2 gnd net@11 0.994f
+Rres@0 net@14 a 1.566
+Rres@1 net@11 net@14 3.133
+Rres@2 b net@8 1.566
+Rres@3 net@8 net@11 3.133
+.ENDS wire-C_0_011f-271_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-271_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-271_1-R_34_667m
+.ENDS wire90-271_1-layer_1-width_3
+
+*** CELL: scanK:scanCellKh{sch}
+.SUBCKT scanCellKh clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin sout
+Xmlat1in1@1 cl[F] cl[T] sin net@58 mlat1in10
+Xmlat2in1@2 clS[F] clS[T] rd[F] rd[T] net@69 din[1] sout mlat2in10
+Xwire90@0 net@58 net@69 wire90-271_1-layer_1-width_3
+.ENDS scanCellKh
+
+*** CELL: scanK:scanKhx1{sch}
+.SUBCKT scanKhx1 clS[F] clS[T] cl[F] cl[T] din[1] mc rd[F] rd[T] sin sout
+XscanCell@1 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin sout scanCellKh
+.ENDS scanKhx1
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-870_8-R_34_667m a b
+Ccap@0 gnd net@14 3.193f
+Ccap@1 gnd net@8 3.193f
+Ccap@2 gnd net@11 3.193f
+Rres@0 net@14 a 5.031
+Rres@1 net@11 net@14 10.063
+Rres@2 b net@8 5.031
+Rres@3 net@8 net@11 10.063
+.ENDS wire-C_0_011f-870_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-870_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-870_8-R_34_667m
+.ENDS wire90-870_8-layer_1-width_3
+
+*** CELL: gaspL:aStageS{sch}
+.SUBCKT aStageS clS[F] clS[T] cl[F] cl[T] fire[1] mc pred rd[F] rd[T] sin 
++sout succ take[1]
+XaStage@0 fire[1] mc pred s[1] succ aStage
+XlatchDri@0 net@1006 take[1] latchDriver60
+XscanKhx1@0 clS[F] clS[T] cl[F] cl[T] s[1] mc rd[F] rd[T] sin sout scanKhx1
+Xwire90@0 fire[1] net@1006 wire90-870_8-layer_1-width_3
+.ENDS aStageS
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_2_5 d g s
+MNMOSf@0 d g s gnd nch W='7.5*(1+ABN/sqrt(7.5*2))' L='2' 
++DELVTO='AVT0N/sqrt(7.5*2)'
+.ENDS NMOSx-X_2_5
+
+*** CELL: redFour:nor2HT_sy{sch}
+.SUBCKT nor2HT_sy-X_5 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_2_5
+XNMOS@1 out ina gnd NMOSx-X_2_5
+Xpms2_sy@0 out ina inb pms2_sy-X_5
+.ENDS nor2HT_sy-X_5
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-252_6-R_34_667m a b
+Ccap@0 gnd net@14 0.926f
+Ccap@1 gnd net@8 0.926f
+Ccap@2 gnd net@11 0.926f
+Rres@0 net@14 a 1.459
+Rres@1 net@11 net@14 2.919
+Rres@2 b net@8 1.459
+Rres@3 net@8 net@11 2.919
+.ENDS wire-C_0_011f-252_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-252_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-252_6-R_34_667m
+.ENDS wire90-252_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-366_8-R_34_667m a b
+Ccap@0 gnd net@14 1.345f
+Ccap@1 gnd net@8 1.345f
+Ccap@2 gnd net@11 1.345f
+Rres@0 net@14 a 2.119
+Rres@1 net@11 net@14 4.239
+Rres@2 b net@8 2.119
+Rres@3 net@8 net@11 4.239
+.ENDS wire-C_0_011f-366_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-366_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-366_8-R_34_667m
+.ENDS wire90-366_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-176_4-R_34_667m a b
+Ccap@0 gnd net@14 0.647f
+Ccap@1 gnd net@8 0.647f
+Ccap@2 gnd net@11 0.647f
+Rres@0 net@14 a 1.019
+Rres@1 net@11 net@14 2.038
+Rres@2 b net@8 1.019
+Rres@3 net@8 net@11 2.038
+.ENDS wire-C_0_011f-176_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-176_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-176_4-R_34_667m
+.ENDS wire90-176_4-layer_1-width_3
+
+*** CELL: centersJ:ctrAND3in30{sch}
+.SUBCKT ctrAND3in30 inA inB inC out
+Xinv@4 inC net@30 inv-X_4
+Xinv@5 net@9 out inv-X_30
+Xnand2@0 net@19 net@15 net@27 nand2-X_10
+Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5
+Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
+Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
+Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
+.ENDS ctrAND3in30
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_9_999 d g s
+MPMOSf@0 d g s vdd pch W='59.994*(1+ABP/sqrt(59.994*2))' L='2'  
++DELVTO='AVT0P/sqrt(59.994*2)'
+.ENDS PMOSx-X_9_999
+
+*** CELL: redFour:pms3{sch}
+.SUBCKT pms3-X_3_333 d g g2 g3
+XPMOS@0 d g3 net@2 PMOSx-X_9_999
+XPMOS@1 net@2 g2 net@5 PMOSx-X_9_999
+XPMOS@2 net@5 g vdd PMOSx-X_9_999
+.ENDS pms3-X_3_333
+
+*** CELL: driversJ:predDri60wMC{sch}
+.SUBCKT predDri60wMC in mc pred
+XNMOSx@0 pred in gnd NMOSx-X_60
+XNMOSx@1 pred mc gnd NMOSx-X_10
+Xinv@0 pred net@145 inv-X_10
+Xpms3@0 pred mc in net@174 pms3-X_3_333
+Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3
+.ENDS predDri60wMC
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-372_8-R_34_667m a b
+Ccap@0 gnd net@14 1.367f
+Ccap@1 gnd net@8 1.367f
+Ccap@2 gnd net@11 1.367f
+Rres@0 net@14 a 2.154
+Rres@1 net@11 net@14 4.308
+Rres@2 b net@8 2.154
+Rres@3 net@8 net@11 4.308
+.ENDS wire-C_0_011f-372_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-372_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-372_8-R_34_667m
+.ENDS wire90-372_8-layer_1-width_3
+
+*** CELL: gaspL:anEpiStart{sch}
+.SUBCKT anEpiStart fire mc pred s[1] succ token torp
+XctrAND3i@0 net@986 succ torp fire ctrAND3in30
+Xinv@4 net@987 s[1] inv-X_10
+Xinv@5 pred net@987 inv-X_5
+Xinv@6 token net@1046 inv-X_10
+XpredDri6@0 fire mc pred predDri60wMC
+XsucANDdr@0 net@1020 fire succ sucANDdri20
+XsucANDdr@1 net@1046 fire torp sucANDdri20
+Xwire90@0 net@987 net@986 wire90-372_8-layer_1-width_3
+Xwire90@1 net@1020 token wire90-372_8-layer_1-width_3
+.ENDS anEpiStart
+
+*** CELL: gaspL:anEpiStartS{sch}
+.SUBCKT anEpiStartS clS[F] clS[T] cl[F] cl[T] mc pred rd[F] rd[T] sin sout 
++succ take[1] token torp
+XanEpiSta@1 net@834 mc pred s[1] succ token torp anEpiStart
+XlatchDri@3 net@832 take[1] latchDriver60
+XscanKhx1@0 clS[F] clS[T] cl[F] cl[T] s[1] mc rd[F] rd[T] sin sout scanKhx1
+Xwire90@1 net@832 net@834 wire90-372_8-layer_1-width_3
+.ENDS anEpiStartS
+
+*** CELL: fifoL:epiFifoCont{sch}
+.SUBCKT epiFifoCont clS[F] clS[T] cl[F] cl[T] mc pred rd[F] rd[T] sin sout 
++succ take[1] take[2] token torp
+XaStageS@0 clS[F] clS[T] cl[F] cl[T] fire[1] mc net@160 rd[F] rd[T] net@194 
++sout succ take[2] aStageS
+XanEpiSta@0 clS[F] clS[T] cl[F] cl[T] mc pred rd[F] rd[T] sin net@194 net@195 
++take[1] token torp anEpiStartS
+Xwire90@0 net@195 net@160 wire90-544_2-layer_1-width_3
+.ENDS epiFifoCont
+
+*** CELL: fifoL:epiFifo{sch}
+.SUBCKT epiFifo clS[F] clS[T] cl[F] cl[T] in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] mc out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred rd[F] rd[T] sin 
++sout succ torp
+Xall1in52@0 in[47] in[48] in[49] in[50] in[51] in[38] in[39] in[40] in[41] 
++in[42] in[43] in[44] in[45] in[46] in[T] net@20[4] net@20[3] net@20[2] 
++net@20[1] net@20[0] net@20[13] net@20[12] net@20[11] net@20[10] net@20[9] 
++net@20[8] net@20[7] net@20[6] net@20[5] net@20[14] take[1] in[10] in[11] 
++in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] 
++in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] 
++in[32] in[33] in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] 
++in[9] net@20[42] net@20[41] net@20[40] net@20[39] net@20[38] net@20[37] 
++net@20[36] net@20[35] net@20[34] net@20[33] net@20[51] net@20[32] net@20[31] 
++net@20[30] net@20[29] net@20[28] net@20[27] net@20[26] net@20[25] net@20[24] 
++net@20[23] net@20[50] net@20[22] net@20[21] net@20[20] net@20[19] net@20[18] 
++net@20[17] net@20[16] net@20[15] net@20[49] net@20[48] net@20[47] net@20[46] 
++net@20[45] net@20[44] net@20[43] all1in52weak
+Xall1in52@1 net@20[4] net@20[3] net@20[2] net@20[1] net@20[0] net@20[13] 
++net@20[12] net@20[11] net@20[10] net@20[9] net@20[8] net@20[7] net@20[6] 
++net@20[5] net@20[14] out[47] out[48] out[49] out[50] out[51] out[38] out[39] 
++out[40] out[41] out[42] out[43] out[44] out[45] out[46] out[T] take[2] 
++net@20[42] net@20[41] net@20[40] net@20[39] net@20[38] net@20[37] net@20[36] 
++net@20[35] net@20[34] net@20[33] net@20[51] net@20[32] net@20[31] net@20[30] 
++net@20[29] net@20[28] net@20[27] net@20[26] net@20[25] net@20[24] net@20[23] 
++net@20[50] net@20[22] net@20[21] net@20[20] net@20[19] net@20[18] net@20[17] 
++net@20[16] net@20[15] net@20[49] net@20[48] net@20[47] net@20[46] net@20[45] 
++net@20[44] net@20[43] out[10] out[11] out[12] out[13] out[14] out[15] out[16] 
++out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] 
++out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] 
++out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] 
++out[8] out[9] all1in52weak
+XepiFifoC@0 clS[F] clS[T] cl[F] cl[T] mc pred rd[F] rd[T] sin sout succ 
++take[1] take[2] in[T] torp epiFifoCont
+.ENDS epiFifo
+
+*** CELL: redFour:nor2_sy{sch}
+.SUBCKT nor2_sy-X_10 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_10
+XNMOS@1 out ina gnd NMOSx-X_10
+Xpms2_sy@0 out ina inb pms2_sy-X_10
+.ENDS nor2_sy-X_10
+
+*** CELL: redFour:nor2n_sy{sch}
+.SUBCKT nor2n_sy-X_10 ina inb out
+Xnor2@0 ina inb out nor2_sy-X_10
+.ENDS nor2n_sy-X_10
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-476_7-R_34_667m a b
+Ccap@0 gnd net@14 1.748f
+Ccap@1 gnd net@8 1.748f
+Ccap@2 gnd net@11 1.748f
+Rres@0 net@14 a 2.754
+Rres@1 net@11 net@14 5.509
+Rres@2 b net@8 2.754
+Rres@3 net@8 net@11 5.509
+.ENDS wire-C_0_011f-476_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-476_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-476_7-R_34_667m
+.ENDS wire90-476_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-472_4-R_34_667m a b
+Ccap@0 gnd net@14 1.732f
+Ccap@1 gnd net@8 1.732f
+Ccap@2 gnd net@11 1.732f
+Rres@0 net@14 a 2.729
+Rres@1 net@11 net@14 5.459
+Rres@2 b net@8 2.729
+Rres@3 net@8 net@11 5.459
+.ENDS wire-C_0_011f-472_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-472_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-472_4-R_34_667m
+.ENDS wire90-472_4-layer_1-width_3
+
+*** CELL: centersJ:ctrAND3in100LT{sch}
+.SUBCKT ctrAND3in100LT inA inB inC out
+Xinv@3 net@104 out inv-X_100
+Xinv@4 inC net@143 inv-X_10
+Xnand2LT_@0 net@138 net@131 net@134 nand2LT_sy-X_30
+Xnor2n_sy@0 inA inB net@130 nor2n_sy-X_10
+Xwire90@0 net@130 net@131 wire90-476_7-layer_1-width_3
+Xwire90@4 net@134 net@104 wire90-1013_8-layer_1-width_3
+Xwire90@5 net@143 net@138 wire90-472_4-layer_1-width_3
+.ENDS ctrAND3in100LT
+
+*** CELL: scanJ:scanEx1vertA{sch}
+.SUBCKT scanEx1vertA dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sor[1]
+XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanCellE
+.ENDS scanEx1vertA
+
+*** CELL: gaspL:gaspTap{sch}
+.SUBCKT gaspTap fire pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
++sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] 
++soc[1] sor[1] succ[A] succ[B]
+XctrAND3i@2 succ[B] succ[A] net@163 fire ctrAND3in100LT
+Xinv@0 pred net@240 inv-X_5
+XpredDri2@0 fire net@104 pred predDri20wMC
+XscanEx1v@0 pred sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sor[1] scanEx1vertA
+XscanFx1v@0 net@405 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] 
++sic[9] soc[1] scanFx1vert
+XsucANDdr@3 net@405 fire succ[B] sucANDdri20
+XsucDri20@2 fire succ[A] sucDri20
+Xwire90@0 net@240 net@163 wire90-602_3-layer_1-width_3
+Xwire90@4 net@104 sir[9] wire90-602_3-layer_1-width_3
+.ENDS gaspTap
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5331_6-R_34_667m a b
+Ccap@0 gnd net@14 19.549f
+Ccap@1 gnd net@8 19.549f
+Ccap@2 gnd net@11 19.549f
+Rres@0 net@14 a 30.805
+Rres@1 net@11 net@14 61.61
+Rres@2 b net@8 30.805
+Rres@3 net@8 net@11 61.61
+.ENDS wire-C_0_011f-5331_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5331_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-5331_6-R_34_667m
+.ENDS wire90-5331_6-layer_1-width_3
+
+*** CELL: stagesL:tapStage{sch}
+.SUBCKT tapStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] 
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] 
++aout[8] aout[9] aout[T] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] 
++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] 
++in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] 
++out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] 
++out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] 
++out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] 
++out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] sic[2] sic[3] sic[4] 
++sic[5] sic[6] sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sir[9] soc[1] sor[1] succ[A] succ[B]
+Xall1in52@3 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] 
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] 
++aout[8] aout[9] aout[T] net@2 in[10] in[11] in[12] in[13] in[14] in[15] 
++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] 
++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] 
++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] 
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] 
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] 
++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] 
++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] all1in52weak
+XgaspSwit@0 net@0 pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
++sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] 
++soc[1] sor[1] succ[A] succ[B] gaspTap
+Xwire90@0 net@0 net@2 wire90-5331_6-layer_1-width_3
+.ENDS tapStage
+
+*** CELL: stageGroupsL:tapPropStop{sch}
+.SUBCKT tapPropStop ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] 
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
++aout[7] aout[8] aout[9] aout[T] cin fin fout gnd in[10] in[11] in[12] in[13] 
++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] 
++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] 
++in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] 
++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] 
++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] 
++sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] 
++succ[tap]
+Xinstruct@0 cin net@90 fin fout net@120[8] sod[2] sod[3] sod[4] sod[5] sid[6] 
++sid[7] sid[8] sid[9] sod[1] instructionCount
+XproperSt@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] net@127[4] net@127[3] 
++net@127[2] net@127[1] net@127[0] net@127[13] net@127[12] net@127[11] 
++net@127[10] net@127[9] net@127[8] net@127[7] net@127[6] net@127[5] 
++net@127[14] net@90 properSt@0_fire in[10] in[11] in[12] in[13] in[14] in[15] 
++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] 
++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] 
++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] net@127[42] 
++net@127[41] net@127[40] net@127[39] net@127[38] net@127[37] net@127[36] 
++net@127[35] net@127[34] net@127[33] net@127[51] net@127[32] net@127[31] 
++net@127[30] net@127[29] net@127[28] net@127[27] net@127[26] net@127[25] 
++net@127[24] net@127[23] net@127[50] net@127[22] net@127[21] net@127[20] 
++net@127[19] net@127[18] net@127[17] net@127[16] net@127[15] net@127[49] 
++net@127[48] net@127[47] net@127[46] net@127[45] net@127[44] net@127[43] pred 
++sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] 
++sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] 
++sir[5] sir[6] sir[7] sir[8] sir[9] net@121[8] net@120[8] sod[2] sod[3] sod[4] 
++sod[5] net@122[8] net@114 properStopper
+XtapStage@1 net@127[4] net@127[3] net@127[2] net@127[1] net@127[0] 
++net@127[13] net@127[12] net@127[11] net@127[10] net@127[9] net@127[8] 
++net@127[7] net@127[6] net@127[5] net@127[14] aout[10] aout[11] aout[12] 
++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] 
++aout[8] aout[9] aout[T] net@127[42] net@127[41] net@127[40] net@127[39] 
++net@127[38] net@127[37] net@127[36] net@127[35] net@127[34] net@127[33] 
++net@127[51] net@127[32] net@127[31] net@127[30] net@127[29] net@127[28] 
++net@127[27] net@127[26] net@127[25] net@127[24] net@127[23] net@127[50] 
++net@127[22] net@127[21] net@127[20] net@127[19] net@127[18] net@127[17] 
++net@127[16] net@127[15] net@127[49] net@127[48] net@127[47] net@127[46] 
++net@127[45] net@127[44] net@127[43] out[10] out[11] out[12] out[13] out[14] 
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] 
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] 
++out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] 
++out[6] out[7] out[8] out[9] net@85 net@121[8] sic[2] sic[3] sic[4] sic[5] 
++sic[6] sic[7] sic[8] sic[9] net@122[8] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sir[9] soc[1] sor[1] gnd succ[tap] tapStage
+Xwire90@2 net@114 net@85 wire90-2080_4-layer_1-width_3
+.ENDS tapPropStop
+
+*** CELL: stageGroupsL:southFifo{sch}
+.SUBCKT southFifo aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] 
++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] cin 
++fin fout out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] 
++out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] 
++out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] 
++out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] 
++out[9] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] 
++sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] 
++sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] 
++sod[5] sor[1] sor[8] succ[tap]
+XtapPropS@0 net@43[4] net@43[3] net@43[2] net@43[1] net@43[0] net@43[13] 
++net@43[12] net@43[11] net@43[10] net@43[9] net@43[8] net@43[7] net@43[6] 
++net@43[5] net@43[14] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] 
++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] cin 
++fin fout gnd net@43[42] net@43[41] net@43[40] net@43[39] net@43[38] 
++net@43[37] net@43[36] net@43[35] net@43[34] net@43[33] net@43[51] net@43[32] 
++net@43[31] net@43[30] net@43[29] net@43[28] net@43[27] net@43[26] net@43[25] 
++net@43[24] net@43[23] net@43[50] net@43[22] net@43[21] net@43[20] net@43[19] 
++net@43[18] net@43[17] net@43[16] net@43[15] net@43[49] net@43[48] net@43[47] 
++net@43[46] net@43[45] net@43[44] net@43[43] out[10] out[11] out[12] out[13] 
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] 
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] 
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] 
++out[5] out[6] out[7] out[8] out[9] net@61 sic[1] sic[2] sic[3] sic[4] sic[5] 
++sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] 
++sid[8] sid[9] net@64[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sor[8] 
++sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] succ[tap] tapPropStop
+XupDown8w@0 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] 
++aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@50[4] 
++net@50[3] net@50[2] net@50[1] net@50[0] net@50[13] net@50[12] net@50[11] 
++net@50[10] net@50[9] net@50[8] net@50[7] net@50[6] net@50[5] net@50[14] 
++net@50[4] net@50[3] net@50[2] net@50[1] net@50[0] net@50[13] net@50[12] 
++net@50[11] net@50[10] net@50[9] net@50[8] net@50[7] net@50[6] net@50[5] 
++net@50[14] net@43[4] net@43[3] net@43[2] net@43[1] net@43[0] net@43[13] 
++net@43[12] net@43[11] net@43[10] net@43[9] net@43[8] net@43[7] net@43[6] 
++net@43[5] net@43[14] out[10] out[11] out[12] out[13] out[14] out[15] out[16] 
++out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] 
++out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] 
++out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] 
++out[8] out[9] net@50[42] net@50[41] net@50[40] net@50[39] net@50[38] 
++net@50[37] net@50[36] net@50[35] net@50[34] net@50[33] net@50[51] net@50[32] 
++net@50[31] net@50[30] net@50[29] net@50[28] net@50[27] net@50[26] net@50[25] 
++net@50[24] net@50[23] net@50[50] net@50[22] net@50[21] net@50[20] net@50[19] 
++net@50[18] net@50[17] net@50[16] net@50[15] net@50[49] net@50[48] net@50[47] 
++net@50[46] net@50[45] net@50[44] net@50[43] net@50[42] net@50[41] net@50[40] 
++net@50[39] net@50[38] net@50[37] net@50[36] net@50[35] net@50[34] net@50[33] 
++net@50[51] net@50[32] net@50[31] net@50[30] net@50[29] net@50[28] net@50[27] 
++net@50[26] net@50[25] net@50[24] net@50[23] net@50[50] net@50[22] net@50[21] 
++net@50[20] net@50[19] net@50[18] net@50[17] net@50[16] net@50[15] net@50[49] 
++net@50[48] net@50[47] net@50[46] net@50[45] net@50[44] net@50[43] net@43[42] 
++net@43[41] net@43[40] net@43[39] net@43[38] net@43[37] net@43[36] net@43[35] 
++net@43[34] net@43[33] net@43[51] net@43[32] net@43[31] net@43[30] net@43[29] 
++net@43[28] net@43[27] net@43[26] net@43[25] net@43[24] net@43[23] net@43[50] 
++net@43[22] net@43[21] net@43[20] net@43[19] net@43[18] net@43[17] net@43[16] 
++net@43[15] net@43[49] net@43[48] net@43[47] net@43[46] net@43[45] net@43[44] 
++net@43[43] gnd net@58 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] 
++sir[9] net@64[8] sor[8] net@58 net@61 upDown8weak
+.ENDS southFifo
+
+*** CELL: wiresL:bitAssignments{sch}
+.SUBCKT bitAssignments
+.ENDS bitAssignments
+
+*** CELL: redFour:nms2{sch}
+.SUBCKT nms2-X_20 d g g2
+XNMOS@0 d g2 net@0 NMOSx-X_40
+XNMOS@1 net@0 g gnd NMOSx-X_40
+.ENDS nms2-X_20
+
+*** CELL: driversL:predCond20wMC{sch}
+.SUBCKT predCond20wMC cond in mc pred
+XNMOSx@1 pred mc gnd NMOSx-X_10
+Xinv@0 pred net@145 inv-X_10
+Xnms2@0 pred cond in nms2-X_20
+Xpms3@0 pred mc in net@186 pms3-X_1
+Xwire90@0 net@186 net@145 wire90-243_6-layer_1-width_3
+.ENDS predCond20wMC
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-297_9-R_34_667m a b
+Ccap@0 gnd net@14 1.092f
+Ccap@1 gnd net@8 1.092f
+Ccap@2 gnd net@11 1.092f
+Rres@0 net@14 a 1.721
+Rres@1 net@11 net@14 3.442
+Rres@2 b net@8 1.721
+Rres@3 net@8 net@11 3.442
+.ENDS wire-C_0_011f-297_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-297_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-297_9-R_34_667m
+.ENDS wire90-297_9-layer_1-width_3
+
+*** CELL: scanK:scanKhx5{sch}
+.SUBCKT scanKhx5 clS[F] clS[T] cl[F] cl[T] din[1] din[2] din[3] din[4] din[5] 
++mc rd[F] rd[T] sin sout
+XscanCell@4 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@18 
++scanCellKh
+XscanCell@5 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@31 net@20 
++scanCellKh
+XscanCell@6 clS[F] clS[T] cl[F] cl[T] din[3] rd[F] rd[T] net@32 net@24 
++scanCellKh
+XscanCell@7 clS[F] clS[T] cl[F] cl[T] din[4] rd[F] rd[T] net@33 net@51 
++scanCellKh
+XscanCell@8 clS[F] clS[T] cl[F] cl[T] din[5] rd[F] rd[T] net@50 sout 
++scanCellKh
+Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
+Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3
+Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3
+Xwire90@3 net@51 net@50 wire90-297_9-layer_1-width_3
+.ENDS scanKhx5
+
+*** CELL: dockPartsK:moveD{sch}
+.SUBCKT moveD clS[F] clS[T] cl[F] cl[T] fire[M] mc od[15] od[16] od[18] 
++od[19] pred[D] pred[T] rd[F] rd[T] s[1] s[2] s[3] sin sout succ[D] succ[T]
+XpredCond@3 od[18] fire[M] mc pred[D] predCond20wMC
+XpredCond@4 od[19] fire[M] mc pred[T] predCond20wMC
+XscanKhx5@2 clS[F] clS[T] cl[F] cl[T] s[1] s[2] pred[D] pred[T] s[3] mc rd[F] 
++rd[T] sin sout scanKhx5
+XsucANDdr@3 od[16] fire[M] succ[D] sucANDdri20
+XsucANDdr@4 od[15] fire[M] succ[T] sucANDdri20
+.ENDS moveD
+
+*** CELL: redFour:nms2_sy{sch}
+.SUBCKT nms2_sy-X_10 d g g2
+Xnms2@0 d g g2 nms2-X_5
+Xnms2@1 d g2 g nms2-X_5
+.ENDS nms2_sy-X_10
+
+*** CELL: redFour:nand2LT_sy{sch}
+.SUBCKT nand2LT_sy-X_10 ina inb out
+XPMOS@0 out ina vdd PMOSx-X_5
+XPMOS@1 out inb vdd PMOSx-X_5
+Xnms2_sy@0 out ina inb nms2_sy-X_10
+.ENDS nand2LT_sy-X_10
+
+*** CELL: centersJ:ctrAND3in30B{sch}
+.SUBCKT ctrAND3in30B inA inB inC out
+Xinv@4 inC net@30 inv-X_5
+Xinv@5 net@9 out inv-X_30
+Xnand2LT_@0 net@15 net@19 net@27 nand2LT_sy-X_10
+Xnor2n_sy@0 inA inB net@6 nor2n_sy-X_5
+Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3
+Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3
+Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3
+.ENDS ctrAND3in30B
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-414-R_34_667m a b
+Ccap@0 gnd net@14 1.518f
+Ccap@1 gnd net@8 1.518f
+Ccap@2 gnd net@11 1.518f
+Rres@0 net@14 a 2.392
+Rres@1 net@11 net@14 4.784
+Rres@2 b net@8 2.392
+Rres@3 net@8 net@11 4.784
+.ENDS wire-C_0_011f-414-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-414-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-414-R_34_667m
+.ENDS wire90-414-layer_1-width_3
+
+*** CELL: fifoL:litStage{sch}
+.SUBCKT litStage do[L] fire[L] mc s[1] succ[D] succ[T]
+XctrAND3i@0 succ[T] succ[D] net@54 fire[L] ctrAND3in30B
+Xinv@0 net@54 s[1] inv-X_10
+Xinv@1 do[L] net@190 inv-X_5
+XpredDri2@1 fire[L] mc do[L] predDri20wMC
+Xwire90@1 net@190 net@54 wire90-414-layer_1-width_3
+.ENDS litStage
+
+*** CELL: redFour:nor2{sch}
+.SUBCKT nor2-X_5 ina inb out
+XNMOS@0 out ina gnd NMOSx-X_5
+XNMOS@1 out inb gnd NMOSx-X_5
+Xpms2@0 out ina inb pms2-X_5
+.ENDS nor2-X_5
+
+*** CELL: redFour:nor2n{sch}
+.SUBCKT nor2n-X_5 ina inb out
+Xnor2@0 ina inb out nor2-X_5
+.ENDS nor2n-X_5
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-238_2-R_34_667m a b
+Ccap@0 gnd net@14 0.873f
+Ccap@1 gnd net@8 0.873f
+Ccap@2 gnd net@11 0.873f
+Rres@0 net@14 a 1.376
+Rres@1 net@11 net@14 2.753
+Rres@2 b net@8 1.376
+Rres@3 net@8 net@11 2.753
+.ENDS wire-C_0_011f-238_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-238_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-238_2-R_34_667m
+.ENDS wire90-238_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-520-R_34_667m a b
+Ccap@0 gnd net@14 1.907f
+Ccap@1 gnd net@8 1.907f
+Ccap@2 gnd net@11 1.907f
+Rres@0 net@14 a 3.004
+Rres@1 net@11 net@14 6.009
+Rres@2 b net@8 3.004
+Rres@3 net@8 net@11 6.009
+.ENDS wire-C_0_011f-520-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-520-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-520-R_34_667m
+.ENDS wire90-520-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-222_3-R_34_667m a b
+Ccap@0 gnd net@14 0.815f
+Ccap@1 gnd net@8 0.815f
+Ccap@2 gnd net@11 0.815f
+Rres@0 net@14 a 1.284
+Rres@1 net@11 net@14 2.569
+Rres@2 b net@8 1.284
+Rres@3 net@8 net@11 2.569
+.ENDS wire-C_0_011f-222_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-222_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-222_3-R_34_667m
+.ENDS wire90-222_3-layer_1-width_3
+
+*** CELL: centersJ:ctrAND4in30{sch}
+.SUBCKT ctrAND4in30 inA inB inC inD out
+Xinv@1 net@3 out inv-X_30
+Xnand2@1 net@43 net@58 net@67 nand2-X_10
+Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4
+Xnor2n@0 inD inC net@64 nor2n-X_5
+Xwire90@0 net@64 net@43 wire90-238_2-layer_1-width_3
+Xwire90@1 net@67 net@3 wire90-520-layer_1-width_3
+Xwire90@2 net@61 net@58 wire90-222_3-layer_1-width_3
+.ENDS ctrAND4in30
+
+*** CELL: redFour:invLT{sch}
+.SUBCKT invLT-X_2 in out
+XNMOS@0 out in gnd NMOSx-X_4
+XPMOS@0 out in vdd PMOSx-X_2
+.ENDS invLT-X_2
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-190_2-R_34_667m a b
+Ccap@0 gnd net@14 0.697f
+Ccap@1 gnd net@8 0.697f
+Ccap@2 gnd net@11 0.697f
+Rres@0 net@14 a 1.099
+Rres@1 net@11 net@14 2.198
+Rres@2 b net@8 1.099
+Rres@3 net@8 net@11 2.198
+.ENDS wire-C_0_011f-190_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-190_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-190_2-R_34_667m
+.ENDS wire90-190_2-layer_1-width_3
+
+*** CELL: latchesK:mlat1in10i{sch}
+.SUBCKT mlat1in10i cl[F] cl[T] in[1] out[1]
+XinvLT@0 out[1] net@33 invLT-X_2
+Xnms2@0 out[1] cl[F] net@33 nms2-X_2
+Xnms2@1 out[1] in[1] cl[T] nms2-X_10
+Xpms2@0 out[1] cl[T] net@138 pms2-X_2
+Xpms2@1 out[1] in[1] cl[F] pms2-X_10
+Xwire90@2 net@138 net@33 wire90-190_2-layer_1-width_3
+.ENDS mlat1in10i
+
+*** CELL: redFour:nand2n{sch}
+.SUBCKT nand2n-X_10 ina inb out
+Xnand2@0 ina inb out nand2-X_10
+.ENDS nand2n-X_10
+
+*** CELL: redFour:pms2{sch}
+.SUBCKT pms2-X_20 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_40
+XPMOS@1 d g2 net@2 PMOSx-X_40
+.ENDS pms2-X_20
+
+*** CELL: redFour:nor2{sch}
+.SUBCKT nor2-X_20 ina inb out
+XNMOS@0 out ina gnd NMOSx-X_20
+XNMOS@1 out inb gnd NMOSx-X_20
+Xpms2@0 out ina inb pms2-X_20
+.ENDS nor2-X_20
+
+*** CELL: redFour:nor2n{sch}
+.SUBCKT nor2n-X_20 ina inb out
+Xnor2@0 ina inb out nor2-X_20
+.ENDS nor2n-X_20
+
+*** CELL: redFour:nor2{sch}
+.SUBCKT nor2-X_10 ina inb out
+XNMOS@0 out ina gnd NMOSx-X_10
+XNMOS@1 out inb gnd NMOSx-X_10
+Xpms2@0 out ina inb pms2-X_10
+.ENDS nor2-X_10
+
+*** CELL: redFour:nor2n{sch}
+.SUBCKT nor2n-X_10 ina inb out
+Xnor2@0 ina inb out nor2-X_10
+.ENDS nor2n-X_10
+
+*** CELL: redFour:pms2{sch}
+.SUBCKT pms2-X_15 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_30
+XPMOS@1 d g2 net@2 PMOSx-X_30
+.ENDS pms2-X_15
+
+*** CELL: redFour:pms2_sy{sch}
+.SUBCKT pms2_sy-X_30 d g g2
+Xpms2@0 d g g2 pms2-X_15
+Xpms2@1 d g2 g pms2-X_15
+.ENDS pms2_sy-X_30
+
+*** CELL: redFour:nor2_sy{sch}
+.SUBCKT nor2_sy-X_30 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_30
+XNMOS@1 out ina gnd NMOSx-X_30
+Xpms2_sy@0 out ina inb pms2_sy-X_30
+.ENDS nor2_sy-X_30
+
+*** CELL: redFour:nor2n_sy{sch}
+.SUBCKT nor2n_sy-X_30 ina inb out
+Xnor2@0 ina inb out nor2_sy-X_30
+.ENDS nor2n_sy-X_30
+
+*** CELL: driversL:predORdri20wMC{sch}
+.SUBCKT predORdri20wMC inA inB mc pred
+XNMOSx@0 pred inA gnd NMOSx-X_20
+XNMOSx@1 pred mc gnd NMOSx-X_4
+XNMOSx@2 pred inB gnd NMOSx-X_20
+XPMOSx@1 pred net@217 net@203 PMOSx-X_4
+XPMOSx@2 net@203 inB net@204 PMOSx-X_4
+XPMOSx@3 net@204 inA net@205 PMOSx-X_4
+XPMOSx@4 net@205 mc vdd PMOSx-X_4
+Xinv@0 pred net@145 inv-X_4
+Xwire90@0 net@217 net@145 wire90-243_6-layer_1-width_3
+.ENDS predORdri20wMC
+
+*** CELL: redFour:pms2{sch}
+.SUBCKT pms2-X_1_5 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_3
+XPMOS@1 d g2 net@2 PMOSx-X_3
+.ENDS pms2-X_1_5
+
+*** CELL: redFour:pms2_sy{sch}
+.SUBCKT pms2_sy-X_3 d g g2
+Xpms2@0 d g g2 pms2-X_1_5
+Xpms2@1 d g2 g pms2-X_1_5
+.ENDS pms2_sy-X_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-218_6-R_34_667m a b
+Ccap@0 gnd net@14 0.802f
+Ccap@1 gnd net@8 0.802f
+Ccap@2 gnd net@11 0.802f
+Rres@0 net@14 a 1.263
+Rres@1 net@11 net@14 2.526
+Rres@2 b net@8 1.263
+Rres@3 net@8 net@11 2.526
+.ENDS wire-C_0_011f-218_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-218_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-218_6-R_34_667m
+.ENDS wire90-218_6-layer_1-width_3
+
+*** CELL: dockPartsK:predWait{sch}
+.SUBCKT predWait ign[2] ign[3] out pred[1] pred[2] pred[3]
+XNMOSx@6 net@108 ign[3] out NMOSx-X_10
+XNMOSx@8 net@87 pred[2] net@108 NMOSx-X_20
+XNMOSx@9 net@87 ign[2] net@86 NMOSx-X_10
+XNMOSx@10 net@86 pred[3] out NMOSx-X_20
+XNMOSx@11 gnd pred[1] net@87 NMOSx-X_20
+XPMOSx@0 vdd pred[1] out PMOSx-X_10
+Xpms2_sy@2 out pred[2] ign[2] pms2_sy-X_3
+Xpms2_sy@3 out pred[3] ign[3] pms2_sy-X_3
+Xwire90@0 net@108 net@86 wire90-218_6-layer_1-width_3
+.ENDS predWait
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-795_4-R_34_667m a b
+Ccap@0 gnd net@14 2.916f
+Ccap@1 gnd net@8 2.916f
+Ccap@2 gnd net@11 2.916f
+Rres@0 net@14 a 4.596
+Rres@1 net@11 net@14 9.191
+Rres@2 b net@8 4.596
+Rres@3 net@8 net@11 9.191
+.ENDS wire-C_0_011f-795_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-795_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-795_4-R_34_667m
+.ENDS wire90-795_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-459_9-R_34_667m a b
+Ccap@0 gnd net@14 1.686f
+Ccap@1 gnd net@8 1.686f
+Ccap@2 gnd net@11 1.686f
+Rres@0 net@14 a 2.657
+Rres@1 net@11 net@14 5.314
+Rres@2 b net@8 2.657
+Rres@3 net@8 net@11 5.314
+.ENDS wire-C_0_011f-459_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-459_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-459_9-R_34_667m
+.ENDS wire90-459_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-361_8-R_34_667m a b
+Ccap@0 gnd net@14 1.327f
+Ccap@1 gnd net@8 1.327f
+Ccap@2 gnd net@11 1.327f
+Rres@0 net@14 a 2.09
+Rres@1 net@11 net@14 4.181
+Rres@2 b net@8 2.09
+Rres@3 net@8 net@11 4.181
+.ENDS wire-C_0_011f-361_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-361_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-361_8-R_34_667m
+.ENDS wire90-361_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-307-R_34_667m a b
+Ccap@0 gnd net@14 1.126f
+Ccap@1 gnd net@8 1.126f
+Ccap@2 gnd net@11 1.126f
+Rres@0 net@14 a 1.774
+Rres@1 net@11 net@14 3.548
+Rres@2 b net@8 1.774
+Rres@3 net@8 net@11 3.548
+.ENDS wire-C_0_011f-307-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-307-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-307-R_34_667m
+.ENDS wire90-307-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-258_6-R_34_667m a b
+Ccap@0 gnd net@14 0.948f
+Ccap@1 gnd net@8 0.948f
+Ccap@2 gnd net@11 0.948f
+Rres@0 net@14 a 1.494
+Rres@1 net@11 net@14 2.988
+Rres@2 b net@8 1.494
+Rres@3 net@8 net@11 2.988
+.ENDS wire-C_0_011f-258_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-258_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-258_6-R_34_667m
+.ENDS wire90-258_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-386_2-R_34_667m a b
+Ccap@0 gnd net@14 1.416f
+Ccap@1 gnd net@8 1.416f
+Ccap@2 gnd net@11 1.416f
+Rres@0 net@14 a 2.231
+Rres@1 net@11 net@14 4.463
+Rres@2 b net@8 2.231
+Rres@3 net@8 net@11 4.463
+.ENDS wire-C_0_011f-386_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-386_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-386_2-R_34_667m
+.ENDS wire90-386_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1409_3-R_34_667m a b
+Ccap@0 gnd net@14 5.167f
+Ccap@1 gnd net@8 5.167f
+Ccap@2 gnd net@11 5.167f
+Rres@0 net@14 a 8.143
+Rres@1 net@11 net@14 16.285
+Rres@2 b net@8 8.143
+Rres@3 net@8 net@11 16.285
+.ENDS wire-C_0_011f-1409_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1409_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1409_3-R_34_667m
+.ENDS wire90-1409_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-316-R_34_667m a b
+Ccap@0 gnd net@14 1.159f
+Ccap@1 gnd net@8 1.159f
+Ccap@2 gnd net@11 1.159f
+Rres@0 net@14 a 1.826
+Rres@1 net@11 net@14 3.652
+Rres@2 b net@8 1.826
+Rres@3 net@8 net@11 3.652
+.ENDS wire-C_0_011f-316-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-316-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-316-R_34_667m
+.ENDS wire90-316-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-324_9-R_34_667m a b
+Ccap@0 gnd net@14 1.191f
+Ccap@1 gnd net@8 1.191f
+Ccap@2 gnd net@11 1.191f
+Rres@0 net@14 a 1.877
+Rres@1 net@11 net@14 3.754
+Rres@2 b net@8 1.877
+Rres@3 net@8 net@11 3.754
+.ENDS wire-C_0_011f-324_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-324_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-324_9-R_34_667m
+.ENDS wire90-324_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-340_7-R_34_667m a b
+Ccap@0 gnd net@14 1.249f
+Ccap@1 gnd net@8 1.249f
+Ccap@2 gnd net@11 1.249f
+Rres@0 net@14 a 1.968
+Rres@1 net@11 net@14 3.937
+Rres@2 b net@8 1.968
+Rres@3 net@8 net@11 3.937
+.ENDS wire-C_0_011f-340_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-340_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-340_7-R_34_667m
+.ENDS wire90-340_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1083_5-R_34_667m a b
+Ccap@0 gnd net@14 3.973f
+Ccap@1 gnd net@8 3.973f
+Ccap@2 gnd net@11 3.973f
+Rres@0 net@14 a 6.26
+Rres@1 net@11 net@14 12.52
+Rres@2 b net@8 6.26
+Rres@3 net@8 net@11 12.52
+.ENDS wire-C_0_011f-1083_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1083_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1083_5-R_34_667m
+.ENDS wire90-1083_5-layer_1-width_3
+
+*** CELL: dockPartsK:moveC{sch}
+.SUBCKT moveC do[M] fire[M] fire[T] ilc[done] mc od[18] od[19] od[20] pred[D] 
++pred[T] succ[D] succ[T] torp
+Xarbiter2@0 net@1653 net@1652 torp net@860 arbiter2
+XctrAND4i@1 net@1475 net@1481 net@1498 od[20] fire[T] ctrAND4in30
+Xinv@39 do[M] net@1494 inv-X_10
+Xinv@43 fire[T] net@1388 inv-X_10
+Xinv@47 net@1415 net@1589 inv-X_10
+Xinv@49 fire[AE] net@1593 inv-X_10
+Xinv@50 exitLO net@1556 inv-X_10
+Xinv@51 od[18] ign[D] inv-X_10
+Xinv@52 od[19] ign[T] inv-X_10
+Xmlat1in1@0 fire[A] fire[AE] ilc[done] net@1561 mlat1in10i
+Xnand2@3 od[20] net@860 net@925 nand2-X_10
+Xnand2_sy@0 net@1612 net@1335 net@1574 nand2_sy-X_20
+Xnand2n@1 net@877 net@926 net@1334 nand2n-X_10
+Xnor2n@5 fire[A] okLO net@652 nor2n-X_20
+Xnor2n@8 exitLO fire[AE] net@1101 nor2n-X_10
+Xnor2n_sy@0 succ[D] succ[T] net@1619 nor2n_sy-X_10
+Xnor2n_sy@1 fire[AE] doLO fire[M] nor2n_sy-X_30
+XpredDri2@1 net@1401 mc torp predDri20wMC
+XpredORdr@0 fire[T] net@1650 mc do[M] predORdri20wMC
+XpredWait@0 ign[D] ign[T] net@1530 do[M] pred[D] pred[T] predWait
+Xwire90@18 net@860 net@652 wire90-795_4-layer_1-width_3
+Xwire90@19 net@1498 net@1494 wire90-459_9-layer_1-width_3
+Xwire90@21 net@1652 net@877 wire90-361_8-layer_1-width_3
+Xwire90@22 net@1653 net@1475 wire90-307-layer_1-width_3
+Xwire90@25 net@925 net@926 wire90-258_6-layer_1-width_3
+Xwire90@33 net@1101 net@1650 wire90-386_2-layer_1-width_3
+Xwire90@38 net@1401 fire[T] wire90-1409_3-layer_1-width_3
+Xwire90@42 net@1388 net@1415 wire90-316-layer_1-width_3
+Xwire90@43 net@1334 net@1335 wire90-324_9-layer_1-width_3
+Xwire90@49 okLO net@1530 wire90-795_4-layer_1-width_3
+Xwire90@51 net@1561 exitLO wire90-340_7-layer_1-width_3
+Xwire90@52 net@1556 doLO wire90-340_7-layer_1-width_3
+Xwire90@53 net@1574 fire[AE] wire90-1083_5-layer_1-width_3
+Xwire90@55 net@1481 net@1589 wire90-316-layer_1-width_3
+Xwire90@56 net@1593 fire[A] wire90-795_4-layer_1-width_3
+Xwire90@57 net@1612 net@1619 wire90-324_9-layer_1-width_3
+.ENDS moveC
+
+*** CELL: dockPartsK:moveLit{sch}
+.SUBCKT moveLit clS[F] clS[T] cl[F] cl[T] do[L] do[M] fire[L] fire[M] fire[T] 
++ilc[done] mc od[15] od[16] od[18] od[19] od[20] pred[D] pred[T] rd[F] rd[T] 
++sin sout succ[D] succ[T] torp
+XdStates@0 clS[F] clS[T] cl[F] cl[T] fire[M] mc od[15] od[16] od[18] od[19] 
++pred[D] pred[T] rd[F] rd[T] s[1] do[M] torp sin sout succ[D] succ[T] moveD
+XlitStage@0 do[L] fire[L] mc s[1] succ[D] succ[T] litStage
+XmoveC@0 do[M] fire[M] fire[T] ilc[done] mc od[18] od[19] od[20] pred[D] 
++pred[T] succ[D] succ[T] torp moveC
+.ENDS moveLit
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-247_2-R_34_667m a b
+Ccap@0 gnd net@14 0.906f
+Ccap@1 gnd net@8 0.906f
+Ccap@2 gnd net@11 0.906f
+Rres@0 net@14 a 1.428
+Rres@1 net@11 net@14 2.857
+Rres@2 b net@8 1.428
+Rres@3 net@8 net@11 2.857
+.ENDS wire-C_0_011f-247_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-247_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-247_2-R_34_667m
+.ENDS wire90-247_2-layer_1-width_3
+
+*** CELL: gaspL:aStageB{sch}
+.SUBCKT aStageB fire mc pred s[1] succ
+XctrAND2i@7 succ net@986 fire ctrAND2in100LT
+Xinv@4 net@987 s[1] inv-X_10
+Xinv@5 pred net@987 inv-X_5
+XpredDri2@1 fire mc pred predDri20wMC
+XsucDri20@1 fire succ sucDri20
+Xwire90@0 net@987 net@986 wire90-247_2-layer_1-width_3
+.ENDS aStageB
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-123_7-R_34_667m a b
+Ccap@0 gnd net@14 0.454f
+Ccap@1 gnd net@8 0.454f
+Ccap@2 gnd net@11 0.454f
+Rres@0 net@14 a 0.715
+Rres@1 net@11 net@14 1.429
+Rres@2 b net@8 0.715
+Rres@3 net@8 net@11 1.429
+.ENDS wire-C_0_011f-123_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-123_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-123_7-R_34_667m
+.ENDS wire90-123_7-layer_1-width_3
+
+*** CELL: latchPartsK:latchPointT{sch}
+.SUBCKT latchPointT hcl in[1] x[F] x[T]
+XPMOSx@0 in[1] hcl x[T] NMOSx-X_6
+XPMOSx@1 net@8 hcl x[F] NMOSx-X_3
+Xinv@0 in[1] net@105 invLT-X_5
+Xwire90@0 net@105 net@8 wire90-123_7-layer_1-width_3
+.ENDS latchPointT
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-180_9-R_34_667m a b
+Ccap@0 gnd net@14 0.663f
+Ccap@1 gnd net@8 0.663f
+Ccap@2 gnd net@11 0.663f
+Rres@0 net@14 a 1.045
+Rres@1 net@11 net@14 2.09
+Rres@2 b net@8 1.045
+Rres@3 net@8 net@11 2.09
+.ENDS wire-C_0_011f-180_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-180_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-180_9-R_34_667m
+.ENDS wire90-180_9-layer_1-width_3
+
+*** CELL: latchesK:raw1inLatchT{sch}
+.SUBCKT raw1inLatchT hcl[A] inA[1] out[T]
+XlatchFlo@0 out[T] net@29 latchKeep
+XlatchPoi@0 hcl[A] inA[1] net@7 out[T] latchPointT
+Xwire90@0 net@7 net@29 wire90-180_9-layer_1-width_3
+.ENDS raw1inLatchT
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-250_9-R_34_667m a b
+Ccap@0 gnd net@14 0.92f
+Ccap@1 gnd net@8 0.92f
+Ccap@2 gnd net@11 0.92f
+Rres@0 net@14 a 1.45
+Rres@1 net@11 net@14 2.899
+Rres@2 b net@8 1.45
+Rres@3 net@8 net@11 2.899
+.ENDS wire-C_0_011f-250_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-250_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-250_9-R_34_667m
+.ENDS wire90-250_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-214_6-R_34_667m a b
+Ccap@0 gnd net@14 0.787f
+Ccap@1 gnd net@8 0.787f
+Ccap@2 gnd net@11 0.787f
+Rres@0 net@14 a 1.24
+Rres@1 net@11 net@14 2.48
+Rres@2 b net@8 1.24
+Rres@3 net@8 net@11 2.48
+.ENDS wire-C_0_011f-214_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-214_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-214_6-R_34_667m
+.ENDS wire90-214_6-layer_1-width_3
+
+*** CELL: latchesK:latch1in20B{sch}
+.SUBCKT latch1in20B hcl in[1] out[1]
+Xhi2inLat@0 hcl in[1] net@19 raw1inLatchT
+Xinv@0 net@23 out[1] inv-X_20
+XinvLT@0 net@18 net@25 inv-X_5
+Xwire90@0 net@19 net@18 wire90-250_9-layer_1-width_3
+Xwire90@1 net@25 net@23 wire90-214_6-layer_1-width_3
+.ENDS latch1in20B
+
+*** CELL: registersL:ins20Bx18{sch}
+.SUBCKT ins20Bx18 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
++in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] 
++out[3] out[4] out[5] out[6] out[7] out[8] out[9]
+Xlx[1] hcl[1] in[1] out[1] latch1in20B
+Xlx[2] hcl[1] in[2] out[2] latch1in20B
+Xlx[3] hcl[1] in[3] out[3] latch1in20B
+Xlx[4] hcl[1] in[4] out[4] latch1in20B
+Xlx[5] hcl[1] in[5] out[5] latch1in20B
+Xlx[6] hcl[1] in[6] out[6] latch1in20B
+Xlx[7] hcl[1] in[7] out[7] latch1in20B
+Xlx[8] hcl[1] in[8] out[8] latch1in20B
+Xlx[9] hcl[1] in[9] out[9] latch1in20B
+Xlx[10] hcl[1] in[10] out[10] latch1in20B
+Xlx[11] hcl[1] in[11] out[11] latch1in20B
+Xlx[12] hcl[1] in[12] out[12] latch1in20B
+Xlx[13] hcl[1] in[13] out[13] latch1in20B
+Xlx[14] hcl[1] in[14] out[14] latch1in20B
+Xlx[15] hcl[1] in[15] out[15] latch1in20B
+Xlx[16] hcl[1] in[16] out[16] latch1in20B
+Xlx[17] hcl[1] in[17] out[17] latch1in20B
+Xlx[18] hcl[1] in[18] out[18] latch1in20B
+.ENDS ins20Bx18
+
+*** CELL: registersL:ins20Bx36{sch}
+.SUBCKT ins20Bx36 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] 
++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] 
++in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] 
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] 
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] 
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] 
++out[6] out[7] out[8] out[9]
+Xins20Bx1@0 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] 
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3] 
++out[4] out[5] out[6] out[7] out[8] out[9] ins20Bx18
+Xins20Bx1@1 hcl[1] in[28] in[29] in[30] in[31] in[32] in[33] in[34] in[35] 
++in[36] in[19] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] out[28] 
++out[29] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[19] 
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] ins20Bx18
+.ENDS ins20Bx36
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-302_4-R_34_667m a b
+Ccap@0 gnd net@14 1.109f
+Ccap@1 gnd net@8 1.109f
+Ccap@2 gnd net@11 1.109f
+Rres@0 net@14 a 1.747
+Rres@1 net@11 net@14 3.494
+Rres@2 b net@8 1.747
+Rres@3 net@8 net@11 3.494
+.ENDS wire-C_0_011f-302_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-302_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-302_4-R_34_667m
+.ENDS wire90-302_4-layer_1-width_3
+
+*** CELL: scanK:scanKhx2{sch}
+.SUBCKT scanKhx2 clS[F] clS[T] cl[F] cl[T] din[1] din[2] mc rd[F] rd[T] sin 
++sout
+XscanCell@1 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@20 
++scanCellKh
+XscanCell@2 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@19 sout 
++scanCellKh
+Xwire90@0 net@20 net@19 wire90-302_4-layer_1-width_3
+.ENDS scanKhx2
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3715_9-R_34_667m a b
+Ccap@0 gnd net@14 13.625f
+Ccap@1 gnd net@8 13.625f
+Ccap@2 gnd net@11 13.625f
+Rres@0 net@14 a 21.47
+Rres@1 net@11 net@14 42.939
+Rres@2 b net@8 21.47
+Rres@3 net@8 net@11 42.939
+.ENDS wire-C_0_011f-3715_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3715_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3715_9-R_34_667m
+.ENDS wire90-3715_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-447_1-R_34_667m a b
+Ccap@0 gnd net@14 1.639f
+Ccap@1 gnd net@8 1.639f
+Ccap@2 gnd net@11 1.639f
+Rres@0 net@14 a 2.583
+Rres@1 net@11 net@14 5.166
+Rres@2 b net@8 2.583
+Rres@3 net@8 net@11 5.166
+.ENDS wire-C_0_011f-447_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-447_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-447_1-R_34_667m
+.ENDS wire90-447_1-layer_1-width_3
+
+*** CELL: fifoL:m1stageD{sch}
+.SUBCKT m1stageD clS[F] clS[T] cl[F] cl[T] fire[1] in[10] in[11] in[12] 
++in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] 
++in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] 
++in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc 
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred rd[F] 
++rd[T] s[m2] sin sout succ
+XaStageB@0 fire[1] mc pred net@39 succ aStageB
+Xins20Bx3@0 net@6 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] 
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] 
++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] 
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] 
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] 
++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] 
++out[7] out[8] out[9] ins20Bx36
+XlatchDri@0 fire[1] take[1] latchDriver60
+XscanKhx2@0 clS[F] clS[T] cl[F] cl[T] s[m2] s[m1] mc rd[F] rd[T] sin sout 
++scanKhx2
+Xwire90@1 net@6 take[1] wire90-3715_9-layer_1-width_3
+Xwire90@2 net@39 s[m1] wire90-447_1-layer_1-width_3
+.ENDS m1stageD
+
+*** CELL: fifoL:m2stageD{sch}
+.SUBCKT m2stageD fire[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] 
++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] 
++in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc out[10] out[11] out[12] out[13] 
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] 
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] 
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] 
++out[6] out[7] out[8] out[9] pred s[m2] succ
+XaStageB@0 fire[1] mc pred s[m2] succ aStageB
+Xins20Bx3@0 net@6 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] 
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] 
++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] 
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] 
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] 
++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] 
++out[7] out[8] out[9] ins20Bx36
+XlatchDri@0 fire[1] take[1] latchDriver60
+Xwire90@1 net@6 take[1] wire90-3715_9-layer_1-width_3
+.ENDS m2stageD
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1239_6-R_26m a b
+Ccap@0 gnd net@14 4.545f
+Ccap@1 gnd net@8 4.545f
+Ccap@2 gnd net@11 4.545f
+Rres@0 net@14 a 5.372
+Rres@1 net@11 net@14 10.743
+Rres@2 b net@8 5.372
+Rres@3 net@8 net@11 10.743
+.ENDS wire-C_0_011f-1239_6-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1239_6-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1239_6-R_26m
+.ENDS wire90-1239_6-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-631_3-R_26m a b
+Ccap@0 gnd net@14 2.315f
+Ccap@1 gnd net@8 2.315f
+Ccap@2 gnd net@11 2.315f
+Rres@0 net@14 a 2.736
+Rres@1 net@11 net@14 5.471
+Rres@2 b net@8 2.736
+Rres@3 net@8 net@11 5.471
+.ENDS wire-C_0_011f-631_3-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-631_3-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-631_3-R_26m
+.ENDS wire90-631_3-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-605_4-R_26m a b
+Ccap@0 gnd net@14 2.22f
+Ccap@1 gnd net@8 2.22f
+Ccap@2 gnd net@11 2.22f
+Rres@0 net@14 a 2.623
+Rres@1 net@11 net@14 5.247
+Rres@2 b net@8 2.623
+Rres@3 net@8 net@11 5.247
+.ENDS wire-C_0_011f-605_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-605_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-605_4-R_26m
+.ENDS wire90-605_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-613_4-R_26m a b
+Ccap@0 gnd net@14 2.249f
+Ccap@1 gnd net@8 2.249f
+Ccap@2 gnd net@11 2.249f
+Rres@0 net@14 a 2.658
+Rres@1 net@11 net@14 5.316
+Rres@2 b net@8 2.658
+Rres@3 net@8 net@11 5.316
+.ENDS wire-C_0_011f-613_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-613_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-613_4-R_26m
+.ENDS wire90-613_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-623_9-R_26m a b
+Ccap@0 gnd net@14 2.288f
+Ccap@1 gnd net@8 2.288f
+Ccap@2 gnd net@11 2.288f
+Rres@0 net@14 a 2.704
+Rres@1 net@11 net@14 5.407
+Rres@2 b net@8 2.704
+Rres@3 net@8 net@11 5.407
+.ENDS wire-C_0_011f-623_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-623_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-623_9-R_26m
+.ENDS wire90-623_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-625_9-R_26m a b
+Ccap@0 gnd net@14 2.295f
+Ccap@1 gnd net@8 2.295f
+Ccap@2 gnd net@11 2.295f
+Rres@0 net@14 a 2.712
+Rres@1 net@11 net@14 5.424
+Rres@2 b net@8 2.712
+Rres@3 net@8 net@11 5.424
+.ENDS wire-C_0_011f-625_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-625_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-625_9-R_26m
+.ENDS wire90-625_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-607_8-R_26m a b
+Ccap@0 gnd net@14 2.229f
+Ccap@1 gnd net@8 2.229f
+Ccap@2 gnd net@11 2.229f
+Rres@0 net@14 a 2.634
+Rres@1 net@11 net@14 5.268
+Rres@2 b net@8 2.634
+Rres@3 net@8 net@11 5.268
+.ENDS wire-C_0_011f-607_8-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-607_8-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-607_8-R_26m
+.ENDS wire90-607_8-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-620_9-R_26m a b
+Ccap@0 gnd net@14 2.277f
+Ccap@1 gnd net@8 2.277f
+Ccap@2 gnd net@11 2.277f
+Rres@0 net@14 a 2.691
+Rres@1 net@11 net@14 5.381
+Rres@2 b net@8 2.691
+Rres@3 net@8 net@11 5.381
+.ENDS wire-C_0_011f-620_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-620_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-620_9-R_26m
+.ENDS wire90-620_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-612_5-R_26m a b
+Ccap@0 gnd net@14 2.246f
+Ccap@1 gnd net@8 2.246f
+Ccap@2 gnd net@11 2.246f
+Rres@0 net@14 a 2.654
+Rres@1 net@11 net@14 5.308
+Rres@2 b net@8 2.654
+Rres@3 net@8 net@11 5.308
+.ENDS wire-C_0_011f-612_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-612_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-612_5-R_26m
+.ENDS wire90-612_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-602_4-R_26m a b
+Ccap@0 gnd net@14 2.209f
+Ccap@1 gnd net@8 2.209f
+Ccap@2 gnd net@11 2.209f
+Rres@0 net@14 a 2.61
+Rres@1 net@11 net@14 5.221
+Rres@2 b net@8 2.61
+Rres@3 net@8 net@11 5.221
+.ENDS wire-C_0_011f-602_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-602_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-602_4-R_26m
+.ENDS wire90-602_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-607-R_26m a b
+Ccap@0 gnd net@14 2.226f
+Ccap@1 gnd net@8 2.226f
+Ccap@2 gnd net@11 2.226f
+Rres@0 net@14 a 2.63
+Rres@1 net@11 net@14 5.261
+Rres@2 b net@8 2.63
+Rres@3 net@8 net@11 5.261
+.ENDS wire-C_0_011f-607-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-607-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-607-R_26m
+.ENDS wire90-607-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-620_5-R_26m a b
+Ccap@0 gnd net@14 2.275f
+Ccap@1 gnd net@8 2.275f
+Ccap@2 gnd net@11 2.275f
+Rres@0 net@14 a 2.689
+Rres@1 net@11 net@14 5.378
+Rres@2 b net@8 2.689
+Rres@3 net@8 net@11 5.378
+.ENDS wire-C_0_011f-620_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-620_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-620_5-R_26m
+.ENDS wire90-620_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-624_5-R_26m a b
+Ccap@0 gnd net@14 2.29f
+Ccap@1 gnd net@8 2.29f
+Ccap@2 gnd net@11 2.29f
+Rres@0 net@14 a 2.706
+Rres@1 net@11 net@14 5.412
+Rres@2 b net@8 2.706
+Rres@3 net@8 net@11 5.412
+.ENDS wire-C_0_011f-624_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-624_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-624_5-R_26m
+.ENDS wire90-624_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-618-R_26m a b
+Ccap@0 gnd net@14 2.266f
+Ccap@1 gnd net@8 2.266f
+Ccap@2 gnd net@11 2.266f
+Rres@0 net@14 a 2.678
+Rres@1 net@11 net@14 5.356
+Rres@2 b net@8 2.678
+Rres@3 net@8 net@11 5.356
+.ENDS wire-C_0_011f-618-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-618-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-618-R_26m
+.ENDS wire90-618-layer_1-width_4
+
+*** CELL: fifoL:m12stageD{sch}
+.SUBCKT m12stageD clS[F] clS[T] cl[F] cl[T] fire[m1] fire[m2] in[10] in[11] 
++in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] 
++in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] 
++in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] 
++mc out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pout[13] 
++pout[14] pout[15] pout[16] pout[17] pout[18] pred rd[F] rd[T] sin sout succ
+Xinv[1] in[31] pout[13] inv-X_10
+Xinv[2] in[32] pout[14] inv-X_10
+Xinv[3] in[33] pout[15] inv-X_10
+Xinv[4] in[34] pout[16] inv-X_10
+Xinv[5] in[35] pout[17] inv-X_10
+Xinv[6] in[36] pout[18] inv-X_10
+Xm1stageD@1 clS[F] clS[T] cl[F] cl[T] fire[m1] m2[10] m2[11] m2[12] m2[13] 
++m2[14] m2[15] m2[16] m2[17] m2[18] m2[19] m2[1] m2[20] m2[21] m2[22] m2[23] 
++m2[24] m2[25] m2[26] m2[27] m2[28] m2[29] m2[2] m2[30] m2[31] m2[32] m2[33] 
++m2[34] m2[35] m2[36] m2[3] m2[4] m2[5] m2[6] m2[7] m2[8] m2[9] mc out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@53 rd[F] rd[T] 
++net@36 sin sout succ m1stageD
+Xm2stageD@2 fire[m2] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] 
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] 
++in[4] in[5] in[6] in[7] in[8] in[9] mc m2[10] m2[11] m2[12] m2[13] m2[14] 
++m2[15] m2[16] m2[17] m2[18] m2[19] m2[1] m2[20] m2[21] m2[22] m2[23] m2[24] 
++m2[25] m2[26] m2[27] m2[28] m2[29] m2[2] m2[30] m2[31] m2[32] m2[33] m2[34] 
++m2[35] m2[36] m2[3] m2[4] m2[5] m2[6] m2[7] m2[8] m2[9] pred s[m2] net@52 
++m2stageD
+Xwire90@0 net@52 net@53 wire90-1239_6-layer_1-width_4
+Xwire90@1 s[m2] net@36 wire90-631_3-layer_1-width_4
+Xwire90@2 m2[1] wire90@2_b wire90-605_4-layer_1-width_4
+Xwire90@3 m2[2] wire90@3_b wire90-613_4-layer_1-width_4
+Xwire90@4 m2[3] wire90@4_b wire90-605_4-layer_1-width_4
+Xwire90@5 m2[4] wire90@5_b wire90-623_9-layer_1-width_4
+Xwire90@6 m2[5] wire90@6_b wire90-605_4-layer_1-width_4
+Xwire90@7 m2[6] wire90@7_b wire90-625_9-layer_1-width_4
+Xwire90@8 m2[7] wire90@8_b wire90-607_8-layer_1-width_4
+Xwire90@9 m2[8] wire90@9_b wire90-620_9-layer_1-width_4
+Xwire90@10 m2[9] wire90@10_b wire90-605_4-layer_1-width_4
+Xwire90@11 m2[10] wire90@11_b wire90-612_5-layer_1-width_4
+Xwire90@12 m2[11] wire90@12_b wire90-602_4-layer_1-width_4
+Xwire90@13 m2[12] wire90@13_b wire90-607-layer_1-width_4
+Xwire90@14 m2[13] wire90@14_b wire90-602_4-layer_1-width_4
+Xwire90@15 m2[14] wire90@15_b wire90-620_5-layer_1-width_4
+Xwire90@16 m2[15] wire90@16_b wire90-602_4-layer_1-width_4
+Xwire90@17 m2[16] wire90@17_b wire90-624_5-layer_1-width_4
+Xwire90@18 m2[17] wire90@18_b wire90-602_4-layer_1-width_4
+Xwire90@19 m2[18] wire90@19_b wire90-618-layer_1-width_4
+Xwire90@20 m2[19] wire90@20_b wire90-605_4-layer_1-width_4
+Xwire90@21 m2[20] wire90@21_b wire90-613_4-layer_1-width_4
+Xwire90@22 m2[21] wire90@22_b wire90-605_4-layer_1-width_4
+Xwire90@23 m2[22] wire90@23_b wire90-623_9-layer_1-width_4
+Xwire90@24 m2[23] wire90@24_b wire90-605_4-layer_1-width_4
+Xwire90@25 m2[24] wire90@25_b wire90-625_9-layer_1-width_4
+Xwire90@26 m2[25] wire90@26_b wire90-607_8-layer_1-width_4
+Xwire90@27 m2[26] wire90@27_b wire90-620_9-layer_1-width_4
+Xwire90@28 m2[27] wire90@28_b wire90-605_4-layer_1-width_4
+Xwire90@29 m2[28] wire90@29_b wire90-612_5-layer_1-width_4
+Xwire90@30 m2[29] wire90@30_b wire90-602_4-layer_1-width_4
+Xwire90@31 m2[30] wire90@31_b wire90-607-layer_1-width_4
+Xwire90@32 m2[31] wire90@32_b wire90-602_4-layer_1-width_4
+Xwire90@33 m2[32] wire90@33_b wire90-620_5-layer_1-width_4
+Xwire90@34 m2[33] wire90@34_b wire90-602_4-layer_1-width_4
+Xwire90@35 m2[34] wire90@35_b wire90-624_5-layer_1-width_4
+Xwire90@36 m2[35] wire90@36_b wire90-602_4-layer_1-width_4
+Xwire90@37 m2[36] wire90@37_b wire90-618-layer_1-width_4
+.ENDS m12stageD
+
+*** CELL: redFour:nms2_sy{sch}
+.SUBCKT nms2_sy-X_40 d g g2
+Xnms2@0 d g g2 nms2-X_20
+Xnms2@1 d g2 g nms2-X_20
+.ENDS nms2_sy-X_40
+
+*** CELL: redFour:nand2_sy{sch}
+.SUBCKT nand2_sy-X_40 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_40
+XPMOS@1 out ina vdd PMOSx-X_40
+Xnms2_sy@0 out ina inb nms2_sy-X_40
+.ENDS nand2_sy-X_40
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-521_7-R_34_667m a b
+Ccap@0 gnd net@14 1.913f
+Ccap@1 gnd net@8 1.913f
+Ccap@2 gnd net@11 1.913f
+Rres@0 net@14 a 3.014
+Rres@1 net@11 net@14 6.029
+Rres@2 b net@8 3.014
+Rres@3 net@8 net@11 6.029
+.ENDS wire-C_0_011f-521_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-521_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-521_7-R_34_667m
+.ENDS wire90-521_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-509_8-R_34_667m a b
+Ccap@0 gnd net@14 1.869f
+Ccap@1 gnd net@8 1.869f
+Ccap@2 gnd net@11 1.869f
+Rres@0 net@14 a 2.946
+Rres@1 net@11 net@14 5.891
+Rres@2 b net@8 2.946
+Rres@3 net@8 net@11 5.891
+.ENDS wire-C_0_011f-509_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-509_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-509_8-R_34_667m
+.ENDS wire90-509_8-layer_1-width_3
+
+*** CELL: centersJ:ctrAND4in40{sch}
+.SUBCKT ctrAND4in40 inA inB inC inD out
+Xnand2_sy@0 net@58 net@43 out nand2_sy-X_40
+Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_10
+Xnor2n_sy@0 inD inC net@64 nor2n_sy-X_10
+Xwire90@0 net@64 net@43 wire90-521_7-layer_1-width_3
+Xwire90@2 net@61 net@58 wire90-509_8-layer_1-width_3
+.ENDS ctrAND4in40
+
+*** CELL: gaspL:odStage{sch}
+.SUBCKT odStage do[L] do[M] do[RQ] fire[ODE] fire[OD] mc pred s[1]
+XctrAND4i@0 net@863 do[RQ] do[L] do[M] fire[ODE] ctrAND4in40
+Xinv@0 net@863 s[1] inv-X_10
+Xinv@5 pred net@664 inv-X_5
+Xinv@16 fire[ODE] fire[OD] inv-X_60
+XpredDri2@0 fire[OD] mc pred predDri20wMC
+XsucDri20@3 fire[OD] do[RQ] sucDri20
+Xwire90@15 net@664 net@863 wire90-413_4-layer_1-width_3
+.ENDS odStage
+
+*** CELL: fifoL:odStageD{sch}
+.SUBCKT odStageD do[L] do[M] do[RQ] fire[ODE] in[10] in[11] in[12] in[13] 
++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] 
++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] 
++in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred s[1]
+Xins20Bx3@0 net@6 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] 
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] 
++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] 
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] 
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] 
++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] 
++out[7] out[8] out[9] ins20Bx36
+XlatchDri@0 net@3 take[1] latchDriver60
+XodStage@0 do[L] do[M] do[RQ] fire[ODE] net@3 mc pred s[1] odStage
+Xwire90@1 net@6 take[1] wire90-3715_9-layer_1-width_3
+.ENDS odStageD
+
+*** CELL: latchesK:latch2in20A{sch}
+.SUBCKT latch2in20A hcl[A] hcl[B] inA[1] inB[1] out[1]
+Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@36 raw2inLatchF
+XinvLT@1 net@16 out[1] inv-X_20
+Xwire90@1 net@36 net@16 wire90-242_1-layer_1-width_3
+.ENDS latch2in20A
+
+*** CELL: registersL:ins2in20Ax36{sch}
+.SUBCKT ins2in20Ax36 hcl[A][1] hcl[B][1] inA[10] inA[11] inA[12] inA[13] 
++inA[14] inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] 
++inA[22] inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] 
++inA[30] inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] 
++inA[6] inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] 
++inB[16] inB[17] inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] 
++inB[24] inB[25] inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] 
++inB[32] inB[33] inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] 
++inB[8] inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] 
++out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] 
++out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] 
++out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9]
+Xlx[1] hcl[A][1] hcl[B][1] inA[1] inB[1] out[1] latch2in20A
+Xlx[2] hcl[A][1] hcl[B][1] inA[2] inB[2] out[2] latch2in20A
+Xlx[3] hcl[A][1] hcl[B][1] inA[3] inB[3] out[3] latch2in20A
+Xlx[4] hcl[A][1] hcl[B][1] inA[4] inB[4] out[4] latch2in20A
+Xlx[5] hcl[A][1] hcl[B][1] inA[5] inB[5] out[5] latch2in20A
+Xlx[6] hcl[A][1] hcl[B][1] inA[6] inB[6] out[6] latch2in20A
+Xlx[7] hcl[A][1] hcl[B][1] inA[7] inB[7] out[7] latch2in20A
+Xlx[8] hcl[A][1] hcl[B][1] inA[8] inB[8] out[8] latch2in20A
+Xlx[9] hcl[A][1] hcl[B][1] inA[9] inB[9] out[9] latch2in20A
+Xlx[10] hcl[A][1] hcl[B][1] inA[10] inB[10] out[10] latch2in20A
+Xlx[11] hcl[A][1] hcl[B][1] inA[11] inB[11] out[11] latch2in20A
+Xlx[12] hcl[A][1] hcl[B][1] inA[12] inB[12] out[12] latch2in20A
+Xlx[13] hcl[A][1] hcl[B][1] inA[13] inB[13] out[13] latch2in20A
+Xlx[14] hcl[A][1] hcl[B][1] inA[14] inB[14] out[14] latch2in20A
+Xlx[15] hcl[A][1] hcl[B][1] inA[15] inB[15] out[15] latch2in20A
+Xlx[16] hcl[A][1] hcl[B][1] inA[16] inB[16] out[16] latch2in20A
+Xlx[17] hcl[A][1] hcl[B][1] inA[17] inB[17] out[17] latch2in20A
+Xlx[18] hcl[A][1] hcl[B][1] inA[18] inB[18] out[18] latch2in20A
+Xlx[19] hcl[A][1] hcl[B][1] inA[19] inB[19] out[19] latch2in20A
+Xlx[20] hcl[A][1] hcl[B][1] inA[20] inB[20] out[20] latch2in20A
+Xlx[21] hcl[A][1] hcl[B][1] inA[21] inB[21] out[21] latch2in20A
+Xlx[22] hcl[A][1] hcl[B][1] inA[22] inB[22] out[22] latch2in20A
+Xlx[23] hcl[A][1] hcl[B][1] inA[23] inB[23] out[23] latch2in20A
+Xlx[24] hcl[A][1] hcl[B][1] inA[24] inB[24] out[24] latch2in20A
+Xlx[25] hcl[A][1] hcl[B][1] inA[25] inB[25] out[25] latch2in20A
+Xlx[26] hcl[A][1] hcl[B][1] inA[26] inB[26] out[26] latch2in20A
+Xlx[27] hcl[A][1] hcl[B][1] inA[27] inB[27] out[27] latch2in20A
+Xlx[28] hcl[A][1] hcl[B][1] inA[28] inB[28] out[28] latch2in20A
+Xlx[29] hcl[A][1] hcl[B][1] inA[29] inB[29] out[29] latch2in20A
+Xlx[30] hcl[A][1] hcl[B][1] inA[30] inB[30] out[30] latch2in20A
+Xlx[31] hcl[A][1] hcl[B][1] inA[31] inB[31] out[31] latch2in20A
+Xlx[32] hcl[A][1] hcl[B][1] inA[32] inB[32] out[32] latch2in20A
+Xlx[33] hcl[A][1] hcl[B][1] inA[33] inB[33] out[33] latch2in20A
+Xlx[34] hcl[A][1] hcl[B][1] inA[34] inB[34] out[34] latch2in20A
+Xlx[35] hcl[A][1] hcl[B][1] inA[35] inB[35] out[35] latch2in20A
+Xlx[36] hcl[A][1] hcl[B][1] inA[36] inB[36] out[36] latch2in20A
+.ENDS ins2in20Ax36
+
+*** CELL: gatesK:andOrInv5{sch}
+.SUBCKT andOrInv5 inA inB inC inD out
+XPMOSx@0 out inA net@42 PMOSx-X_5
+XPMOSx@1 out inB net@42 PMOSx-X_5
+XPMOSx@2 out inC net@39 PMOSx-X_5
+XPMOSx@3 out inD net@39 PMOSx-X_5
+XPMOSx@4 net@39 inA vdd PMOSx-X_5
+XPMOSx@5 net@39 inB vdd PMOSx-X_5
+XPMOSx@6 net@42 inC vdd PMOSx-X_5
+XPMOSx@7 net@42 inD vdd PMOSx-X_5
+Xnms2@0 out inA inB nms2-X_5
+Xnms2@2 out inD inC nms2-X_5
+.ENDS andOrInv5
+
+*** CELL: redFour:nms2_sy{sch}
+.SUBCKT nms2_sy-X_4 d g g2
+Xnms2@0 d g g2 nms2-X_2
+Xnms2@1 d g2 g nms2-X_2
+.ENDS nms2_sy-X_4
+
+*** CELL: redFour:nand2_sy{sch}
+.SUBCKT nand2_sy-X_4 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_4
+XPMOS@1 out ina vdd PMOSx-X_4
+Xnms2_sy@0 out ina inb nms2_sy-X_4
+.ENDS nand2_sy-X_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-210_3-R_34_667m a b
+Ccap@0 gnd net@14 0.771f
+Ccap@1 gnd net@8 0.771f
+Ccap@2 gnd net@11 0.771f
+Rres@0 net@14 a 1.215
+Rres@1 net@11 net@14 2.43
+Rres@2 b net@8 1.215
+Rres@3 net@8 net@11 2.43
+.ENDS wire-C_0_011f-210_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-210_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-210_3-R_34_667m
+.ENDS wire90-210_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-353_2-R_34_667m a b
+Ccap@0 gnd net@14 1.295f
+Ccap@1 gnd net@8 1.295f
+Ccap@2 gnd net@11 1.295f
+Rres@0 net@14 a 2.041
+Rres@1 net@11 net@14 4.081
+Rres@2 b net@8 2.041
+Rres@3 net@8 net@11 4.081
+.ENDS wire-C_0_011f-353_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-353_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-353_2-R_34_667m
+.ENDS wire90-353_2-layer_1-width_3
+
+*** CELL: latchesK:rsLatchC{sch}
+.SUBCKT rsLatchC mc out outBar resetA resetB setA setB
+XNMOSx@1 net@188 mc gnd NMOSx-X_4
+XPMOSx@3 net@188 net@177 vdd PMOSx-X_10
+XPMOSx@4 net@274 resetA vdd PMOSx-X_5
+XPMOSx@5 net@274 resetB vdd PMOSx-X_5
+XPMOSx@6 net@226 outBar net@273 PMOSx-X_5
+XPMOSx@7 net@273 mc net@274 PMOSx-X_5
+Xinv@0 net@226 outBar inv-X_20
+Xinv@2 outBar out inv-X_20
+Xnand2_sy@0 setA setB net@267 nand2_sy-X_4
+Xnms2@1 net@188 outBar net@177 nms2-X_2
+Xnms2_sy@0 net@226 resetB resetA nms2_sy-X_10
+Xwire90@0 net@267 net@177 wire90-210_3-layer_1-width_3
+Xwire90@1 net@188 net@226 wire90-353_2-layer_1-width_3
+.ENDS rsLatchC
+
+*** CELL: driversL:sucDri20plain{sch}
+.SUBCKT sucDri20plain in succ
+XPMOSx@0 succ in vdd PMOSx-X_20
+Xinv@1 succ net@94 inv-X_4
+Xnms2@0 succ net@127 in nms2-X_2
+Xwire90@0 net@127 net@94 wire90-124_7-layer_1-width_3
+.ENDS sucDri20plain
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-314_7-R_34_667m a b
+Ccap@0 gnd net@14 1.154f
+Ccap@1 gnd net@8 1.154f
+Ccap@2 gnd net@11 1.154f
+Rres@0 net@14 a 1.818
+Rres@1 net@11 net@14 3.637
+Rres@2 b net@8 1.818
+Rres@3 net@8 net@11 3.637
+.ENDS wire-C_0_011f-314_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-314_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-314_7-R_34_667m
+.ENDS wire90-314_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1526_5-R_34_667m a b
+Ccap@0 gnd net@14 5.597f
+Ccap@1 gnd net@8 5.597f
+Ccap@2 gnd net@11 5.597f
+Rres@0 net@14 a 8.82
+Rres@1 net@11 net@14 17.64
+Rres@2 b net@8 8.82
+Rres@3 net@8 net@11 17.64
+.ENDS wire-C_0_011f-1526_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1526_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1526_5-R_34_667m
+.ENDS wire90-1526_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1328_7-R_34_667m a b
+Ccap@0 gnd net@14 4.872f
+Ccap@1 gnd net@8 4.872f
+Ccap@2 gnd net@11 4.872f
+Rres@0 net@14 a 7.677
+Rres@1 net@11 net@14 15.354
+Rres@2 b net@8 7.677
+Rres@3 net@8 net@11 15.354
+.ENDS wire-C_0_011f-1328_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1328_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1328_7-R_34_667m
+.ENDS wire90-1328_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-234_9-R_34_667m a b
+Ccap@0 gnd net@14 0.861f
+Ccap@1 gnd net@8 0.861f
+Ccap@2 gnd net@11 0.861f
+Rres@0 net@14 a 1.357
+Rres@1 net@11 net@14 2.714
+Rres@2 b net@8 1.357
+Rres@3 net@8 net@11 2.714
+.ENDS wire-C_0_011f-234_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-234_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-234_9-R_34_667m
+.ENDS wire90-234_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1122_1-R_34_667m a b
+Ccap@0 gnd net@14 4.114f
+Ccap@1 gnd net@8 4.114f
+Ccap@2 gnd net@11 4.114f
+Rres@0 net@14 a 6.483
+Rres@1 net@11 net@14 12.966
+Rres@2 b net@8 6.483
+Rres@3 net@8 net@11 12.966
+.ENDS wire-C_0_011f-1122_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1122_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1122_1-R_34_667m
+.ENDS wire90-1122_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-820_7-R_34_667m a b
+Ccap@0 gnd net@14 3.009f
+Ccap@1 gnd net@8 3.009f
+Ccap@2 gnd net@11 3.009f
+Rres@0 net@14 a 4.742
+Rres@1 net@11 net@14 9.484
+Rres@2 b net@8 4.742
+Rres@3 net@8 net@11 9.484
+.ENDS wire-C_0_011f-820_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-820_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-820_7-R_34_667m
+.ENDS wire90-820_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-228_4-R_34_667m a b
+Ccap@0 gnd net@14 0.837f
+Ccap@1 gnd net@8 0.837f
+Ccap@2 gnd net@11 0.837f
+Rres@0 net@14 a 1.32
+Rres@1 net@11 net@14 2.639
+Rres@2 b net@8 1.32
+Rres@3 net@8 net@11 2.639
+.ENDS wire-C_0_011f-228_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-228_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-228_4-R_34_667m
+.ENDS wire90-228_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-707_6-R_34_667m a b
+Ccap@0 gnd net@14 2.595f
+Ccap@1 gnd net@8 2.595f
+Ccap@2 gnd net@11 2.595f
+Rres@0 net@14 a 4.088
+Rres@1 net@11 net@14 8.177
+Rres@2 b net@8 4.088
+Rres@3 net@8 net@11 8.177
+.ENDS wire-C_0_011f-707_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-707_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-707_6-R_34_667m
+.ENDS wire90-707_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-812_8-R_34_667m a b
+Ccap@0 gnd net@14 2.98f
+Ccap@1 gnd net@8 2.98f
+Ccap@2 gnd net@11 2.98f
+Rres@0 net@14 a 4.696
+Rres@1 net@11 net@14 9.392
+Rres@2 b net@8 4.696
+Rres@3 net@8 net@11 9.392
+.ENDS wire-C_0_011f-812_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-812_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-812_8-R_34_667m
+.ENDS wire90-812_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-428_6-R_34_667m a b
+Ccap@0 gnd net@14 1.572f
+Ccap@1 gnd net@8 1.572f
+Ccap@2 gnd net@11 1.572f
+Rres@0 net@14 a 2.476
+Rres@1 net@11 net@14 4.953
+Rres@2 b net@8 2.476
+Rres@3 net@8 net@11 4.953
+.ENDS wire-C_0_011f-428_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-428_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-428_6-R_34_667m
+.ENDS wire90-428_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-672_2-R_34_667m a b
+Ccap@0 gnd net@14 2.465f
+Ccap@1 gnd net@8 2.465f
+Ccap@2 gnd net@11 2.465f
+Rres@0 net@14 a 3.884
+Rres@1 net@11 net@14 7.768
+Rres@2 b net@8 3.884
+Rres@3 net@8 net@11 7.768
+.ENDS wire-C_0_011f-672_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-672_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-672_2-R_34_667m
+.ENDS wire90-672_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-495_5-R_34_667m a b
+Ccap@0 gnd net@14 1.817f
+Ccap@1 gnd net@8 1.817f
+Ccap@2 gnd net@11 1.817f
+Rres@0 net@14 a 2.863
+Rres@1 net@11 net@14 5.726
+Rres@2 b net@8 2.863
+Rres@3 net@8 net@11 5.726
+.ENDS wire-C_0_011f-495_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-495_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-495_5-R_34_667m
+.ENDS wire90-495_5-layer_1-width_3
+
+*** CELL: gaspL:rqStage{sch}
+.SUBCKT rqStage do[RQ] do[epi] do[ring] in[RQ] in[Z] mc s[1] s[2] s[3] s[4] 
++tail take[E] take[R]
+XandOrInv@0 nzrq fire[R] fire[E] tailBAR net@239 andOrInv5
+XctrAND2i@0 net@324 net@129 fireB ctrAND2in30
+XctrAND3i@0 net@8 do[ring] net@124 fire[E] ctrAND3in30
+XctrAND4i@1 do[ring] net@205 net@193 net@197 fire[R] ctrAND4in30
+Xinv@12 do[epi] net@7 inv-X_5
+Xinv@13 net@8 s[1] inv-X_5
+Xinv@14 net@197 s[2] inv-X_5
+Xinv@15 net@193 s[4] inv-X_5
+Xinv@16 net@205 s[3] inv-X_5
+Xinv@17 do[RQ] net@324 inv-X_10
+Xinv@18 tail net@305 inv-X_10
+XlatchDri@0 fire[R] take[R] latchDriver60
+XlatchDri@1 fire[E] take[E] latchDriver60
+Xnor2n_sy@2 in[Z] in[RQ] net@287 nor2n_sy-X_10
+XpredDri2@0 net@121 mc do[epi] predDri20wMC
+XpredORdr@0 net@142 net@139 mc do[RQ] predORdri20wMC
+XrsLatchC@0 mc net@105 filling fire[R] in[Z] fire[E] tail rsLatchC
+XrsLatchC@1 mc net@40 draining fire[R] in[Z] fireB nzrq rsLatchC
+XsucDri20@1 net@240 do[ring] sucDri20plain
+Xwire90@0 net@7 net@8 wire90-314_7-layer_1-width_3
+Xwire90@2 net@142 fire[R] wire90-1526_5-layer_1-width_3
+Xwire90@3 net@121 fire[E] wire90-1328_7-layer_1-width_3
+Xwire90@4 net@124 net@105 wire90-234_9-layer_1-width_3
+Xwire90@5 filling net@197 wire90-1122_1-layer_1-width_3
+Xwire90@6 draining net@193 wire90-820_7-layer_1-width_3
+Xwire90@7 net@129 net@40 wire90-228_4-layer_1-width_3
+Xwire90@8 net@324 net@205 wire90-707_6-layer_1-width_3
+Xwire90@9 net@139 fireB wire90-812_8-layer_1-width_3
+Xwire90@14 net@239 net@240 wire90-428_6-layer_1-width_3
+Xwire90@17 nzrq net@287 wire90-672_2-layer_1-width_3
+Xwire90@18 net@305 tailBAR wire90-495_5-layer_1-width_3
+.ENDS rqStage
+
+*** CELL: fifoL:rqStageD{sch}
+.SUBCKT rqStageD do[RQ] do[epi] do[ring] inE[10] inE[11] inE[12] inE[13] 
++inE[14] inE[15] inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] 
++inE[22] inE[23] inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] 
++inE[30] inE[31] inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] 
++inE[6] inE[7] inE[8] inE[9] inR[10] inR[11] inR[12] inR[13] inR[14] inR[15] 
++inR[16] inR[17] inR[18] inR[19] inR[1] inR[20] inR[21] inR[22] inR[23] 
++inR[24] inR[25] inR[26] inR[27] inR[28] inR[29] inR[2] inR[30] inR[31] 
++inR[32] inR[33] inR[34] inR[35] inR[36] inR[3] inR[4] inR[5] inR[6] inR[7] 
++inR[8] inR[9] mc olcZ out[10] out[11] out[12] out[13] out[14] out[15] out[16] 
++out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] 
++out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] 
++out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] 
++out[9] s[1] s[2] s[3] s[4]
+XbitAssig@0 bitAssignments
+Xins2in20@1 net@49 net@47 inR[10] inR[11] inR[12] inR[13] inR[14] inR[15] 
++inR[16] inR[17] inR[18] inR[19] inR[1] inR[20] inR[21] inR[22] inR[23] 
++inR[24] inR[25] inR[26] inR[27] inR[28] inR[29] inR[2] inR[30] inR[31] 
++inR[32] inR[33] inR[34] inR[35] inR[36] inR[3] inR[4] inR[5] inR[6] inR[7] 
++inR[8] inR[9] inE[10] inE[11] inE[12] inE[13] inE[14] inE[15] inE[16] inE[17] 
++inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] inE[23] inE[24] inE[25] 
++inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] inE[31] inE[32] inE[33] 
++inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7] inE[8] inE[9] 
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax36
+XrqStage@0 do[RQ] do[epi] do[ring] inR[30] olcZ mc s[1] s[2] s[3] s[4] 
++inE[21] take[E] take[R] rqStage
+Xwire90@2 take[R] net@49 wire90-242_1-layer_1-width_3
+Xwire90@3 take[E] net@47 wire90-242_1-layer_1-width_3
+.ENDS rqStageD
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1358_4-R_26m a b
+Ccap@0 gnd net@14 4.981f
+Ccap@1 gnd net@8 4.981f
+Ccap@2 gnd net@11 4.981f
+Rres@0 net@14 a 5.886
+Rres@1 net@11 net@14 11.773
+Rres@2 b net@8 5.886
+Rres@3 net@8 net@11 11.773
+.ENDS wire-C_0_011f-1358_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1358_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1358_4-R_26m
+.ENDS wire90-1358_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-641-R_26m a b
+Ccap@0 gnd net@14 2.35f
+Ccap@1 gnd net@8 2.35f
+Ccap@2 gnd net@11 2.35f
+Rres@0 net@14 a 2.778
+Rres@1 net@11 net@14 5.555
+Rres@2 b net@8 2.778
+Rres@3 net@8 net@11 5.555
+.ENDS wire-C_0_011f-641-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-641-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-641-R_26m
+.ENDS wire90-641-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-644-R_26m a b
+Ccap@0 gnd net@14 2.361f
+Ccap@1 gnd net@8 2.361f
+Ccap@2 gnd net@11 2.361f
+Rres@0 net@14 a 2.791
+Rres@1 net@11 net@14 5.581
+Rres@2 b net@8 2.791
+Rres@3 net@8 net@11 5.581
+.ENDS wire-C_0_011f-644-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-644-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-644-R_26m
+.ENDS wire90-644-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-647-R_26m a b
+Ccap@0 gnd net@14 2.372f
+Ccap@1 gnd net@8 2.372f
+Ccap@2 gnd net@11 2.372f
+Rres@0 net@14 a 2.804
+Rres@1 net@11 net@14 5.607
+Rres@2 b net@8 2.804
+Rres@3 net@8 net@11 5.607
+.ENDS wire-C_0_011f-647-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-647-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-647-R_26m
+.ENDS wire90-647-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-638-R_26m a b
+Ccap@0 gnd net@14 2.339f
+Ccap@1 gnd net@8 2.339f
+Ccap@2 gnd net@11 2.339f
+Rres@0 net@14 a 2.765
+Rres@1 net@11 net@14 5.529
+Rres@2 b net@8 2.765
+Rres@3 net@8 net@11 5.529
+.ENDS wire-C_0_011f-638-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-638-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-638-R_26m
+.ENDS wire90-638-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-654-R_26m a b
+Ccap@0 gnd net@14 2.398f
+Ccap@1 gnd net@8 2.398f
+Ccap@2 gnd net@11 2.398f
+Rres@0 net@14 a 2.834
+Rres@1 net@11 net@14 5.668
+Rres@2 b net@8 2.834
+Rres@3 net@8 net@11 5.668
+.ENDS wire-C_0_011f-654-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-654-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-654-R_26m
+.ENDS wire90-654-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-636_5-R_26m a b
+Ccap@0 gnd net@14 2.334f
+Ccap@1 gnd net@8 2.334f
+Ccap@2 gnd net@11 2.334f
+Rres@0 net@14 a 2.758
+Rres@1 net@11 net@14 5.516
+Rres@2 b net@8 2.758
+Rres@3 net@8 net@11 5.516
+.ENDS wire-C_0_011f-636_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-636_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-636_5-R_26m
+.ENDS wire90-636_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-645_5-R_26m a b
+Ccap@0 gnd net@14 2.367f
+Ccap@1 gnd net@8 2.367f
+Ccap@2 gnd net@11 2.367f
+Rres@0 net@14 a 2.797
+Rres@1 net@11 net@14 5.594
+Rres@2 b net@8 2.797
+Rres@3 net@8 net@11 5.594
+.ENDS wire-C_0_011f-645_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-645_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-645_5-R_26m
+.ENDS wire90-645_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-639_5-R_26m a b
+Ccap@0 gnd net@14 2.345f
+Ccap@1 gnd net@8 2.345f
+Ccap@2 gnd net@11 2.345f
+Rres@0 net@14 a 2.771
+Rres@1 net@11 net@14 5.542
+Rres@2 b net@8 2.771
+Rres@3 net@8 net@11 5.542
+.ENDS wire-C_0_011f-639_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-639_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-639_5-R_26m
+.ENDS wire90-639_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-604_5-R_26m a b
+Ccap@0 gnd net@14 2.216f
+Ccap@1 gnd net@8 2.216f
+Ccap@2 gnd net@11 2.216f
+Rres@0 net@14 a 2.619
+Rres@1 net@11 net@14 5.239
+Rres@2 b net@8 2.619
+Rres@3 net@8 net@11 5.239
+.ENDS wire-C_0_011f-604_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-604_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-604_5-R_26m
+.ENDS wire90-604_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-625-R_26m a b
+Ccap@0 gnd net@14 2.292f
+Ccap@1 gnd net@8 2.292f
+Ccap@2 gnd net@11 2.292f
+Rres@0 net@14 a 2.708
+Rres@1 net@11 net@14 5.417
+Rres@2 b net@8 2.708
+Rres@3 net@8 net@11 5.417
+.ENDS wire-C_0_011f-625-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-625-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-625-R_26m
+.ENDS wire90-625-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-604_6-R_26m a b
+Ccap@0 gnd net@14 2.217f
+Ccap@1 gnd net@8 2.217f
+Ccap@2 gnd net@11 2.217f
+Rres@0 net@14 a 2.62
+Rres@1 net@11 net@14 5.24
+Rres@2 b net@8 2.62
+Rres@3 net@8 net@11 5.24
+.ENDS wire-C_0_011f-604_6-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-604_6-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-604_6-R_26m
+.ENDS wire90-604_6-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-623-R_26m a b
+Ccap@0 gnd net@14 2.284f
+Ccap@1 gnd net@8 2.284f
+Ccap@2 gnd net@11 2.284f
+Rres@0 net@14 a 2.7
+Rres@1 net@11 net@14 5.399
+Rres@2 b net@8 2.7
+Rres@3 net@8 net@11 5.399
+.ENDS wire-C_0_011f-623-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-623-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-623-R_26m
+.ENDS wire90-623-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-597_9-R_26m a b
+Ccap@0 gnd net@14 2.192f
+Ccap@1 gnd net@8 2.192f
+Ccap@2 gnd net@11 2.192f
+Rres@0 net@14 a 2.591
+Rres@1 net@11 net@14 5.182
+Rres@2 b net@8 2.591
+Rres@3 net@8 net@11 5.182
+.ENDS wire-C_0_011f-597_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-597_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-597_9-R_26m
+.ENDS wire90-597_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2012_6-R_26m a b
+Ccap@0 gnd net@14 7.38f
+Ccap@1 gnd net@8 7.38f
+Ccap@2 gnd net@11 7.38f
+Rres@0 net@14 a 8.721
+Rres@1 net@11 net@14 17.443
+Rres@2 b net@8 8.721
+Rres@3 net@8 net@11 17.443
+.ENDS wire-C_0_011f-2012_6-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2012_6-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2012_6-R_26m
+.ENDS wire90-2012_6-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1745_9-R_26m a b
+Ccap@0 gnd net@14 6.402f
+Ccap@1 gnd net@8 6.402f
+Ccap@2 gnd net@11 6.402f
+Rres@0 net@14 a 7.566
+Rres@1 net@11 net@14 15.131
+Rres@2 b net@8 7.566
+Rres@3 net@8 net@11 15.131
+.ENDS wire-C_0_011f-1745_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1745_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1745_9-R_26m
+.ENDS wire90-1745_9-layer_1-width_4
+
+*** CELL: fifoL:odRQstageD{sch}
+.SUBCKT odRQstageD clS[F] clS[T] cl[F] cl[T] do[L] do[M] do[epi] do[ring] 
++fire[ODE] inE[10] inE[11] inE[12] inE[13] inE[14] inE[15] inE[16] inE[17] 
++inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] inE[23] inE[24] inE[25] 
++inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] inE[31] inE[32] inE[33] 
++inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7] inE[8] inE[9] 
++in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] 
++in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] 
++in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] 
++in[7] in[8] in[9] mc od[10] od[11] od[12] od[13] od[14] od[15] od[16] od[17] 
++od[18] od[19] od[1] od[20] od[2] od[3] od[4] od[5] od[6] od[7] od[8] od[9] 
++olcZ out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred rd[F] 
++rd[T] sin sout
+XodStageD@1 do[L] do[M] net@17 fire[ODE] in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc od[10] od[11] 
++od[12] od[13] od[14] od[15] od[16] od[17] od[18] od[19] od[1] od[20] od[21] 
++od[22] od[23] od[24] od[25] od[26] od[27] od[28] od[29] od[2] od[30] od[31] 
++od[32] od[33] od[34] od[35] od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] 
++pred s[1] odStageD
+XrqStageD@0 net@63 do[epi] do[ring] inE[10] inE[11] inE[12] inE[13] inE[14] 
++inE[15] inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] 
++inE[23] inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] 
++inE[31] inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] 
++inE[7] inE[8] inE[9] od[10] od[11] od[12] od[13] od[14] od[15] od[16] od[17] 
++od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25] od[26] od[27] 
++od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35] od[36] od[3] 
++od[4] od[5] od[6] od[7] od[8] od[9] mc olcZ out[10] out[11] out[12] out[13] 
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] 
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] 
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] 
++out[6] out[7] out[8] out[9] s[2] s[3] s[4] s[5] rqStageD
+XscanKhx5@0 clS[F] clS[T] cl[F] cl[T] s[1] s[2] s[3] s[4] s[5] mc rd[F] rd[T] 
++sin sout scanKhx5
+Xwire90@0 net@17 net@63 wire90-1358_4-layer_1-width_4
+Xwire90@1 od[1] wire90@1_b wire90-641-layer_1-width_4
+Xwire90@2 od[2] wire90@2_b wire90-641-layer_1-width_4
+Xwire90@3 od[3] wire90@3_b wire90-644-layer_1-width_4
+Xwire90@4 od[4] wire90@4_b wire90-647-layer_1-width_4
+Xwire90@5 od[5] wire90@5_b wire90-638-layer_1-width_4
+Xwire90@6 od[6] wire90@6_b wire90-654-layer_1-width_4
+Xwire90@7 od[7] wire90@7_b wire90-636_5-layer_1-width_4
+Xwire90@8 od[8] wire90@8_b wire90-645_5-layer_1-width_4
+Xwire90@9 od[9] wire90@9_b wire90-639_5-layer_1-width_4
+Xwire90@10 od[10] wire90@10_b wire90-612_5-layer_1-width_4
+Xwire90@11 od[11] wire90@11_b wire90-602_4-layer_1-width_4
+Xwire90@12 od[12] wire90@12_b wire90-604_5-layer_1-width_4
+Xwire90@13 od[13] wire90@13_b wire90-605_4-layer_1-width_4
+Xwire90@14 od[14] wire90@14_b wire90-625-layer_1-width_4
+Xwire90@15 od[15] wire90@15_b wire90-604_6-layer_1-width_4
+Xwire90@16 od[16] wire90@16_b wire90-623-layer_1-width_4
+Xwire90@17 od[17] wire90@17_b wire90-597_9-layer_1-width_4
+Xwire90@18 od[18] wire90@18_b wire90-618-layer_1-width_4
+Xwire90@19 od[19] wire90@19_b wire90-641-layer_1-width_4
+Xwire90@20 od[20] wire90@20_b wire90-641-layer_1-width_4
+Xwire90@21 od[21] wire90@21_b wire90-2012_6-layer_1-width_4
+Xwire90@22 od[22] wire90@22_b wire90-647-layer_1-width_4
+Xwire90@23 od[23] wire90@23_b wire90-638-layer_1-width_4
+Xwire90@24 od[24] wire90@24_b wire90-654-layer_1-width_4
+Xwire90@25 od[25] wire90@25_b wire90-636_5-layer_1-width_4
+Xwire90@26 od[26] wire90@26_b wire90-645_5-layer_1-width_4
+Xwire90@27 od[27] wire90@27_b wire90-639_5-layer_1-width_4
+Xwire90@28 od[28] wire90@28_b wire90-612_5-layer_1-width_4
+Xwire90@29 od[29] wire90@29_b wire90-602_4-layer_1-width_4
+Xwire90@30 od[30] wire90@30_b wire90-1745_9-layer_1-width_4
+Xwire90@31 od[31] wire90@31_b wire90-605_4-layer_1-width_4
+Xwire90@32 od[32] wire90@32_b wire90-625-layer_1-width_4
+Xwire90@33 od[33] wire90@33_b wire90-604_6-layer_1-width_4
+Xwire90@34 od[34] wire90@34_b wire90-623-layer_1-width_4
+Xwire90@35 od[35] wire90@35_b wire90-597_9-layer_1-width_4
+Xwire90@36 od[36] wire90@36_b wire90-618-layer_1-width_4
+.ENDS odRQstageD
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-162_4-R_34_667m a b
+Ccap@0 gnd net@14 0.595f
+Ccap@1 gnd net@8 0.595f
+Ccap@2 gnd net@11 0.595f
+Rres@0 net@14 a 0.938
+Rres@1 net@11 net@14 1.877
+Rres@2 b net@8 0.938
+Rres@3 net@8 net@11 1.877
+.ENDS wire-C_0_011f-162_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-162_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-162_4-R_34_667m
+.ENDS wire90-162_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-228_5-R_34_667m a b
+Ccap@0 gnd net@14 0.838f
+Ccap@1 gnd net@8 0.838f
+Ccap@2 gnd net@11 0.838f
+Rres@0 net@14 a 1.32
+Rres@1 net@11 net@14 2.64
+Rres@2 b net@8 1.32
+Rres@3 net@8 net@11 2.64
+.ENDS wire-C_0_011f-228_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-228_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-228_5-R_34_667m
+.ENDS wire90-228_5-layer_1-width_3
+
+*** CELL: latchesK:rsLatchA{sch}
+.SUBCKT rsLatchA mc out outBar reset set
+XNMOSx@0 net@193 reset gnd NMOSx-X_10
+XNMOSx@1 net@188 mc gnd NMOSx-X_4
+XPMOSx@3 net@188 net@177 vdd PMOSx-X_10
+Xinv@0 net@193 outBar inv-X_10
+Xinv@1 set net@213 inv-X_4
+Xinv@2 outBar out inv-X_10
+Xnms2@0 net@188 outBar net@177 nms2-X_2
+Xpms3@0 net@193 mc outBar reset pms3-X_1
+Xwire90@0 net@213 net@177 wire90-162_4-layer_1-width_3
+Xwire90@1 net@188 net@193 wire90-228_5-layer_1-width_3
+.ENDS rsLatchA
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-345_1-R_34_667m a b
+Ccap@0 gnd net@14 1.265f
+Ccap@1 gnd net@8 1.265f
+Ccap@2 gnd net@11 1.265f
+Rres@0 net@14 a 1.994
+Rres@1 net@11 net@14 3.988
+Rres@2 b net@8 1.994
+Rres@3 net@8 net@11 3.988
+.ENDS wire-C_0_011f-345_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-345_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-345_1-R_34_667m
+.ENDS wire90-345_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-537-R_34_667m a b
+Ccap@0 gnd net@14 1.969f
+Ccap@1 gnd net@8 1.969f
+Ccap@2 gnd net@11 1.969f
+Rres@0 net@14 a 3.103
+Rres@1 net@11 net@14 6.205
+Rres@2 b net@8 3.103
+Rres@3 net@8 net@11 6.205
+.ENDS wire-C_0_011f-537-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-537-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-537-R_34_667m
+.ENDS wire90-537-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-470_7-R_34_667m a b
+Ccap@0 gnd net@14 1.726f
+Ccap@1 gnd net@8 1.726f
+Ccap@2 gnd net@11 1.726f
+Rres@0 net@14 a 2.72
+Rres@1 net@11 net@14 5.439
+Rres@2 b net@8 2.72
+Rres@3 net@8 net@11 5.439
+.ENDS wire-C_0_011f-470_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-470_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-470_7-R_34_667m
+.ENDS wire90-470_7-layer_1-width_3
+
+*** CELL: gaspL:anAltEnd{sch}
+.SUBCKT anAltEnd fire[A] fire[B] mc predA predB s[1] s[2] s[3] succ
+XctrAND4i@2 net@1013 succ fire[B] s[2] fire[A] ctrAND4in30
+XctrAND4i@3 net@1007 succ net@1127 fire[A] fire[B] ctrAND4in30
+Xinv@3 net@822 s[1] inv-X_10
+Xinv@4 net@824 s[3] inv-X_10
+Xinv@5 predA net@822 inv-X_5
+Xinv@6 predB net@824 inv-X_5
+XpredDri2@0 fire[A] mc predA predDri20wMC
+XpredDri2@1 fire[B] mc predB predDri20wMC
+XrsLatchA@1 mc net@1040 net@1082 fire[B] fire[A] rsLatchA
+XsucORdri@0 fire[A] fire[B] succ sucORdri20
+Xwire90@34 net@824 net@1007 wire90-345_1-layer_1-width_3
+Xwire90@35 net@822 net@1013 wire90-345_1-layer_1-width_3
+Xwire90@36 net@1127 net@1082 wire90-537-layer_1-width_3
+Xwire90@37 s[2] net@1040 wire90-470_7-layer_1-width_3
+.ENDS anAltEnd
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-293_4-R_34_667m a b
+Ccap@0 gnd net@14 1.076f
+Ccap@1 gnd net@8 1.076f
+Ccap@2 gnd net@11 1.076f
+Rres@0 net@14 a 1.695
+Rres@1 net@11 net@14 3.39
+Rres@2 b net@8 1.695
+Rres@3 net@8 net@11 3.39
+.ENDS wire-C_0_011f-293_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-293_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-293_4-R_34_667m
+.ENDS wire90-293_4-layer_1-width_3
+
+*** CELL: scanK:scanKhx3{sch}
+.SUBCKT scanKhx3 clS[F] clS[T] cl[F] cl[T] din[1] din[2] din[3] mc rd[F] 
++rd[T] sin sout
+XscanCell@4 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@18 
++scanCellKh
+XscanCell@5 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@31 net@20 
++scanCellKh
+XscanCell@6 clS[F] clS[T] cl[F] cl[T] din[3] rd[F] rd[T] net@32 sout 
++scanCellKh
+Xwire90@0 net@18 net@31 wire90-293_4-layer_1-width_3
+Xwire90@1 net@20 net@32 wire90-293_4-layer_1-width_3
+.ENDS scanKhx3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1336_2-R_34_667m a b
+Ccap@0 gnd net@14 4.899f
+Ccap@1 gnd net@8 4.899f
+Ccap@2 gnd net@11 4.899f
+Rres@0 net@14 a 7.72
+Rres@1 net@11 net@14 15.441
+Rres@2 b net@8 7.72
+Rres@3 net@8 net@11 15.441
+.ENDS wire-C_0_011f-1336_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1336_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1336_2-R_34_667m
+.ENDS wire90-1336_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1307-R_34_667m a b
+Ccap@0 gnd net@14 4.792f
+Ccap@1 gnd net@8 4.792f
+Ccap@2 gnd net@11 4.792f
+Rres@0 net@14 a 7.552
+Rres@1 net@11 net@14 15.103
+Rres@2 b net@8 7.552
+Rres@3 net@8 net@11 15.103
+.ENDS wire-C_0_011f-1307-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1307-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1307-R_34_667m
+.ENDS wire90-1307-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-403_1-R_34_667m a b
+Ccap@0 gnd net@14 1.478f
+Ccap@1 gnd net@8 1.478f
+Ccap@2 gnd net@11 1.478f
+Rres@0 net@14 a 2.329
+Rres@1 net@11 net@14 4.658
+Rres@2 b net@8 2.329
+Rres@3 net@8 net@11 4.658
+.ENDS wire-C_0_011f-403_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-403_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-403_1-R_34_667m
+.ENDS wire90-403_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-600_8-R_34_667m a b
+Ccap@0 gnd net@14 2.203f
+Ccap@1 gnd net@8 2.203f
+Ccap@2 gnd net@11 2.203f
+Rres@0 net@14 a 3.471
+Rres@1 net@11 net@14 6.943
+Rres@2 b net@8 3.471
+Rres@3 net@8 net@11 6.943
+.ENDS wire-C_0_011f-600_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-600_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-600_8-R_34_667m
+.ENDS wire90-600_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-274_5-R_34_667m a b
+Ccap@0 gnd net@14 1.006f
+Ccap@1 gnd net@8 1.006f
+Ccap@2 gnd net@11 1.006f
+Rres@0 net@14 a 1.586
+Rres@1 net@11 net@14 3.172
+Rres@2 b net@8 1.586
+Rres@3 net@8 net@11 3.172
+.ENDS wire-C_0_011f-274_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-274_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-274_5-R_34_667m
+.ENDS wire90-274_5-layer_1-width_3
+
+*** CELL: gaspL:anAltEndS{sch}
+.SUBCKT anAltEndS clS[F] clS[T] cl[F] cl[T] mc predA predB rd[F] rd[T] sin 
++sout succ take[A] take[B]
+XanAltEnd@1 fire[A] fire[B] mc predA predB ss[1] ss[2] ss[3] succ anAltEnd
+XlatchDri@2 net@942 take[A] latchDriver60
+XlatchDri@5 net@946 take[B] latchDriver60
+XscanKhx3@0 clS[F] clS[T] cl[F] cl[T] ss[1] ss[2] ss[3] mc rd[F] rd[T] sin 
++sout scanKhx3
+Xwire90@0 net@946 fire[B] wire90-1336_2-layer_1-width_3
+Xwire90@1 net@942 fire[A] wire90-1307-layer_1-width_3
+Xwire90@2 wire90@2_a ss[1] wire90-403_1-layer_1-width_3
+Xwire90@3 wire90@3_a ss[2] wire90-600_8-layer_1-width_3
+Xwire90@4 wire90@4_a ss[3] wire90-274_5-layer_1-width_3
+.ENDS anAltEndS
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3929_3-R_34_667m a b
+Ccap@0 gnd net@14 14.407f
+Ccap@1 gnd net@8 14.407f
+Ccap@2 gnd net@11 14.407f
+Rres@0 net@14 a 22.703
+Rres@1 net@11 net@14 45.405
+Rres@2 b net@8 22.703
+Rres@3 net@8 net@11 45.405
+.ENDS wire-C_0_011f-3929_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3929_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3929_3-R_34_667m
+.ENDS wire90-3929_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3970_7-R_34_667m a b
+Ccap@0 gnd net@14 14.559f
+Ccap@1 gnd net@8 14.559f
+Ccap@2 gnd net@11 14.559f
+Rres@0 net@14 a 22.942
+Rres@1 net@11 net@14 45.884
+Rres@2 b net@8 22.942
+Rres@3 net@8 net@11 45.884
+.ENDS wire-C_0_011f-3970_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3970_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3970_7-R_34_667m
+.ENDS wire90-3970_7-layer_1-width_3
+
+*** CELL: fifoL:splitEnd{sch}
+.SUBCKT splitEnd clS[F] clS[T] cl[F] cl[T] inA[10] inA[11] inA[12] inA[13] 
++inA[14] inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] 
++inA[22] inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] 
++inA[30] inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] 
++inA[6] inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] 
++inB[16] inB[17] inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] 
++inB[24] inB[25] inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] 
++inB[32] inB[33] inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] 
++inB[8] inB[9] mc out[10] out[11] out[12] out[13] out[14] out[15] out[16] 
++out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] 
++out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] 
++out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] 
++out[9] predA predB rd[F] rd[T] sin sout succ
+XanAltEnd@1 clS[F] clS[T] cl[F] cl[T] mc predA predB rd[F] rd[T] sin sout 
++succ take[A] take[B] anAltEndS
+Xins2in20@0 net@38 net@34 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] 
++inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] 
++inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] 
++inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7] 
++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] 
++inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] 
++inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33] 
++inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9] 
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax36
+Xwire90@0 net@34 take[B] wire90-3929_3-layer_1-width_3
+Xwire90@1 net@38 take[A] wire90-3970_7-layer_1-width_3
+.ENDS splitEnd
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-237_2-R_34_667m a b
+Ccap@0 gnd net@14 0.87f
+Ccap@1 gnd net@8 0.87f
+Ccap@2 gnd net@11 0.87f
+Rres@0 net@14 a 1.37
+Rres@1 net@11 net@14 2.741
+Rres@2 b net@8 1.37
+Rres@3 net@8 net@11 2.741
+.ENDS wire-C_0_011f-237_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-237_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-237_2-R_34_667m
+.ENDS wire90-237_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-221_8-R_34_667m a b
+Ccap@0 gnd net@14 0.813f
+Ccap@1 gnd net@8 0.813f
+Ccap@2 gnd net@11 0.813f
+Rres@0 net@14 a 1.282
+Rres@1 net@11 net@14 2.563
+Rres@2 b net@8 1.282
+Rres@3 net@8 net@11 2.563
+.ENDS wire-C_0_011f-221_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-221_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-221_8-R_34_667m
+.ENDS wire90-221_8-layer_1-width_3
+
+*** CELL: centersJ:ctrAND4in30M{sch}
+.SUBCKT ctrAND4in30M inA inB inC inD out outM
+Xinv@1 outM out inv-X_30
+Xnand2@1 net@43 net@58 outM nand2-X_10
+Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4
+Xnor2n@0 inD inC net@64 nor2n-X_5
+Xwire90@0 net@64 net@43 wire90-237_2-layer_1-width_3
+Xwire90@2 net@61 net@58 wire90-221_8-layer_1-width_3
+.ENDS ctrAND4in30M
+
+*** CELL: redFour:nand2_sy{sch}
+.SUBCKT nand2_sy-X_10 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_10
+XPMOS@1 out ina vdd PMOSx-X_10
+Xnms2_sy@0 out ina inb nms2_sy-X_10
+.ENDS nand2_sy-X_10
+
+*** CELL: redFour:nand2n_sy{sch}
+.SUBCKT nand2n_sy-X_10 ina inb out
+Xnand2_sy@0 ina inb out nand2_sy-X_10
+.ENDS nand2n_sy-X_10
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-700-R_34_667m a b
+Ccap@0 gnd net@14 2.567f
+Ccap@1 gnd net@8 2.567f
+Ccap@2 gnd net@11 2.567f
+Rres@0 net@14 a 4.044
+Rres@1 net@11 net@14 8.089
+Rres@2 b net@8 4.044
+Rres@3 net@8 net@11 8.089
+.ENDS wire-C_0_011f-700-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-700-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-700-R_34_667m
+.ENDS wire90-700-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-839_6-R_34_667m a b
+Ccap@0 gnd net@14 3.079f
+Ccap@1 gnd net@8 3.079f
+Ccap@2 gnd net@11 3.079f
+Rres@0 net@14 a 4.851
+Rres@1 net@11 net@14 9.702
+Rres@2 b net@8 4.851
+Rres@3 net@8 net@11 9.702
+.ENDS wire-C_0_011f-839_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-839_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-839_6-R_34_667m
+.ENDS wire90-839_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-438_2-R_34_667m a b
+Ccap@0 gnd net@14 1.607f
+Ccap@1 gnd net@8 1.607f
+Ccap@2 gnd net@11 1.607f
+Rres@0 net@14 a 2.532
+Rres@1 net@11 net@14 5.064
+Rres@2 b net@8 2.532
+Rres@3 net@8 net@11 5.064
+.ENDS wire-C_0_011f-438_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-438_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-438_2-R_34_667m
+.ENDS wire90-438_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-257_4-R_34_667m a b
+Ccap@0 gnd net@14 0.944f
+Ccap@1 gnd net@8 0.944f
+Ccap@2 gnd net@11 0.944f
+Rres@0 net@14 a 1.487
+Rres@1 net@11 net@14 2.974
+Rres@2 b net@8 1.487
+Rres@3 net@8 net@11 2.974
+.ENDS wire-C_0_011f-257_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-257_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-257_4-R_34_667m
+.ENDS wire90-257_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-458_8-R_34_667m a b
+Ccap@0 gnd net@14 1.682f
+Ccap@1 gnd net@8 1.682f
+Ccap@2 gnd net@11 1.682f
+Rres@0 net@14 a 2.651
+Rres@1 net@11 net@14 5.302
+Rres@2 b net@8 2.651
+Rres@3 net@8 net@11 5.302
+.ENDS wire-C_0_011f-458_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-458_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-458_8-R_34_667m
+.ENDS wire90-458_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-744_5-R_34_667m a b
+Ccap@0 gnd net@14 2.73f
+Ccap@1 gnd net@8 2.73f
+Ccap@2 gnd net@11 2.73f
+Rres@0 net@14 a 4.302
+Rres@1 net@11 net@14 8.603
+Rres@2 b net@8 4.302
+Rres@3 net@8 net@11 8.603
+.ENDS wire-C_0_011f-744_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-744_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-744_5-R_34_667m
+.ENDS wire90-744_5-layer_1-width_3
+
+*** CELL: gaspL:anAltStart{sch}
+.SUBCKT anAltStart fire[A] fire[B] mc pred s[1] s[2] succA succB
+XctrAND4i@1 net@634 succA fire[B] s[2] fire[A] net@866 ctrAND4in30M
+XctrAND4i@3 net@634 succB net@909 fire[A] fire[B] net@885 ctrAND4in30M
+Xinv@3 net@634 s[1] inv-X_10
+Xinv@4 pred net@787 inv-X_10
+Xnand2n_s@0 net@143 net@410 net@422 nand2n_sy-X_10
+XpredDri2@0 net@815 mc pred predDri20wMC
+XrsLatchA@1 mc net@905 net@911 fire[B] fire[A] rsLatchA
+XsucDri20@0 fire[A] succA sucDri20
+XsucDri20@1 fire[B] succB sucDri20
+Xwire90@16 net@410 net@866 wire90-700-layer_1-width_3
+Xwire90@17 net@143 net@885 wire90-839_6-layer_1-width_3
+Xwire90@19 s[2] net@905 wire90-438_2-layer_1-width_3
+Xwire90@20 net@815 net@422 wire90-257_4-layer_1-width_3
+Xwire90@27 net@909 net@911 wire90-458_8-layer_1-width_3
+Xwire90@28 net@787 net@634 wire90-744_5-layer_1-width_3
+.ENDS anAltStart
+
+*** CELL: redFour:pms2_sy{sch}
+.SUBCKT pms2_sy-X_20 d g g2
+Xpms2@0 d g g2 pms2-X_10
+Xpms2@1 d g2 g pms2-X_10
+.ENDS pms2_sy-X_20
+
+*** CELL: redFour:nor2_sy{sch}
+.SUBCKT nor2_sy-X_20 ina inb out
+XNMOS@0 out inb gnd NMOSx-X_20
+XNMOS@1 out ina gnd NMOSx-X_20
+Xpms2_sy@0 out ina inb pms2_sy-X_20
+.ENDS nor2_sy-X_20
+
+*** CELL: driversJ:latchOrDriver60{sch}
+.SUBCKT latchOrDriver60 inA inB out
+Xinv@0 net@8 out inv-X_60
+Xnor2_sy@0 inA inB net@31 nor2_sy-X_20
+Xwire90@0 net@31 net@8 wire90-544_2-layer_1-width_3
+.ENDS latchOrDriver60
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1300-R_34_667m a b
+Ccap@0 gnd net@14 4.767f
+Ccap@1 gnd net@8 4.767f
+Ccap@2 gnd net@11 4.767f
+Rres@0 net@14 a 7.511
+Rres@1 net@11 net@14 15.022
+Rres@2 b net@8 7.511
+Rres@3 net@8 net@11 15.022
+.ENDS wire-C_0_011f-1300-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1300-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1300-R_34_667m
+.ENDS wire90-1300-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1301_9-R_34_667m a b
+Ccap@0 gnd net@14 4.774f
+Ccap@1 gnd net@8 4.774f
+Ccap@2 gnd net@11 4.774f
+Rres@0 net@14 a 7.522
+Rres@1 net@11 net@14 15.044
+Rres@2 b net@8 7.522
+Rres@3 net@8 net@11 15.044
+.ENDS wire-C_0_011f-1301_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1301_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1301_9-R_34_667m
+.ENDS wire90-1301_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-292_5-R_34_667m a b
+Ccap@0 gnd net@14 1.072f
+Ccap@1 gnd net@8 1.072f
+Ccap@2 gnd net@11 1.072f
+Rres@0 net@14 a 1.69
+Rres@1 net@11 net@14 3.38
+Rres@2 b net@8 1.69
+Rres@3 net@8 net@11 3.38
+.ENDS wire-C_0_011f-292_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-292_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-292_5-R_34_667m
+.ENDS wire90-292_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-559_6-R_34_667m a b
+Ccap@0 gnd net@14 2.052f
+Ccap@1 gnd net@8 2.052f
+Ccap@2 gnd net@11 2.052f
+Rres@0 net@14 a 3.233
+Rres@1 net@11 net@14 6.466
+Rres@2 b net@8 3.233
+Rres@3 net@8 net@11 6.466
+.ENDS wire-C_0_011f-559_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-559_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-559_6-R_34_667m
+.ENDS wire90-559_6-layer_1-width_3
+
+*** CELL: gaspL:anAltStartS{sch}
+.SUBCKT anAltStartS clS[F] clS[T] cl[F] cl[T] mc pred rd[F] rd[T] sin sout 
++succA succB take
+XanAltSta@1 fire[A] fire[B] mc pred s[1] s[2] succA succB anAltStart
+XlatchOrD@0 net@789 net@792 take latchOrDriver60
+XscanKhx2@0 clS[F] clS[T] cl[F] cl[T] s[1] s[2] mc rd[F] rd[T] sin sout 
++scanKhx2
+Xwire90@0 fire[A] net@789 wire90-1300-layer_1-width_3
+Xwire90@1 fire[B] net@792 wire90-1301_9-layer_1-width_3
+Xwire90@2 wire90@2_a s[1] wire90-292_5-layer_1-width_3
+Xwire90@3 wire90@3_a s[2] wire90-559_6-layer_1-width_3
+.ENDS anAltStartS
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3692_5-R_34_667m a b
+Ccap@0 gnd net@14 13.539f
+Ccap@1 gnd net@8 13.539f
+Ccap@2 gnd net@11 13.539f
+Rres@0 net@14 a 21.334
+Rres@1 net@11 net@14 42.669
+Rres@2 b net@8 21.334
+Rres@3 net@8 net@11 42.669
+.ENDS wire-C_0_011f-3692_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3692_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3692_5-R_34_667m
+.ENDS wire90-3692_5-layer_1-width_3
+
+*** CELL: fifoL:splitStart{sch}
+.SUBCKT splitStart clS[F] clS[T] cl[F] cl[T] in[10] in[11] in[12] in[13] 
++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] 
++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] 
++in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred rd[F] rd[T] sin 
++sout succA succB
+XanAltSta@0 clS[F] clS[T] cl[F] cl[T] mc pred rd[F] rd[T] sin sout succA 
++succB net@2 anAltStartS
+Xins20Bx3@0 net@3 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] 
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] 
++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] 
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] 
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] 
++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] 
++out[7] out[8] out[9] ins20Bx36
+Xwire90@0 net@3 net@2 wire90-3692_5-layer_1-width_3
+.ENDS splitStart
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3704_051-R_34_667m a b
+Ccap@0 gnd net@14 13.582f
+Ccap@1 gnd net@8 13.582f
+Ccap@2 gnd net@11 13.582f
+Rres@0 net@14 a 21.401
+Rres@1 net@11 net@14 42.802
+Rres@2 b net@8 21.401
+Rres@3 net@8 net@11 42.802
+.ENDS wire-C_0_011f-3704_051-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3704_051-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3704_051-R_34_667m
+.ENDS wire90-3704_051-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-809_6-R_34_667m a b
+Ccap@0 gnd net@14 2.969f
+Ccap@1 gnd net@8 2.969f
+Ccap@2 gnd net@11 2.969f
+Rres@0 net@14 a 4.678
+Rres@1 net@11 net@14 9.355
+Rres@2 b net@8 4.678
+Rres@3 net@8 net@11 9.355
+.ENDS wire-C_0_011f-809_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-809_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-809_6-R_34_667m
+.ENDS wire90-809_6-layer_1-width_3
+
+*** CELL: fifoL:splitStageD{sch}
+.SUBCKT splitStageD in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] 
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] 
++in[4] in[5] in[6] in[7] in[8] in[9] mc out[10] out[11] out[12] out[13] 
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] 
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] 
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] 
++out[6] out[7] out[8] out[9] pred s[1] succ take[1]
+XaStage@0 net@104 mc pred s[1] succ aStage
+Xins20Bx3@0 net@120 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] 
++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] 
++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] 
++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] 
++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] 
++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] 
++out[7] out[8] out[9] ins20Bx36
+XlatchDri@0 fire[1] take[1] latchDriver60
+Xwire90@1 net@120 take[1] wire90-3704_051-layer_1-width_3
+Xwire90@2 net@104 fire[1] wire90-809_6-layer_1-width_3
+.ENDS splitStageD
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-982_1-R_34_667m a b
+Ccap@0 gnd net@14 3.601f
+Ccap@1 gnd net@8 3.601f
+Ccap@2 gnd net@11 3.601f
+Rres@0 net@14 a 5.674
+Rres@1 net@11 net@14 11.349
+Rres@2 b net@8 5.674
+Rres@3 net@8 net@11 11.349
+.ENDS wire-C_0_011f-982_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-982_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-982_1-R_34_667m
+.ENDS wire90-982_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-605_4-R_34_667m a b
+Ccap@0 gnd net@14 2.22f
+Ccap@1 gnd net@8 2.22f
+Ccap@2 gnd net@11 2.22f
+Rres@0 net@14 a 3.498
+Rres@1 net@11 net@14 6.996
+Rres@2 b net@8 3.498
+Rres@3 net@8 net@11 6.996
+.ENDS wire-C_0_011f-605_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-605_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-605_4-R_34_667m
+.ENDS wire90-605_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-613_4-R_34_667m a b
+Ccap@0 gnd net@14 2.249f
+Ccap@1 gnd net@8 2.249f
+Ccap@2 gnd net@11 2.249f
+Rres@0 net@14 a 3.544
+Rres@1 net@11 net@14 7.088
+Rres@2 b net@8 3.544
+Rres@3 net@8 net@11 7.088
+.ENDS wire-C_0_011f-613_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-613_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-613_4-R_34_667m
+.ENDS wire90-613_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-623_9-R_34_667m a b
+Ccap@0 gnd net@14 2.288f
+Ccap@1 gnd net@8 2.288f
+Ccap@2 gnd net@11 2.288f
+Rres@0 net@14 a 3.605
+Rres@1 net@11 net@14 7.21
+Rres@2 b net@8 3.605
+Rres@3 net@8 net@11 7.21
+.ENDS wire-C_0_011f-623_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-623_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-623_9-R_34_667m
+.ENDS wire90-623_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-625_9-R_34_667m a b
+Ccap@0 gnd net@14 2.295f
+Ccap@1 gnd net@8 2.295f
+Ccap@2 gnd net@11 2.295f
+Rres@0 net@14 a 3.616
+Rres@1 net@11 net@14 7.233
+Rres@2 b net@8 3.616
+Rres@3 net@8 net@11 7.233
+.ENDS wire-C_0_011f-625_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-625_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-625_9-R_34_667m
+.ENDS wire90-625_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-607_8-R_34_667m a b
+Ccap@0 gnd net@14 2.229f
+Ccap@1 gnd net@8 2.229f
+Ccap@2 gnd net@11 2.229f
+Rres@0 net@14 a 3.512
+Rres@1 net@11 net@14 7.023
+Rres@2 b net@8 3.512
+Rres@3 net@8 net@11 7.023
+.ENDS wire-C_0_011f-607_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-607_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-607_8-R_34_667m
+.ENDS wire90-607_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-620_9-R_34_667m a b
+Ccap@0 gnd net@14 2.277f
+Ccap@1 gnd net@8 2.277f
+Ccap@2 gnd net@11 2.277f
+Rres@0 net@14 a 3.587
+Rres@1 net@11 net@14 7.175
+Rres@2 b net@8 3.587
+Rres@3 net@8 net@11 7.175
+.ENDS wire-C_0_011f-620_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-620_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-620_9-R_34_667m
+.ENDS wire90-620_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-612_5-R_34_667m a b
+Ccap@0 gnd net@14 2.246f
+Ccap@1 gnd net@8 2.246f
+Ccap@2 gnd net@11 2.246f
+Rres@0 net@14 a 3.539
+Rres@1 net@11 net@14 7.078
+Rres@2 b net@8 3.539
+Rres@3 net@8 net@11 7.078
+.ENDS wire-C_0_011f-612_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-612_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-612_5-R_34_667m
+.ENDS wire90-612_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-602_4-R_34_667m a b
+Ccap@0 gnd net@14 2.209f
+Ccap@1 gnd net@8 2.209f
+Ccap@2 gnd net@11 2.209f
+Rres@0 net@14 a 3.481
+Rres@1 net@11 net@14 6.961
+Rres@2 b net@8 3.481
+Rres@3 net@8 net@11 6.961
+.ENDS wire-C_0_011f-602_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-602_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-602_4-R_34_667m
+.ENDS wire90-602_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-607-R_34_667m a b
+Ccap@0 gnd net@14 2.226f
+Ccap@1 gnd net@8 2.226f
+Ccap@2 gnd net@11 2.226f
+Rres@0 net@14 a 3.507
+Rres@1 net@11 net@14 7.014
+Rres@2 b net@8 3.507
+Rres@3 net@8 net@11 7.014
+.ENDS wire-C_0_011f-607-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-607-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-607-R_34_667m
+.ENDS wire90-607-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-620_5-R_34_667m a b
+Ccap@0 gnd net@14 2.275f
+Ccap@1 gnd net@8 2.275f
+Ccap@2 gnd net@11 2.275f
+Rres@0 net@14 a 3.585
+Rres@1 net@11 net@14 7.17
+Rres@2 b net@8 3.585
+Rres@3 net@8 net@11 7.17
+.ENDS wire-C_0_011f-620_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-620_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-620_5-R_34_667m
+.ENDS wire90-620_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-624_5-R_34_667m a b
+Ccap@0 gnd net@14 2.29f
+Ccap@1 gnd net@8 2.29f
+Ccap@2 gnd net@11 2.29f
+Rres@0 net@14 a 3.608
+Rres@1 net@11 net@14 7.216
+Rres@2 b net@8 3.608
+Rres@3 net@8 net@11 7.216
+.ENDS wire-C_0_011f-624_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-624_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-624_5-R_34_667m
+.ENDS wire90-624_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-618-R_34_667m a b
+Ccap@0 gnd net@14 2.266f
+Ccap@1 gnd net@8 2.266f
+Ccap@2 gnd net@11 2.266f
+Rres@0 net@14 a 3.571
+Rres@1 net@11 net@14 7.141
+Rres@2 b net@8 3.571
+Rres@3 net@8 net@11 7.141
+.ENDS wire-C_0_011f-618-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-618-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-618-R_34_667m
+.ENDS wire90-618-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-532-R_34_667m a b
+Ccap@0 gnd net@14 1.951f
+Ccap@1 gnd net@8 1.951f
+Ccap@2 gnd net@11 1.951f
+Rres@0 net@14 a 3.074
+Rres@1 net@11 net@14 6.148
+Rres@2 b net@8 3.074
+Rres@3 net@8 net@11 6.148
+.ENDS wire-C_0_011f-532-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-532-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-532-R_34_667m
+.ENDS wire90-532-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-238-R_34_667m a b
+Ccap@0 gnd net@14 0.873f
+Ccap@1 gnd net@8 0.873f
+Ccap@2 gnd net@11 0.873f
+Rres@0 net@14 a 1.375
+Rres@1 net@11 net@14 2.75
+Rres@2 b net@8 1.375
+Rres@3 net@8 net@11 2.75
+.ENDS wire-C_0_011f-238-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-238-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-238-R_34_667m
+.ENDS wire90-238-layer_1-width_3
+
+*** CELL: fifoL:splitStageDx2{sch}
+.SUBCKT splitStageDx2 clS[F] clS[T] cl[F] cl[T] freqOut in[10] in[11] in[12] 
++in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] 
++in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] 
++in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc 
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred rd[F] 
++rd[T] sin sout succ
+XscanKhx2@0 clS[F] clS[T] cl[F] cl[T] s[1] s[2] mc rd[F] rd[T] sin sout 
++scanKhx2
+XsplitSta@1 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] 
++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] 
++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] 
++in[5] in[6] in[7] in[8] in[9] mc x[10] x[11] x[12] x[13] x[14] x[15] x[16] 
++x[17] x[18] x[19] x[1] x[20] x[21] x[22] x[23] x[24] x[25] x[26] x[27] x[28] 
++x[29] x[2] x[30] x[31] x[32] x[33] x[34] x[35] x[36] x[3] x[4] x[5] x[6] x[7] 
++x[8] x[9] pred s[1] net@155 splitSta@1_take[1] splitStageD
+XsplitSta@2 x[10] x[11] x[12] x[13] x[14] x[15] x[16] x[17] x[18] x[19] x[1] 
++x[20] x[21] x[22] x[23] x[24] x[25] x[26] x[27] x[28] x[29] x[2] x[30] x[31] 
++x[32] x[33] x[34] x[35] x[36] x[3] x[4] x[5] x[6] x[7] x[8] x[9] mc out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@154 s[2] succ 
++freqOut splitStageD
+Xwire90@3 net@155 net@154 wire90-982_1-layer_1-width_3
+Xwire90@4 x[1] wire90@4_b wire90-605_4-layer_1-width_3
+Xwire90@5 x[2] wire90@5_b wire90-613_4-layer_1-width_3
+Xwire90@6 x[3] wire90@6_b wire90-605_4-layer_1-width_3
+Xwire90@7 x[4] wire90@7_b wire90-623_9-layer_1-width_3
+Xwire90@8 x[5] wire90@8_b wire90-605_4-layer_1-width_3
+Xwire90@9 x[6] wire90@9_b wire90-625_9-layer_1-width_3
+Xwire90@10 x[7] wire90@10_b wire90-607_8-layer_1-width_3
+Xwire90@11 x[8] wire90@11_b wire90-620_9-layer_1-width_3
+Xwire90@12 x[9] wire90@12_b wire90-605_4-layer_1-width_3
+Xwire90@13 x[10] wire90@13_b wire90-612_5-layer_1-width_3
+Xwire90@14 x[11] wire90@14_b wire90-602_4-layer_1-width_3
+Xwire90@15 x[12] wire90@15_b wire90-607-layer_1-width_3
+Xwire90@16 x[13] wire90@16_b wire90-602_4-layer_1-width_3
+Xwire90@17 x[14] wire90@17_b wire90-620_5-layer_1-width_3
+Xwire90@18 x[15] wire90@18_b wire90-602_4-layer_1-width_3
+Xwire90@19 x[16] wire90@19_b wire90-624_5-layer_1-width_3
+Xwire90@20 x[17] wire90@20_b wire90-602_4-layer_1-width_3
+Xwire90@21 x[18] wire90@21_b wire90-618-layer_1-width_3
+Xwire90@22 x[19] wire90@22_b wire90-605_4-layer_1-width_3
+Xwire90@23 x[20] wire90@23_b wire90-613_4-layer_1-width_3
+Xwire90@24 x[21] wire90@24_b wire90-605_4-layer_1-width_3
+Xwire90@25 x[22] wire90@25_b wire90-623_9-layer_1-width_3
+Xwire90@26 x[23] wire90@26_b wire90-605_4-layer_1-width_3
+Xwire90@27 x[24] wire90@27_b wire90-625_9-layer_1-width_3
+Xwire90@28 x[25] wire90@28_b wire90-607_8-layer_1-width_3
+Xwire90@29 x[26] wire90@29_b wire90-620_9-layer_1-width_3
+Xwire90@30 x[27] wire90@30_b wire90-605_4-layer_1-width_3
+Xwire90@31 x[28] wire90@31_b wire90-612_5-layer_1-width_3
+Xwire90@32 x[29] wire90@32_b wire90-602_4-layer_1-width_3
+Xwire90@33 x[30] wire90@33_b wire90-607-layer_1-width_3
+Xwire90@34 x[31] wire90@34_b wire90-602_4-layer_1-width_3
+Xwire90@35 x[32] wire90@35_b wire90-620_5-layer_1-width_3
+Xwire90@36 x[33] wire90@36_b wire90-602_4-layer_1-width_3
+Xwire90@37 x[34] wire90@37_b wire90-624_5-layer_1-width_3
+Xwire90@38 x[35] wire90@38_b wire90-602_4-layer_1-width_3
+Xwire90@39 x[36] wire90@39_b wire90-618-layer_1-width_3
+Xwire90@40 wire90@40_a s[2] wire90-532-layer_1-width_3
+Xwire90@41 wire90@41_a s[1] wire90-238-layer_1-width_3
+.ENDS splitStageDx2
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2777_3-R_34_667m a b
+Ccap@0 gnd net@14 10.183f
+Ccap@1 gnd net@8 10.183f
+Ccap@2 gnd net@11 10.183f
+Rres@0 net@14 a 16.047
+Rres@1 net@11 net@14 32.093
+Rres@2 b net@8 16.047
+Rres@3 net@8 net@11 32.093
+.ENDS wire-C_0_011f-2777_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2777_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2777_3-R_34_667m
+.ENDS wire90-2777_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2581_1-R_34_667m a b
+Ccap@0 gnd net@14 9.464f
+Ccap@1 gnd net@8 9.464f
+Ccap@2 gnd net@11 9.464f
+Rres@0 net@14 a 14.913
+Rres@1 net@11 net@14 29.826
+Rres@2 b net@8 14.913
+Rres@3 net@8 net@11 29.826
+.ENDS wire-C_0_011f-2581_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2581_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2581_1-R_34_667m
+.ENDS wire90-2581_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2599_6-R_34_667m a b
+Ccap@0 gnd net@14 9.532f
+Ccap@1 gnd net@8 9.532f
+Ccap@2 gnd net@11 9.532f
+Rres@0 net@14 a 15.02
+Rres@1 net@11 net@14 30.04
+Rres@2 b net@8 15.02
+Rres@3 net@8 net@11 30.04
+.ENDS wire-C_0_011f-2599_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2599_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2599_6-R_34_667m
+.ENDS wire90-2599_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2611_1-R_34_667m a b
+Ccap@0 gnd net@14 9.574f
+Ccap@1 gnd net@8 9.574f
+Ccap@2 gnd net@11 9.574f
+Rres@0 net@14 a 15.086
+Rres@1 net@11 net@14 30.173
+Rres@2 b net@8 15.086
+Rres@3 net@8 net@11 30.173
+.ENDS wire-C_0_011f-2611_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2611_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2611_1-R_34_667m
+.ENDS wire90-2611_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2654_1-R_34_667m a b
+Ccap@0 gnd net@14 9.732f
+Ccap@1 gnd net@8 9.732f
+Ccap@2 gnd net@11 9.732f
+Rres@0 net@14 a 15.335
+Rres@1 net@11 net@14 30.67
+Rres@2 b net@8 15.335
+Rres@3 net@8 net@11 30.67
+.ENDS wire-C_0_011f-2654_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2654_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2654_1-R_34_667m
+.ENDS wire90-2654_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2637_1-R_34_667m a b
+Ccap@0 gnd net@14 9.669f
+Ccap@1 gnd net@8 9.669f
+Ccap@2 gnd net@11 9.669f
+Rres@0 net@14 a 15.237
+Rres@1 net@11 net@14 30.473
+Rres@2 b net@8 15.237
+Rres@3 net@8 net@11 30.473
+.ENDS wire-C_0_011f-2637_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2637_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2637_1-R_34_667m
+.ENDS wire90-2637_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2690_6-R_34_667m a b
+Ccap@0 gnd net@14 9.866f
+Ccap@1 gnd net@8 9.866f
+Ccap@2 gnd net@11 9.866f
+Rres@0 net@14 a 15.546
+Rres@1 net@11 net@14 31.091
+Rres@2 b net@8 15.546
+Rres@3 net@8 net@11 31.091
+.ENDS wire-C_0_011f-2690_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2690_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2690_6-R_34_667m
+.ENDS wire90-2690_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2675_5-R_34_667m a b
+Ccap@0 gnd net@14 9.81f
+Ccap@1 gnd net@8 9.81f
+Ccap@2 gnd net@11 9.81f
+Rres@0 net@14 a 15.458
+Rres@1 net@11 net@14 30.917
+Rres@2 b net@8 15.458
+Rres@3 net@8 net@11 30.917
+.ENDS wire-C_0_011f-2675_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2675_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2675_5-R_34_667m
+.ENDS wire90-2675_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2737_6-R_34_667m a b
+Ccap@0 gnd net@14 10.038f
+Ccap@1 gnd net@8 10.038f
+Ccap@2 gnd net@11 10.038f
+Rres@0 net@14 a 15.817
+Rres@1 net@11 net@14 31.634
+Rres@2 b net@8 15.817
+Rres@3 net@8 net@11 31.634
+.ENDS wire-C_0_011f-2737_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2737_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2737_6-R_34_667m
+.ENDS wire90-2737_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2725_1-R_34_667m a b
+Ccap@0 gnd net@14 9.992f
+Ccap@1 gnd net@8 9.992f
+Ccap@2 gnd net@11 9.992f
+Rres@0 net@14 a 15.745
+Rres@1 net@11 net@14 31.49
+Rres@2 b net@8 15.745
+Rres@3 net@8 net@11 31.49
+.ENDS wire-C_0_011f-2725_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2725_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2725_1-R_34_667m
+.ENDS wire90-2725_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2582_2-R_34_667m a b
+Ccap@0 gnd net@14 9.468f
+Ccap@1 gnd net@8 9.468f
+Ccap@2 gnd net@11 9.468f
+Rres@0 net@14 a 14.919
+Rres@1 net@11 net@14 29.839
+Rres@2 b net@8 14.919
+Rres@3 net@8 net@11 29.839
+.ENDS wire-C_0_011f-2582_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2582_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2582_2-R_34_667m
+.ENDS wire90-2582_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2584_1-R_34_667m a b
+Ccap@0 gnd net@14 9.475f
+Ccap@1 gnd net@8 9.475f
+Ccap@2 gnd net@11 9.475f
+Rres@0 net@14 a 14.93
+Rres@1 net@11 net@14 29.861
+Rres@2 b net@8 14.93
+Rres@3 net@8 net@11 29.861
+.ENDS wire-C_0_011f-2584_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2584_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2584_1-R_34_667m
+.ENDS wire90-2584_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2620_2-R_34_667m a b
+Ccap@0 gnd net@14 9.607f
+Ccap@1 gnd net@8 9.607f
+Ccap@2 gnd net@11 9.607f
+Rres@0 net@14 a 15.139
+Rres@1 net@11 net@14 30.278
+Rres@2 b net@8 15.139
+Rres@3 net@8 net@11 30.278
+.ENDS wire-C_0_011f-2620_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2620_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2620_2-R_34_667m
+.ENDS wire90-2620_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2660_1-R_34_667m a b
+Ccap@0 gnd net@14 9.754f
+Ccap@1 gnd net@8 9.754f
+Ccap@2 gnd net@11 9.754f
+Rres@0 net@14 a 15.369
+Rres@1 net@11 net@14 30.739
+Rres@2 b net@8 15.369
+Rres@3 net@8 net@11 30.739
+.ENDS wire-C_0_011f-2660_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2660_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2660_1-R_34_667m
+.ENDS wire90-2660_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2681_2-R_34_667m a b
+Ccap@0 gnd net@14 9.831f
+Ccap@1 gnd net@8 9.831f
+Ccap@2 gnd net@11 9.831f
+Rres@0 net@14 a 15.491
+Rres@1 net@11 net@14 30.983
+Rres@2 b net@8 15.491
+Rres@3 net@8 net@11 30.983
+.ENDS wire-C_0_011f-2681_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2681_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2681_2-R_34_667m
+.ENDS wire90-2681_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2708_1-R_34_667m a b
+Ccap@0 gnd net@14 9.93f
+Ccap@1 gnd net@8 9.93f
+Ccap@2 gnd net@11 9.93f
+Rres@0 net@14 a 15.647
+Rres@1 net@11 net@14 31.294
+Rres@2 b net@8 15.647
+Rres@3 net@8 net@11 31.294
+.ENDS wire-C_0_011f-2708_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2708_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2708_1-R_34_667m
+.ENDS wire90-2708_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2733_2-R_34_667m a b
+Ccap@0 gnd net@14 10.022f
+Ccap@1 gnd net@8 10.022f
+Ccap@2 gnd net@11 10.022f
+Rres@0 net@14 a 15.792
+Rres@1 net@11 net@14 31.584
+Rres@2 b net@8 15.792
+Rres@3 net@8 net@11 31.584
+.ENDS wire-C_0_011f-2733_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2733_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2733_2-R_34_667m
+.ENDS wire90-2733_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2760_1-R_34_667m a b
+Ccap@0 gnd net@14 10.12f
+Ccap@1 gnd net@8 10.12f
+Ccap@2 gnd net@11 10.12f
+Rres@0 net@14 a 15.947
+Rres@1 net@11 net@14 31.894
+Rres@2 b net@8 15.947
+Rres@3 net@8 net@11 31.894
+.ENDS wire-C_0_011f-2760_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2760_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2760_1-R_34_667m
+.ENDS wire90-2760_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2778_7-R_34_667m a b
+Ccap@0 gnd net@14 10.189f
+Ccap@1 gnd net@8 10.189f
+Ccap@2 gnd net@11 10.189f
+Rres@0 net@14 a 16.055
+Rres@1 net@11 net@14 32.109
+Rres@2 b net@8 16.055
+Rres@3 net@8 net@11 32.109
+.ENDS wire-C_0_011f-2778_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2778_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2778_7-R_34_667m
+.ENDS wire90-2778_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3023_6-R_34_667m a b
+Ccap@0 gnd net@14 11.087f
+Ccap@1 gnd net@8 11.087f
+Ccap@2 gnd net@11 11.087f
+Rres@0 net@14 a 17.47
+Rres@1 net@11 net@14 34.939
+Rres@2 b net@8 17.47
+Rres@3 net@8 net@11 34.939
+.ENDS wire-C_0_011f-3023_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3023_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3023_6-R_34_667m
+.ENDS wire90-3023_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3036_1-R_34_667m a b
+Ccap@0 gnd net@14 11.132f
+Ccap@1 gnd net@8 11.132f
+Ccap@2 gnd net@11 11.132f
+Rres@0 net@14 a 17.542
+Rres@1 net@11 net@14 35.084
+Rres@2 b net@8 17.542
+Rres@3 net@8 net@11 35.084
+.ENDS wire-C_0_011f-3036_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3036_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3036_1-R_34_667m
+.ENDS wire90-3036_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3046_6-R_34_667m a b
+Ccap@0 gnd net@14 11.171f
+Ccap@1 gnd net@8 11.171f
+Ccap@2 gnd net@11 11.171f
+Rres@0 net@14 a 17.603
+Rres@1 net@11 net@14 35.205
+Rres@2 b net@8 17.603
+Rres@3 net@8 net@11 35.205
+.ENDS wire-C_0_011f-3046_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3046_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3046_6-R_34_667m
+.ENDS wire90-3046_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3053_1-R_34_667m a b
+Ccap@0 gnd net@14 11.195f
+Ccap@1 gnd net@8 11.195f
+Ccap@2 gnd net@11 11.195f
+Rres@0 net@14 a 17.64
+Rres@1 net@11 net@14 35.28
+Rres@2 b net@8 17.64
+Rres@3 net@8 net@11 35.28
+.ENDS wire-C_0_011f-3053_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3053_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3053_1-R_34_667m
+.ENDS wire90-3053_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3026-R_34_667m a b
+Ccap@0 gnd net@14 11.095f
+Ccap@1 gnd net@8 11.095f
+Ccap@2 gnd net@11 11.095f
+Rres@0 net@14 a 17.484
+Rres@1 net@11 net@14 34.967
+Rres@2 b net@8 17.484
+Rres@3 net@8 net@11 34.967
+.ENDS wire-C_0_011f-3026-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3026-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3026-R_34_667m
+.ENDS wire90-3026-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3048_1-R_34_667m a b
+Ccap@0 gnd net@14 11.176f
+Ccap@1 gnd net@8 11.176f
+Ccap@2 gnd net@11 11.176f
+Rres@0 net@14 a 17.611
+Rres@1 net@11 net@14 35.222
+Rres@2 b net@8 17.611
+Rres@3 net@8 net@11 35.222
+.ENDS wire-C_0_011f-3048_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3048_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3048_1-R_34_667m
+.ENDS wire90-3048_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3091_7-R_34_667m a b
+Ccap@0 gnd net@14 11.336f
+Ccap@1 gnd net@8 11.336f
+Ccap@2 gnd net@11 11.336f
+Rres@0 net@14 a 17.863
+Rres@1 net@11 net@14 35.726
+Rres@2 b net@8 17.863
+Rres@3 net@8 net@11 35.726
+.ENDS wire-C_0_011f-3091_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3091_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3091_7-R_34_667m
+.ENDS wire90-3091_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3099_6-R_34_667m a b
+Ccap@0 gnd net@14 11.365f
+Ccap@1 gnd net@8 11.365f
+Ccap@2 gnd net@11 11.365f
+Rres@0 net@14 a 17.909
+Rres@1 net@11 net@14 35.818
+Rres@2 b net@8 17.909
+Rres@3 net@8 net@11 35.818
+.ENDS wire-C_0_011f-3099_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3099_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3099_6-R_34_667m
+.ENDS wire90-3099_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3147_7-R_34_667m a b
+Ccap@0 gnd net@14 11.542f
+Ccap@1 gnd net@8 11.542f
+Ccap@2 gnd net@11 11.542f
+Rres@0 net@14 a 18.187
+Rres@1 net@11 net@14 36.373
+Rres@2 b net@8 18.187
+Rres@3 net@8 net@11 36.373
+.ENDS wire-C_0_011f-3147_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3147_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3147_7-R_34_667m
+.ENDS wire90-3147_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3187_6-R_34_667m a b
+Ccap@0 gnd net@14 11.688f
+Ccap@1 gnd net@8 11.688f
+Ccap@2 gnd net@11 11.688f
+Rres@0 net@14 a 18.417
+Rres@1 net@11 net@14 36.834
+Rres@2 b net@8 18.417
+Rres@3 net@8 net@11 36.834
+.ENDS wire-C_0_011f-3187_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3187_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3187_6-R_34_667m
+.ENDS wire90-3187_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3208_7-R_34_667m a b
+Ccap@0 gnd net@14 11.765f
+Ccap@1 gnd net@8 11.765f
+Ccap@2 gnd net@11 11.765f
+Rres@0 net@14 a 18.539
+Rres@1 net@11 net@14 37.078
+Rres@2 b net@8 18.539
+Rres@3 net@8 net@11 37.078
+.ENDS wire-C_0_011f-3208_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3208_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3208_7-R_34_667m
+.ENDS wire90-3208_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3235_6-R_34_667m a b
+Ccap@0 gnd net@14 11.864f
+Ccap@1 gnd net@8 11.864f
+Ccap@2 gnd net@11 11.864f
+Rres@0 net@14 a 18.695
+Rres@1 net@11 net@14 37.389
+Rres@2 b net@8 18.695
+Rres@3 net@8 net@11 37.389
+.ENDS wire-C_0_011f-3235_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3235_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3235_6-R_34_667m
+.ENDS wire90-3235_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3260_7-R_34_667m a b
+Ccap@0 gnd net@14 11.956f
+Ccap@1 gnd net@8 11.956f
+Ccap@2 gnd net@11 11.956f
+Rres@0 net@14 a 18.84
+Rres@1 net@11 net@14 37.679
+Rres@2 b net@8 18.84
+Rres@3 net@8 net@11 37.679
+.ENDS wire-C_0_011f-3260_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3260_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3260_7-R_34_667m
+.ENDS wire90-3260_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3287_6-R_34_667m a b
+Ccap@0 gnd net@14 12.055f
+Ccap@1 gnd net@8 12.055f
+Ccap@2 gnd net@11 12.055f
+Rres@0 net@14 a 18.995
+Rres@1 net@11 net@14 37.99
+Rres@2 b net@8 18.995
+Rres@3 net@8 net@11 37.99
+.ENDS wire-C_0_011f-3287_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3287_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3287_6-R_34_667m
+.ENDS wire90-3287_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3306_2-R_34_667m a b
+Ccap@0 gnd net@14 12.123f
+Ccap@1 gnd net@8 12.123f
+Ccap@2 gnd net@11 12.123f
+Rres@0 net@14 a 19.102
+Rres@1 net@11 net@14 38.205
+Rres@2 b net@8 19.102
+Rres@3 net@8 net@11 38.205
+.ENDS wire-C_0_011f-3306_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3306_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3306_2-R_34_667m
+.ENDS wire90-3306_2-layer_1-width_3
+
+*** CELL: fifoL:splitStageDx4{sch}
+.SUBCKT splitStageDx4 clS[1][F] clS[1][T] clS[2][F] clS[2][T] cl[1][F] 
++cl[1][T] cl[2][F] cl[2][T] freqOut in[10] in[11] in[12] in[13] in[14] in[15] 
++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] 
++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] 
++in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc[1] mc[2] out[10] out[11] 
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] 
++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] 
++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] 
++out[4] out[5] out[6] out[7] out[8] out[9] pred rd[1][F] rd[1][T] rd[2][F] 
++rd[2][T] sin[1] sin[2] sout[1] sout[2] succ
+XsplitSta@4 clS[1][F] clS[1][T] cl[1][F] cl[1][T] splitSta@4_freqOut in[10] 
++in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] 
++in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] 
++in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] 
++in[9] mc[1] xx[10] xx[11] xx[12] xx[13] xx[14] xx[15] xx[16] xx[17] xx[18] 
++xx[19] xx[1] xx[20] xx[21] xx[22] xx[23] xx[24] xx[25] xx[26] xx[27] xx[28] 
++xx[29] xx[2] xx[30] xx[31] xx[32] xx[33] xx[34] xx[35] xx[36] xx[3] xx[4] 
++xx[5] xx[6] xx[7] xx[8] xx[9] pred rd[1][F] rd[1][T] sin[1] sout[1] net@255 
++splitStageDx2
+XsplitSta@5 clS[2][F] clS[2][T] cl[2][F] cl[2][T] freqOut xx[10] xx[11] 
++xx[12] xx[13] xx[14] xx[15] xx[16] xx[17] xx[18] xx[19] xx[1] xx[20] xx[21] 
++xx[22] xx[23] xx[24] xx[25] xx[26] xx[27] xx[28] xx[29] xx[2] xx[30] xx[31] 
++xx[32] xx[33] xx[34] xx[35] xx[36] xx[3] xx[4] xx[5] xx[6] xx[7] xx[8] xx[9] 
++mc[2] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@258 
++rd[2][F] rd[2][T] sin[2] sout[2] succ splitStageDx2
+Xwire90@3 net@255 net@258 wire90-2777_3-layer_1-width_3
+Xwire90@4 xx[1] wire90@4_b wire90-2581_1-layer_1-width_3
+Xwire90@5 xx[2] wire90@5_b wire90-2599_6-layer_1-width_3
+Xwire90@6 xx[3] wire90@6_b wire90-2611_1-layer_1-width_3
+Xwire90@7 xx[4] wire90@7_b wire90-2654_1-layer_1-width_3
+Xwire90@8 xx[5] wire90@8_b wire90-2637_1-layer_1-width_3
+Xwire90@9 xx[6] wire90@9_b wire90-2690_6-layer_1-width_3
+Xwire90@10 xx[7] wire90@10_b wire90-2675_5-layer_1-width_3
+Xwire90@11 xx[8] wire90@11_b wire90-2737_6-layer_1-width_3
+Xwire90@12 xx[9] wire90@12_b wire90-2725_1-layer_1-width_3
+Xwire90@13 xx[10] wire90@13_b wire90-2582_2-layer_1-width_3
+Xwire90@14 xx[11] wire90@14_b wire90-2584_1-layer_1-width_3
+Xwire90@15 xx[12] wire90@15_b wire90-2620_2-layer_1-width_3
+Xwire90@16 xx[13] wire90@16_b wire90-2660_1-layer_1-width_3
+Xwire90@17 xx[14] wire90@17_b wire90-2681_2-layer_1-width_3
+Xwire90@18 xx[15] wire90@18_b wire90-2708_1-layer_1-width_3
+Xwire90@19 xx[16] wire90@19_b wire90-2733_2-layer_1-width_3
+Xwire90@20 xx[17] wire90@20_b wire90-2760_1-layer_1-width_3
+Xwire90@21 xx[18] wire90@21_b wire90-2778_7-layer_1-width_3
+Xwire90@22 xx[19] wire90@22_b wire90-3023_6-layer_1-width_3
+Xwire90@23 xx[20] wire90@23_b wire90-3036_1-layer_1-width_3
+Xwire90@24 xx[21] wire90@24_b wire90-3023_6-layer_1-width_3
+Xwire90@25 xx[22] wire90@25_b wire90-3046_6-layer_1-width_3
+Xwire90@26 xx[23] wire90@26_b wire90-3023_6-layer_1-width_3
+Xwire90@27 xx[24] wire90@27_b wire90-3053_1-layer_1-width_3
+Xwire90@28 xx[25] wire90@28_b wire90-3026-layer_1-width_3
+Xwire90@29 xx[26] wire90@29_b wire90-3048_1-layer_1-width_3
+Xwire90@30 xx[27] wire90@30_b wire90-3023_6-layer_1-width_3
+Xwire90@31 xx[28] wire90@31_b wire90-3091_7-layer_1-width_3
+Xwire90@32 xx[29] wire90@32_b wire90-3099_6-layer_1-width_3
+Xwire90@33 xx[30] wire90@33_b wire90-3147_7-layer_1-width_3
+Xwire90@34 xx[31] wire90@34_b wire90-3187_6-layer_1-width_3
+Xwire90@35 xx[32] wire90@35_b wire90-3208_7-layer_1-width_3
+Xwire90@36 xx[33] wire90@36_b wire90-3235_6-layer_1-width_3
+Xwire90@37 xx[34] wire90@37_b wire90-3260_7-layer_1-width_3
+Xwire90@38 xx[35] wire90@38_b wire90-3287_6-layer_1-width_3
+Xwire90@39 xx[36] wire90@39_b wire90-3306_2-layer_1-width_3
+.ENDS splitStageDx4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1085-R_34_667m a b
+Ccap@0 gnd net@14 3.978f
+Ccap@1 gnd net@8 3.978f
+Ccap@2 gnd net@11 3.978f
+Rres@0 net@14 a 6.269
+Rres@1 net@11 net@14 12.538
+Rres@2 b net@8 6.269
+Rres@3 net@8 net@11 12.538
+.ENDS wire-C_0_011f-1085-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1085-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1085-R_34_667m
+.ENDS wire90-1085-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2816_7-R_34_667m a b
+Ccap@0 gnd net@14 10.328f
+Ccap@1 gnd net@8 10.328f
+Ccap@2 gnd net@11 10.328f
+Rres@0 net@14 a 16.274
+Rres@1 net@11 net@14 32.549
+Rres@2 b net@8 16.274
+Rres@3 net@8 net@11 32.549
+.ENDS wire-C_0_011f-2816_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2816_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2816_7-R_34_667m
+.ENDS wire90-2816_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1847-R_34_667m a b
+Ccap@0 gnd net@14 6.772f
+Ccap@1 gnd net@8 6.772f
+Ccap@2 gnd net@11 6.772f
+Rres@0 net@14 a 10.672
+Rres@1 net@11 net@14 21.343
+Rres@2 b net@8 10.672
+Rres@3 net@8 net@11 21.343
+.ENDS wire-C_0_011f-1847-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1847-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1847-R_34_667m
+.ENDS wire90-1847-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1161-R_34_667m a b
+Ccap@0 gnd net@14 4.257f
+Ccap@1 gnd net@8 4.257f
+Ccap@2 gnd net@11 4.257f
+Rres@0 net@14 a 6.708
+Rres@1 net@11 net@14 13.416
+Rres@2 b net@8 6.708
+Rres@3 net@8 net@11 13.416
+.ENDS wire-C_0_011f-1161-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1161-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1161-R_34_667m
+.ENDS wire90-1161-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-941-R_34_667m a b
+Ccap@0 gnd net@14 3.45f
+Ccap@1 gnd net@8 3.45f
+Ccap@2 gnd net@11 3.45f
+Rres@0 net@14 a 5.437
+Rres@1 net@11 net@14 10.874
+Rres@2 b net@8 5.437
+Rres@3 net@8 net@11 10.874
+.ENDS wire-C_0_011f-941-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-941-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-941-R_34_667m
+.ENDS wire90-941-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-992_5-R_34_667m a b
+Ccap@0 gnd net@14 3.639f
+Ccap@1 gnd net@8 3.639f
+Ccap@2 gnd net@11 3.639f
+Rres@0 net@14 a 5.734
+Rres@1 net@11 net@14 11.469
+Rres@2 b net@8 5.734
+Rres@3 net@8 net@11 11.469
+.ENDS wire-C_0_011f-992_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-992_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-992_5-R_34_667m
+.ENDS wire90-992_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-924_4-R_34_667m a b
+Ccap@0 gnd net@14 3.389f
+Ccap@1 gnd net@8 3.389f
+Ccap@2 gnd net@11 3.389f
+Rres@0 net@14 a 5.341
+Rres@1 net@11 net@14 10.682
+Rres@2 b net@8 5.341
+Rres@3 net@8 net@11 10.682
+.ENDS wire-C_0_011f-924_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-924_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-924_4-R_34_667m
+.ENDS wire90-924_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1463_4-R_34_667m a b
+Ccap@0 gnd net@14 5.366f
+Ccap@1 gnd net@8 5.366f
+Ccap@2 gnd net@11 5.366f
+Rres@0 net@14 a 8.455
+Rres@1 net@11 net@14 16.91
+Rres@2 b net@8 8.455
+Rres@3 net@8 net@11 16.91
+.ENDS wire-C_0_011f-1463_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1463_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1463_4-R_34_667m
+.ENDS wire90-1463_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1346_1-R_34_667m a b
+Ccap@0 gnd net@14 4.936f
+Ccap@1 gnd net@8 4.936f
+Ccap@2 gnd net@11 4.936f
+Rres@0 net@14 a 7.777
+Rres@1 net@11 net@14 15.555
+Rres@2 b net@8 7.777
+Rres@3 net@8 net@11 15.555
+.ENDS wire-C_0_011f-1346_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1346_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1346_1-R_34_667m
+.ENDS wire90-1346_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1337_6-R_34_667m a b
+Ccap@0 gnd net@14 4.905f
+Ccap@1 gnd net@8 4.905f
+Ccap@2 gnd net@11 4.905f
+Rres@0 net@14 a 7.728
+Rres@1 net@11 net@14 15.457
+Rres@2 b net@8 7.728
+Rres@3 net@8 net@11 15.457
+.ENDS wire-C_0_011f-1337_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1337_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1337_6-R_34_667m
+.ENDS wire90-1337_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1339_1-R_34_667m a b
+Ccap@0 gnd net@14 4.91f
+Ccap@1 gnd net@8 4.91f
+Ccap@2 gnd net@11 4.91f
+Rres@0 net@14 a 7.737
+Rres@1 net@11 net@14 15.474
+Rres@2 b net@8 7.737
+Rres@3 net@8 net@11 15.474
+.ENDS wire-C_0_011f-1339_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1339_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1339_1-R_34_667m
+.ENDS wire90-1339_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1356_6-R_34_667m a b
+Ccap@0 gnd net@14 4.974f
+Ccap@1 gnd net@8 4.974f
+Ccap@2 gnd net@11 4.974f
+Rres@0 net@14 a 7.838
+Rres@1 net@11 net@14 15.676
+Rres@2 b net@8 7.838
+Rres@3 net@8 net@11 15.676
+.ENDS wire-C_0_011f-1356_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1356_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1356_6-R_34_667m
+.ENDS wire90-1356_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1341_1-R_34_667m a b
+Ccap@0 gnd net@14 4.917f
+Ccap@1 gnd net@8 4.917f
+Ccap@2 gnd net@11 4.917f
+Rres@0 net@14 a 7.749
+Rres@1 net@11 net@14 15.497
+Rres@2 b net@8 7.749
+Rres@3 net@8 net@11 15.497
+.ENDS wire-C_0_011f-1341_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1341_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1341_1-R_34_667m
+.ENDS wire90-1341_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1345_1-R_34_667m a b
+Ccap@0 gnd net@14 4.932f
+Ccap@1 gnd net@8 4.932f
+Ccap@2 gnd net@11 4.932f
+Rres@0 net@14 a 7.772
+Rres@1 net@11 net@14 15.543
+Rres@2 b net@8 7.772
+Rres@3 net@8 net@11 15.543
+.ENDS wire-C_0_011f-1345_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1345_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1345_1-R_34_667m
+.ENDS wire90-1345_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1361_4-R_34_667m a b
+Ccap@0 gnd net@14 4.992f
+Ccap@1 gnd net@8 4.992f
+Ccap@2 gnd net@11 4.992f
+Rres@0 net@14 a 7.866
+Rres@1 net@11 net@14 15.732
+Rres@2 b net@8 7.866
+Rres@3 net@8 net@11 15.732
+.ENDS wire-C_0_011f-1361_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1361_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1361_4-R_34_667m
+.ENDS wire90-1361_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1342_1-R_34_667m a b
+Ccap@0 gnd net@14 4.921f
+Ccap@1 gnd net@8 4.921f
+Ccap@2 gnd net@11 4.921f
+Rres@0 net@14 a 7.754
+Rres@1 net@11 net@14 15.509
+Rres@2 b net@8 7.754
+Rres@3 net@8 net@11 15.509
+.ENDS wire-C_0_011f-1342_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1342_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1342_1-R_34_667m
+.ENDS wire90-1342_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1349_6-R_34_667m a b
+Ccap@0 gnd net@14 4.949f
+Ccap@1 gnd net@8 4.949f
+Ccap@2 gnd net@11 4.949f
+Rres@0 net@14 a 7.798
+Rres@1 net@11 net@14 15.595
+Rres@2 b net@8 7.798
+Rres@3 net@8 net@11 15.595
+.ENDS wire-C_0_011f-1349_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1349_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1349_6-R_34_667m
+.ENDS wire90-1349_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1345_8-R_34_667m a b
+Ccap@0 gnd net@14 4.935f
+Ccap@1 gnd net@8 4.935f
+Ccap@2 gnd net@11 4.935f
+Rres@0 net@14 a 7.776
+Rres@1 net@11 net@14 15.551
+Rres@2 b net@8 7.776
+Rres@3 net@8 net@11 15.551
+.ENDS wire-C_0_011f-1345_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1345_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1345_8-R_34_667m
+.ENDS wire90-1345_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1346_7-R_34_667m a b
+Ccap@0 gnd net@14 4.938f
+Ccap@1 gnd net@8 4.938f
+Ccap@2 gnd net@11 4.938f
+Rres@0 net@14 a 7.781
+Rres@1 net@11 net@14 15.562
+Rres@2 b net@8 7.781
+Rres@3 net@8 net@11 15.562
+.ENDS wire-C_0_011f-1346_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1346_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1346_7-R_34_667m
+.ENDS wire90-1346_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1330_8-R_34_667m a b
+Ccap@0 gnd net@14 4.88f
+Ccap@1 gnd net@8 4.88f
+Ccap@2 gnd net@11 4.88f
+Rres@0 net@14 a 7.689
+Rres@1 net@11 net@14 15.378
+Rres@2 b net@8 7.689
+Rres@3 net@8 net@11 15.378
+.ENDS wire-C_0_011f-1330_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1330_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1330_8-R_34_667m
+.ENDS wire90-1330_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1339_7-R_34_667m a b
+Ccap@0 gnd net@14 4.912f
+Ccap@1 gnd net@8 4.912f
+Ccap@2 gnd net@11 4.912f
+Rres@0 net@14 a 7.74
+Rres@1 net@11 net@14 15.481
+Rres@2 b net@8 7.74
+Rres@3 net@8 net@11 15.481
+.ENDS wire-C_0_011f-1339_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1339_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1339_7-R_34_667m
+.ENDS wire90-1339_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1353_3-R_34_667m a b
+Ccap@0 gnd net@14 4.962f
+Ccap@1 gnd net@8 4.962f
+Ccap@2 gnd net@11 4.962f
+Rres@0 net@14 a 7.819
+Rres@1 net@11 net@14 15.638
+Rres@2 b net@8 7.819
+Rres@3 net@8 net@11 15.638
+.ENDS wire-C_0_011f-1353_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1353_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1353_3-R_34_667m
+.ENDS wire90-1353_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1355_2-R_34_667m a b
+Ccap@0 gnd net@14 4.969f
+Ccap@1 gnd net@8 4.969f
+Ccap@2 gnd net@11 4.969f
+Rres@0 net@14 a 7.83
+Rres@1 net@11 net@14 15.66
+Rres@2 b net@8 7.83
+Rres@3 net@8 net@11 15.66
+.ENDS wire-C_0_011f-1355_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1355_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1355_2-R_34_667m
+.ENDS wire90-1355_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1359_3-R_34_667m a b
+Ccap@0 gnd net@14 4.984f
+Ccap@1 gnd net@8 4.984f
+Ccap@2 gnd net@11 4.984f
+Rres@0 net@14 a 7.854
+Rres@1 net@11 net@14 15.707
+Rres@2 b net@8 7.854
+Rres@3 net@8 net@11 15.707
+.ENDS wire-C_0_011f-1359_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1359_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1359_3-R_34_667m
+.ENDS wire90-1359_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1357_2-R_34_667m a b
+Ccap@0 gnd net@14 4.976f
+Ccap@1 gnd net@8 4.976f
+Ccap@2 gnd net@11 4.976f
+Rres@0 net@14 a 7.842
+Rres@1 net@11 net@14 15.683
+Rres@2 b net@8 7.842
+Rres@3 net@8 net@11 15.683
+.ENDS wire-C_0_011f-1357_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1357_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1357_2-R_34_667m
+.ENDS wire90-1357_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1356_1-R_34_667m a b
+Ccap@0 gnd net@14 4.972f
+Ccap@1 gnd net@8 4.972f
+Ccap@2 gnd net@11 4.972f
+Rres@0 net@14 a 7.835
+Rres@1 net@11 net@14 15.67
+Rres@2 b net@8 7.835
+Rres@3 net@8 net@11 15.67
+.ENDS wire-C_0_011f-1356_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1356_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1356_1-R_34_667m
+.ENDS wire90-1356_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1379_1-R_34_667m a b
+Ccap@0 gnd net@14 5.057f
+Ccap@1 gnd net@8 5.057f
+Ccap@2 gnd net@11 5.057f
+Rres@0 net@14 a 7.968
+Rres@1 net@11 net@14 15.936
+Rres@2 b net@8 7.968
+Rres@3 net@8 net@11 15.936
+.ENDS wire-C_0_011f-1379_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1379_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1379_1-R_34_667m
+.ENDS wire90-1379_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1351_6-R_34_667m a b
+Ccap@0 gnd net@14 4.956f
+Ccap@1 gnd net@8 4.956f
+Ccap@2 gnd net@11 4.956f
+Rres@0 net@14 a 7.809
+Rres@1 net@11 net@14 15.618
+Rres@2 b net@8 7.809
+Rres@3 net@8 net@11 15.618
+.ENDS wire-C_0_011f-1351_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1351_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1351_6-R_34_667m
+.ENDS wire90-1351_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1376_6-R_34_667m a b
+Ccap@0 gnd net@14 5.048f
+Ccap@1 gnd net@8 5.048f
+Ccap@2 gnd net@11 5.048f
+Rres@0 net@14 a 7.954
+Rres@1 net@11 net@14 15.907
+Rres@2 b net@8 7.954
+Rres@3 net@8 net@11 15.907
+.ENDS wire-C_0_011f-1376_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1376_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1376_6-R_34_667m
+.ENDS wire90-1376_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1372_4-R_34_667m a b
+Ccap@0 gnd net@14 5.032f
+Ccap@1 gnd net@8 5.032f
+Ccap@2 gnd net@11 5.032f
+Rres@0 net@14 a 7.929
+Rres@1 net@11 net@14 15.859
+Rres@2 b net@8 7.929
+Rres@3 net@8 net@11 15.859
+.ENDS wire-C_0_011f-1372_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1372_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1372_4-R_34_667m
+.ENDS wire90-1372_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1373_6-R_34_667m a b
+Ccap@0 gnd net@14 5.037f
+Ccap@1 gnd net@8 5.037f
+Ccap@2 gnd net@11 5.037f
+Rres@0 net@14 a 7.936
+Rres@1 net@11 net@14 15.873
+Rres@2 b net@8 7.936
+Rres@3 net@8 net@11 15.873
+.ENDS wire-C_0_011f-1373_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1373_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1373_6-R_34_667m
+.ENDS wire90-1373_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1360_1-R_34_667m a b
+Ccap@0 gnd net@14 4.987f
+Ccap@1 gnd net@8 4.987f
+Ccap@2 gnd net@11 4.987f
+Rres@0 net@14 a 7.858
+Rres@1 net@11 net@14 15.717
+Rres@2 b net@8 7.858
+Rres@3 net@8 net@11 15.717
+.ENDS wire-C_0_011f-1360_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1360_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1360_1-R_34_667m
+.ENDS wire90-1360_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1323_3-R_34_667m a b
+Ccap@0 gnd net@14 4.852f
+Ccap@1 gnd net@8 4.852f
+Ccap@2 gnd net@11 4.852f
+Rres@0 net@14 a 7.646
+Rres@1 net@11 net@14 15.291
+Rres@2 b net@8 7.646
+Rres@3 net@8 net@11 15.291
+.ENDS wire-C_0_011f-1323_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1323_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1323_3-R_34_667m
+.ENDS wire90-1323_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1330_3-R_34_667m a b
+Ccap@0 gnd net@14 4.878f
+Ccap@1 gnd net@8 4.878f
+Ccap@2 gnd net@11 4.878f
+Rres@0 net@14 a 7.686
+Rres@1 net@11 net@14 15.372
+Rres@2 b net@8 7.686
+Rres@3 net@8 net@11 15.372
+.ENDS wire-C_0_011f-1330_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1330_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1330_3-R_34_667m
+.ENDS wire90-1330_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1329_2-R_34_667m a b
+Ccap@0 gnd net@14 4.874f
+Ccap@1 gnd net@8 4.874f
+Ccap@2 gnd net@11 4.874f
+Rres@0 net@14 a 7.68
+Rres@1 net@11 net@14 15.36
+Rres@2 b net@8 7.68
+Rres@3 net@8 net@11 15.36
+.ENDS wire-C_0_011f-1329_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1329_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1329_2-R_34_667m
+.ENDS wire90-1329_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1325_8-R_34_667m a b
+Ccap@0 gnd net@14 4.861f
+Ccap@1 gnd net@8 4.861f
+Ccap@2 gnd net@11 4.861f
+Rres@0 net@14 a 7.66
+Rres@1 net@11 net@14 15.32
+Rres@2 b net@8 7.66
+Rres@3 net@8 net@11 15.32
+.ENDS wire-C_0_011f-1325_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1325_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1325_8-R_34_667m
+.ENDS wire90-1325_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1344_7-R_34_667m a b
+Ccap@0 gnd net@14 4.931f
+Ccap@1 gnd net@8 4.931f
+Ccap@2 gnd net@11 4.931f
+Rres@0 net@14 a 7.769
+Rres@1 net@11 net@14 15.539
+Rres@2 b net@8 7.769
+Rres@3 net@8 net@11 15.539
+.ENDS wire-C_0_011f-1344_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1344_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1344_7-R_34_667m
+.ENDS wire90-1344_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1327_8-R_34_667m a b
+Ccap@0 gnd net@14 4.869f
+Ccap@1 gnd net@8 4.869f
+Ccap@2 gnd net@11 4.869f
+Rres@0 net@14 a 7.672
+Rres@1 net@11 net@14 15.343
+Rres@2 b net@8 7.672
+Rres@3 net@8 net@11 15.343
+.ENDS wire-C_0_011f-1327_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1327_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1327_8-R_34_667m
+.ENDS wire90-1327_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1321_8-R_34_667m a b
+Ccap@0 gnd net@14 4.847f
+Ccap@1 gnd net@8 4.847f
+Ccap@2 gnd net@11 4.847f
+Rres@0 net@14 a 7.637
+Rres@1 net@11 net@14 15.274
+Rres@2 b net@8 7.637
+Rres@3 net@8 net@11 15.274
+.ENDS wire-C_0_011f-1321_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1321_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1321_8-R_34_667m
+.ENDS wire90-1321_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-638-R_34_667m a b
+Ccap@0 gnd net@14 2.339f
+Ccap@1 gnd net@8 2.339f
+Ccap@2 gnd net@11 2.339f
+Rres@0 net@14 a 3.686
+Rres@1 net@11 net@14 7.372
+Rres@2 b net@8 3.686
+Rres@3 net@8 net@11 7.372
+.ENDS wire-C_0_011f-638-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-638-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-638-R_34_667m
+.ENDS wire90-638-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-641-R_34_667m a b
+Ccap@0 gnd net@14 2.35f
+Ccap@1 gnd net@8 2.35f
+Ccap@2 gnd net@11 2.35f
+Rres@0 net@14 a 3.704
+Rres@1 net@11 net@14 7.407
+Rres@2 b net@8 3.704
+Rres@3 net@8 net@11 7.407
+.ENDS wire-C_0_011f-641-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-641-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-641-R_34_667m
+.ENDS wire90-641-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-644-R_34_667m a b
+Ccap@0 gnd net@14 2.361f
+Ccap@1 gnd net@8 2.361f
+Ccap@2 gnd net@11 2.361f
+Rres@0 net@14 a 3.721
+Rres@1 net@11 net@14 7.442
+Rres@2 b net@8 3.721
+Rres@3 net@8 net@11 7.442
+.ENDS wire-C_0_011f-644-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-644-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-644-R_34_667m
+.ENDS wire90-644-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-635-R_34_667m a b
+Ccap@0 gnd net@14 2.328f
+Ccap@1 gnd net@8 2.328f
+Ccap@2 gnd net@11 2.328f
+Rres@0 net@14 a 3.669
+Rres@1 net@11 net@14 7.338
+Rres@2 b net@8 3.669
+Rres@3 net@8 net@11 7.338
+.ENDS wire-C_0_011f-635-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-635-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-635-R_34_667m
+.ENDS wire90-635-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-666-R_34_667m a b
+Ccap@0 gnd net@14 2.442f
+Ccap@1 gnd net@8 2.442f
+Ccap@2 gnd net@11 2.442f
+Rres@0 net@14 a 3.848
+Rres@1 net@11 net@14 7.696
+Rres@2 b net@8 3.848
+Rres@3 net@8 net@11 7.696
+.ENDS wire-C_0_011f-666-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-666-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-666-R_34_667m
+.ENDS wire90-666-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-633_5-R_34_667m a b
+Ccap@0 gnd net@14 2.323f
+Ccap@1 gnd net@8 2.323f
+Ccap@2 gnd net@11 2.323f
+Rres@0 net@14 a 3.66
+Rres@1 net@11 net@14 7.32
+Rres@2 b net@8 3.66
+Rres@3 net@8 net@11 7.32
+.ENDS wire-C_0_011f-633_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-633_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-633_5-R_34_667m
+.ENDS wire90-633_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-655-R_34_667m a b
+Ccap@0 gnd net@14 2.402f
+Ccap@1 gnd net@8 2.402f
+Ccap@2 gnd net@11 2.402f
+Rres@0 net@14 a 3.784
+Rres@1 net@11 net@14 7.569
+Rres@2 b net@8 3.784
+Rres@3 net@8 net@11 7.569
+.ENDS wire-C_0_011f-655-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-655-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-655-R_34_667m
+.ENDS wire90-655-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-636_5-R_34_667m a b
+Ccap@0 gnd net@14 2.334f
+Ccap@1 gnd net@8 2.334f
+Ccap@2 gnd net@11 2.334f
+Rres@0 net@14 a 3.678
+Rres@1 net@11 net@14 7.355
+Rres@2 b net@8 3.678
+Rres@3 net@8 net@11 7.355
+.ENDS wire-C_0_011f-636_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-636_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-636_5-R_34_667m
+.ENDS wire90-636_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-594_5-R_34_667m a b
+Ccap@0 gnd net@14 2.18f
+Ccap@1 gnd net@8 2.18f
+Ccap@2 gnd net@11 2.18f
+Rres@0 net@14 a 3.435
+Rres@1 net@11 net@14 6.87
+Rres@2 b net@8 3.435
+Rres@3 net@8 net@11 6.87
+.ENDS wire-C_0_011f-594_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-594_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-594_5-R_34_667m
+.ENDS wire90-594_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-599_4-R_34_667m a b
+Ccap@0 gnd net@14 2.198f
+Ccap@1 gnd net@8 2.198f
+Ccap@2 gnd net@11 2.198f
+Rres@0 net@14 a 3.463
+Rres@1 net@11 net@14 6.926
+Rres@2 b net@8 3.463
+Rres@3 net@8 net@11 6.926
+.ENDS wire-C_0_011f-599_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-599_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-599_4-R_34_667m
+.ENDS wire90-599_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-590_5-R_34_667m a b
+Ccap@0 gnd net@14 2.165f
+Ccap@1 gnd net@8 2.165f
+Ccap@2 gnd net@11 2.165f
+Rres@0 net@14 a 3.412
+Rres@1 net@11 net@14 6.824
+Rres@2 b net@8 3.412
+Rres@3 net@8 net@11 6.824
+.ENDS wire-C_0_011f-590_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-590_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-590_5-R_34_667m
+.ENDS wire90-590_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-601_6-R_34_667m a b
+Ccap@0 gnd net@14 2.206f
+Ccap@1 gnd net@8 2.206f
+Ccap@2 gnd net@11 2.206f
+Rres@0 net@14 a 3.476
+Rres@1 net@11 net@14 6.952
+Rres@2 b net@8 3.476
+Rres@3 net@8 net@11 6.952
+.ENDS wire-C_0_011f-601_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-601_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-601_6-R_34_667m
+.ENDS wire90-601_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-605-R_34_667m a b
+Ccap@0 gnd net@14 2.218f
+Ccap@1 gnd net@8 2.218f
+Ccap@2 gnd net@11 2.218f
+Rres@0 net@14 a 3.496
+Rres@1 net@11 net@14 6.991
+Rres@2 b net@8 3.496
+Rres@3 net@8 net@11 6.991
+.ENDS wire-C_0_011f-605-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-605-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-605-R_34_667m
+.ENDS wire90-605-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-594_9-R_34_667m a b
+Ccap@0 gnd net@14 2.181f
+Ccap@1 gnd net@8 2.181f
+Ccap@2 gnd net@11 2.181f
+Rres@0 net@14 a 3.437
+Rres@1 net@11 net@14 6.874
+Rres@2 b net@8 3.437
+Rres@3 net@8 net@11 6.874
+.ENDS wire-C_0_011f-594_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-594_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-594_9-R_34_667m
+.ENDS wire90-594_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-600-R_34_667m a b
+Ccap@0 gnd net@14 2.2f
+Ccap@1 gnd net@8 2.2f
+Ccap@2 gnd net@11 2.2f
+Rres@0 net@14 a 3.467
+Rres@1 net@11 net@14 6.933
+Rres@2 b net@8 3.467
+Rres@3 net@8 net@11 6.933
+.ENDS wire-C_0_011f-600-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-600-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-600-R_34_667m
+.ENDS wire90-600-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-639_5-R_34_667m a b
+Ccap@0 gnd net@14 2.345f
+Ccap@1 gnd net@8 2.345f
+Ccap@2 gnd net@11 2.345f
+Rres@0 net@14 a 3.695
+Rres@1 net@11 net@14 7.39
+Rres@2 b net@8 3.695
+Rres@3 net@8 net@11 7.39
+.ENDS wire-C_0_011f-639_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-639_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-639_5-R_34_667m
+.ENDS wire90-639_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-655_5-R_34_667m a b
+Ccap@0 gnd net@14 2.403f
+Ccap@1 gnd net@8 2.403f
+Ccap@2 gnd net@11 2.403f
+Rres@0 net@14 a 3.787
+Rres@1 net@11 net@14 7.575
+Rres@2 b net@8 3.787
+Rres@3 net@8 net@11 7.575
+.ENDS wire-C_0_011f-655_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-655_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-655_5-R_34_667m
+.ENDS wire90-655_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-632-R_34_667m a b
+Ccap@0 gnd net@14 2.317f
+Ccap@1 gnd net@8 2.317f
+Ccap@2 gnd net@11 2.317f
+Rres@0 net@14 a 3.652
+Rres@1 net@11 net@14 7.303
+Rres@2 b net@8 3.652
+Rres@3 net@8 net@11 7.303
+.ENDS wire-C_0_011f-632-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-632-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-632-R_34_667m
+.ENDS wire90-632-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-645-R_34_667m a b
+Ccap@0 gnd net@14 2.365f
+Ccap@1 gnd net@8 2.365f
+Ccap@2 gnd net@11 2.365f
+Rres@0 net@14 a 3.727
+Rres@1 net@11 net@14 7.453
+Rres@2 b net@8 3.727
+Rres@3 net@8 net@11 7.453
+.ENDS wire-C_0_011f-645-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-645-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-645-R_34_667m
+.ENDS wire90-645-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-600_5-R_34_667m a b
+Ccap@0 gnd net@14 2.202f
+Ccap@1 gnd net@8 2.202f
+Ccap@2 gnd net@11 2.202f
+Rres@0 net@14 a 3.47
+Rres@1 net@11 net@14 6.939
+Rres@2 b net@8 3.47
+Rres@3 net@8 net@11 6.939
+.ENDS wire-C_0_011f-600_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-600_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-600_5-R_34_667m
+.ENDS wire90-600_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-596_4-R_34_667m a b
+Ccap@0 gnd net@14 2.187f
+Ccap@1 gnd net@8 2.187f
+Ccap@2 gnd net@11 2.187f
+Rres@0 net@14 a 3.446
+Rres@1 net@11 net@14 6.892
+Rres@2 b net@8 3.446
+Rres@3 net@8 net@11 6.892
+.ENDS wire-C_0_011f-596_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-596_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-596_4-R_34_667m
+.ENDS wire90-596_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-595-R_34_667m a b
+Ccap@0 gnd net@14 2.182f
+Ccap@1 gnd net@8 2.182f
+Ccap@2 gnd net@11 2.182f
+Rres@0 net@14 a 3.438
+Rres@1 net@11 net@14 6.876
+Rres@2 b net@8 3.438
+Rres@3 net@8 net@11 6.876
+.ENDS wire-C_0_011f-595-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-595-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-595-R_34_667m
+.ENDS wire90-595-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-613-R_34_667m a b
+Ccap@0 gnd net@14 2.248f
+Ccap@1 gnd net@8 2.248f
+Ccap@2 gnd net@11 2.248f
+Rres@0 net@14 a 3.542
+Rres@1 net@11 net@14 7.084
+Rres@2 b net@8 3.542
+Rres@3 net@8 net@11 7.084
+.ENDS wire-C_0_011f-613-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-613-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-613-R_34_667m
+.ENDS wire90-613-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-598_6-R_34_667m a b
+Ccap@0 gnd net@14 2.195f
+Ccap@1 gnd net@8 2.195f
+Ccap@2 gnd net@11 2.195f
+Rres@0 net@14 a 3.459
+Rres@1 net@11 net@14 6.917
+Rres@2 b net@8 3.459
+Rres@3 net@8 net@11 6.917
+.ENDS wire-C_0_011f-598_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-598_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-598_6-R_34_667m
+.ENDS wire90-598_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-611-R_34_667m a b
+Ccap@0 gnd net@14 2.24f
+Ccap@1 gnd net@8 2.24f
+Ccap@2 gnd net@11 2.24f
+Rres@0 net@14 a 3.53
+Rres@1 net@11 net@14 7.06
+Rres@2 b net@8 3.53
+Rres@3 net@8 net@11 7.06
+.ENDS wire-C_0_011f-611-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-611-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-611-R_34_667m
+.ENDS wire90-611-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-591_9-R_34_667m a b
+Ccap@0 gnd net@14 2.17f
+Ccap@1 gnd net@8 2.17f
+Ccap@2 gnd net@11 2.17f
+Rres@0 net@14 a 3.42
+Rres@1 net@11 net@14 6.84
+Rres@2 b net@8 3.42
+Rres@3 net@8 net@11 6.84
+.ENDS wire-C_0_011f-591_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-591_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-591_9-R_34_667m
+.ENDS wire90-591_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-606-R_34_667m a b
+Ccap@0 gnd net@14 2.222f
+Ccap@1 gnd net@8 2.222f
+Ccap@2 gnd net@11 2.222f
+Rres@0 net@14 a 3.501
+Rres@1 net@11 net@14 7.003
+Rres@2 b net@8 3.501
+Rres@3 net@8 net@11 7.003
+.ENDS wire-C_0_011f-606-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-606-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-606-R_34_667m
+.ENDS wire90-606-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1186_7-R_34_667m a b
+Ccap@0 gnd net@14 4.351f
+Ccap@1 gnd net@8 4.351f
+Ccap@2 gnd net@11 4.351f
+Rres@0 net@14 a 6.856
+Rres@1 net@11 net@14 13.713
+Rres@2 b net@8 6.856
+Rres@3 net@8 net@11 13.713
+.ENDS wire-C_0_011f-1186_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1186_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1186_7-R_34_667m
+.ENDS wire90-1186_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1241_2-R_34_667m a b
+Ccap@0 gnd net@14 4.551f
+Ccap@1 gnd net@8 4.551f
+Ccap@2 gnd net@11 4.551f
+Rres@0 net@14 a 7.171
+Rres@1 net@11 net@14 14.343
+Rres@2 b net@8 7.171
+Rres@3 net@8 net@11 14.343
+.ENDS wire-C_0_011f-1241_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1241_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1241_2-R_34_667m
+.ENDS wire90-1241_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1192_7-R_34_667m a b
+Ccap@0 gnd net@14 4.373f
+Ccap@1 gnd net@8 4.373f
+Ccap@2 gnd net@11 4.373f
+Rres@0 net@14 a 6.891
+Rres@1 net@11 net@14 13.782
+Rres@2 b net@8 6.891
+Rres@3 net@8 net@11 13.782
+.ENDS wire-C_0_011f-1192_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1192_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1192_7-R_34_667m
+.ENDS wire90-1192_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1239_2-R_34_667m a b
+Ccap@0 gnd net@14 4.544f
+Ccap@1 gnd net@8 4.544f
+Ccap@2 gnd net@11 4.544f
+Rres@0 net@14 a 7.16
+Rres@1 net@11 net@14 14.32
+Rres@2 b net@8 7.16
+Rres@3 net@8 net@11 14.32
+.ENDS wire-C_0_011f-1239_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1239_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1239_2-R_34_667m
+.ENDS wire90-1239_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1190_7-R_34_667m a b
+Ccap@0 gnd net@14 4.366f
+Ccap@1 gnd net@8 4.366f
+Ccap@2 gnd net@11 4.366f
+Rres@0 net@14 a 6.88
+Rres@1 net@11 net@14 13.759
+Rres@2 b net@8 6.88
+Rres@3 net@8 net@11 13.759
+.ENDS wire-C_0_011f-1190_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1190_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1190_7-R_34_667m
+.ENDS wire90-1190_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1268_7-R_34_667m a b
+Ccap@0 gnd net@14 4.652f
+Ccap@1 gnd net@8 4.652f
+Ccap@2 gnd net@11 4.652f
+Rres@0 net@14 a 7.33
+Rres@1 net@11 net@14 14.661
+Rres@2 b net@8 7.33
+Rres@3 net@8 net@11 14.661
+.ENDS wire-C_0_011f-1268_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1268_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1268_7-R_34_667m
+.ENDS wire90-1268_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1187_7-R_34_667m a b
+Ccap@0 gnd net@14 4.355f
+Ccap@1 gnd net@8 4.355f
+Ccap@2 gnd net@11 4.355f
+Rres@0 net@14 a 6.862
+Rres@1 net@11 net@14 13.725
+Rres@2 b net@8 6.862
+Rres@3 net@8 net@11 13.725
+.ENDS wire-C_0_011f-1187_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1187_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1187_7-R_34_667m
+.ENDS wire90-1187_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1257_7-R_34_667m a b
+Ccap@0 gnd net@14 4.612f
+Ccap@1 gnd net@8 4.612f
+Ccap@2 gnd net@11 4.612f
+Rres@0 net@14 a 7.267
+Rres@1 net@11 net@14 14.533
+Rres@2 b net@8 7.267
+Rres@3 net@8 net@11 14.533
+.ENDS wire-C_0_011f-1257_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1257_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1257_7-R_34_667m
+.ENDS wire90-1257_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1190_2-R_34_667m a b
+Ccap@0 gnd net@14 4.364f
+Ccap@1 gnd net@8 4.364f
+Ccap@2 gnd net@11 4.364f
+Rres@0 net@14 a 6.877
+Rres@1 net@11 net@14 13.753
+Rres@2 b net@8 6.877
+Rres@3 net@8 net@11 13.753
+.ENDS wire-C_0_011f-1190_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1190_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1190_2-R_34_667m
+.ENDS wire90-1190_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1197_6-R_34_667m a b
+Ccap@0 gnd net@14 4.391f
+Ccap@1 gnd net@8 4.391f
+Ccap@2 gnd net@11 4.391f
+Rres@0 net@14 a 6.919
+Rres@1 net@11 net@14 13.839
+Rres@2 b net@8 6.919
+Rres@3 net@8 net@11 13.839
+.ENDS wire-C_0_011f-1197_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1197_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1197_6-R_34_667m
+.ENDS wire90-1197_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1171-R_34_667m a b
+Ccap@0 gnd net@14 4.294f
+Ccap@1 gnd net@8 4.294f
+Ccap@2 gnd net@11 4.294f
+Rres@0 net@14 a 6.766
+Rres@1 net@11 net@14 13.532
+Rres@2 b net@8 6.766
+Rres@3 net@8 net@11 13.532
+.ENDS wire-C_0_011f-1171-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1171-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1171-R_34_667m
+.ENDS wire90-1171-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1186_6-R_34_667m a b
+Ccap@0 gnd net@14 4.351f
+Ccap@1 gnd net@8 4.351f
+Ccap@2 gnd net@11 4.351f
+Rres@0 net@14 a 6.856
+Rres@1 net@11 net@14 13.712
+Rres@2 b net@8 6.856
+Rres@3 net@8 net@11 13.712
+.ENDS wire-C_0_011f-1186_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1186_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1186_6-R_34_667m
+.ENDS wire90-1186_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1178-R_34_667m a b
+Ccap@0 gnd net@14 4.319f
+Ccap@1 gnd net@8 4.319f
+Ccap@2 gnd net@11 4.319f
+Rres@0 net@14 a 6.806
+Rres@1 net@11 net@14 13.612
+Rres@2 b net@8 6.806
+Rres@3 net@8 net@11 13.612
+.ENDS wire-C_0_011f-1178-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1178-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1178-R_34_667m
+.ENDS wire90-1178-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1216_1-R_34_667m a b
+Ccap@0 gnd net@14 4.459f
+Ccap@1 gnd net@8 4.459f
+Ccap@2 gnd net@11 4.459f
+Rres@0 net@14 a 7.026
+Rres@1 net@11 net@14 14.053
+Rres@2 b net@8 7.026
+Rres@3 net@8 net@11 14.053
+.ENDS wire-C_0_011f-1216_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1216_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1216_1-R_34_667m
+.ENDS wire90-1216_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1172_5-R_34_667m a b
+Ccap@0 gnd net@14 4.299f
+Ccap@1 gnd net@8 4.299f
+Ccap@2 gnd net@11 4.299f
+Rres@0 net@14 a 6.774
+Rres@1 net@11 net@14 13.549
+Rres@2 b net@8 6.774
+Rres@3 net@8 net@11 13.549
+.ENDS wire-C_0_011f-1172_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1172_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1172_5-R_34_667m
+.ENDS wire90-1172_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1214_1-R_34_667m a b
+Ccap@0 gnd net@14 4.452f
+Ccap@1 gnd net@8 4.452f
+Ccap@2 gnd net@11 4.452f
+Rres@0 net@14 a 7.015
+Rres@1 net@11 net@14 14.03
+Rres@2 b net@8 7.015
+Rres@3 net@8 net@11 14.03
+.ENDS wire-C_0_011f-1214_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1214_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1214_1-R_34_667m
+.ENDS wire90-1214_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1166_5-R_34_667m a b
+Ccap@0 gnd net@14 4.277f
+Ccap@1 gnd net@8 4.277f
+Ccap@2 gnd net@11 4.277f
+Rres@0 net@14 a 6.74
+Rres@1 net@11 net@14 13.48
+Rres@2 b net@8 6.74
+Rres@3 net@8 net@11 13.48
+.ENDS wire-C_0_011f-1166_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1166_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1166_5-R_34_667m
+.ENDS wire90-1166_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1203_1-R_34_667m a b
+Ccap@0 gnd net@14 4.411f
+Ccap@1 gnd net@8 4.411f
+Ccap@2 gnd net@11 4.411f
+Rres@0 net@14 a 6.951
+Rres@1 net@11 net@14 13.902
+Rres@2 b net@8 6.951
+Rres@3 net@8 net@11 13.902
+.ENDS wire-C_0_011f-1203_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1203_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1203_1-R_34_667m
+.ENDS wire90-1203_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1199_2-R_34_667m a b
+Ccap@0 gnd net@14 4.397f
+Ccap@1 gnd net@8 4.397f
+Ccap@2 gnd net@11 4.397f
+Rres@0 net@14 a 6.929
+Rres@1 net@11 net@14 13.857
+Rres@2 b net@8 6.929
+Rres@3 net@8 net@11 13.857
+.ENDS wire-C_0_011f-1199_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1199_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1199_2-R_34_667m
+.ENDS wire90-1199_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1217_2-R_34_667m a b
+Ccap@0 gnd net@14 4.463f
+Ccap@1 gnd net@8 4.463f
+Ccap@2 gnd net@11 4.463f
+Rres@0 net@14 a 7.033
+Rres@1 net@11 net@14 14.065
+Rres@2 b net@8 7.033
+Rres@3 net@8 net@11 14.065
+.ENDS wire-C_0_011f-1217_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1217_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1217_2-R_34_667m
+.ENDS wire90-1217_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1208_2-R_34_667m a b
+Ccap@0 gnd net@14 4.43f
+Ccap@1 gnd net@8 4.43f
+Ccap@2 gnd net@11 4.43f
+Rres@0 net@14 a 6.981
+Rres@1 net@11 net@14 13.961
+Rres@2 b net@8 6.981
+Rres@3 net@8 net@11 13.961
+.ENDS wire-C_0_011f-1208_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1208_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1208_2-R_34_667m
+.ENDS wire90-1208_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1215_2-R_34_667m a b
+Ccap@0 gnd net@14 4.456f
+Ccap@1 gnd net@8 4.456f
+Ccap@2 gnd net@11 4.456f
+Rres@0 net@14 a 7.021
+Rres@1 net@11 net@14 14.042
+Rres@2 b net@8 7.021
+Rres@3 net@8 net@11 14.042
+.ENDS wire-C_0_011f-1215_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1215_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1215_2-R_34_667m
+.ENDS wire90-1215_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1205_2-R_34_667m a b
+Ccap@0 gnd net@14 4.419f
+Ccap@1 gnd net@8 4.419f
+Ccap@2 gnd net@11 4.419f
+Rres@0 net@14 a 6.963
+Rres@1 net@11 net@14 13.927
+Rres@2 b net@8 6.963
+Rres@3 net@8 net@11 13.927
+.ENDS wire-C_0_011f-1205_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1205_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1205_2-R_34_667m
+.ENDS wire90-1205_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1244_7-R_34_667m a b
+Ccap@0 gnd net@14 4.564f
+Ccap@1 gnd net@8 4.564f
+Ccap@2 gnd net@11 4.564f
+Rres@0 net@14 a 7.192
+Rres@1 net@11 net@14 14.383
+Rres@2 b net@8 7.192
+Rres@3 net@8 net@11 14.383
+.ENDS wire-C_0_011f-1244_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1244_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1244_7-R_34_667m
+.ENDS wire90-1244_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1184_2-R_34_667m a b
+Ccap@0 gnd net@14 4.342f
+Ccap@1 gnd net@8 4.342f
+Ccap@2 gnd net@11 4.342f
+Rres@0 net@14 a 6.842
+Rres@1 net@11 net@14 13.684
+Rres@2 b net@8 6.842
+Rres@3 net@8 net@11 13.684
+.ENDS wire-C_0_011f-1184_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1184_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1184_2-R_34_667m
+.ENDS wire90-1184_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1233_7-R_34_667m a b
+Ccap@0 gnd net@14 4.524f
+Ccap@1 gnd net@8 4.524f
+Ccap@2 gnd net@11 4.524f
+Rres@0 net@14 a 7.128
+Rres@1 net@11 net@14 14.256
+Rres@2 b net@8 7.128
+Rres@3 net@8 net@11 14.256
+.ENDS wire-C_0_011f-1233_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1233_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1233_7-R_34_667m
+.ENDS wire90-1233_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1187_2-R_34_667m a b
+Ccap@0 gnd net@14 4.353f
+Ccap@1 gnd net@8 4.353f
+Ccap@2 gnd net@11 4.353f
+Rres@0 net@14 a 6.859
+Rres@1 net@11 net@14 13.719
+Rres@2 b net@8 6.859
+Rres@3 net@8 net@11 13.719
+.ENDS wire-C_0_011f-1187_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1187_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1187_2-R_34_667m
+.ENDS wire90-1187_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1215_6-R_34_667m a b
+Ccap@0 gnd net@14 4.457f
+Ccap@1 gnd net@8 4.457f
+Ccap@2 gnd net@11 4.457f
+Rres@0 net@14 a 7.023
+Rres@1 net@11 net@14 14.047
+Rres@2 b net@8 7.023
+Rres@3 net@8 net@11 14.047
+.ENDS wire-C_0_011f-1215_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1215_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1215_6-R_34_667m
+.ENDS wire90-1215_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1168-R_34_667m a b
+Ccap@0 gnd net@14 4.283f
+Ccap@1 gnd net@8 4.283f
+Ccap@2 gnd net@11 4.283f
+Rres@0 net@14 a 6.748
+Rres@1 net@11 net@14 13.497
+Rres@2 b net@8 6.748
+Rres@3 net@8 net@11 13.497
+.ENDS wire-C_0_011f-1168-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1168-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1168-R_34_667m
+.ENDS wire90-1168-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1204_6-R_34_667m a b
+Ccap@0 gnd net@14 4.417f
+Ccap@1 gnd net@8 4.417f
+Ccap@2 gnd net@11 4.417f
+Rres@0 net@14 a 6.96
+Rres@1 net@11 net@14 13.92
+Rres@2 b net@8 6.96
+Rres@3 net@8 net@11 13.92
+.ENDS wire-C_0_011f-1204_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1204_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1204_6-R_34_667m
+.ENDS wire90-1204_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1234_1-R_34_667m a b
+Ccap@0 gnd net@14 4.525f
+Ccap@1 gnd net@8 4.525f
+Ccap@2 gnd net@11 4.525f
+Rres@0 net@14 a 7.13
+Rres@1 net@11 net@14 14.261
+Rres@2 b net@8 7.13
+Rres@3 net@8 net@11 14.261
+.ENDS wire-C_0_011f-1234_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1234_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1234_1-R_34_667m
+.ENDS wire90-1234_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1169_5-R_34_667m a b
+Ccap@0 gnd net@14 4.288f
+Ccap@1 gnd net@8 4.288f
+Ccap@2 gnd net@11 4.288f
+Rres@0 net@14 a 6.757
+Rres@1 net@11 net@14 13.514
+Rres@2 b net@8 6.757
+Rres@3 net@8 net@11 13.514
+.ENDS wire-C_0_011f-1169_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1169_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1169_5-R_34_667m
+.ENDS wire90-1169_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1232_1-R_34_667m a b
+Ccap@0 gnd net@14 4.518f
+Ccap@1 gnd net@8 4.518f
+Ccap@2 gnd net@11 4.518f
+Rres@0 net@14 a 7.119
+Rres@1 net@11 net@14 14.238
+Rres@2 b net@8 7.119
+Rres@3 net@8 net@11 14.238
+.ENDS wire-C_0_011f-1232_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1232_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1232_1-R_34_667m
+.ENDS wire90-1232_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1163_5-R_34_667m a b
+Ccap@0 gnd net@14 4.266f
+Ccap@1 gnd net@8 4.266f
+Ccap@2 gnd net@11 4.266f
+Rres@0 net@14 a 6.722
+Rres@1 net@11 net@14 13.445
+Rres@2 b net@8 6.722
+Rres@3 net@8 net@11 13.445
+.ENDS wire-C_0_011f-1163_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1163_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1163_5-R_34_667m
+.ENDS wire90-1163_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1221_1-R_34_667m a b
+Ccap@0 gnd net@14 4.477f
+Ccap@1 gnd net@8 4.477f
+Ccap@2 gnd net@11 4.477f
+Rres@0 net@14 a 7.055
+Rres@1 net@11 net@14 14.11
+Rres@2 b net@8 7.055
+Rres@3 net@8 net@11 14.11
+.ENDS wire-C_0_011f-1221_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1221_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1221_1-R_34_667m
+.ENDS wire90-1221_1-layer_1-width_3
+
+*** CELL: fifoL:split10{sch}
+.SUBCKT split10 clS[F] clS[T] cl[F] cl[T] freqOut in[10] in[11] in[12] in[13] 
++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] 
++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] 
++in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
++out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred rd[F] rd[T] sin 
++sout succ
+XsplitEnd@0 clS[F] clS[T] cl[F] cl[T] a[10] a[11] a[12] a[13] a[14] a[15] 
++a[16] a[17] a[18] a[19] a[1] a[20] a[21] a[22] a[23] a[24] a[25] a[26] a[27] 
++a[28] a[29] a[2] a[30] a[31] a[32] a[33] a[34] a[35] a[36] a[3] a[4] a[5] 
++a[6] a[7] a[8] a[9] b[10] b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] 
++b[19] b[1] b[20] b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[2] 
++b[30] b[31] b[32] b[33] b[34] b[35] b[36] b[3] b[4] b[5] b[6] b[7] b[8] b[9] 
++mc out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@336 
++net@337 rd[F] rd[T] net@335 sout succ splitEnd
+XsplitSta@0 clS[F] clS[T] cl[F] cl[T] in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
++in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
++in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc x[10] x[11] x[12] 
++x[13] x[14] x[15] x[16] x[17] x[18] x[19] x[1] x[20] x[21] x[22] x[23] x[24] 
++x[25] x[26] x[27] x[28] x[29] x[2] x[30] x[31] x[32] x[33] x[34] x[35] x[36] 
++x[3] x[4] x[5] x[6] x[7] x[8] x[9] pred rd[F] rd[T] sin net@315 net@312 
++net@313 splitStart
+XsplitSta@1 clS[F] clS[T] clS[F] clS[T] cl[F] cl[T] cl[F] cl[T] 
++splitSta@1_freqOut x[10] x[11] x[12] x[13] x[14] x[15] x[16] x[17] x[18] 
++x[19] x[1] x[20] x[21] x[22] x[23] x[24] x[25] x[26] x[27] x[28] x[29] x[2] 
++x[30] x[31] x[32] x[33] x[34] x[35] x[36] x[3] x[4] x[5] x[6] x[7] x[8] x[9] 
++mc mc a[10] a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[1] a[20] 
++a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[2] a[30] a[31] a[32] 
++a[33] a[34] a[35] a[36] a[3] a[4] a[5] a[6] a[7] a[8] a[9] net@245 rd[F] 
++rd[T] rd[F] rd[T] net@285 net@252 net@251 net@270 net@276 splitStageDx4
+XsplitSta@2 clS[F] clS[T] clS[F] clS[T] cl[F] cl[T] cl[F] cl[T] freqOut x[10] 
++x[11] x[12] x[13] x[14] x[15] x[16] x[17] x[18] x[19] x[1] x[20] x[21] x[22] 
++x[23] x[24] x[25] x[26] x[27] x[28] x[29] x[2] x[30] x[31] x[32] x[33] x[34] 
++x[35] x[36] x[3] x[4] x[5] x[6] x[7] x[8] x[9] mc mc b[10] b[11] b[12] b[13] 
++b[14] b[15] b[16] b[17] b[18] b[19] b[1] b[20] b[21] b[22] b[23] b[24] b[25] 
++b[26] b[27] b[28] b[29] b[2] b[30] b[31] b[32] b[33] b[34] b[35] b[36] b[3] 
++b[4] b[5] b[6] b[7] b[8] b[9] net@248 rd[F] rd[T] rd[F] rd[T] net@316 net@309 
++net@307 net@322 net@279 splitStageDx4
+Xwire90@0 net@316 net@251 wire90-1085-layer_1-width_3
+Xwire90@1 net@307 net@309 wire90-2816_7-layer_1-width_3
+Xwire90@2 net@313 net@248 wire90-1847-layer_1-width_3
+Xwire90@3 net@312 net@245 wire90-1161-layer_1-width_3
+Xwire90@4 net@315 net@285 wire90-941-layer_1-width_3
+Xwire90@5 net@322 net@252 wire90-1085-layer_1-width_3
+Xwire90@6 net@270 net@335 wire90-992_5-layer_1-width_3
+Xwire90@7 net@276 net@336 wire90-924_4-layer_1-width_3
+Xwire90@8 net@279 net@337 wire90-1463_4-layer_1-width_3
+Xwire90@9 x[1] wire90@9_b wire90-1346_1-layer_1-width_3
+Xwire90@10 x[2] wire90@10_b wire90-1337_6-layer_1-width_3
+Xwire90@11 x[3] wire90@11_b wire90-1339_1-layer_1-width_3
+Xwire90@12 x[4] wire90@12_b wire90-1356_6-layer_1-width_3
+Xwire90@13 x[5] wire90@13_b wire90-1341_1-layer_1-width_3
+Xwire90@14 x[6] wire90@14_b wire90-1345_1-layer_1-width_3
+Xwire90@15 x[7] wire90@15_b wire90-1361_4-layer_1-width_3
+Xwire90@16 x[8] wire90@16_b wire90-1342_1-layer_1-width_3
+Xwire90@17 x[9] wire90@17_b wire90-1349_6-layer_1-width_3
+Xwire90@18 x[10] wire90@18_b wire90-1345_8-layer_1-width_3
+Xwire90@19 x[11] wire90@19_b wire90-1346_7-layer_1-width_3
+Xwire90@20 x[12] wire90@20_b wire90-1330_8-layer_1-width_3
+Xwire90@21 x[13] wire90@21_b wire90-1339_7-layer_1-width_3
+Xwire90@22 x[14] wire90@22_b wire90-1353_3-layer_1-width_3
+Xwire90@23 x[15] wire90@23_b wire90-1355_2-layer_1-width_3
+Xwire90@24 x[16] wire90@24_b wire90-1359_3-layer_1-width_3
+Xwire90@25 x[17] wire90@25_b wire90-1357_2-layer_1-width_3
+Xwire90@26 x[18] wire90@26_b wire90-1353_3-layer_1-width_3
+Xwire90@27 x[19] wire90@27_b wire90-1356_6-layer_1-width_3
+Xwire90@28 x[20] wire90@28_b wire90-1356_1-layer_1-width_3
+Xwire90@29 x[21] wire90@29_b wire90-1349_6-layer_1-width_3
+Xwire90@30 x[22] wire90@30_b wire90-1379_1-layer_1-width_3
+Xwire90@31 x[23] wire90@31_b wire90-1351_6-layer_1-width_3
+Xwire90@32 x[24] wire90@32_b wire90-1376_6-layer_1-width_3
+Xwire90@33 x[25] wire90@33_b wire90-1372_4-layer_1-width_3
+Xwire90@34 x[26] wire90@34_b wire90-1373_6-layer_1-width_3
+Xwire90@35 x[27] wire90@35_b wire90-1360_1-layer_1-width_3
+Xwire90@36 x[28] wire90@36_b wire90-1323_3-layer_1-width_3
+Xwire90@37 x[29] wire90@37_b wire90-1336_2-layer_1-width_3
+Xwire90@38 x[30] wire90@38_b wire90-1330_3-layer_1-width_3
+Xwire90@39 x[31] wire90@39_b wire90-1329_2-layer_1-width_3
+Xwire90@40 x[32] wire90@40_b wire90-1325_8-layer_1-width_3
+Xwire90@41 x[33] wire90@41_b wire90-1344_7-layer_1-width_3
+Xwire90@42 x[34] wire90@42_b wire90-1327_8-layer_1-width_3
+Xwire90@43 x[35] wire90@43_b wire90-1346_7-layer_1-width_3
+Xwire90@44 x[36] wire90@44_b wire90-1321_8-layer_1-width_3
+Xwire90@45 a[1] wire90@45_b wire90-638-layer_1-width_3
+Xwire90@46 a[2] wire90@46_b wire90-638-layer_1-width_3
+Xwire90@47 a[3] wire90@47_b wire90-641-layer_1-width_3
+Xwire90@48 a[4] wire90@48_b wire90-644-layer_1-width_3
+Xwire90@49 a[5] wire90@49_b wire90-635-layer_1-width_3
+Xwire90@50 a[6] wire90@50_b wire90-666-layer_1-width_3
+Xwire90@51 a[7] wire90@51_b wire90-633_5-layer_1-width_3
+Xwire90@52 a[8] wire90@52_b wire90-655-layer_1-width_3
+Xwire90@53 a[9] wire90@53_b wire90-636_5-layer_1-width_3
+Xwire90@54 a[10] wire90@54_b wire90-594_5-layer_1-width_3
+Xwire90@55 a[11] wire90@55_b wire90-599_4-layer_1-width_3
+Xwire90@56 a[12] wire90@56_b wire90-590_5-layer_1-width_3
+Xwire90@57 a[13] wire90@57_b wire90-602_4-layer_1-width_3
+Xwire90@58 a[14] wire90@58_b wire90-607-layer_1-width_3
+Xwire90@59 a[15] wire90@59_b wire90-601_6-layer_1-width_3
+Xwire90@60 a[16] wire90@60_b wire90-605-layer_1-width_3
+Xwire90@61 a[17] wire90@61_b wire90-594_9-layer_1-width_3
+Xwire90@62 a[18] wire90@62_b wire90-600-layer_1-width_3
+Xwire90@63 a[19] wire90@63_b wire90-636_5-layer_1-width_3
+Xwire90@64 a[20] wire90@64_b wire90-635-layer_1-width_3
+Xwire90@65 a[21] wire90@65_b wire90-639_5-layer_1-width_3
+Xwire90@66 a[22] wire90@66_b wire90-641-layer_1-width_3
+Xwire90@67 a[23] wire90@67_b wire90-633_5-layer_1-width_3
+Xwire90@68 a[24] wire90@68_b wire90-655_5-layer_1-width_3
+Xwire90@69 a[25] wire90@69_b wire90-632-layer_1-width_3
+Xwire90@70 a[26] wire90@70_b wire90-645-layer_1-width_3
+Xwire90@71 a[27] wire90@71_b wire90-635-layer_1-width_3
+Xwire90@72 a[28] wire90@72_b wire90-600_5-layer_1-width_3
+Xwire90@73 a[29] wire90@73_b wire90-596_4-layer_1-width_3
+Xwire90@74 a[30] wire90@74_b wire90-595-layer_1-width_3
+Xwire90@75 a[31] wire90@75_b wire90-599_4-layer_1-width_3
+Xwire90@76 a[32] wire90@76_b wire90-613-layer_1-width_3
+Xwire90@77 a[33] wire90@77_b wire90-598_6-layer_1-width_3
+Xwire90@78 a[34] wire90@78_b wire90-611-layer_1-width_3
+Xwire90@79 a[35] wire90@79_b wire90-591_9-layer_1-width_3
+Xwire90@80 a[36] wire90@80_b wire90-606-layer_1-width_3
+Xwire90@81 b[1] wire90@81_b wire90-1186_7-layer_1-width_3
+Xwire90@82 b[2] wire90@82_b wire90-1241_2-layer_1-width_3
+Xwire90@83 b[3] wire90@83_b wire90-1192_7-layer_1-width_3
+Xwire90@84 b[4] wire90@84_b wire90-1239_2-layer_1-width_3
+Xwire90@85 b[5] wire90@85_b wire90-1190_7-layer_1-width_3
+Xwire90@86 b[6] wire90@86_b wire90-1268_7-layer_1-width_3
+Xwire90@87 b[7] wire90@87_b wire90-1187_7-layer_1-width_3
+Xwire90@88 b[8] wire90@88_b wire90-1257_7-layer_1-width_3
+Xwire90@89 b[9] wire90@89_b wire90-1190_2-layer_1-width_3
+Xwire90@90 b[10] wire90@90_b wire90-1197_6-layer_1-width_3
+Xwire90@91 b[11] wire90@91_b wire90-1171-layer_1-width_3
+Xwire90@92 b[12] wire90@92_b wire90-1186_6-layer_1-width_3
+Xwire90@93 b[13] wire90@93_b wire90-1178-layer_1-width_3
+Xwire90@94 b[14] wire90@94_b wire90-1216_1-layer_1-width_3
+Xwire90@95 b[15] wire90@95_b wire90-1172_5-layer_1-width_3
+Xwire90@96 b[16] wire90@96_b wire90-1214_1-layer_1-width_3
+Xwire90@97 b[17] wire90@97_b wire90-1166_5-layer_1-width_3
+Xwire90@98 b[18] wire90@98_b wire90-1203_1-layer_1-width_3
+Xwire90@99 b[19] wire90@99_b wire90-1199_2-layer_1-width_3
+Xwire90@100 b[20] wire90@100_b wire90-1217_2-layer_1-width_3
+Xwire90@101 b[21] wire90@101_b wire90-1208_2-layer_1-width_3
+Xwire90@102 b[22] wire90@102_b wire90-1215_2-layer_1-width_3
+Xwire90@103 b[23] wire90@103_b wire90-1205_2-layer_1-width_3
+Xwire90@104 b[24] wire90@104_b wire90-1244_7-layer_1-width_3
+Xwire90@105 b[25] wire90@105_b wire90-1184_2-layer_1-width_3
+Xwire90@106 b[26] wire90@106_b wire90-1233_7-layer_1-width_3
+Xwire90@107 b[27] wire90@107_b wire90-1187_2-layer_1-width_3
+Xwire90@108 b[28] wire90@108_b wire90-1215_6-layer_1-width_3
+Xwire90@109 b[29] wire90@109_b wire90-1168-layer_1-width_3
+Xwire90@110 b[30] wire90@110_b wire90-1204_6-layer_1-width_3
+Xwire90@111 b[31] wire90@111_b wire90-1171-layer_1-width_3
+Xwire90@112 b[32] wire90@112_b wire90-1234_1-layer_1-width_3
+Xwire90@113 b[33] wire90@113_b wire90-1169_5-layer_1-width_3
+Xwire90@114 b[34] wire90@114_b wire90-1232_1-layer_1-width_3
+Xwire90@115 b[35] wire90@115_b wire90-1163_5-layer_1-width_3
+Xwire90@116 b[36] wire90@116_b wire90-1221_1-layer_1-width_3
+.ENDS split10
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3513_1-R_34_667m a b
+Ccap@0 gnd net@14 12.881f
+Ccap@1 gnd net@8 12.881f
+Ccap@2 gnd net@11 12.881f
+Rres@0 net@14 a 20.298
+Rres@1 net@11 net@14 40.596
+Rres@2 b net@8 20.298
+Rres@3 net@8 net@11 40.596
+.ENDS wire-C_0_011f-3513_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3513_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3513_1-R_34_667m
+.ENDS wire90-3513_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3124_7-R_34_667m a b
+Ccap@0 gnd net@14 11.457f
+Ccap@1 gnd net@8 11.457f
+Ccap@2 gnd net@11 11.457f
+Rres@0 net@14 a 18.054
+Rres@1 net@11 net@14 36.108
+Rres@2 b net@8 18.054
+Rres@3 net@8 net@11 36.108
+.ENDS wire-C_0_011f-3124_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3124_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3124_7-R_34_667m
+.ENDS wire90-3124_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-603_9-R_26m a b
+Ccap@0 gnd net@14 2.214f
+Ccap@1 gnd net@8 2.214f
+Ccap@2 gnd net@11 2.214f
+Rres@0 net@14 a 2.617
+Rres@1 net@11 net@14 5.234
+Rres@2 b net@8 2.617
+Rres@3 net@8 net@11 5.234
+.ENDS wire-C_0_011f-603_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-603_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-603_9-R_26m
+.ENDS wire90-603_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-608_4-R_26m a b
+Ccap@0 gnd net@14 2.231f
+Ccap@1 gnd net@8 2.231f
+Ccap@2 gnd net@11 2.231f
+Rres@0 net@14 a 2.636
+Rres@1 net@11 net@14 5.273
+Rres@2 b net@8 2.636
+Rres@3 net@8 net@11 5.273
+.ENDS wire-C_0_011f-608_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-608_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-608_4-R_26m
+.ENDS wire90-608_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-632_5-R_26m a b
+Ccap@0 gnd net@14 2.319f
+Ccap@1 gnd net@8 2.319f
+Ccap@2 gnd net@11 2.319f
+Rres@0 net@14 a 2.741
+Rres@1 net@11 net@14 5.482
+Rres@2 b net@8 2.741
+Rres@3 net@8 net@11 5.482
+.ENDS wire-C_0_011f-632_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-632_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-632_5-R_26m
+.ENDS wire90-632_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-630-R_26m a b
+Ccap@0 gnd net@14 2.31f
+Ccap@1 gnd net@8 2.31f
+Ccap@2 gnd net@11 2.31f
+Rres@0 net@14 a 2.73
+Rres@1 net@11 net@14 5.46
+Rres@2 b net@8 2.73
+Rres@3 net@8 net@11 5.46
+.ENDS wire-C_0_011f-630-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-630-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-630-R_26m
+.ENDS wire90-630-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-611_4-R_26m a b
+Ccap@0 gnd net@14 2.242f
+Ccap@1 gnd net@8 2.242f
+Ccap@2 gnd net@11 2.242f
+Rres@0 net@14 a 2.649
+Rres@1 net@11 net@14 5.299
+Rres@2 b net@8 2.649
+Rres@3 net@8 net@11 5.299
+.ENDS wire-C_0_011f-611_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-611_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-611_4-R_26m
+.ENDS wire90-611_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-613_5-R_26m a b
+Ccap@0 gnd net@14 2.25f
+Ccap@1 gnd net@8 2.25f
+Ccap@2 gnd net@11 2.25f
+Rres@0 net@14 a 2.658
+Rres@1 net@11 net@14 5.317
+Rres@2 b net@8 2.658
+Rres@3 net@8 net@11 5.317
+.ENDS wire-C_0_011f-613_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-613_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-613_5-R_26m
+.ENDS wire90-613_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-613_8-R_26m a b
+Ccap@0 gnd net@14 2.251f
+Ccap@1 gnd net@8 2.251f
+Ccap@2 gnd net@11 2.251f
+Rres@0 net@14 a 2.66
+Rres@1 net@11 net@14 5.32
+Rres@2 b net@8 2.66
+Rres@3 net@8 net@11 5.32
+.ENDS wire-C_0_011f-613_8-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-613_8-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-613_8-R_26m
+.ENDS wire90-613_8-layer_1-width_4
+
+*** CELL: fifoL:ringFIFO{sch}
+.SUBCKT ringFIFO clS[F] clS[T] cl[F] cl[T] do[L] do[M] do[epi] fire[ODE] 
++fire[m1] fire[m2] freqOut inE[10] inE[11] inE[12] inE[13] inE[14] inE[15] 
++inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] inE[23] 
++inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] inE[31] 
++inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7] 
++inE[8] inE[9] mc od[10] od[11] od[12] od[13] od[14] od[15] od[16] od[17] 
++od[18] od[19] od[1] od[20] od[2] od[3] od[4] od[5] od[6] od[7] od[8] od[9] 
++olcZ outm1[1] outm1[20] outm1[22] outm1[23] outm1[24] outm1[25] outm1[26] 
++outm1[27] outm1[2] outm1[3] outm1[4] outm1[5] outm1[6] outm1[8] pout[10] 
++pout[11] pout[12] pout[13] pout[14] pout[15] pout[16] pout[17] pout[18] 
++pout[1] pout[2] pout[3] pout[4] pout[5] pout[6] pout[7] pout[8] pout[9] rd[F] 
++rd[T] sin sout
+Xm12stage@0 clS[F] clS[T] cl[F] cl[T] fire[m1] fire[m2] pout[10] pout[11] 
++pout[12] m3[13] m3[14] m3[15] m3[16] m3[17] m3[18] m3[19] pout[1] m3[20] 
++m3[21] m3[22] m3[23] m3[24] m3[25] m3[26] m3[27] m3[28] m3[29] pout[2] m3[30] 
++m3[31] m3[32] m3[33] m3[34] m3[35] m3[36] pout[3] pout[4] pout[5] pout[6] 
++pout[7] pout[8] pout[9] mc m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] 
++m1[17] m1[18] m1[19] outm1[1] outm1[20] m1[21] outm1[22] outm1[23] outm1[24] 
++outm1[25] outm1[26] outm1[27] m1[28] m1[29] outm1[2] m1[30] m1[31] m1[32] 
++m1[33] m1[34] m1[35] m1[36] outm1[3] outm1[4] outm1[5] outm1[6] m1[7] 
++outm1[8] m1[9] pout[13] pout[14] pout[15] pout[16] pout[17] pout[18] net@233 
++rd[F] rd[T] net@291 sout net@122 m12stageD
+XodRQstag@0 clS[F] clS[T] cl[F] cl[T] do[L] do[M] do[epi] net@236 fire[ODE] 
++inE[10] inE[11] inE[12] inE[13] inE[14] inE[15] inE[16] inE[17] inE[18] 
++inE[19] inE[1] inE[20] inE[21] inE[22] inE[23] inE[24] inE[25] inE[26] 
++inE[27] inE[28] inE[29] inE[2] inE[30] inE[31] inE[32] inE[33] inE[34] 
++inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7] inE[8] inE[9] m1[10] 
++m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] outm1[1] 
++outm1[20] m1[21] outm1[22] outm1[23] outm1[24] outm1[25] outm1[26] outm1[27] 
++m1[28] m1[29] outm1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] 
++outm1[3] outm1[4] outm1[5] outm1[6] m1[7] outm1[8] m1[9] mc od[10] od[11] 
++od[12] od[13] od[14] od[15] od[16] od[17] od[18] od[19] od[1] od[20] od[2] 
++od[3] od[4] od[5] od[6] od[7] od[8] od[9] olcZ rq[10] rq[11] rq[12] rq[13] 
++rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] 
++rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] 
++rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9] net@149 rd[F] 
++rd[T] sin net@253 odRQstageD
+Xsplit10@0 clS[F] clS[T] cl[F] cl[T] freqOut rq[10] rq[11] rq[12] rq[13] 
++rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] 
++rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] 
++rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9] mc pout[10] 
++pout[11] pout[12] m3[13] m3[14] m3[15] m3[16] m3[17] m3[18] m3[19] pout[1] 
++m3[20] m3[21] m3[22] m3[23] m3[24] m3[25] m3[26] m3[27] m3[28] m3[29] pout[2] 
++m3[30] m3[31] m3[32] m3[33] m3[34] m3[35] m3[36] pout[3] pout[4] pout[5] 
++pout[6] pout[7] pout[8] pout[9] net@238 rd[F] rd[T] net@260 net@290 net@289 
++split10
+Xwire90@2 net@122 net@149 wire90-3513_1-layer_1-width_3
+Xwire90@39 net@238 net@236 wire90-3124_7-layer_1-width_3
+Xwire90@40 net@260 net@253 wire90-3124_7-layer_1-width_3
+Xwire90@41 net@289 net@233 wire90-3513_1-layer_1-width_3
+Xwire90@42 net@290 net@291 wire90-3513_1-layer_1-width_3
+Xwire90@46 m3[19] wire90@46_b wire90-605_4-layer_1-width_4
+Xwire90@47 m3[20] wire90@47_b wire90-613_4-layer_1-width_4
+Xwire90@48 m3[21] wire90@48_b wire90-605_4-layer_1-width_4
+Xwire90@49 m3[22] wire90@49_b wire90-623_9-layer_1-width_4
+Xwire90@50 m3[23] wire90@50_b wire90-603_9-layer_1-width_4
+Xwire90@51 m3[24] wire90@51_b wire90-625_9-layer_1-width_4
+Xwire90@52 m3[25] wire90@52_b wire90-607_8-layer_1-width_4
+Xwire90@53 m3[26] wire90@53_b wire90-620_9-layer_1-width_4
+Xwire90@54 m3[27] wire90@54_b wire90-605_4-layer_1-width_4
+Xwire90@56 m3[28] wire90@56_b wire90-612_5-layer_1-width_4
+Xwire90@58 m3[29] wire90@58_b wire90-602_4-layer_1-width_4
+Xwire90@59 m3[30] wire90@59_b wire90-607-layer_1-width_4
+Xwire90@60 m3[31] wire90@60_b wire90-602_4-layer_1-width_4
+Xwire90@61 m3[32] wire90@61_b wire90-620_5-layer_1-width_4
+Xwire90@62 m3[33] wire90@62_b wire90-602_4-layer_1-width_4
+Xwire90@63 m3[34] wire90@63_b wire90-624_5-layer_1-width_4
+Xwire90@64 m3[35] wire90@64_b wire90-602_4-layer_1-width_4
+Xwire90@65 m3[36] wire90@65_b wire90-618-layer_1-width_4
+Xwire90@73 m3[13] wire90@73_b wire90-608_4-layer_1-width_4
+Xwire90@74 m3[14] wire90@74_b wire90-632_5-layer_1-width_4
+Xwire90@75 m3[15] wire90@75_b wire90-608_4-layer_1-width_4
+Xwire90@76 m3[16] wire90@76_b wire90-636_5-layer_1-width_4
+Xwire90@77 m3[17] wire90@77_b wire90-608_4-layer_1-width_4
+Xwire90@78 m3[18] wire90@78_b wire90-630-layer_1-width_4
+Xwire90@79 m1[9] wire90@79_b wire90-611_4-layer_1-width_4
+Xwire90@80 m1[10] wire90@80_b wire90-624_5-layer_1-width_4
+Xwire90@82 m1[19] wire90@82_b wire90-605_4-layer_1-width_4
+Xwire90@91 m1[11] wire90@91_b wire90-608_4-layer_1-width_4
+Xwire90@92 m1[28] wire90@92_b wire90-612_5-layer_1-width_4
+Xwire90@94 m1[29] wire90@94_b wire90-602_4-layer_1-width_4
+Xwire90@95 m1[30] wire90@95_b wire90-607-layer_1-width_4
+Xwire90@96 m1[31] wire90@96_b wire90-602_4-layer_1-width_4
+Xwire90@97 m1[32] wire90@97_b wire90-620_5-layer_1-width_4
+Xwire90@98 m1[33] wire90@98_b wire90-602_4-layer_1-width_4
+Xwire90@99 m1[34] wire90@99_b wire90-624_5-layer_1-width_4
+Xwire90@100 m1[35] wire90@100_b wire90-602_4-layer_1-width_4
+Xwire90@101 m1[36] wire90@101_b wire90-618-layer_1-width_4
+Xwire90@102 m1[12] wire90@102_b wire90-613_5-layer_1-width_4
+Xwire90@107 m1[7] wire90@107_b wire90-613_8-layer_1-width_4
+Xwire90@109 m1[13] wire90@109_b wire90-608_4-layer_1-width_4
+Xwire90@110 m1[14] wire90@110_b wire90-632_5-layer_1-width_4
+Xwire90@111 m1[15] wire90@111_b wire90-608_4-layer_1-width_4
+Xwire90@112 m1[16] wire90@112_b wire90-636_5-layer_1-width_4
+Xwire90@113 m1[17] wire90@113_b wire90-608_4-layer_1-width_4
+Xwire90@114 m1[18] wire90@114_b wire90-630-layer_1-width_4
+Xwire90@115 rq[9] wire90@115_b wire90-611_4-layer_1-width_4
+Xwire90@116 rq[10] wire90@116_b wire90-624_5-layer_1-width_4
+Xwire90@117 rq[1] wire90@117_b wire90-611_4-layer_1-width_4
+Xwire90@118 rq[19] wire90@118_b wire90-605_4-layer_1-width_4
+Xwire90@119 rq[20] wire90@119_b wire90-613_4-layer_1-width_4
+Xwire90@120 rq[21] wire90@120_b wire90-605_4-layer_1-width_4
+Xwire90@121 rq[22] wire90@121_b wire90-623_9-layer_1-width_4
+Xwire90@122 rq[23] wire90@122_b wire90-603_9-layer_1-width_4
+Xwire90@123 rq[24] wire90@123_b wire90-625_9-layer_1-width_4
+Xwire90@124 rq[25] wire90@124_b wire90-607_8-layer_1-width_4
+Xwire90@125 rq[26] wire90@125_b wire90-620_9-layer_1-width_4
+Xwire90@126 rq[27] wire90@126_b wire90-605_4-layer_1-width_4
+Xwire90@127 rq[11] wire90@127_b wire90-608_4-layer_1-width_4
+Xwire90@128 rq[28] wire90@128_b wire90-612_5-layer_1-width_4
+Xwire90@129 rq[2] wire90@129_b wire90-613_4-layer_1-width_4
+Xwire90@130 rq[29] wire90@130_b wire90-602_4-layer_1-width_4
+Xwire90@131 rq[30] wire90@131_b wire90-607-layer_1-width_4
+Xwire90@132 rq[31] wire90@132_b wire90-602_4-layer_1-width_4
+Xwire90@133 rq[32] wire90@133_b wire90-620_5-layer_1-width_4
+Xwire90@134 rq[33] wire90@134_b wire90-602_4-layer_1-width_4
+Xwire90@135 rq[34] wire90@135_b wire90-624_5-layer_1-width_4
+Xwire90@136 rq[35] wire90@136_b wire90-602_4-layer_1-width_4
+Xwire90@137 rq[36] wire90@137_b wire90-618-layer_1-width_4
+Xwire90@138 rq[12] wire90@138_b wire90-613_5-layer_1-width_4
+Xwire90@139 rq[3] wire90@139_b wire90-611_4-layer_1-width_4
+Xwire90@140 rq[4] wire90@140_b wire90-623_9-layer_1-width_4
+Xwire90@141 rq[5] wire90@141_b wire90-608_4-layer_1-width_4
+Xwire90@142 rq[6] wire90@142_b wire90-625_9-layer_1-width_4
+Xwire90@143 rq[7] wire90@143_b wire90-613_8-layer_1-width_4
+Xwire90@144 rq[8] wire90@144_b wire90-620_9-layer_1-width_4
+Xwire90@145 rq[13] wire90@145_b wire90-608_4-layer_1-width_4
+Xwire90@146 rq[14] wire90@146_b wire90-632_5-layer_1-width_4
+Xwire90@147 rq[15] wire90@147_b wire90-608_4-layer_1-width_4
+Xwire90@148 rq[16] wire90@148_b wire90-636_5-layer_1-width_4
+Xwire90@149 rq[17] wire90@149_b wire90-608_4-layer_1-width_4
+Xwire90@150 rq[18] wire90@150_b wire90-630-layer_1-width_4
+.ENDS ringFIFO
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-216_3-R_34_667m a b
+Ccap@0 gnd net@14 0.793f
+Ccap@1 gnd net@8 0.793f
+Ccap@2 gnd net@11 0.793f
+Rres@0 net@14 a 1.25
+Rres@1 net@11 net@14 2.499
+Rres@2 b net@8 1.25
+Rres@3 net@8 net@11 2.499
+.ENDS wire-C_0_011f-216_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-216_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-216_3-R_34_667m
+.ENDS wire90-216_3-layer_1-width_3
+
+*** CELL: latchesK:latchZ10{sch}
+.SUBCKT latchZ10 c[1] c[2] cl[F] cl[T] in[1] mc out[TT] out[T]
+MNMOSf@1 out[T] net@186 gnd gnd nch W='12*(1+ABN/sqrt(12*3))' L='3' 
++DELVTO='AVT0N/sqrt(12*3)'
+XNMOSx@2 out[T] mc gnd NMOSx-X_10
+XNMOSx@3 out[T] c[1] gnd NMOSx-X_10
+XNMOSx@4 out[T] c[2] gnd NMOSx-X_20
+XPMOSx@2 out[T] net@186 vdd PMOSx-X_2
+Xinv@0 net@240 out[TT] inv-X_10
+XinvLT@0 out[T] net@186 invLT-X_2
+Xnms2@0 out[T] in[1] cl[T] nms2-X_10
+Xpms2@0 out[T] in[1] cl[F] pms2-X_10
+Xwire90@0 net@240 net@186 wire90-216_3-layer_1-width_3
+.ENDS latchZ10
+
+*** CELL: redFour:nor2n_sy{sch}
+.SUBCKT nor2n_sy-X_20 ina inb out
+Xnor2@0 ina inb out nor2_sy-X_20
+.ENDS nor2n_sy-X_20
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-133_8-R_34_667m a b
+Ccap@0 gnd net@14 0.491f
+Ccap@1 gnd net@8 0.491f
+Ccap@2 gnd net@11 0.491f
+Rres@0 net@14 a 0.773
+Rres@1 net@11 net@14 1.546
+Rres@2 b net@8 0.773
+Rres@3 net@8 net@11 1.546
+.ENDS wire-C_0_011f-133_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-133_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-133_8-R_34_667m
+.ENDS wire90-133_8-layer_1-width_3
+
+*** CELL: latchesK:mlat1in5i{sch}
+.SUBCKT mlat1in5i c[F] c[T] in out
+XinvLT@0 out net@119 invLT-X_2
+Xnms2@2 out in c[T] nms2-X_5
+Xnms2@3 out net@114 c[F] nms2-X_2
+Xpms2@0 out net@114 c[T] pms2-X_1
+Xpms2@1 out in c[F] pms2-X_5
+Xwire90@19 net@114 net@119 wire90-133_8-layer_1-width_3
+.ENDS mlat1in5i
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-200_9-R_34_667m a b
+Ccap@0 gnd net@14 0.737f
+Ccap@1 gnd net@8 0.737f
+Ccap@2 gnd net@11 0.737f
+Rres@0 net@14 a 1.161
+Rres@1 net@11 net@14 2.322
+Rres@2 b net@8 1.161
+Rres@3 net@8 net@11 2.322
+.ENDS wire-C_0_011f-200_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-200_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-200_9-R_34_667m
+.ENDS wire90-200_9-layer_1-width_3
+
+*** CELL: latchesK:mlat2in10i{sch}
+.SUBCKT mlat2in10i clA[F] clA[T] clB[F] clB[T] inA inB out[1]
+Xinv@0 out[1] net@33 inv-X_4
+Xnms2@0 out[1] inB clB[T] nms2-X_10
+Xnms2@1 out[1] inA clA[T] nms2-X_10
+Xnms3@0 out[1] clB[F] clA[F] net@33 nms3-X_2
+Xpms2@0 out[1] inB clB[F] pms2-X_10
+Xpms2@1 out[1] inA clA[F] pms2-X_10
+Xpms3@0 out[1] clA[T] clB[T] net@81 pms3-X_1
+Xwire90@1 net@81 net@33 wire90-200_9-layer_1-width_3
+.ENDS mlat2in10i
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-173_2-R_34_667m a b
+Ccap@0 gnd net@14 0.635f
+Ccap@1 gnd net@8 0.635f
+Ccap@2 gnd net@11 0.635f
+Rres@0 net@14 a 1.001
+Rres@1 net@11 net@14 2.001
+Rres@2 b net@8 1.001
+Rres@3 net@8 net@11 2.001
+.ENDS wire-C_0_011f-173_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-173_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-173_2-R_34_667m
+.ENDS wire90-173_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-381_1-R_34_667m a b
+Ccap@0 gnd net@14 1.397f
+Ccap@1 gnd net@8 1.397f
+Ccap@2 gnd net@11 1.397f
+Rres@0 net@14 a 2.202
+Rres@1 net@11 net@14 4.404
+Rres@2 b net@8 2.202
+Rres@3 net@8 net@11 4.404
+.ENDS wire-C_0_011f-381_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-381_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-381_1-R_34_667m
+.ENDS wire90-381_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-981_4-R_34_667m a b
+Ccap@0 gnd net@14 3.598f
+Ccap@1 gnd net@8 3.598f
+Ccap@2 gnd net@11 3.598f
+Rres@0 net@14 a 5.67
+Rres@1 net@11 net@14 11.341
+Rres@2 b net@8 5.67
+Rres@3 net@8 net@11 11.341
+.ENDS wire-C_0_011f-981_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-981_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-981_4-R_34_667m
+.ENDS wire90-981_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-523_4-R_34_667m a b
+Ccap@0 gnd net@14 1.919f
+Ccap@1 gnd net@8 1.919f
+Ccap@2 gnd net@11 1.919f
+Rres@0 net@14 a 3.024
+Rres@1 net@11 net@14 6.048
+Rres@2 b net@8 3.024
+Rres@3 net@8 net@11 6.048
+.ENDS wire-C_0_011f-523_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-523_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-523_4-R_34_667m
+.ENDS wire90-523_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-535_1-R_34_667m a b
+Ccap@0 gnd net@14 1.962f
+Ccap@1 gnd net@8 1.962f
+Ccap@2 gnd net@11 1.962f
+Rres@0 net@14 a 3.092
+Rres@1 net@11 net@14 6.183
+Rres@2 b net@8 3.092
+Rres@3 net@8 net@11 6.183
+.ENDS wire-C_0_011f-535_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-535_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-535_1-R_34_667m
+.ENDS wire90-535_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-555_1-R_34_667m a b
+Ccap@0 gnd net@14 2.035f
+Ccap@1 gnd net@8 2.035f
+Ccap@2 gnd net@11 2.035f
+Rres@0 net@14 a 3.207
+Rres@1 net@11 net@14 6.414
+Rres@2 b net@8 3.207
+Rres@3 net@8 net@11 6.414
+.ENDS wire-C_0_011f-555_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-555_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-555_1-R_34_667m
+.ENDS wire90-555_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-677_1-R_34_667m a b
+Ccap@0 gnd net@14 2.483f
+Ccap@1 gnd net@8 2.483f
+Ccap@2 gnd net@11 2.483f
+Rres@0 net@14 a 3.912
+Rres@1 net@11 net@14 7.824
+Rres@2 b net@8 3.912
+Rres@3 net@8 net@11 7.824
+.ENDS wire-C_0_011f-677_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-677_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-677_1-R_34_667m
+.ENDS wire90-677_1-layer_1-width_3
+
+*** CELL: loopCountL:ringB{sch}
+.SUBCKT ringB bit[1] count[F] count[T] do[1] inLO[1] load[F] load[T]
+Xinv@0 net@60 bit[1] inv-X_20
+Xinv@1 bit[1] net@67 inv-X_5
+Xinv@2 net@68 net@65 inv-X_10
+Xinv@3 xx[T] net@64 inv-X_10
+Xmlat1in5@0 xx[T] xx[F] net@66 net@9 mlat1in5i
+Xmlat1in5@1 count[T] count[F] do[1] net@77 mlat1in5i
+Xmlat2in1@0 load[F] load[T] xx[F] xx[T] inLO[1] net@63 net@61 mlat2in10i
+Xnor2n@0 net@78 count[F] net@84 nor2n-X_10
+Xwire90@1 net@67 net@68 wire90-173_2-layer_1-width_3
+Xwire90@2 net@65 net@66 wire90-381_1-layer_1-width_3
+Xwire90@3 net@60 net@61 wire90-981_4-layer_1-width_3
+Xwire90@5 net@63 net@9 wire90-523_4-layer_1-width_3
+Xwire90@6 net@64 xx[F] wire90-535_1-layer_1-width_3
+Xwire90@7 net@77 net@78 wire90-555_1-layer_1-width_3
+Xwire90@8 net@84 xx[T] wire90-677_1-layer_1-width_3
+.ENDS ringB
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1350_3-R_34_667m a b
+Ccap@0 gnd net@14 4.951f
+Ccap@1 gnd net@8 4.951f
+Ccap@2 gnd net@11 4.951f
+Rres@0 net@14 a 7.802
+Rres@1 net@11 net@14 15.603
+Rres@2 b net@8 7.802
+Rres@3 net@8 net@11 15.603
+.ENDS wire-C_0_011f-1350_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1350_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1350_3-R_34_667m
+.ENDS wire90-1350_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-985_7-R_34_667m a b
+Ccap@0 gnd net@14 3.614f
+Ccap@1 gnd net@8 3.614f
+Ccap@2 gnd net@11 3.614f
+Rres@0 net@14 a 5.695
+Rres@1 net@11 net@14 11.39
+Rres@2 b net@8 5.695
+Rres@3 net@8 net@11 11.39
+.ENDS wire-C_0_011f-985_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-985_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-985_7-R_34_667m
+.ENDS wire90-985_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1915_8-R_34_667m a b
+Ccap@0 gnd net@14 7.025f
+Ccap@1 gnd net@8 7.025f
+Ccap@2 gnd net@11 7.025f
+Rres@0 net@14 a 11.069
+Rres@1 net@11 net@14 22.138
+Rres@2 b net@8 11.069
+Rres@3 net@8 net@11 22.138
+.ENDS wire-C_0_011f-1915_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1915_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1915_8-R_34_667m
+.ENDS wire90-1915_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1810_4-R_34_667m a b
+Ccap@0 gnd net@14 6.638f
+Ccap@1 gnd net@8 6.638f
+Ccap@2 gnd net@11 6.638f
+Rres@0 net@14 a 10.46
+Rres@1 net@11 net@14 20.92
+Rres@2 b net@8 10.46
+Rres@3 net@8 net@11 20.92
+.ENDS wire-C_0_011f-1810_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1810_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1810_4-R_34_667m
+.ENDS wire90-1810_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-520_8-R_34_667m a b
+Ccap@0 gnd net@14 1.91f
+Ccap@1 gnd net@8 1.91f
+Ccap@2 gnd net@11 1.91f
+Rres@0 net@14 a 3.009
+Rres@1 net@11 net@14 6.018
+Rres@2 b net@8 3.009
+Rres@3 net@8 net@11 6.018
+.ENDS wire-C_0_011f-520_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-520_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-520_8-R_34_667m
+.ENDS wire90-520_8-layer_1-width_3
+
+*** CELL: loopCountL:ilcEven{sch}
+.SUBCKT ilcEven bit[2] bit[4] bit[6] bitt[7] count do[2] do[4] do[6] 
++ilc[done] inLO[2] inLO[4] inLO[6] inLO[8] kill load mc zeroLO
+Xinv@5 load[F] net@269 inv-X_30
+Xinv@6 count[F] net@271 inv-X_30
+Xinv@7 count net@273 inv-X_30
+Xinv@8 load net@275 inv-X_30
+Xinv@9 ilc[done] bitt[7] inv-X_10
+XlatchZ10@0 gnd kill load[F] load[T] inLO[8] mc net@317 latchZ10@0_out[T] 
++latchZ10
+Xnor2n_sy@1 net@318 zeroLO ilc[done] nor2n_sy-X_20
+XringB@0 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
+XringB@1 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
+XringB@2 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
+Xwire90@6 net@269 load[T] wire90-1350_3-layer_1-width_3
+Xwire90@7 net@271 count[T] wire90-985_7-layer_1-width_3
+Xwire90@8 net@273 count[F] wire90-1915_8-layer_1-width_3
+Xwire90@9 net@275 load[F] wire90-1810_4-layer_1-width_3
+Xwire90@11 net@318 net@317 wire90-520_8-layer_1-width_3
+.ENDS ilcEven
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1278-R_34_667m a b
+Ccap@0 gnd net@14 4.686f
+Ccap@1 gnd net@8 4.686f
+Ccap@2 gnd net@11 4.686f
+Rres@0 net@14 a 7.384
+Rres@1 net@11 net@14 14.768
+Rres@2 b net@8 7.384
+Rres@3 net@8 net@11 14.768
+.ENDS wire-C_0_011f-1278-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1278-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1278-R_34_667m
+.ENDS wire90-1278-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2344-R_34_667m a b
+Ccap@0 gnd net@14 8.595f
+Ccap@1 gnd net@8 8.595f
+Ccap@2 gnd net@11 8.595f
+Rres@0 net@14 a 13.543
+Rres@1 net@11 net@14 27.086
+Rres@2 b net@8 13.543
+Rres@3 net@8 net@11 27.086
+.ENDS wire-C_0_011f-2344-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2344-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2344-R_34_667m
+.ENDS wire90-2344-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-285_1-R_34_667m a b
+Ccap@0 gnd net@14 1.045f
+Ccap@1 gnd net@8 1.045f
+Ccap@2 gnd net@11 1.045f
+Rres@0 net@14 a 1.647
+Rres@1 net@11 net@14 3.294
+Rres@2 b net@8 1.647
+Rres@3 net@8 net@11 3.294
+.ENDS wire-C_0_011f-285_1-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-285_1-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-285_1-R_34_667m
+.ENDS wire90-285_1-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-556_6-R_34_667m a b
+Ccap@0 gnd net@14 2.041f
+Ccap@1 gnd net@8 2.041f
+Ccap@2 gnd net@11 2.041f
+Rres@0 net@14 a 3.216
+Rres@1 net@11 net@14 6.432
+Rres@2 b net@8 3.216
+Rres@3 net@8 net@11 6.432
+.ENDS wire-C_0_011f-556_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-556_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-556_6-R_34_667m
+.ENDS wire90-556_6-layer_1-width_3
+
+*** CELL: loopCountL:ilcOdd{sch}
+.SUBCKT ilcOdd bit[1] bit[3] bit[5] count do[3] do[5] do[7] inLO[1] inLO[3] 
++inLO[5] inLO[7] kill load mc zeroLO
+Xinv@3 load[F] net@269 inv-X_30
+Xinv@4 count[F] net@271 inv-X_30
+Xinv@5 count net@273 inv-X_30
+Xinv@6 load net@275 inv-X_30
+XlatchZ10@0 kill net@369 load[F] load[T] inLO[7] mc zeroLO latchZ10@0_out[T] 
++latchZ10
+Xmlat1in5@0 count[T] count[F] do[7] net@376 mlat1in5i
+Xnor2n@0 net@378 count[F] net@372 nor2n-X_10
+XringB@0 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB
+XringB@1 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB
+XringB@2 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB
+Xwire90@2 net@269 load[T] wire90-1350_3-layer_1-width_3
+Xwire90@3 net@271 count[T] wire90-1278-layer_1-width_3
+Xwire90@4 net@273 count[F] wire90-2344-layer_1-width_3
+Xwire90@5 net@275 load[F] wire90-1810_4-layer_1-width_3
+Xwire90@10 net@369 net@372 wire90-285_1-layer_1-width_3
+Xwire90@11 net@376 net@378 wire90-556_6-layer_1-width_3
+.ENDS ilcOdd
+
+*** CELL: orangeTSMC090nm:PMOSx{sch}
+.SUBCKT PMOSx-X_6_667 d g s
+MPMOSf@0 d g s vdd pch W='40.002*(1+ABP/sqrt(40.002*2))' L='2'  
++DELVTO='AVT0P/sqrt(40.002*2)'
+.ENDS PMOSx-X_6_667
+
+*** CELL: orangeTSMC090nm:NMOSx{sch}
+.SUBCKT NMOSx-X_20_001 d g s
+MNMOSf@0 d g s gnd nch W='60.003*(1+ABN/sqrt(60.003*2))' L='2' 
++DELVTO='AVT0N/sqrt(60.003*2)'
+.ENDS NMOSx-X_20_001
+
+*** CELL: redFour:nms3{sch}
+.SUBCKT nms3-X_6_667 d g g2 g3
+XNMOS@0 d g3 net@6 NMOSx-X_20_001
+XNMOS@1 net@7 g gnd NMOSx-X_20_001
+XNMOS@2 net@6 g2 net@7 NMOSx-X_20_001
+.ENDS nms3-X_6_667
+
+*** CELL: redFour:nand3{sch}
+.SUBCKT nand3-X_6_667 ina inb inc out
+XPMOS@0 out inc vdd PMOSx-X_6_667
+XPMOS@1 out inb vdd PMOSx-X_6_667
+XPMOS@2 out ina vdd PMOSx-X_6_667
+Xnms3@0 out ina inb inc nms3-X_6_667
+.ENDS nand3-X_6_667
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-549_2-R_34_667m a b
+Ccap@0 gnd net@14 2.014f
+Ccap@1 gnd net@8 2.014f
+Ccap@2 gnd net@11 2.014f
+Rres@0 net@14 a 3.173
+Rres@1 net@11 net@14 6.346
+Rres@2 b net@8 3.173
+Rres@3 net@8 net@11 6.346
+.ENDS wire-C_0_011f-549_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-549_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-549_2-R_34_667m
+.ENDS wire90-549_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-703_8-R_34_667m a b
+Ccap@0 gnd net@14 2.581f
+Ccap@1 gnd net@8 2.581f
+Ccap@2 gnd net@11 2.581f
+Rres@0 net@14 a 4.066
+Rres@1 net@11 net@14 8.133
+Rres@2 b net@8 4.066
+Rres@3 net@8 net@11 8.133
+.ENDS wire-C_0_011f-703_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-703_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-703_8-R_34_667m
+.ENDS wire90-703_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-543_6-R_34_667m a b
+Ccap@0 gnd net@14 1.993f
+Ccap@1 gnd net@8 1.993f
+Ccap@2 gnd net@11 1.993f
+Rres@0 net@14 a 3.141
+Rres@1 net@11 net@14 6.282
+Rres@2 b net@8 3.141
+Rres@3 net@8 net@11 6.282
+.ENDS wire-C_0_011f-543_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-543_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-543_6-R_34_667m
+.ENDS wire90-543_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-645_3-R_34_667m a b
+Ccap@0 gnd net@14 2.366f
+Ccap@1 gnd net@8 2.366f
+Ccap@2 gnd net@11 2.366f
+Rres@0 net@14 a 3.728
+Rres@1 net@11 net@14 7.457
+Rres@2 b net@8 3.728
+Rres@3 net@8 net@11 7.457
+.ENDS wire-C_0_011f-645_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-645_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-645_3-R_34_667m
+.ENDS wire90-645_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-378_8-R_34_667m a b
+Ccap@0 gnd net@14 1.389f
+Ccap@1 gnd net@8 1.389f
+Ccap@2 gnd net@11 1.389f
+Rres@0 net@14 a 2.189
+Rres@1 net@11 net@14 4.377
+Rres@2 b net@8 2.189
+Rres@3 net@8 net@11 4.377
+.ENDS wire-C_0_011f-378_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-378_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-378_8-R_34_667m
+.ENDS wire90-378_8-layer_1-width_3
+
+*** CELL: loopCountL:countLogic{sch}
+.SUBCKT countLogic bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] do[2] do[3] 
++do[4] do[5] do[6] do[7]
+Xinv@0 net@257 do[2] inv-X_10
+Xinv@1 bit[2] net@128 inv-X_10
+Xinv@2 bit[1] net@257 inv-X_10
+Xnand2@0 bit[3] bit[1] net@145 nand2-X_10
+Xnand2@1 bit[4] bit[2] net@195 nand2-X_10
+Xnand2@2 bit[3] bit[5] net@315 nand2-X_10
+Xnand3@0 bit[5] bit[3] bit[1] net@264 nand3-X_6_667
+Xnand3@1 bit[6] bit[4] bit[2] net@198 nand3-X_6_667
+Xnor2n@1 net@128 net@257 do[3] nor2n-X_10
+Xnor2n@2 net@145 net@146 do[4] nor2n-X_10
+Xnor2n@3 net@195 net@58 do[5] nor2n-X_10
+Xnor2n@4 net@221 net@56 do[6] nor2n-X_10
+Xnor2n@5 net@289 net@267 do[7] nor2n-X_10
+Xwire90@0 net@264 net@221 wire90-549_2-layer_1-width_3
+Xwire90@1 net@58 net@145 wire90-703_8-layer_1-width_3
+Xwire90@3 net@56 net@195 wire90-703_8-layer_1-width_3
+Xwire90@5 net@198 net@289 wire90-543_6-layer_1-width_3
+Xwire90@6 net@146 net@128 wire90-645_3-layer_1-width_3
+Xwire90@8 net@267 net@315 wire90-378_8-layer_1-width_3
+.ENDS countLogic
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-374_2-R_34_667m a b
+Ccap@0 gnd net@14 1.372f
+Ccap@1 gnd net@8 1.372f
+Ccap@2 gnd net@11 1.372f
+Rres@0 net@14 a 2.162
+Rres@1 net@11 net@14 4.324
+Rres@2 b net@8 2.162
+Rres@3 net@8 net@11 4.324
+.ENDS wire-C_0_011f-374_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-374_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-374_2-R_34_667m
+.ENDS wire90-374_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-464_8-R_34_667m a b
+Ccap@0 gnd net@14 1.704f
+Ccap@1 gnd net@8 1.704f
+Ccap@2 gnd net@11 1.704f
+Rres@0 net@14 a 2.686
+Rres@1 net@11 net@14 5.371
+Rres@2 b net@8 2.686
+Rres@3 net@8 net@11 5.371
+.ENDS wire-C_0_011f-464_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-464_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-464_8-R_34_667m
+.ENDS wire90-464_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-398_8-R_34_667m a b
+Ccap@0 gnd net@14 1.462f
+Ccap@1 gnd net@8 1.462f
+Ccap@2 gnd net@11 1.462f
+Rres@0 net@14 a 2.304
+Rres@1 net@11 net@14 4.608
+Rres@2 b net@8 2.304
+Rres@3 net@8 net@11 4.608
+.ENDS wire-C_0_011f-398_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-398_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-398_8-R_34_667m
+.ENDS wire90-398_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-474_8-R_34_667m a b
+Ccap@0 gnd net@14 1.741f
+Ccap@1 gnd net@8 1.741f
+Ccap@2 gnd net@11 1.741f
+Rres@0 net@14 a 2.743
+Rres@1 net@11 net@14 5.487
+Rres@2 b net@8 2.743
+Rres@3 net@8 net@11 5.487
+.ENDS wire-C_0_011f-474_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-474_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-474_8-R_34_667m
+.ENDS wire90-474_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-383_8-R_34_667m a b
+Ccap@0 gnd net@14 1.407f
+Ccap@1 gnd net@8 1.407f
+Ccap@2 gnd net@11 1.407f
+Rres@0 net@14 a 2.218
+Rres@1 net@11 net@14 4.435
+Rres@2 b net@8 2.218
+Rres@3 net@8 net@11 4.435
+.ENDS wire-C_0_011f-383_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-383_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-383_8-R_34_667m
+.ENDS wire90-383_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-399_8-R_34_667m a b
+Ccap@0 gnd net@14 1.466f
+Ccap@1 gnd net@8 1.466f
+Ccap@2 gnd net@11 1.466f
+Rres@0 net@14 a 2.31
+Rres@1 net@11 net@14 4.62
+Rres@2 b net@8 2.31
+Rres@3 net@8 net@11 4.62
+.ENDS wire-C_0_011f-399_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-399_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-399_8-R_34_667m
+.ENDS wire90-399_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-975_7-R_34_667m a b
+Ccap@0 gnd net@14 3.578f
+Ccap@1 gnd net@8 3.578f
+Ccap@2 gnd net@11 3.578f
+Rres@0 net@14 a 5.637
+Rres@1 net@11 net@14 11.275
+Rres@2 b net@8 5.637
+Rres@3 net@8 net@11 11.275
+.ENDS wire-C_0_011f-975_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-975_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-975_7-R_34_667m
+.ENDS wire90-975_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1009_4-R_34_667m a b
+Ccap@0 gnd net@14 3.701f
+Ccap@1 gnd net@8 3.701f
+Ccap@2 gnd net@11 3.701f
+Rres@0 net@14 a 5.832
+Rres@1 net@11 net@14 11.664
+Rres@2 b net@8 5.832
+Rres@3 net@8 net@11 11.664
+.ENDS wire-C_0_011f-1009_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1009_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1009_4-R_34_667m
+.ENDS wire90-1009_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-905_8-R_34_667m a b
+Ccap@0 gnd net@14 3.321f
+Ccap@1 gnd net@8 3.321f
+Ccap@2 gnd net@11 3.321f
+Rres@0 net@14 a 5.234
+Rres@1 net@11 net@14 10.467
+Rres@2 b net@8 5.234
+Rres@3 net@8 net@11 10.467
+.ENDS wire-C_0_011f-905_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-905_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-905_8-R_34_667m
+.ENDS wire90-905_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-758_3-R_34_667m a b
+Ccap@0 gnd net@14 2.78f
+Ccap@1 gnd net@8 2.78f
+Ccap@2 gnd net@11 2.78f
+Rres@0 net@14 a 4.381
+Rres@1 net@11 net@14 8.763
+Rres@2 b net@8 4.381
+Rres@3 net@8 net@11 8.763
+.ENDS wire-C_0_011f-758_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-758_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-758_3-R_34_667m
+.ENDS wire90-758_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-643_7-R_34_667m a b
+Ccap@0 gnd net@14 2.36f
+Ccap@1 gnd net@8 2.36f
+Ccap@2 gnd net@11 2.36f
+Rres@0 net@14 a 3.719
+Rres@1 net@11 net@14 7.438
+Rres@2 b net@8 3.719
+Rres@3 net@8 net@11 7.438
+.ENDS wire-C_0_011f-643_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-643_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-643_7-R_34_667m
+.ENDS wire90-643_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-561_7-R_34_667m a b
+Ccap@0 gnd net@14 2.06f
+Ccap@1 gnd net@8 2.06f
+Ccap@2 gnd net@11 2.06f
+Rres@0 net@14 a 3.245
+Rres@1 net@11 net@14 6.491
+Rres@2 b net@8 3.245
+Rres@3 net@8 net@11 6.491
+.ENDS wire-C_0_011f-561_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-561_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-561_7-R_34_667m
+.ENDS wire90-561_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-898_9-R_34_667m a b
+Ccap@0 gnd net@14 3.296f
+Ccap@1 gnd net@8 3.296f
+Ccap@2 gnd net@11 3.296f
+Rres@0 net@14 a 5.194
+Rres@1 net@11 net@14 10.387
+Rres@2 b net@8 5.194
+Rres@3 net@8 net@11 10.387
+.ENDS wire-C_0_011f-898_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-898_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-898_9-R_34_667m
+.ENDS wire90-898_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-902_4-R_34_667m a b
+Ccap@0 gnd net@14 3.309f
+Ccap@1 gnd net@8 3.309f
+Ccap@2 gnd net@11 3.309f
+Rres@0 net@14 a 5.214
+Rres@1 net@11 net@14 10.428
+Rres@2 b net@8 5.214
+Rres@3 net@8 net@11 10.428
+.ENDS wire-C_0_011f-902_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-902_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-902_4-R_34_667m
+.ENDS wire90-902_4-layer_1-width_3
+
+*** CELL: loopCountL:ilc{sch}
+.SUBCKT ilc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] ilc[cnt] 
++ilc[done] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[7] 
++inLO[8] kill mc
+XilcEven@0 bitt[2] bitt[4] bitt[6] bitt[7] ilc[cnt] do[2] do[4] do[6] 
++ilc[done] inLO[2] inLO[4] inLO[6] inLO[8] kill net@109 mc bit[7] ilcEven
+XilcOdd@0 bitt[1] bitt[3] bitt[5] ilc[cnt] do[3] do[5] do[7] inLO[1] inLO[3] 
++inLO[5] inLO[7] kill net@109 mc bit[7] ilcOdd
+Xinv@4 ilc[load] net@304 inv-X_30
+XolcCente@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4] 
++do[5] do[6] do[7] countLogic
+Xwire90@1 wire90@1_a do[2] wire90-374_2-layer_1-width_3
+Xwire90@2 wire90@2_a do[3] wire90-464_8-layer_1-width_3
+Xwire90@3 wire90@3_a do[4] wire90-398_8-layer_1-width_3
+Xwire90@4 wire90@4_a do[5] wire90-474_8-layer_1-width_3
+Xwire90@5 wire90@5_a do[6] wire90-383_8-layer_1-width_3
+Xwire90@6 wire90@6_a do[7] wire90-399_8-layer_1-width_3
+Xwire90@7 wire90@7_a bitt[1] wire90-975_7-layer_1-width_3
+Xwire90@8 wire90@8_a bitt[2] wire90-1009_4-layer_1-width_3
+Xwire90@9 wire90@9_a bitt[3] wire90-905_8-layer_1-width_3
+Xwire90@10 wire90@10_a bitt[4] wire90-758_3-layer_1-width_3
+Xwire90@11 wire90@11_a bitt[5] wire90-643_7-layer_1-width_3
+Xwire90@12 wire90@12_a bitt[6] wire90-561_7-layer_1-width_3
+Xwire90@35 net@109 net@304 wire90-898_9-layer_1-width_3
+Xwire90@36 wire90@36_a bit[7] wire90-902_4-layer_1-width_3
+.ENDS ilc
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2_74-R_34_667m a b
+Ccap@0 gnd net@14 0.01f
+Ccap@1 gnd net@8 0.01f
+Ccap@2 gnd net@11 0.01f
+Rres@0 net@14 a 15.833m
+Rres@1 net@11 net@14 31.666m
+Rres@2 b net@8 15.833m
+Rres@3 net@8 net@11 31.666m
+.ENDS wire-C_0_011f-2_74-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2_7403-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2_74-R_34_667m
+.ENDS wire90-2_7403-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2_463-R_34_667m a b
+Ccap@0 gnd net@14 0.00903f
+Ccap@1 gnd net@8 0.00903f
+Ccap@2 gnd net@11 0.00903f
+Rres@0 net@14 a 14.231m
+Rres@1 net@11 net@14 28.461m
+Rres@2 b net@8 14.231m
+Rres@3 net@8 net@11 28.461m
+.ENDS wire-C_0_011f-2_463-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2_463-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2_463-R_34_667m
+.ENDS wire90-2_463-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4_063-R_34_667m a b
+Ccap@0 gnd net@14 0.0149f
+Ccap@1 gnd net@8 0.0149f
+Ccap@2 gnd net@11 0.0149f
+Rres@0 net@14 a 23.475m
+Rres@1 net@11 net@14 46.95m
+Rres@2 b net@8 23.475m
+Rres@3 net@8 net@11 46.95m
+.ENDS wire-C_0_011f-4_063-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4_063-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-4_063-R_34_667m
+.ENDS wire90-4_063-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3_818-R_34_667m a b
+Ccap@0 gnd net@14 0.014f
+Ccap@1 gnd net@8 0.014f
+Ccap@2 gnd net@11 0.014f
+Rres@0 net@14 a 22.06m
+Rres@1 net@11 net@14 44.119m
+Rres@2 b net@8 22.06m
+Rres@3 net@8 net@11 44.119m
+.ENDS wire-C_0_011f-3_818-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3_818-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3_818-R_34_667m
+.ENDS wire90-3_818-layer_1-width_3
+
+*** CELL: loopCountL:inMux{sch}
+.SUBCKT inMux inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inB[1] inB[2] inB[3] 
++inB[4] inB[5] inB[6] inB[8] out[1] out[2] out[3] out[4] out[5] out[6] out[7] 
++out[8] sel[A]
+Xinv@0 sel[A] net@10 inv-X_20
+Xinv@1 s[F] net@12 inv-X_20
+Xmux[1] inA[1] inB[1] out[1] s[F] s[T] mux10
+Xmux[2] inA[2] inB[2] out[2] s[F] s[T] mux10
+Xmux[3] inA[3] inB[3] out[3] s[F] s[T] mux10
+Xmux[4] inA[4] inB[4] out[4] s[F] s[T] mux10
+Xmux[5] inA[5] inB[5] out[5] s[F] s[T] mux10
+Xmux[6] inA[6] inB[6] out[6] s[F] s[T] mux10
+Xmux[8] gnd inB[8] out[8] s[F] s[T] mux10
+Xnand3@1 out[1] out[2] out[5] net@25 nand3-X_6_667
+Xnand3@2 out[3] out[4] out[6] net@24 nand3-X_6_667
+Xnor2n_sy@0 net@18 net@20 out[7] nor2n_sy-X_10
+Xwire90@0 net@10 s[F] wire90-2_7403-layer_1-width_3
+Xwire90@1 net@12 s[T] wire90-2_463-layer_1-width_3
+Xwire90@2 net@24 net@20 wire90-4_063-layer_1-width_3
+Xwire90@3 net@18 net@25 wire90-3_818-layer_1-width_3
+.ENDS inMux
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-836_8-R_34_667m a b
+Ccap@0 gnd net@14 3.068f
+Ccap@1 gnd net@8 3.068f
+Ccap@2 gnd net@11 3.068f
+Rres@0 net@14 a 4.835
+Rres@1 net@11 net@14 9.67
+Rres@2 b net@8 4.835
+Rres@3 net@8 net@11 9.67
+.ENDS wire-C_0_011f-836_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-836_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-836_8-R_34_667m
+.ENDS wire90-836_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1053_4-R_34_667m a b
+Ccap@0 gnd net@14 3.862f
+Ccap@1 gnd net@8 3.862f
+Ccap@2 gnd net@11 3.862f
+Rres@0 net@14 a 6.086
+Rres@1 net@11 net@14 12.173
+Rres@2 b net@8 6.086
+Rres@3 net@8 net@11 12.173
+.ENDS wire-C_0_011f-1053_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1053_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1053_4-R_34_667m
+.ENDS wire90-1053_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b
+Ccap@0 gnd net@14 6.469f
+Ccap@1 gnd net@8 6.469f
+Ccap@2 gnd net@11 6.469f
+Rres@0 net@14 a 10.194
+Rres@1 net@11 net@14 20.389
+Rres@2 b net@8 10.194
+Rres@3 net@8 net@11 20.389
+.ENDS wire-C_0_011f-1764_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1764_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m
+.ENDS wire90-1764_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b
+Ccap@0 gnd net@14 5.036f
+Ccap@1 gnd net@8 5.036f
+Ccap@2 gnd net@11 5.036f
+Rres@0 net@14 a 7.935
+Rres@1 net@11 net@14 15.87
+Rres@2 b net@8 7.935
+Rres@3 net@8 net@11 15.87
+.ENDS wire-C_0_011f-1373_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1373_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m
+.ENDS wire90-1373_4-layer_1-width_3
+
+*** CELL: loopCountL:olcEven{sch}
+.SUBCKT olcEven bit[2] bit[4] bit[6] count[2] do[2] do[4] do[6] inLO[2] 
++inLO[4] inLO[6] load[2]
+Xinv@0 count[F] net@196 inv-X_20
+Xinv@1 load[F] net@207 inv-X_20
+Xinv@2 count[2] net@210 inv-X_30
+Xinv@3 load[2] net@211 inv-X_30
+XringB@0 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB
+XringB@1 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB
+XringB@2 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB
+Xwire90@1 net@196 count[T] wire90-836_8-layer_1-width_3
+Xwire90@2 net@207 load[T] wire90-1053_4-layer_1-width_3
+Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3
+Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3
+.ENDS olcEven
+
+*** CELL: loopCountL:olcOdd{sch}
+.SUBCKT olcOdd bit[1] bit[3] bit[5] count[1] do[3] do[5] inLO[1] inLO[3] 
++inLO[5] load[1]
+Xinv@0 count[F] net@299 inv-X_20
+Xinv@1 load[F] net@300 inv-X_20
+Xinv@2 load[1] net@307 inv-X_30
+Xinv@3 count[1] net@310 inv-X_30
+XringB@0 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB
+XringB@1 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB
+XringB@2 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB
+Xwire90@0 net@299 count[T] wire90-836_8-layer_1-width_3
+Xwire90@1 net@300 load[T] wire90-1053_4-layer_1-width_3
+Xwire90@2 net@307 load[F] wire90-1373_4-layer_1-width_3
+Xwire90@3 net@310 count[F] wire90-1764_4-layer_1-width_3
+.ENDS olcOdd
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-538_8-R_34_667m a b
+Ccap@0 gnd net@14 1.976f
+Ccap@1 gnd net@8 1.976f
+Ccap@2 gnd net@11 1.976f
+Rres@0 net@14 a 3.113
+Rres@1 net@11 net@14 6.226
+Rres@2 b net@8 3.113
+Rres@3 net@8 net@11 6.226
+.ENDS wire-C_0_011f-538_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-538_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-538_8-R_34_667m
+.ENDS wire90-538_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-472_8-R_34_667m a b
+Ccap@0 gnd net@14 1.734f
+Ccap@1 gnd net@8 1.734f
+Ccap@2 gnd net@11 1.734f
+Rres@0 net@14 a 2.732
+Rres@1 net@11 net@14 5.463
+Rres@2 b net@8 2.732
+Rres@3 net@8 net@11 5.463
+.ENDS wire-C_0_011f-472_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-472_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-472_8-R_34_667m
+.ENDS wire90-472_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-548_8-R_34_667m a b
+Ccap@0 gnd net@14 2.012f
+Ccap@1 gnd net@8 2.012f
+Ccap@2 gnd net@11 2.012f
+Rres@0 net@14 a 3.171
+Rres@1 net@11 net@14 6.342
+Rres@2 b net@8 3.171
+Rres@3 net@8 net@11 6.342
+.ENDS wire-C_0_011f-548_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-548_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-548_8-R_34_667m
+.ENDS wire90-548_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-457_8-R_34_667m a b
+Ccap@0 gnd net@14 1.679f
+Ccap@1 gnd net@8 1.679f
+Ccap@2 gnd net@11 1.679f
+Rres@0 net@14 a 2.645
+Rres@1 net@11 net@14 5.29
+Rres@2 b net@8 2.645
+Rres@3 net@8 net@11 5.29
+.ENDS wire-C_0_011f-457_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-457_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-457_8-R_34_667m
+.ENDS wire90-457_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1049_7-R_34_667m a b
+Ccap@0 gnd net@14 3.849f
+Ccap@1 gnd net@8 3.849f
+Ccap@2 gnd net@11 3.849f
+Rres@0 net@14 a 6.065
+Rres@1 net@11 net@14 12.13
+Rres@2 b net@8 6.065
+Rres@3 net@8 net@11 12.13
+.ENDS wire-C_0_011f-1049_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1049_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1049_7-R_34_667m
+.ENDS wire90-1049_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1049_4-R_34_667m a b
+Ccap@0 gnd net@14 3.848f
+Ccap@1 gnd net@8 3.848f
+Ccap@2 gnd net@11 3.848f
+Rres@0 net@14 a 6.063
+Rres@1 net@11 net@14 12.126
+Rres@2 b net@8 6.063
+Rres@3 net@8 net@11 12.126
+.ENDS wire-C_0_011f-1049_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1049_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1049_4-R_34_667m
+.ENDS wire90-1049_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-979_8-R_34_667m a b
+Ccap@0 gnd net@14 3.593f
+Ccap@1 gnd net@8 3.593f
+Ccap@2 gnd net@11 3.593f
+Rres@0 net@14 a 5.661
+Rres@1 net@11 net@14 11.322
+Rres@2 b net@8 5.661
+Rres@3 net@8 net@11 11.322
+.ENDS wire-C_0_011f-979_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-979_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-979_8-R_34_667m
+.ENDS wire90-979_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-786_3-R_34_667m a b
+Ccap@0 gnd net@14 2.883f
+Ccap@1 gnd net@8 2.883f
+Ccap@2 gnd net@11 2.883f
+Rres@0 net@14 a 4.543
+Rres@1 net@11 net@14 9.086
+Rres@2 b net@8 4.543
+Rres@3 net@8 net@11 9.086
+.ENDS wire-C_0_011f-786_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-786_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-786_3-R_34_667m
+.ENDS wire90-786_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-717_7-R_34_667m a b
+Ccap@0 gnd net@14 2.632f
+Ccap@1 gnd net@8 2.632f
+Ccap@2 gnd net@11 2.632f
+Rres@0 net@14 a 4.147
+Rres@1 net@11 net@14 8.293
+Rres@2 b net@8 4.147
+Rres@3 net@8 net@11 8.293
+.ENDS wire-C_0_011f-717_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-717_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-717_7-R_34_667m
+.ENDS wire90-717_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-487_7-R_34_667m a b
+Ccap@0 gnd net@14 1.788f
+Ccap@1 gnd net@8 1.788f
+Ccap@2 gnd net@11 1.788f
+Rres@0 net@14 a 2.818
+Rres@1 net@11 net@14 5.636
+Rres@2 b net@8 2.818
+Rres@3 net@8 net@11 5.636
+.ENDS wire-C_0_011f-487_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-487_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-487_7-R_34_667m
+.ENDS wire90-487_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-426-R_34_667m a b
+Ccap@0 gnd net@14 1.562f
+Ccap@1 gnd net@8 1.562f
+Ccap@2 gnd net@11 1.562f
+Rres@0 net@14 a 2.461
+Rres@1 net@11 net@14 4.923
+Rres@2 b net@8 2.461
+Rres@3 net@8 net@11 4.923
+.ENDS wire-C_0_011f-426-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-426-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-426-R_34_667m
+.ENDS wire90-426-layer_1-width_3
+
+*** CELL: loopCountL:olc{sch}
+.SUBCKT olc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] doLO[7] inLO[1] 
++inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] olc[dec][1] olc[dec][2] olc[load][1] 
++olc[load][2]
+Xinv@6 net@270 doLO[7] inv-X_20
+XolcCente@1 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4] 
++do[5] do[6] net@271 countLogic
+XolcEven@0 bitt[2] bitt[4] bitt[6] olc[dec][2] do[2] do[4] do[6] inLO[2] 
++inLO[4] inLO[6] olc[load][2] olcEven
+XolcOdd@1 bitt[1] bitt[3] bitt[5] olc[dec][1] do[3] do[5] inLO[1] inLO[3] 
++inLO[5] olc[load][1] olcOdd
+Xwire90@1 wire90@1_a do[2] wire90-374_2-layer_1-width_3
+Xwire90@2 wire90@2_a do[3] wire90-538_8-layer_1-width_3
+Xwire90@3 wire90@3_a do[4] wire90-472_8-layer_1-width_3
+Xwire90@4 wire90@4_a do[5] wire90-548_8-layer_1-width_3
+Xwire90@5 wire90@5_a do[6] wire90-457_8-layer_1-width_3
+Xwire90@7 wire90@7_a bitt[1] wire90-1049_7-layer_1-width_3
+Xwire90@8 wire90@8_a bitt[2] wire90-1049_4-layer_1-width_3
+Xwire90@9 wire90@9_a bitt[3] wire90-979_8-layer_1-width_3
+Xwire90@10 wire90@10_a bitt[4] wire90-786_3-layer_1-width_3
+Xwire90@11 wire90@11_a bitt[5] wire90-717_7-layer_1-width_3
+Xwire90@12 wire90@12_a bitt[6] wire90-487_7-layer_1-width_3
+Xwire90@29 net@270 net@271 wire90-426-layer_1-width_3
+.ENDS olc
+
+*** CELL: scanK:scanKx3{sch}
+.SUBCKT scanKx3 clS[F] clS[T] cl[F] cl[T] din[1] din[2] din[3] mc rd[F] rd[T] 
++sin sout
+XscanCell@4 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@18 
++scanCellKh
+XscanCell@5 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@31 net@20 
++scanCellKh
+XscanCell@6 clS[F] clS[T] cl[F] cl[T] din[3] rd[F] rd[T] net@32 sout 
++scanCellKh
+Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
+Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3
+.ENDS scanKx3
+
+*** CELL: scanK:scanKx6{sch}
+.SUBCKT scanKx6 clS[F] clS[T] cl[F] cl[T] din[1] din[2] din[3] din[4] din[5] 
++din[6] mc rd[F] rd[T] sin sout
+XscanCell@4 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@18 
++scanCellKh
+XscanCell@5 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@31 net@20 
++scanCellKh
+XscanCell@6 clS[F] clS[T] cl[F] cl[T] din[3] rd[F] rd[T] net@32 net@24 
++scanCellKh
+XscanCell@7 clS[F] clS[T] cl[F] cl[T] din[4] rd[F] rd[T] net@33 net@51 
++scanCellKh
+XscanCell@8 clS[F] clS[T] cl[F] cl[T] din[5] rd[F] rd[T] net@50 net@56 
++scanCellKh
+XscanCell@9 clS[F] clS[T] cl[F] cl[T] din[6] rd[F] rd[T] net@55 sout 
++scanCellKh
+Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
+Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3
+Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3
+Xwire90@3 net@51 net@50 wire90-297_9-layer_1-width_3
+Xwire90@4 net@56 net@55 wire90-297_9-layer_1-width_3
+.ENDS scanKx6
+
+*** CELL: scanK:scanKx7{sch}
+.SUBCKT scanKx7 clS[F] clS[T] cl[F] cl[T] din[1] din[2] din[3] din[4] din[5] 
++din[6] din[7] mc rd[F] rd[T] sin sout
+XscanCell@4 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@18 
++scanCellKh
+XscanCell@5 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@31 net@20 
++scanCellKh
+XscanCell@6 clS[F] clS[T] cl[F] cl[T] din[3] rd[F] rd[T] net@32 net@24 
++scanCellKh
+XscanCell@7 clS[F] clS[T] cl[F] cl[T] din[4] rd[F] rd[T] net@33 net@51 
++scanCellKh
+XscanCell@8 clS[F] clS[T] cl[F] cl[T] din[5] rd[F] rd[T] net@50 net@56 
++scanCellKh
+XscanCell@9 clS[F] clS[T] cl[F] cl[T] din[6] rd[F] rd[T] net@55 net@63 
++scanCellKh
+XscanCell@10 clS[F] clS[T] cl[F] cl[T] din[7] rd[F] rd[T] net@61 sout 
++scanCellKh
+Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3
+Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3
+Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3
+Xwire90@3 net@51 net@50 wire90-297_9-layer_1-width_3
+Xwire90@4 net@56 net@55 wire90-297_9-layer_1-width_3
+Xwire90@5 net@63 net@61 wire90-297_9-layer_1-width_3
+.ENDS scanKx7
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-99_3-R_34_667m a b
+Ccap@0 gnd net@14 0.364f
+Ccap@1 gnd net@8 0.364f
+Ccap@2 gnd net@11 0.364f
+Rres@0 net@14 a 0.574
+Rres@1 net@11 net@14 1.147
+Rres@2 b net@8 0.574
+Rres@3 net@8 net@11 1.147
+.ENDS wire-C_0_011f-99_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-99_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-99_3-R_34_667m
+.ENDS wire90-99_3-layer_1-width_3
+
+*** CELL: skipL:latchA20{sch}
+.SUBCKT latchA20 cl[F] cl[T] in[1] mc out[1]
+MNMOSf@1 out[1] net@186 gnd gnd nch W='12*(1+ABN/sqrt(12*3))' L='3' 
++DELVTO='AVT0N/sqrt(12*3)'
+XNMOSx@2 out[1] mc gnd NMOSx-X_10
+XPMOSx@2 out[1] net@193 vdd PMOSx-X_2
+XinvLT@0 out[1] net@186 invLT-X_2
+Xnms2@0 out[1] in[1] cl[T] nms2-X_20
+Xpms2@0 out[1] in[1] cl[F] pms2-X_20
+Xwire90@0 net@186 net@193 wire90-99_3-layer_1-width_3
+.ENDS latchA20
+
+*** CELL: skipL:flagDrivers{sch}
+.SUBCKT flagDrivers flag[A] flag[B] flag[C] in[A] in[B] in[C] loadC[T] 
++loadFlags[F] mc
+Xinv@0 loadFlags[F] net@511 inv-X_20
+Xinv@1 loadC[T] net@540 inv-X_10
+XlatchA20@0 loadFlags[F] loadFlags[T] in[A] mc flag[A] latchA20
+XlatchA20@1 loadFlags[F] loadFlags[T] in[B] mc flag[B] latchA20
+XlatchA20@2 loadC[F] loadC[T] in[C] mc flag[C] latchA20
+Xwire90@0 net@511 loadFlags[T] wire90-99_3-layer_1-width_3
+Xwire90@1 net@540 loadC[F] wire90-99_3-layer_1-width_3
+.ENDS flagDrivers
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-183-R_34_667m a b
+Ccap@0 gnd net@14 0.671f
+Ccap@1 gnd net@8 0.671f
+Ccap@2 gnd net@11 0.671f
+Rres@0 net@14 a 1.057
+Rres@1 net@11 net@14 2.115
+Rres@2 b net@8 1.057
+Rres@3 net@8 net@11 2.115
+.ENDS wire-C_0_011f-183-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-183-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-183-R_34_667m
+.ENDS wire90-183-layer_1-width_3
+
+*** CELL: skipL:muxInv{sch}
+.SUBCKT muxInv flag in[1][F] in[1][T] out
+Xinv@3 flag net@119 inv-X_5
+XtriInv@0 net@123 flag in[1][F] out triInv-X_5
+XtriInv@1 flag net@123 in[1][T] out triInv-X_5
+Xwire90@3 net@119 net@123 wire90-183-layer_1-width_3
+.ENDS muxInv
+
+*** CELL: redFour:nms2_sy{sch}
+.SUBCKT nms2_sy-X_6 d g g2
+Xnms2@0 d g g2 nms2-X_3
+Xnms2@1 d g2 g nms2-X_3
+.ENDS nms2_sy-X_6
+
+*** CELL: redFour:nand2_sy{sch}
+.SUBCKT nand2_sy-X_6 ina inb out
+XPMOS@0 out inb vdd PMOSx-X_6
+XPMOS@1 out ina vdd PMOSx-X_6
+Xnms2_sy@0 out ina inb nms2_sy-X_6
+.ENDS nand2_sy-X_6
+
+*** CELL: redFour:nand2n_sy{sch}
+.SUBCKT nand2n_sy-X_6 ina inb out
+Xnand2_sy@0 ina inb out nand2_sy-X_6
+.ENDS nand2n_sy-X_6
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-239_6-R_34_667m a b
+Ccap@0 gnd net@14 0.879f
+Ccap@1 gnd net@8 0.879f
+Ccap@2 gnd net@11 0.879f
+Rres@0 net@14 a 1.384
+Rres@1 net@11 net@14 2.769
+Rres@2 b net@8 1.384
+Rres@3 net@8 net@11 2.769
+.ENDS wire-C_0_011f-239_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-239_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-239_6-R_34_667m
+.ENDS wire90-239_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-321_6-R_34_667m a b
+Ccap@0 gnd net@14 1.179f
+Ccap@1 gnd net@8 1.179f
+Ccap@2 gnd net@11 1.179f
+Rres@0 net@14 a 1.858
+Rres@1 net@11 net@14 3.716
+Rres@2 b net@8 1.858
+Rres@3 net@8 net@11 3.716
+.ENDS wire-C_0_011f-321_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-321_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-321_6-R_34_667m
+.ENDS wire90-321_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-345-R_34_667m a b
+Ccap@0 gnd net@14 1.265f
+Ccap@1 gnd net@8 1.265f
+Ccap@2 gnd net@11 1.265f
+Rres@0 net@14 a 1.993
+Rres@1 net@11 net@14 3.987
+Rres@2 b net@8 1.993
+Rres@3 net@8 net@11 3.987
+.ENDS wire-C_0_011f-345-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-345-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-345-R_34_667m
+.ENDS wire90-345-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-883_7-R_34_667m a b
+Ccap@0 gnd net@14 3.24f
+Ccap@1 gnd net@8 3.24f
+Ccap@2 gnd net@11 3.24f
+Rres@0 net@14 a 5.106
+Rres@1 net@11 net@14 10.212
+Rres@2 b net@8 5.106
+Rres@3 net@8 net@11 10.212
+.ENDS wire-C_0_011f-883_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-883_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-883_7-R_34_667m
+.ENDS wire90-883_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1192-R_34_667m a b
+Ccap@0 gnd net@14 4.371f
+Ccap@1 gnd net@8 4.371f
+Ccap@2 gnd net@11 4.371f
+Rres@0 net@14 a 6.887
+Rres@1 net@11 net@14 13.774
+Rres@2 b net@8 6.887
+Rres@3 net@8 net@11 13.774
+.ENDS wire-C_0_011f-1192-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1192-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1192-R_34_667m
+.ENDS wire90-1192-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1256-R_34_667m a b
+Ccap@0 gnd net@14 4.605f
+Ccap@1 gnd net@8 4.605f
+Ccap@2 gnd net@11 4.605f
+Rres@0 net@14 a 7.257
+Rres@1 net@11 net@14 14.514
+Rres@2 b net@8 7.257
+Rres@3 net@8 net@11 14.514
+.ENDS wire-C_0_011f-1256-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1256-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1256-R_34_667m
+.ENDS wire90-1256-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1068_8-R_34_667m a b
+Ccap@0 gnd net@14 3.919f
+Ccap@1 gnd net@8 3.919f
+Ccap@2 gnd net@11 3.919f
+Rres@0 net@14 a 6.175
+Rres@1 net@11 net@14 12.351
+Rres@2 b net@8 6.175
+Rres@3 net@8 net@11 12.351
+.ENDS wire-C_0_011f-1068_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1068_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1068_8-R_34_667m
+.ENDS wire90-1068_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-839_7-R_34_667m a b
+Ccap@0 gnd net@14 3.079f
+Ccap@1 gnd net@8 3.079f
+Ccap@2 gnd net@11 3.079f
+Rres@0 net@14 a 4.852
+Rres@1 net@11 net@14 9.703
+Rres@2 b net@8 4.852
+Rres@3 net@8 net@11 9.703
+.ENDS wire-C_0_011f-839_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-839_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-839_7-R_34_667m
+.ENDS wire90-839_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-247_7-R_34_667m a b
+Ccap@0 gnd net@14 0.908f
+Ccap@1 gnd net@8 0.908f
+Ccap@2 gnd net@11 0.908f
+Rres@0 net@14 a 1.431
+Rres@1 net@11 net@14 2.862
+Rres@2 b net@8 1.431
+Rres@3 net@8 net@11 2.862
+.ENDS wire-C_0_011f-247_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-247_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-247_7-R_34_667m
+.ENDS wire90-247_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-245_7-R_34_667m a b
+Ccap@0 gnd net@14 0.901f
+Ccap@1 gnd net@8 0.901f
+Ccap@2 gnd net@11 0.901f
+Rres@0 net@14 a 1.42
+Rres@1 net@11 net@14 2.839
+Rres@2 b net@8 1.42
+Rres@3 net@8 net@11 2.839
+.ENDS wire-C_0_011f-245_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-245_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-245_7-R_34_667m
+.ENDS wire90-245_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-216_4-R_37_143m a b
+Ccap@0 gnd net@14 0.793f
+Ccap@1 gnd net@8 0.793f
+Ccap@2 gnd net@11 0.793f
+Rres@0 net@14 a 1.34
+Rres@1 net@11 net@14 2.679
+Rres@2 b net@8 1.34
+Rres@3 net@8 net@11 2.679
+.ENDS wire-C_0_011f-216_4-R_37_143m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-216_4-layer_1-width_2_8 a b
+Xwire@0 a b wire-C_0_011f-216_4-R_37_143m
+.ENDS wire90-216_4-layer_1-width_2_8
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-505_7-R_34_667m a b
+Ccap@0 gnd net@14 1.854f
+Ccap@1 gnd net@8 1.854f
+Ccap@2 gnd net@11 1.854f
+Rres@0 net@14 a 2.922
+Rres@1 net@11 net@14 5.844
+Rres@2 b net@8 2.922
+Rres@3 net@8 net@11 5.844
+.ENDS wire-C_0_011f-505_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-505_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-505_7-R_34_667m
+.ENDS wire90-505_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-353_6-R_34_667m a b
+Ccap@0 gnd net@14 1.297f
+Ccap@1 gnd net@8 1.297f
+Ccap@2 gnd net@11 1.297f
+Rres@0 net@14 a 2.043
+Rres@1 net@11 net@14 4.086
+Rres@2 b net@8 2.043
+Rres@3 net@8 net@11 4.086
+.ENDS wire-C_0_011f-353_6-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-353_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-353_6-R_34_667m
+.ENDS wire90-353_6-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-313_9-R_34_667m a b
+Ccap@0 gnd net@14 1.151f
+Ccap@1 gnd net@8 1.151f
+Ccap@2 gnd net@11 1.151f
+Rres@0 net@14 a 1.814
+Rres@1 net@11 net@14 3.627
+Rres@2 b net@8 1.814
+Rres@3 net@8 net@11 3.627
+.ENDS wire-C_0_011f-313_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-313_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-313_9-R_34_667m
+.ENDS wire90-313_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-309_5-R_34_667m a b
+Ccap@0 gnd net@14 1.135f
+Ccap@1 gnd net@8 1.135f
+Ccap@2 gnd net@11 1.135f
+Rres@0 net@14 a 1.788
+Rres@1 net@11 net@14 3.576
+Rres@2 b net@8 1.788
+Rres@3 net@8 net@11 3.576
+.ENDS wire-C_0_011f-309_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-309_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-309_5-R_34_667m
+.ENDS wire90-309_5-layer_1-width_3
+
+*** CELL: skipL:array{sch}
+.SUBCKT array doit flag[A] flag[B] flag[C] flag[NZ] in[1][F] in[1][T] 
++in[2][F] in[2][T] in[3][F] in[3][T] in[4][F] in[4][T] in[5][F] in[5][T] 
++in[6][F] in[6][T] in[7][F] in[7][T] in[8][F] in[8][T] in[9][F] in[9][T] in[C] 
++loadC[T] loadFlags[F] m1[F] m1[T] mc
+XflagDriv@0 net@1022 net@1015 net@1007 net@1012 net@1009 in[C] loadC[T] 
++loadFlags[F] mc flagDrivers
+Xinv@3 net@57 net@344 inv-X_10
+Xinv@9 net@352 net@350 inv-X_10
+Xinv@13 net@876 doit inv-X_20
+Xinv@14 net@924 net@925 inv-X_5
+Xinv@15 net@978 net@948 inv-X_5
+Xinv@16 net@977 net@963 inv-X_5
+Xmlat1in5@2 m1[F] m1[T] net@906 net@45 mlat1in5i
+Xmlat1in5@4 m1[F] m1[T] net@927 net@912 mlat1in5i
+Xmlat1in5@5 m1[F] m1[T] net@938 net@937 mlat1in5i
+Xmlat1in5@6 m1[F] m1[T] net@949 net@940 mlat1in5i
+Xmlat1in5@7 m1[F] m1[T] net@953 net@952 mlat1in5i
+Xmlat1in5@8 m1[F] m1[T] net@964 net@955 mlat1in5i
+XmuxInv@24 flag[A] in[1][F] in[1][T] net@711 muxInv
+XmuxInv@25 flag[B] in[2][F] in[2][T] net@722 muxInv
+XmuxInv@26 flag[C] in[3][F] in[3][T] net@733 muxInv
+XmuxInv@27 flag[A] in[4][F] in[4][T] net@744 muxInv
+XmuxInv@28 flag[B] in[5][F] in[5][T] net@755 muxInv
+XmuxInv@29 flag[C] in[6][F] in[6][T] net@766 muxInv
+XmuxInv@30 flag[A] in[7][F] in[7][T] net@777 muxInv
+XmuxInv@31 flag[B] in[8][F] in[8][T] net@788 muxInv
+XmuxInv@32 flag[NZ] in[9][F] in[9][T] net@799 muxInv
+Xnand2n_s@0 net@895 net@896 net@909 nand2n_sy-X_6
+Xnand2n_s@3 net@913 net@916 pFlag[A] nand2n_sy-X_6
+Xnand2n_s@4 net@973 net@974 net@939 nand2n_sy-X_6
+Xnand2n_s@5 net@941 net@944 pFlag[B] nand2n_sy-X_6
+Xnand2n_s@6 net@971 net@972 net@954 nand2n_sy-X_6
+Xnand2n_s@7 net@956 net@959 net@993 nand2n_sy-X_10
+Xwire90@12 net@925 net@906 wire90-239_6-layer_1-width_3
+Xwire90@13 net@45 net@913 wire90-321_6-layer_1-width_3
+Xwire90@15 net@57 pFlag[B] wire90-345-layer_1-width_3
+Xwire90@17 net@344 net@1009 wire90-883_7-layer_1-width_3
+Xwire90@19 flag[A] net@1022 wire90-1192-layer_1-width_3
+Xwire90@42 flag[B] net@1015 wire90-1256-layer_1-width_3
+Xwire90@43 flag[C] net@1007 wire90-1068_8-layer_1-width_3
+Xwire90@44 net@352 pFlag[A] wire90-345-layer_1-width_3
+Xwire90@45 net@350 net@1012 wire90-839_7-layer_1-width_3
+Xwire90@47 net@711 net@896 wire90-247_7-layer_1-width_3
+Xwire90@50 net@744 net@974 wire90-247_7-layer_1-width_3
+Xwire90@66 net@777 net@972 wire90-247_7-layer_1-width_3
+Xwire90@68 net@722 net@895 wire90-245_7-layer_1-width_3
+Xwire90@69 net@755 net@973 wire90-245_7-layer_1-width_3
+Xwire90@70 net@788 net@971 wire90-245_7-layer_1-width_3
+Xwire90@71 net@733 net@924 wire90-216_4-layer_1-width_2_8
+Xwire90@72 net@766 net@978 wire90-216_4-layer_1-width_2_8
+Xwire90@73 net@799 net@977 wire90-216_4-layer_1-width_2_8
+Xwire90@74 net@993 net@876 wire90-505_7-layer_1-width_3
+Xwire90@75 net@909 net@927 wire90-353_6-layer_1-width_3
+Xwire90@76 net@912 net@916 wire90-321_6-layer_1-width_3
+Xwire90@77 net@948 net@938 wire90-239_6-layer_1-width_3
+Xwire90@78 net@937 net@941 wire90-321_6-layer_1-width_3
+Xwire90@79 net@939 net@949 wire90-353_6-layer_1-width_3
+Xwire90@80 net@940 net@944 wire90-321_6-layer_1-width_3
+Xwire90@81 net@963 net@953 wire90-239_6-layer_1-width_3
+Xwire90@82 net@952 net@956 wire90-313_9-layer_1-width_3
+Xwire90@83 net@954 net@964 wire90-353_6-layer_1-width_3
+Xwire90@84 net@955 net@959 wire90-309_5-layer_1-width_3
+.ENDS array
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-262_8-R_34_667m a b
+Ccap@0 gnd net@14 0.964f
+Ccap@1 gnd net@8 0.964f
+Ccap@2 gnd net@11 0.964f
+Rres@0 net@14 a 1.518
+Rres@1 net@11 net@14 3.037
+Rres@2 b net@8 1.518
+Rres@3 net@8 net@11 3.037
+.ENDS wire-C_0_011f-262_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-262_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-262_8-R_34_667m
+.ENDS wire90-262_8-layer_1-width_3
+
+*** CELL: skipL:proposeZero{sch}
+.SUBCKT proposeZero doLO[7] flag[NZ] inLO[7] kill mc olcNZ olc[dec][F] 
++olc[load][F]
+Xinv@1 olc[load][F] net@39 inv-X_10
+XlatchZ10@1 kill net@14 olc[load][F] olc[load][T] inLO[7] mc olcNZ flag[NZ] 
++latchZ10
+Xnor2n_sy@0 olc[dec][F] doLO[7] net@12 nor2n_sy-X_5
+Xwire90@0 olc[load][T] net@39 wire90-262_8-layer_1-width_3
+Xwire90@1 net@12 net@14 wire90-216_3-layer_1-width_3
+.ENDS proposeZero
+
+*** CELL: skipL:skipReg18{sch}
+.SUBCKT skipReg18 c[F] c[T] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
++in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] 
++out[3] out[4] out[5] out[6] out[7] out[8] out[9]
+Xinv@0 in[1] xx[1] inv-X_10
+Xinv@15 in[2] xx[2] inv-X_10
+Xinv@16 in[3] xx[3] inv-X_10
+Xinv@17 in[4] xx[4] inv-X_10
+Xinv@18 in[5] xx[5] inv-X_10
+Xinv@19 in[6] xx[6] inv-X_10
+Xinv@20 in[7] xx[7] inv-X_10
+Xinv@21 in[8] xx[8] inv-X_10
+Xinv@22 in[9] xx[9] inv-X_10
+Xinv@23 in[10] xx[10] inv-X_10
+Xinv@24 in[11] xx[11] inv-X_10
+Xinv@25 in[12] xx[12] inv-X_10
+Xlat[1] c[F] c[T] xx[1] out[1] mlat1in5i
+Xlat[2] c[F] c[T] xx[2] out[2] mlat1in5i
+Xlat[3] c[F] c[T] xx[3] out[3] mlat1in5i
+Xlat[4] c[F] c[T] xx[4] out[4] mlat1in5i
+Xlat[5] c[F] c[T] xx[5] out[5] mlat1in5i
+Xlat[6] c[F] c[T] xx[6] out[6] mlat1in5i
+Xlat[7] c[F] c[T] xx[7] out[7] mlat1in5i
+Xlat[8] c[F] c[T] xx[8] out[8] mlat1in5i
+Xlat[9] c[F] c[T] xx[9] out[9] mlat1in5i
+Xlat[10] c[F] c[T] xx[10] out[10] mlat1in5i
+Xlat[11] c[F] c[T] xx[11] out[11] mlat1in5i
+Xlat[12] c[F] c[T] xx[12] out[12] mlat1in5i
+Xlat[13] c[F] c[T] in[13] out[13] mlat1in5i
+Xlat[14] c[F] c[T] in[14] out[14] mlat1in5i
+Xlat[15] c[F] c[T] in[15] out[15] mlat1in5i
+Xlat[16] c[F] c[T] in[16] out[16] mlat1in5i
+Xlat[17] c[F] c[T] in[17] out[17] mlat1in5i
+Xlat[18] c[F] c[T] in[18] out[18] mlat1in5i
+.ENDS skipReg18
+
+*** CELL: redFour:invLT{sch}
+.SUBCKT invLT-X_30 in out
+XNMOS@0 out in gnd NMOSx-X_60
+XPMOS@0 out in vdd PMOSx-X_30
+.ENDS invLT-X_30
+
+*** CELL: driversL:sucDri20cond{sch}
+.SUBCKT sucDri20cond cond in succ
+XNMOSx@0 succ in net@160 NMOSx-X_5
+XNMOSx@1 succ cond net@160 NMOSx-X_5
+XNMOSx@2 net@160 net@158 gnd NMOSx-X_10
+Xinv@1 succ net@94 inv-X_5
+Xpms2@0 succ cond in pms2-X_20
+Xwire90@0 net@158 net@94 wire90-124_7-layer_1-width_3
+.ENDS sucDri20cond
+
+*** CELL: skipL:timeDrive20{sch}
+.SUBCKT timeDrive20 inA inB out
+XNMOSx@0 out inB inA NMOSx-X_20
+XPMOSx@0 out inB vdd PMOSx-X_10
+.ENDS timeDrive20
+
+*** CELL: skipL:timeDrive40{sch}
+.SUBCKT timeDrive40 inA inB out
+XNMOSx@0 out inB inA NMOSx-X_40
+XPMOSx@0 out inB vdd PMOSx-X_30
+.ENDS timeDrive40
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-287_2-R_34_667m a b
+Ccap@0 gnd net@14 1.053f
+Ccap@1 gnd net@8 1.053f
+Ccap@2 gnd net@11 1.053f
+Rres@0 net@14 a 1.659
+Rres@1 net@11 net@14 3.319
+Rres@2 b net@8 1.659
+Rres@3 net@8 net@11 3.319
+.ENDS wire-C_0_011f-287_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-287_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-287_2-R_34_667m
+.ENDS wire90-287_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-284_2-R_34_667m a b
+Ccap@0 gnd net@14 1.042f
+Ccap@1 gnd net@8 1.042f
+Ccap@2 gnd net@11 1.042f
+Rres@0 net@14 a 1.642
+Rres@1 net@11 net@14 3.284
+Rres@2 b net@8 1.642
+Rres@3 net@8 net@11 3.284
+.ENDS wire-C_0_011f-284_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-284_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-284_2-R_34_667m
+.ENDS wire90-284_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-391_7-R_34_667m a b
+Ccap@0 gnd net@14 1.436f
+Ccap@1 gnd net@8 1.436f
+Ccap@2 gnd net@11 1.436f
+Rres@0 net@14 a 2.263
+Rres@1 net@11 net@14 4.526
+Rres@2 b net@8 2.263
+Rres@3 net@8 net@11 4.526
+.ENDS wire-C_0_011f-391_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-391_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-391_7-R_34_667m
+.ENDS wire90-391_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1092_8-R_34_667m a b
+Ccap@0 gnd net@14 4.007f
+Ccap@1 gnd net@8 4.007f
+Ccap@2 gnd net@11 4.007f
+Rres@0 net@14 a 6.314
+Rres@1 net@11 net@14 12.628
+Rres@2 b net@8 6.314
+Rres@3 net@8 net@11 12.628
+.ENDS wire-C_0_011f-1092_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1092_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1092_8-R_34_667m
+.ENDS wire90-1092_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-296_2-R_34_667m a b
+Ccap@0 gnd net@14 1.086f
+Ccap@1 gnd net@8 1.086f
+Ccap@2 gnd net@11 1.086f
+Rres@0 net@14 a 1.711
+Rres@1 net@11 net@14 3.423
+Rres@2 b net@8 1.711
+Rres@3 net@8 net@11 3.423
+.ENDS wire-C_0_011f-296_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-296_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-296_2-R_34_667m
+.ENDS wire90-296_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-463_3-R_34_667m a b
+Ccap@0 gnd net@14 1.699f
+Ccap@1 gnd net@8 1.699f
+Ccap@2 gnd net@11 1.699f
+Rres@0 net@14 a 2.677
+Rres@1 net@11 net@14 5.354
+Rres@2 b net@8 2.677
+Rres@3 net@8 net@11 5.354
+.ENDS wire-C_0_011f-463_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-463_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-463_3-R_34_667m
+.ENDS wire90-463_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-181-R_34_667m a b
+Ccap@0 gnd net@14 0.664f
+Ccap@1 gnd net@8 0.664f
+Ccap@2 gnd net@11 0.664f
+Rres@0 net@14 a 1.046
+Rres@1 net@11 net@14 2.092
+Rres@2 b net@8 1.046
+Rres@3 net@8 net@11 2.092
+.ENDS wire-C_0_011f-181-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-181-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-181-R_34_667m
+.ENDS wire90-181-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-184-R_34_667m a b
+Ccap@0 gnd net@14 0.675f
+Ccap@1 gnd net@8 0.675f
+Ccap@2 gnd net@11 0.675f
+Rres@0 net@14 a 1.063
+Rres@1 net@11 net@14 2.126
+Rres@2 b net@8 1.063
+Rres@3 net@8 net@11 2.126
+.ENDS wire-C_0_011f-184-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-184-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-184-R_34_667m
+.ENDS wire90-184-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-439_3-R_34_667m a b
+Ccap@0 gnd net@14 1.611f
+Ccap@1 gnd net@8 1.611f
+Ccap@2 gnd net@11 1.611f
+Rres@0 net@14 a 2.538
+Rres@1 net@11 net@14 5.076
+Rres@2 b net@8 2.538
+Rres@3 net@8 net@11 5.076
+.ENDS wire-C_0_011f-439_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-439_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-439_3-R_34_667m
+.ENDS wire90-439_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-191-R_34_667m a b
+Ccap@0 gnd net@14 0.7f
+Ccap@1 gnd net@8 0.7f
+Ccap@2 gnd net@11 0.7f
+Rres@0 net@14 a 1.104
+Rres@1 net@11 net@14 2.207
+Rres@2 b net@8 1.104
+Rres@3 net@8 net@11 2.207
+.ENDS wire-C_0_011f-191-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-191-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-191-R_34_667m
+.ENDS wire90-191-layer_1-width_3
+
+*** CELL: skipL:skipTimer{sch}
+.SUBCKT skipTimer do[L] do[M] doit fire[ODE] ilc[load][F] loadFlags[F] 
++olc[dec][1] olc[dec][2] olc[dec][F] olc[load][1] olc[load][2] olc[load][F] 
++selLO[Co] selLO[Dl] selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo]
+Xinv@1 fire[ODE] net@68 inv-X_20
+Xinv@2 net@249 olc[dec][1] inv-X_10
+Xinv@4 net@252 olc[dec][2] inv-X_10
+Xinv@5 net@261 olc[load][1] inv-X_10
+Xinv@6 olc[load][F] olc[load][2] inv-X_10
+XinvLT@0 doit net@304 invLT-X_30
+Xnor2n@5 selLO[Lf] fire[ODE] net@18 nor2n-X_10
+Xnor2n@7 selLO[Co] fire[ODE] net@0 nor2n-X_10
+Xnor2n@9 selLO[Li] fire[ODE] net@165 nor2n-X_10
+Xnor2n@10 selLO[Co] fire[ODE] net@206 nor2n-X_10
+Xnor2n@12 selLO[Lo] fire[ODE] net@256 nor2n-X_10
+XsucDri20@0 selLO[Dl] net@334 do[L] sucDri20cond
+XsucDri20@1 selLO[Dm] net@334 do[M] sucDri20cond
+XtimeDriv@1 net@133 net@144 loadFlags[F] timeDrive20
+XtimeDriv@3 net@133 net@255 olc[load][F] timeDrive20
+XtimeDriv@4 net@133 net@164 ilc[load][F] timeDrive20
+XtimeDriv@5 net@133 net@147 net@331 timeDrive40
+XtimeDriv@8 net@133 net@207 net@248 timeDrive20
+XtimeDriv@9 net@133 net@145 olc[dec][F] timeDrive20
+XtimeDriv@10 net@133 net@207 net@247 timeDrive20
+XtimeDriv@11 net@133 net@255 net@263 timeDrive20
+Xwire90@0 net@18 net@144 wire90-287_2-layer_1-width_3
+Xwire90@1 net@0 net@145 wire90-284_2-layer_1-width_3
+Xwire90@3 net@68 net@147 wire90-391_7-layer_1-width_3
+Xwire90@4 net@304 net@133 wire90-1092_8-layer_1-width_3
+Xwire90@5 net@165 net@164 wire90-296_2-layer_1-width_3
+Xwire90@6 net@206 net@207 wire90-463_3-layer_1-width_3
+Xwire90@8 net@248 net@249 wire90-181-layer_1-width_3
+Xwire90@9 net@247 net@252 wire90-184-layer_1-width_3
+Xwire90@10 net@256 net@255 wire90-439_3-layer_1-width_3
+Xwire90@11 net@263 net@261 wire90-191-layer_1-width_3
+Xwire90@12 net@331 net@334 wire90-391_7-layer_1-width_3
+.ENDS skipTimer
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-657_5-R_34_667m a b
+Ccap@0 gnd net@14 2.411f
+Ccap@1 gnd net@8 2.411f
+Ccap@2 gnd net@11 2.411f
+Rres@0 net@14 a 3.799
+Rres@1 net@11 net@14 7.598
+Rres@2 b net@8 3.799
+Rres@3 net@8 net@11 7.598
+.ENDS wire-C_0_011f-657_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-657_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-657_5-R_34_667m
+.ENDS wire90-657_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-439_9-R_34_667m a b
+Ccap@0 gnd net@14 1.613f
+Ccap@1 gnd net@8 1.613f
+Ccap@2 gnd net@11 1.613f
+Rres@0 net@14 a 2.542
+Rres@1 net@11 net@14 5.083
+Rres@2 b net@8 2.542
+Rres@3 net@8 net@11 5.083
+.ENDS wire-C_0_011f-439_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-439_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-439_9-R_34_667m
+.ENDS wire90-439_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1282_5-R_34_667m a b
+Ccap@0 gnd net@14 4.703f
+Ccap@1 gnd net@8 4.703f
+Ccap@2 gnd net@11 4.703f
+Rres@0 net@14 a 7.41
+Rres@1 net@11 net@14 14.82
+Rres@2 b net@8 7.41
+Rres@3 net@8 net@11 14.82
+.ENDS wire-C_0_011f-1282_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1282_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1282_5-R_34_667m
+.ENDS wire90-1282_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3646_5-R_34_667m a b
+Ccap@0 gnd net@14 13.371f
+Ccap@1 gnd net@8 13.371f
+Ccap@2 gnd net@11 13.371f
+Rres@0 net@14 a 21.069
+Rres@1 net@11 net@14 42.137
+Rres@2 b net@8 21.069
+Rres@3 net@8 net@11 42.137
+.ENDS wire-C_0_011f-3646_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3646_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-3646_5-R_34_667m
+.ENDS wire90-3646_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2967_8-R_34_667m a b
+Ccap@0 gnd net@14 10.882f
+Ccap@1 gnd net@8 10.882f
+Ccap@2 gnd net@11 10.882f
+Rres@0 net@14 a 17.147
+Rres@1 net@11 net@14 34.295
+Rres@2 b net@8 17.147
+Rres@3 net@8 net@11 34.295
+.ENDS wire-C_0_011f-2967_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2967_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2967_8-R_34_667m
+.ENDS wire90-2967_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1704_4-R_34_667m a b
+Ccap@0 gnd net@14 6.249f
+Ccap@1 gnd net@8 6.249f
+Ccap@2 gnd net@11 6.249f
+Rres@0 net@14 a 9.848
+Rres@1 net@11 net@14 19.695
+Rres@2 b net@8 9.848
+Rres@3 net@8 net@11 19.695
+.ENDS wire-C_0_011f-1704_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1704_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1704_4-R_34_667m
+.ENDS wire90-1704_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-649-R_34_667m a b
+Ccap@0 gnd net@14 2.38f
+Ccap@1 gnd net@8 2.38f
+Ccap@2 gnd net@11 2.38f
+Rres@0 net@14 a 3.75
+Rres@1 net@11 net@14 7.5
+Rres@2 b net@8 3.75
+Rres@3 net@8 net@11 7.5
+.ENDS wire-C_0_011f-649-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-649-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-649-R_34_667m
+.ENDS wire90-649-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-306-R_34_667m a b
+Ccap@0 gnd net@14 1.122f
+Ccap@1 gnd net@8 1.122f
+Ccap@2 gnd net@11 1.122f
+Rres@0 net@14 a 1.768
+Rres@1 net@11 net@14 3.536
+Rres@2 b net@8 1.768
+Rres@3 net@8 net@11 3.536
+.ENDS wire-C_0_011f-306-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-306-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-306-R_34_667m
+.ENDS wire90-306-layer_1-width_3
+
+*** CELL: skipL:skipAll{sch}
+.SUBCKT skipAll doLO[7] do[L] do[M] fire[ODE] fire[m1] fire[m2] flag[A] 
++flag[B] flag[C] ilc[load][F] inLO[7] in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] 
++in[9] in[C] kill loadC[T] mc olcNZ olc[dec][1] olc[dec][2] olc[load][1] 
++olc[load][2] selLO[Co] selLO[Dl] selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo]
+Xarray@0 net@331 flag[A] flag[B] flag[C] flag[NZ] in[1][F] in[1][T] in[2][F] 
++in[2][T] in[3][F] in[3][T] in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] 
++in[6][T] in[7][F] in[7][T] in[8][F] in[8][T] in[9][F] in[9][T] in[C] loadC[T] 
++loadFlags[F] m1[F] m1[T] mc array
+Xinv@0 m1[F] net@179 inv-X_20
+Xinv@1 fire[m2] net@302 inv-X_80
+Xinv@2 m2[F] net@304 inv-X_40
+Xinv@3 fire[m1] net@308 inv-X_30
+XproposeZ@1 doLO[7] net@177 inLO[7] kill mc olcNZ olc[dec][F] olc[load][F] 
++proposeZero
+XskipReg1@0 m2[F] m2[T] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
++in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[5][F] 
++in[6][T] in[6][F] in[7][T] in[7][F] in[8][T] in[8][F] in[9][T] in[9][F] 
++in[1][T] in[1][F] in[2][T] in[2][F] in[3][T] in[3][F] in[4][T] in[4][F] 
++in[5][T] skipReg18
+XskipTime@4 do[L] do[M] doIt fire[ODE] ilc[load][F] loadFlags[F] olc[dec][1] 
++olc[dec][2] olc[dec][F] olc[load][1] olc[load][2] olc[load][F] selLO[Co] 
++selLO[Dl] selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo] skipTimer
+Xwire90@3 net@177 flag[NZ] wire90-657_5-layer_1-width_3
+Xwire90@5 net@331 doIt wire90-439_9-layer_1-width_3
+Xwire90@13 m1[T] net@179 wire90-1282_5-layer_1-width_3
+Xwire90@14 m2[F] net@302 wire90-3646_5-layer_1-width_3
+Xwire90@15 m2[T] net@304 wire90-2967_8-layer_1-width_3
+Xwire90@16 m1[F] net@308 wire90-1704_4-layer_1-width_3
+Xwire90@17 olc[load][F] wire90@17_b wire90-649-layer_1-width_3
+Xwire90@18 olc[dec][F] wire90@18_b wire90-306-layer_1-width_3
+.ENDS skipAll
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-654_3-R_34_667m a b
+Ccap@0 gnd net@14 2.399f
+Ccap@1 gnd net@8 2.399f
+Ccap@2 gnd net@11 2.399f
+Rres@0 net@14 a 3.78
+Rres@1 net@11 net@14 7.561
+Rres@2 b net@8 3.78
+Rres@3 net@8 net@11 7.561
+.ENDS wire-C_0_011f-654_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-654_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-654_3-R_34_667m
+.ENDS wire90-654_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-338_3-R_34_667m a b
+Ccap@0 gnd net@14 1.24f
+Ccap@1 gnd net@8 1.24f
+Ccap@2 gnd net@11 1.24f
+Rres@0 net@14 a 1.955
+Rres@1 net@11 net@14 3.909
+Rres@2 b net@8 1.955
+Rres@3 net@8 net@11 3.909
+.ENDS wire-C_0_011f-338_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-338_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-338_3-R_34_667m
+.ENDS wire90-338_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-467_4-R_34_667m a b
+Ccap@0 gnd net@14 1.714f
+Ccap@1 gnd net@8 1.714f
+Ccap@2 gnd net@11 1.714f
+Rres@0 net@14 a 2.701
+Rres@1 net@11 net@14 5.401
+Rres@2 b net@8 2.701
+Rres@3 net@8 net@11 5.401
+.ENDS wire-C_0_011f-467_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-467_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-467_4-R_34_667m
+.ENDS wire90-467_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-466_9-R_34_667m a b
+Ccap@0 gnd net@14 1.712f
+Ccap@1 gnd net@8 1.712f
+Ccap@2 gnd net@11 1.712f
+Rres@0 net@14 a 2.698
+Rres@1 net@11 net@14 5.395
+Rres@2 b net@8 2.698
+Rres@3 net@8 net@11 5.395
+.ENDS wire-C_0_011f-466_9-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-466_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-466_9-R_34_667m
+.ENDS wire90-466_9-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2321_3-R_34_667m a b
+Ccap@0 gnd net@14 8.511f
+Ccap@1 gnd net@8 8.511f
+Ccap@2 gnd net@11 8.511f
+Rres@0 net@14 a 13.412
+Rres@1 net@11 net@14 26.824
+Rres@2 b net@8 13.412
+Rres@3 net@8 net@11 26.824
+.ENDS wire-C_0_011f-2321_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2321_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2321_3-R_34_667m
+.ENDS wire90-2321_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2286_4-R_34_667m a b
+Ccap@0 gnd net@14 8.383f
+Ccap@1 gnd net@8 8.383f
+Ccap@2 gnd net@11 8.383f
+Rres@0 net@14 a 13.21
+Rres@1 net@11 net@14 26.421
+Rres@2 b net@8 13.21
+Rres@3 net@8 net@11 26.421
+.ENDS wire-C_0_011f-2286_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2286_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2286_4-R_34_667m
+.ENDS wire90-2286_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2339_2-R_34_667m a b
+Ccap@0 gnd net@14 8.577f
+Ccap@1 gnd net@8 8.577f
+Ccap@2 gnd net@11 8.577f
+Rres@0 net@14 a 13.515
+Rres@1 net@11 net@14 27.031
+Rres@2 b net@8 13.515
+Rres@3 net@8 net@11 27.031
+.ENDS wire-C_0_011f-2339_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2339_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2339_2-R_34_667m
+.ENDS wire90-2339_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2336_8-R_34_667m a b
+Ccap@0 gnd net@14 8.568f
+Ccap@1 gnd net@8 8.568f
+Ccap@2 gnd net@11 8.568f
+Rres@0 net@14 a 13.502
+Rres@1 net@11 net@14 27.003
+Rres@2 b net@8 13.502
+Rres@3 net@8 net@11 27.003
+.ENDS wire-C_0_011f-2336_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2336_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2336_8-R_34_667m
+.ENDS wire90-2336_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2277-R_34_667m a b
+Ccap@0 gnd net@14 8.349f
+Ccap@1 gnd net@8 8.349f
+Ccap@2 gnd net@11 8.349f
+Rres@0 net@14 a 13.156
+Rres@1 net@11 net@14 26.312
+Rres@2 b net@8 13.156
+Rres@3 net@8 net@11 26.312
+.ENDS wire-C_0_011f-2277-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2277-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2277-R_34_667m
+.ENDS wire90-2277-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2338_5-R_34_667m a b
+Ccap@0 gnd net@14 8.574f
+Ccap@1 gnd net@8 8.574f
+Ccap@2 gnd net@11 8.574f
+Rres@0 net@14 a 13.511
+Rres@1 net@11 net@14 27.023
+Rres@2 b net@8 13.511
+Rres@3 net@8 net@11 27.023
+.ENDS wire-C_0_011f-2338_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2338_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2338_5-R_34_667m
+.ENDS wire90-2338_5-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1105_2-R_34_667m a b
+Ccap@0 gnd net@14 4.052f
+Ccap@1 gnd net@8 4.052f
+Ccap@2 gnd net@11 4.052f
+Rres@0 net@14 a 6.386
+Rres@1 net@11 net@14 12.771
+Rres@2 b net@8 6.386
+Rres@3 net@8 net@11 12.771
+.ENDS wire-C_0_011f-1105_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1105_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1105_2-R_34_667m
+.ENDS wire90-1105_2-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2165_4-R_34_667m a b
+Ccap@0 gnd net@14 7.94f
+Ccap@1 gnd net@8 7.94f
+Ccap@2 gnd net@11 7.94f
+Rres@0 net@14 a 12.511
+Rres@1 net@11 net@14 25.022
+Rres@2 b net@8 12.511
+Rres@3 net@8 net@11 25.022
+.ENDS wire-C_0_011f-2165_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2165_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2165_4-R_34_667m
+.ENDS wire90-2165_4-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1272_5-R_34_667m a b
+Ccap@0 gnd net@14 4.666f
+Ccap@1 gnd net@8 4.666f
+Ccap@2 gnd net@11 4.666f
+Rres@0 net@14 a 7.352
+Rres@1 net@11 net@14 14.704
+Rres@2 b net@8 7.352
+Rres@3 net@8 net@11 14.704
+.ENDS wire-C_0_011f-1272_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1272_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1272_5-R_34_667m
+.ENDS wire90-1272_5-layer_1-width_3
+
+*** CELL: dockPartOD:skipCount{sch}
+.SUBCKT skipCount clS[F] clS[T] cl[F] cl[T] do[L] do[M] fire[ODE] fire[m1] 
++fire[m2] ilc[cnt] ilc[done] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inB[1] 
++inB[2] inB[3] inB[4] inB[5] inB[6] inB[8] in[10] in[11] in[12] in[13] in[14] 
++in[15] in[16] in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] 
++in[9] in[C] kill loadC[T] mc olcNZ rd[F] rd[T] selLO[Co] selLO[Dl] selLO[Dm] 
++selLO[Lf] selLO[Li] selLO[Lo] sel[A] sin sout
+Xilc@0 net@129[6] net@129[5] net@129[4] net@129[3] net@129[2] net@129[1] 
++net@129[0] ilc[cnt] ilc[done] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] 
++inLO[5] inLO[6] inLO[7] inLO[8] kill mc ilc
+XinMux@0 inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inB[1] inB[2] inB[3] 
++inB[4] inB[5] inB[6] inB[8] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] 
++inLO[7] inLO[8] sel[A] inMux
+Xolc@0 net@130[5] net@130[4] net@130[3] net@130[2] net@130[1] net@130[0] 
++net@10 inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] olc[dec][1] 
++olc[dec][2] olc[load][1] olc[load][2] olc
+XscanKx3@0 clS[F] clS[T] cl[F] cl[T] flag[C] flag[B] flag[A] mc rd[F] rd[T] 
++net@104 sout scanKx3
+XscanKx6@0 clS[F] clS[T] cl[F] cl[T] net@130[5] net@130[4] net@130[3] 
++net@130[2] net@130[1] net@130[0] mc rd[F] rd[T] net@103 net@104 scanKx6
+XscanKx7@0 clS[F] clS[T] cl[F] cl[T] net@129[6] net@129[5] net@129[4] 
++net@129[3] net@129[2] net@129[1] net@129[0] mc rd[F] rd[T] sin net@103 
++scanKx7
+XskipAll@0 doLO[7] do[L] do[M] fire[ODE] fire[m1] fire[m2] flag[A] flag[B] 
++flag[C] net@99 inLO[7] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
++in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[C] 
++kill loadC[T] mc olcNZ olc[dec][1] olc[dec][2] olc[load][1] olc[load][2] 
++selLO[Co] selLO[Dl] selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo] skipAll
+Xwire90@0 net@10 doLO[7] wire90-654_3-layer_1-width_3
+Xwire90@1 wire90@1_a olc[dec][1] wire90-338_3-layer_1-width_3
+Xwire90@2 wire90@2_a olc[load][1] wire90-467_4-layer_1-width_3
+Xwire90@3 wire90@3_a olc[load][2] wire90-466_9-layer_1-width_3
+Xwire90@4 wire90@4_a olc[dec][2] wire90-338_3-layer_1-width_3
+Xwire90@5 wire90@5_a inLO[1] wire90-2321_3-layer_1-width_3
+Xwire90@6 wire90@6_a inLO[2] wire90-2286_4-layer_1-width_3
+Xwire90@7 wire90@7_a inLO[3] wire90-2339_2-layer_1-width_3
+Xwire90@8 wire90@8_a inLO[4] wire90-2336_8-layer_1-width_3
+Xwire90@9 wire90@9_a inLO[5] wire90-2277-layer_1-width_3
+Xwire90@10 wire90@10_a inLO[6] wire90-2338_5-layer_1-width_3
+Xwire90@11 wire90@11_a inLO[8] wire90-1105_2-layer_1-width_3
+Xwire90@12 wire90@12_a inLO[7] wire90-2165_4-layer_1-width_3
+Xwire90@13 ilc[load] net@99 wire90-1272_5-layer_1-width_3
+.ENDS skipCount
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2416_4-R_26m a b
+Ccap@0 gnd net@14 8.86f
+Ccap@1 gnd net@8 8.86f
+Ccap@2 gnd net@11 8.86f
+Rres@0 net@14 a 10.471
+Rres@1 net@11 net@14 20.942
+Rres@2 b net@8 10.471
+Rres@3 net@8 net@11 20.942
+.ENDS wire-C_0_011f-2416_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2416_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2416_4-R_26m
+.ENDS wire90-2416_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2384_4-R_26m a b
+Ccap@0 gnd net@14 8.743f
+Ccap@1 gnd net@8 8.743f
+Ccap@2 gnd net@11 8.743f
+Rres@0 net@14 a 10.332
+Rres@1 net@11 net@14 20.665
+Rres@2 b net@8 10.332
+Rres@3 net@8 net@11 20.665
+.ENDS wire-C_0_011f-2384_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2384_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2384_4-R_26m
+.ENDS wire90-2384_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2330_4-R_26m a b
+Ccap@0 gnd net@14 8.545f
+Ccap@1 gnd net@8 8.545f
+Ccap@2 gnd net@11 8.545f
+Rres@0 net@14 a 10.098
+Rres@1 net@11 net@14 20.197
+Rres@2 b net@8 10.098
+Rres@3 net@8 net@11 20.197
+.ENDS wire-C_0_011f-2330_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2330_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2330_4-R_26m
+.ENDS wire90-2330_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2135_9-R_26m a b
+Ccap@0 gnd net@14 7.832f
+Ccap@1 gnd net@8 7.832f
+Ccap@2 gnd net@11 7.832f
+Rres@0 net@14 a 9.256
+Rres@1 net@11 net@14 18.511
+Rres@2 b net@8 9.256
+Rres@3 net@8 net@11 18.511
+.ENDS wire-C_0_011f-2135_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2135_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2135_9-R_26m
+.ENDS wire90-2135_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1987_4-R_26m a b
+Ccap@0 gnd net@14 7.287f
+Ccap@1 gnd net@8 7.287f
+Ccap@2 gnd net@11 7.287f
+Rres@0 net@14 a 8.612
+Rres@1 net@11 net@14 17.224
+Rres@2 b net@8 8.612
+Rres@3 net@8 net@11 17.224
+.ENDS wire-C_0_011f-1987_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1987_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1987_4-R_26m
+.ENDS wire90-1987_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1996_4-R_26m a b
+Ccap@0 gnd net@14 7.32f
+Ccap@1 gnd net@8 7.32f
+Ccap@2 gnd net@11 7.32f
+Rres@0 net@14 a 8.651
+Rres@1 net@11 net@14 17.302
+Rres@2 b net@8 8.651
+Rres@3 net@8 net@11 17.302
+.ENDS wire-C_0_011f-1996_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1996_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1996_4-R_26m
+.ENDS wire90-1996_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1636_3-R_26m a b
+Ccap@0 gnd net@14 6f
+Ccap@1 gnd net@8 6f
+Ccap@2 gnd net@11 6f
+Rres@0 net@14 a 7.091
+Rres@1 net@11 net@14 14.181
+Rres@2 b net@8 7.091
+Rres@3 net@8 net@11 14.181
+.ENDS wire-C_0_011f-1636_3-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1636_3-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1636_3-R_26m
+.ENDS wire90-1636_3-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1776_4-R_26m a b
+Ccap@0 gnd net@14 6.513f
+Ccap@1 gnd net@8 6.513f
+Ccap@2 gnd net@11 6.513f
+Rres@0 net@14 a 7.698
+Rres@1 net@11 net@14 15.395
+Rres@2 b net@8 7.698
+Rres@3 net@8 net@11 15.395
+.ENDS wire-C_0_011f-1776_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1776_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1776_4-R_26m
+.ENDS wire90-1776_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1870_9-R_26m a b
+Ccap@0 gnd net@14 6.86f
+Ccap@1 gnd net@8 6.86f
+Ccap@2 gnd net@11 6.86f
+Rres@0 net@14 a 8.107
+Rres@1 net@11 net@14 16.214
+Rres@2 b net@8 8.107
+Rres@3 net@8 net@11 16.214
+.ENDS wire-C_0_011f-1870_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1870_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1870_9-R_26m
+.ENDS wire90-1870_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1565_5-R_26m a b
+Ccap@0 gnd net@14 5.74f
+Ccap@1 gnd net@8 5.74f
+Ccap@2 gnd net@11 5.74f
+Rres@0 net@14 a 6.784
+Rres@1 net@11 net@14 13.568
+Rres@2 b net@8 6.784
+Rres@3 net@8 net@11 13.568
+.ENDS wire-C_0_011f-1565_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1565_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1565_5-R_26m
+.ENDS wire90-1565_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1506-R_26m a b
+Ccap@0 gnd net@14 5.522f
+Ccap@1 gnd net@8 5.522f
+Ccap@2 gnd net@11 5.522f
+Rres@0 net@14 a 6.526
+Rres@1 net@11 net@14 13.052
+Rres@2 b net@8 6.526
+Rres@3 net@8 net@11 13.052
+.ENDS wire-C_0_011f-1506-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1506-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1506-R_26m
+.ENDS wire90-1506-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1605_5-R_26m a b
+Ccap@0 gnd net@14 5.887f
+Ccap@1 gnd net@8 5.887f
+Ccap@2 gnd net@11 5.887f
+Rres@0 net@14 a 6.957
+Rres@1 net@11 net@14 13.914
+Rres@2 b net@8 6.957
+Rres@3 net@8 net@11 13.914
+.ENDS wire-C_0_011f-1605_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1605_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1605_5-R_26m
+.ENDS wire90-1605_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1227_3-R_26m a b
+Ccap@0 gnd net@14 4.5f
+Ccap@1 gnd net@8 4.5f
+Ccap@2 gnd net@11 4.5f
+Rres@0 net@14 a 5.318
+Rres@1 net@11 net@14 10.637
+Rres@2 b net@8 5.318
+Rres@3 net@8 net@11 10.637
+.ENDS wire-C_0_011f-1227_3-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1227_3-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1227_3-R_26m
+.ENDS wire90-1227_3-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1254_9-R_26m a b
+Ccap@0 gnd net@14 4.601f
+Ccap@1 gnd net@8 4.601f
+Ccap@2 gnd net@11 4.601f
+Rres@0 net@14 a 5.438
+Rres@1 net@11 net@14 10.876
+Rres@2 b net@8 5.438
+Rres@3 net@8 net@11 10.876
+.ENDS wire-C_0_011f-1254_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1254_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1254_9-R_26m
+.ENDS wire90-1254_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1280_2-R_26m a b
+Ccap@0 gnd net@14 4.694f
+Ccap@1 gnd net@8 4.694f
+Ccap@2 gnd net@11 4.694f
+Rres@0 net@14 a 5.548
+Rres@1 net@11 net@14 11.095
+Rres@2 b net@8 5.548
+Rres@3 net@8 net@11 11.095
+.ENDS wire-C_0_011f-1280_2-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1280_2-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1280_2-R_26m
+.ENDS wire90-1280_2-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1012_7-R_26m a b
+Ccap@0 gnd net@14 3.713f
+Ccap@1 gnd net@8 3.713f
+Ccap@2 gnd net@11 3.713f
+Rres@0 net@14 a 4.388
+Rres@1 net@11 net@14 8.777
+Rres@2 b net@8 4.388
+Rres@3 net@8 net@11 8.777
+.ENDS wire-C_0_011f-1012_7-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1012_7-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1012_7-R_26m
+.ENDS wire90-1012_7-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-960_9-R_26m a b
+Ccap@0 gnd net@14 3.523f
+Ccap@1 gnd net@8 3.523f
+Ccap@2 gnd net@11 3.523f
+Rres@0 net@14 a 4.164
+Rres@1 net@11 net@14 8.328
+Rres@2 b net@8 4.164
+Rres@3 net@8 net@11 8.328
+.ENDS wire-C_0_011f-960_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-960_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-960_9-R_26m
+.ENDS wire90-960_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-904_3-R_26m a b
+Ccap@0 gnd net@14 3.316f
+Ccap@1 gnd net@8 3.316f
+Ccap@2 gnd net@11 3.316f
+Rres@0 net@14 a 3.919
+Rres@1 net@11 net@14 7.837
+Rres@2 b net@8 3.919
+Rres@3 net@8 net@11 7.837
+.ENDS wire-C_0_011f-904_3-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-904_3-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-904_3-R_26m
+.ENDS wire90-904_3-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4579_4-R_26m a b
+Ccap@0 gnd net@14 16.791f
+Ccap@1 gnd net@8 16.791f
+Ccap@2 gnd net@11 16.791f
+Rres@0 net@14 a 19.844
+Rres@1 net@11 net@14 39.688
+Rres@2 b net@8 19.844
+Rres@3 net@8 net@11 39.688
+.ENDS wire-C_0_011f-4579_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4579_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4579_4-R_26m
+.ENDS wire90-4579_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4580_9-R_26m a b
+Ccap@0 gnd net@14 16.797f
+Ccap@1 gnd net@8 16.797f
+Ccap@2 gnd net@11 16.797f
+Rres@0 net@14 a 19.851
+Rres@1 net@11 net@14 39.701
+Rres@2 b net@8 19.851
+Rres@3 net@8 net@11 39.701
+.ENDS wire-C_0_011f-4580_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4580_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4580_9-R_26m
+.ENDS wire90-4580_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4864_4-R_26m a b
+Ccap@0 gnd net@14 17.836f
+Ccap@1 gnd net@8 17.836f
+Ccap@2 gnd net@11 17.836f
+Rres@0 net@14 a 21.079
+Rres@1 net@11 net@14 42.158
+Rres@2 b net@8 21.079
+Rres@3 net@8 net@11 42.158
+.ENDS wire-C_0_011f-4864_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4864_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4864_4-R_26m
+.ENDS wire90-4864_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4970_4-R_26m a b
+Ccap@0 gnd net@14 18.225f
+Ccap@1 gnd net@8 18.225f
+Ccap@2 gnd net@11 18.225f
+Rres@0 net@14 a 21.538
+Rres@1 net@11 net@14 43.077
+Rres@2 b net@8 21.538
+Rres@3 net@8 net@11 43.077
+.ENDS wire-C_0_011f-4970_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4970_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4970_4-R_26m
+.ENDS wire90-4970_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5067_4-R_26m a b
+Ccap@0 gnd net@14 18.58f
+Ccap@1 gnd net@8 18.58f
+Ccap@2 gnd net@11 18.58f
+Rres@0 net@14 a 21.959
+Rres@1 net@11 net@14 43.917
+Rres@2 b net@8 21.959
+Rres@3 net@8 net@11 43.917
+.ENDS wire-C_0_011f-5067_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5067_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-5067_4-R_26m
+.ENDS wire90-5067_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5238_9-R_26m a b
+Ccap@0 gnd net@14 19.209f
+Ccap@1 gnd net@8 19.209f
+Ccap@2 gnd net@11 19.209f
+Rres@0 net@14 a 22.702
+Rres@1 net@11 net@14 45.404
+Rres@2 b net@8 22.702
+Rres@3 net@8 net@11 45.404
+.ENDS wire-C_0_011f-5238_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5238_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-5238_9-R_26m
+.ENDS wire90-5238_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5485_4-R_26m a b
+Ccap@0 gnd net@14 20.113f
+Ccap@1 gnd net@8 20.113f
+Ccap@2 gnd net@11 20.113f
+Rres@0 net@14 a 23.77
+Rres@1 net@11 net@14 47.54
+Rres@2 b net@8 23.77
+Rres@3 net@8 net@11 47.54
+.ENDS wire-C_0_011f-5485_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5485_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-5485_4-R_26m
+.ENDS wire90-5485_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3582_8-R_26m a b
+Ccap@0 gnd net@14 13.137f
+Ccap@1 gnd net@8 13.137f
+Ccap@2 gnd net@11 13.137f
+Rres@0 net@14 a 15.525
+Rres@1 net@11 net@14 31.051
+Rres@2 b net@8 15.525
+Rres@3 net@8 net@11 31.051
+.ENDS wire-C_0_011f-3582_8-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3582_8-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-3582_8-R_26m
+.ENDS wire90-3582_8-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4216_8-R_26m a b
+Ccap@0 gnd net@14 15.462f
+Ccap@1 gnd net@8 15.462f
+Ccap@2 gnd net@11 15.462f
+Rres@0 net@14 a 18.273
+Rres@1 net@11 net@14 36.546
+Rres@2 b net@8 18.273
+Rres@3 net@8 net@11 36.546
+.ENDS wire-C_0_011f-4216_8-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4216_8-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4216_8-R_26m
+.ENDS wire90-4216_8-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4217_8-R_26m a b
+Ccap@0 gnd net@14 15.465f
+Ccap@1 gnd net@8 15.465f
+Ccap@2 gnd net@11 15.465f
+Rres@0 net@14 a 18.277
+Rres@1 net@11 net@14 36.554
+Rres@2 b net@8 18.277
+Rres@3 net@8 net@11 36.554
+.ENDS wire-C_0_011f-4217_8-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4217_8-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4217_8-R_26m
+.ENDS wire90-4217_8-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4580_7-R_26m a b
+Ccap@0 gnd net@14 16.796f
+Ccap@1 gnd net@8 16.796f
+Ccap@2 gnd net@11 16.796f
+Rres@0 net@14 a 19.85
+Rres@1 net@11 net@14 39.699
+Rres@2 b net@8 19.85
+Rres@3 net@8 net@11 39.699
+.ENDS wire-C_0_011f-4580_7-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4580_7-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4580_7-R_26m
+.ENDS wire90-4580_7-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4914_8-R_26m a b
+Ccap@0 gnd net@14 18.021f
+Ccap@1 gnd net@8 18.021f
+Ccap@2 gnd net@11 18.021f
+Rres@0 net@14 a 21.297
+Rres@1 net@11 net@14 42.595
+Rres@2 b net@8 21.297
+Rres@3 net@8 net@11 42.595
+.ENDS wire-C_0_011f-4914_8-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4914_8-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4914_8-R_26m
+.ENDS wire90-4914_8-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-5109_1-R_26m a b
+Ccap@0 gnd net@14 18.733f
+Ccap@1 gnd net@8 18.733f
+Ccap@2 gnd net@11 18.733f
+Rres@0 net@14 a 22.139
+Rres@1 net@11 net@14 44.279
+Rres@2 b net@8 22.139
+Rres@3 net@8 net@11 44.279
+.ENDS wire-C_0_011f-5109_1-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-5109_1-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-5109_1-R_26m
+.ENDS wire90-5109_1-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4659_8-R_26m a b
+Ccap@0 gnd net@14 17.086f
+Ccap@1 gnd net@8 17.086f
+Ccap@2 gnd net@11 17.086f
+Rres@0 net@14 a 20.192
+Rres@1 net@11 net@14 40.385
+Rres@2 b net@8 20.192
+Rres@3 net@8 net@11 40.385
+.ENDS wire-C_0_011f-4659_8-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4659_8-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4659_8-R_26m
+.ENDS wire90-4659_8-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-3105_9-R_26m a b
+Ccap@0 gnd net@14 11.388f
+Ccap@1 gnd net@8 11.388f
+Ccap@2 gnd net@11 11.388f
+Rres@0 net@14 a 13.459
+Rres@1 net@11 net@14 26.918
+Rres@2 b net@8 13.459
+Rres@3 net@8 net@11 26.918
+.ENDS wire-C_0_011f-3105_9-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-3105_9-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-3105_9-R_26m
+.ENDS wire90-3105_9-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2229_2-R_26m a b
+Ccap@0 gnd net@14 8.174f
+Ccap@1 gnd net@8 8.174f
+Ccap@2 gnd net@11 8.174f
+Rres@0 net@14 a 9.66
+Rres@1 net@11 net@14 19.32
+Rres@2 b net@8 9.66
+Rres@3 net@8 net@11 19.32
+.ENDS wire-C_0_011f-2229_2-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2229_2-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2229_2-R_26m
+.ENDS wire90-2229_2-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4552_2-R_26m a b
+Ccap@0 gnd net@14 16.691f
+Ccap@1 gnd net@8 16.691f
+Ccap@2 gnd net@11 16.691f
+Rres@0 net@14 a 19.726
+Rres@1 net@11 net@14 39.452
+Rres@2 b net@8 19.726
+Rres@3 net@8 net@11 39.452
+.ENDS wire-C_0_011f-4552_2-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4552_2-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4552_2-R_26m
+.ENDS wire90-4552_2-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4224_4-R_26m a b
+Ccap@0 gnd net@14 15.489f
+Ccap@1 gnd net@8 15.489f
+Ccap@2 gnd net@11 15.489f
+Rres@0 net@14 a 18.306
+Rres@1 net@11 net@14 36.611
+Rres@2 b net@8 18.306
+Rres@3 net@8 net@11 36.611
+.ENDS wire-C_0_011f-4224_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4224_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4224_4-R_26m
+.ENDS wire90-4224_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-4964_8-R_26m a b
+Ccap@0 gnd net@14 18.204f
+Ccap@1 gnd net@8 18.204f
+Ccap@2 gnd net@11 18.204f
+Rres@0 net@14 a 21.514
+Rres@1 net@11 net@14 43.028
+Rres@2 b net@8 21.514
+Rres@3 net@8 net@11 43.028
+.ENDS wire-C_0_011f-4964_8-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-4964_8-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-4964_8-R_26m
+.ENDS wire90-4964_8-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2102_8-R_26m a b
+Ccap@0 gnd net@14 7.71f
+Ccap@1 gnd net@8 7.71f
+Ccap@2 gnd net@11 7.71f
+Rres@0 net@14 a 9.112
+Rres@1 net@11 net@14 18.224
+Rres@2 b net@8 9.112
+Rres@3 net@8 net@11 18.224
+.ENDS wire-C_0_011f-2102_8-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2102_8-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2102_8-R_26m
+.ENDS wire90-2102_8-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2117_2-R_26m a b
+Ccap@0 gnd net@14 7.763f
+Ccap@1 gnd net@8 7.763f
+Ccap@2 gnd net@11 7.763f
+Rres@0 net@14 a 9.175
+Rres@1 net@11 net@14 18.349
+Rres@2 b net@8 9.175
+Rres@3 net@8 net@11 18.349
+.ENDS wire-C_0_011f-2117_2-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2117_2-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2117_2-R_26m
+.ENDS wire90-2117_2-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-840_4-R_26m a b
+Ccap@0 gnd net@14 3.081f
+Ccap@1 gnd net@8 3.081f
+Ccap@2 gnd net@11 3.081f
+Rres@0 net@14 a 3.642
+Rres@1 net@11 net@14 7.283
+Rres@2 b net@8 3.642
+Rres@3 net@8 net@11 7.283
+.ENDS wire-C_0_011f-840_4-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-840_4-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-840_4-R_26m
+.ENDS wire90-840_4-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2017_6-R_26m a b
+Ccap@0 gnd net@14 7.398f
+Ccap@1 gnd net@8 7.398f
+Ccap@2 gnd net@11 7.398f
+Rres@0 net@14 a 8.743
+Rres@1 net@11 net@14 17.486
+Rres@2 b net@8 8.743
+Rres@3 net@8 net@11 17.486
+.ENDS wire-C_0_011f-2017_6-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2017_6-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2017_6-R_26m
+.ENDS wire90-2017_6-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2584_1-R_26m a b
+Ccap@0 gnd net@14 9.475f
+Ccap@1 gnd net@8 9.475f
+Ccap@2 gnd net@11 9.475f
+Rres@0 net@14 a 11.198
+Rres@1 net@11 net@14 22.396
+Rres@2 b net@8 11.198
+Rres@3 net@8 net@11 22.396
+.ENDS wire-C_0_011f-2584_1-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2584_1-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2584_1-R_26m
+.ENDS wire90-2584_1-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2385_3-R_26m a b
+Ccap@0 gnd net@14 8.746f
+Ccap@1 gnd net@8 8.746f
+Ccap@2 gnd net@11 8.746f
+Rres@0 net@14 a 10.336
+Rres@1 net@11 net@14 20.673
+Rres@2 b net@8 10.336
+Rres@3 net@8 net@11 20.673
+.ENDS wire-C_0_011f-2385_3-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2385_3-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2385_3-R_26m
+.ENDS wire90-2385_3-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-1928_3-R_26m a b
+Ccap@0 gnd net@14 7.07f
+Ccap@1 gnd net@8 7.07f
+Ccap@2 gnd net@11 7.07f
+Rres@0 net@14 a 8.356
+Rres@1 net@11 net@14 16.712
+Rres@2 b net@8 8.356
+Rres@3 net@8 net@11 16.712
+.ENDS wire-C_0_011f-1928_3-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-1928_3-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-1928_3-R_26m
+.ENDS wire90-1928_3-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2790_5-R_26m a b
+Ccap@0 gnd net@14 10.232f
+Ccap@1 gnd net@8 10.232f
+Ccap@2 gnd net@11 10.232f
+Rres@0 net@14 a 12.092
+Rres@1 net@11 net@14 24.184
+Rres@2 b net@8 12.092
+Rres@3 net@8 net@11 24.184
+.ENDS wire-C_0_011f-2790_5-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2790_5-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2790_5-R_26m
+.ENDS wire90-2790_5-layer_1-width_4
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-2752_3-R_26m a b
+Ccap@0 gnd net@14 10.092f
+Ccap@1 gnd net@8 10.092f
+Ccap@2 gnd net@11 10.092f
+Rres@0 net@14 a 11.927
+Rres@1 net@11 net@14 23.853
+Rres@2 b net@8 11.927
+Rres@3 net@8 net@11 23.853
+.ENDS wire-C_0_011f-2752_3-R_26m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-2752_3-layer_1-width_4 a b
+Xwire@0 a b wire-C_0_011f-2752_3-R_26m
+.ENDS wire90-2752_3-layer_1-width_4
+
+*** CELL: dockPartOD:ringSkipMoveLit{sch}
+.SUBCKT ringSkipMoveLit clS[F] clS[T] cl[F] cl[T] do[epi] fire[L] fire[M] 
++inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inE[10] inE[11] inE[12] inE[13] 
++inE[14] inE[15] inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] 
++inE[22] inE[23] inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] 
++inE[30] inE[31] inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] 
++inE[6] inE[7] inE[8] inE[9] in[C] loadC[T] mc od[10] od[11] od[12] od[13] 
++od[14] od[15] od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] 
++od[24] od[25] od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] 
++od[34] od[35] od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] pred[D] 
++pred[T] rd[F] rd[T] sin sout succ[D] succ[T] torp
+XbitAssig@0 bitAssignments
+Xinv@0 net@395 olcZ inv-X_20
+XmoveLit@0 clS[F] clS[T] cl[F] cl[T] do[L] do[M] fire[L] fire[M] fire[T] 
++net@332 mc odx[15] odx[16] odx[18] odx[19] odx[20] pred[D] pred[T] rd[F] 
++rd[T] net@372 sout succ[D] succ[T] torp moveLit
+XringFIFO@0 clS[F] clS[T] cl[F] cl[T] net@304 net@295 do[epi] fire[ODE] 
++fire[m1] fire[m2] ringFIFO@0_freqOut inE[10] inE[11] inE[12] inE[13] inE[14] 
++inE[15] inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] 
++inE[23] inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] 
++inE[31] inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] 
++inE[7] inE[8] inE[9] mc od[10] od[11] od[12] od[13] od[14] od[15] od[16] 
++od[17] od[18] od[19] od[1] od[20] od[2] od[3] od[4] od[5] od[6] od[7] od[8] 
++od[9] olcZ m1s[1] m1s[20] m1s[22] m1s[23] m1s[24] m1s[25] m1s[26] m1s[27] 
++m1s[2] m1s[3] m1s[4] m1s[5] m1s[6] m1s[8] pout[10] pout[11] pout[12] pout[13] 
++pout[14] pout[15] pout[16] pout[17] pout[18] pout[1] pout[2] pout[3] pout[4] 
++pout[5] pout[6] pout[7] pout[8] pout[9] rd[F] rd[T] sin net@377 ringFIFO
+XskipCoun@0 clS[F] clS[T] cl[F] cl[T] net@304 net@295 fire[ODE] fire[m1] 
++fire[m2] fire[M] ilc[done] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] m1d[1] 
++m1d[2] m1d[3] m1d[4] m1d[5] m1d[6] m1d[8] pout[10] pout[11] pout[12] pout[13] 
++pout[14] pout[15] pout[16] pout[17] pout[18] pout[1] pout[2] pout[3] pout[4] 
++pout[5] pout[6] pout[7] pout[8] pout[9] in[C] kill loadC[T] mc net@395 rd[F] 
++rd[T] m1d[24] m1d[26] m1d[25] m1d[22] m1d[27] m1d[23] m1d[20] net@378 net@376 
++skipCount
+Xwire90@0 wire90@0_a pout[1] wire90-2416_4-layer_1-width_4
+Xwire90@1 wire90@1_a pout[2] wire90-2384_4-layer_1-width_4
+Xwire90@2 wire90@2_a pout[3] wire90-2330_4-layer_1-width_4
+Xwire90@3 wire90@3_a pout[4] wire90-2135_9-layer_1-width_4
+Xwire90@4 wire90@4_a pout[5] wire90-1987_4-layer_1-width_4
+Xwire90@5 wire90@5_a pout[6] wire90-1996_4-layer_1-width_4
+Xwire90@6 wire90@6_a pout[7] wire90-1636_3-layer_1-width_4
+Xwire90@7 wire90@7_a pout[8] wire90-1776_4-layer_1-width_4
+Xwire90@8 wire90@8_a pout[9] wire90-1870_9-layer_1-width_4
+Xwire90@9 wire90@9_a pout[10] wire90-1565_5-layer_1-width_4
+Xwire90@10 wire90@10_a pout[11] wire90-1506-layer_1-width_4
+Xwire90@11 wire90@11_a pout[12] wire90-1605_5-layer_1-width_4
+Xwire90@12 wire90@12_a pout[13] wire90-1227_3-layer_1-width_4
+Xwire90@13 wire90@13_a pout[14] wire90-1254_9-layer_1-width_4
+Xwire90@14 wire90@14_a pout[15] wire90-1280_2-layer_1-width_4
+Xwire90@15 wire90@15_a pout[16] wire90-1012_7-layer_1-width_4
+Xwire90@16 wire90@16_a pout[17] wire90-960_9-layer_1-width_4
+Xwire90@17 wire90@17_a pout[18] wire90-904_3-layer_1-width_4
+Xwire90@18 m1s[1] m1d[1] wire90-4579_4-layer_1-width_4
+Xwire90@19 m1s[2] m1d[2] wire90-4580_9-layer_1-width_4
+Xwire90@20 m1s[3] m1d[3] wire90-4864_4-layer_1-width_4
+Xwire90@21 m1s[4] m1d[4] wire90-4970_4-layer_1-width_4
+Xwire90@22 m1s[5] m1d[5] wire90-5067_4-layer_1-width_4
+Xwire90@23 m1s[6] m1d[6] wire90-5238_9-layer_1-width_4
+Xwire90@25 m1s[8] m1d[8] wire90-5485_4-layer_1-width_4
+Xwire90@37 m1s[20] m1d[20] wire90-3582_8-layer_1-width_4
+Xwire90@39 m1s[22] m1d[22] wire90-4216_8-layer_1-width_4
+Xwire90@40 m1s[23] m1d[23] wire90-4217_8-layer_1-width_4
+Xwire90@41 m1s[24] m1d[24] wire90-4580_7-layer_1-width_4
+Xwire90@42 m1s[25] m1d[25] wire90-4914_8-layer_1-width_4
+Xwire90@43 m1s[26] m1d[26] wire90-5109_1-layer_1-width_4
+Xwire90@44 m1s[27] m1d[27] wire90-4659_8-layer_1-width_4
+Xwire90@56 wire90@56_a fire[m2] wire90-3105_9-layer_1-width_4
+Xwire90@57 wire90@57_a fire[m1] wire90-2229_2-layer_1-width_4
+Xwire90@58 wire90@58_a fire[ODE] wire90-4552_2-layer_1-width_4
+Xwire90@59 net@304 do[L] wire90-4224_4-layer_1-width_4
+Xwire90@60 net@295 do[M] wire90-4964_8-layer_1-width_4
+Xwire90@61 od[15] odx[15] wire90-2102_8-layer_1-width_4
+Xwire90@62 od[16] odx[16] wire90-2117_2-layer_1-width_4
+Xwire90@63 od[17] odx[17] wire90-840_4-layer_1-width_4
+Xwire90@64 od[18] odx[18] wire90-2017_6-layer_1-width_4
+Xwire90@65 od[19] odx[19] wire90-2584_1-layer_1-width_4
+Xwire90@66 od[20] odx[20] wire90-2385_3-layer_1-width_4
+Xwire90@67 ilc[done] net@332 wire90-1928_3-layer_1-width_4
+Xwire90@68 net@377 net@378 wire90-2790_5-layer_1-width_4
+Xwire90@69 net@376 net@372 wire90-2752_3-layer_1-width_4
+Xwire90@70 kill fire[T] wire90-2416_4-layer_1-width_4
+.ENDS ringSkipMoveLit
+
+*** CELL: scanJ:scanCap{sch}
+.SUBCKT scanCap si[1] si[2] si[3] si[4] si[5] si[9]
+.ENDS scanCap
+
+*** CELL: scanConverter{sch}
+.SUBCKT scanConverter clS[F] clS[T] cl[F] cl[T] mc oldScan[2] oldScan[3] 
++oldScan[4] oldScan[5] oldScan[6] oldScan[7] oldScan[8] oldScan[9] rd[F] rd[T]
+Xinv@0 oldScan[2] cl[F] inv-X_5
+Xinv@1 cl[F] cl[T] inv-X_5
+Xinv@2 oldScan[3] clS[F] inv-X_5
+Xinv@3 clS[F] clS[T] inv-X_5
+Xinv@4 oldScan[5] rd[F] inv-X_5
+Xinv@5 rd[F] rd[T] inv-X_5
+Xinv@6 oldScan[9] net@3 inv-X_5
+Xinv@7 net@3 mc inv-X_5
+.ENDS scanConverter
+
+.global gnd vdd
+
+*** TOP LEVEL CELL: marina{sch}
+XdRegAll@0 fireL fireM dIn[11] dIn[12] dIn[13] dIn[14] dIn[15] dIn[16] 
++dIn[17] dIn[18] dIn[19] dIn[20] dIn[2] dIn[21] dIn[22] dIn[23] dIn[24] 
++dIn[25] dIn[26] dIn[27] dIn[28] dIn[29] dIn[30] dIn[3] dIn[31] dIn[32] 
++dIn[33] dIn[34] dIn[35] dIn[36] dIn[37] dIn[T] dIn[4] dIn[5] dIn[6] dIn[7] 
++dIn[8] dIn[9] dIn[10] dIn[1] od[10] od[11] od[12] od[13] od[14] od[15] od[16] 
++od[17] od[18] od[19] od[1] od[2] od[3] od[4] od[5] od[6] od[7] od[8] od[9] 
++gnd dOut[10] dOut[11] dOut[12] dOut[13] dOut[14] dOut[15] dOut[16] dOut[17] 
++dOut[18] dOut[19] dOut[1] dOut[20] dOut[21] dOut[22] dOut[23] dOut[24] 
++dOut[25] dOut[26] dOut[27] dOut[28] dOut[29] dOut[2] dOut[30] dOut[31] 
++dOut[32] dOut[33] dOut[34] dOut[35] dOut[36] dOut[37] dOut[3] dOut[4] dOut[5] 
++dOut[6] dOut[7] dOut[8] dOut[9] dOut[T] od[20] dRegAll
+Xdata dOut[47] dOut[48] dOut[49] dOut[50] dOut[51] dOut[38] dOut[39] dOut[40] 
++dOut[41] dOut[42] dOut[43] dOut[44] dOut[45] dOut[46] dOut[T] dIn[47] dIn[48] 
++dIn[49] dIn[50] dIn[51] dIn[38] dIn[39] dIn[40] dIn[41] dIn[42] dIn[43] 
++dIn[44] dIn[45] dIn[46] dIn[T] data_fin data_fout dOut[10] dOut[11] dOut[12] 
++dOut[13] dOut[14] dOut[15] dOut[16] dOut[17] dOut[18] dOut[19] dOut[1] 
++dOut[20] dOut[21] dOut[22] dOut[23] dOut[24] dOut[25] dOut[26] dOut[27] 
++dOut[28] dOut[29] dOut[2] dOut[30] dOut[31] dOut[32] dOut[33] dOut[34] 
++dOut[35] dOut[36] dOut[37] dOut[3] dOut[4] dOut[5] dOut[6] dOut[7] dOut[8] 
++dOut[9] dIn[10] dIn[11] dIn[12] dIn[13] dIn[14] dIn[15] dIn[16] dIn[17] 
++dIn[18] dIn[19] dIn[1] dIn[20] dIn[21] dIn[22] dIn[23] dIn[24] dIn[25] 
++dIn[26] dIn[27] dIn[28] dIn[29] dIn[2] dIn[30] dIn[31] dIn[32] dIn[33] 
++dIn[34] dIn[35] dIn[36] dIn[37] dIn[3] dIn[4] dIn[5] dIn[6] dIn[7] dIn[8] 
++dIn[9] dOutS scanC3[1] scanInC[2] scanInC[3] scanInC[4] scanInC[5] scanInC[3] 
++scanInC[2] scanInC[8] scanInC[9] scanD3[1] scanD3[2] scanD3[3] scanD3[4] 
++scanD3[5] scanInD[6] scanInD[7] scanInD[8] scanInD[9] scanR3[1] scanInR[2] 
++scanInR[3] scanInR[4] scanInR[5] scanInR[3] scanInR[2] scanR1[8] scanInR[9] 
++scanInC[8] scanInD[8] scanInD[7] scanInD[6] net@56[5] net@56[4] net@58[8] 
++net@58[8] dInS northFifo
+XepiFifo@0 net@29[3] net@29[4] net@29[5] net@29[6] epi[10] epi[11] epi[12] 
++epi[13] epi[14] epi[15] epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] 
++epi[21] epi[22] epi[23] epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] 
++epi[2] epi[30] epi[31] epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] 
++epi[5] epi[6] epi[7] epi[8] epi[9] epi[T] net@29[0] instr[10] instr[11] 
++instr[12] instr[13] instr[14] instr[15] instr[16] instr[17] instr[18] 
++instr[19] instr[1] instr[20] instr[21] instr[22] instr[23] instr[24] 
++instr[25] instr[26] instr[27] instr[28] instr[29] instr[2] instr[30] 
++instr[31] instr[32] instr[33] instr[34] instr[35] instr[36] instr[3] instr[4] 
++instr[5] instr[6] instr[7] instr[8] instr[9] epiS net@29[1] net@29[2] 
++scanR1[1] net@0 instrS torpS epiFifo
+XinstrIn epi[47] epi[48] epi[49] epi[50] epi[51] epi[38] epi[39] epi[40] 
++epi[41] epi[42] epi[43] epi[44] epi[45] epi[46] epi[T] instrIn_cin 
++instrIn_fin instrIn_fout epi[10] epi[11] epi[12] epi[13] epi[14] epi[15] 
++epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] epi[21] epi[22] epi[23] 
++epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30] epi[31] 
++epi[32] epi[33] epi[34] epi[35] epi[36] epi[37] epi[3] epi[4] epi[5] epi[6] 
++epi[7] epi[8] epi[9] scanInC[1] scanInC[2] scanInC[3] scanInC[4] scanInC[5] 
++scanInC[3] scanInC[2] scanInC[8] scanInC[9] scanInD[1] scanInD[2] scanInD[3] 
++scanInD[4] scanInD[5] scanInD[6] scanInD[7] scanInD[8] scanInD[9] scanInR[1] 
++scanInR[2] scanInR[3] scanInR[4] scanInR[5] scanInR[3] scanInR[2] scanInR[8] 
++scanInR[9] scanC1[1] scanD1[1] scanD1[2] scanD1[3] scanD1[4] scanD1[5] 
++scanR1[1] scanR1[8] epiS southFifo
+XringSkip@0 net@29[3] net@29[4] net@29[5] net@29[6] instrS net@2 net@23 gnd 
++gnd gnd gnd gnd gnd instr[10] instr[11] instr[12] instr[13] instr[14] 
++instr[15] instr[16] instr[17] instr[18] instr[19] instr[1] instr[20] 
++instr[21] instr[22] instr[23] instr[24] instr[25] instr[26] instr[27] 
++instr[28] instr[29] instr[2] instr[30] instr[31] instr[32] instr[33] 
++instr[34] instr[35] instr[36] instr[3] instr[4] instr[5] instr[6] instr[7] 
++instr[8] instr[9] dIn[38] fireM net@29[0] od[10] od[11] od[12] od[13] od[14] 
++od[15] od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] 
++od[25] od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] 
++od[35] od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] dInS tInS net@29[1] 
++net@29[2] net@12 scanR2[1] dOutS tOutS torpS ringSkipMoveLit
+XscanCap@0 scanInD[8] scanInD[7] scanInD[6] net@56[5] net@56[4] scanInD[9] 
++scanCap
+XscanCap@1 scanInC[8] scanInC[2] scanInC[3] scanInC[4] scanInC[5] scanInC[9] 
++scanCap
+XscanCap@2 net@58[8] scanInR[2] scanInR[3] scanInR[4] scanInR[5] scanInR[9] 
++scanCap
+XscanConv@0 net@29[3] net@29[4] net@29[5] net@29[6] net@29[0] scanInR[2] 
++scanInR[3] scanInR[4] scanInR[5] scanInR[3] scanInR[2] scanR1[8] scanInR[9] 
++net@29[1] net@29[2] scanConverter
+XtokOut gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd net@61[4] 
++net@61[3] net@61[2] net@61[1] net@61[0] net@61[13] net@61[12] net@61[11] 
++net@61[10] net@61[9] net@61[8] net@61[7] net@61[6] net@61[5] net@61[14] 
++net@62 tokOut_fire gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 
++gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 
++gnd gnd gnd gnd net@61[42] net@61[41] net@61[40] net@61[39] net@61[38] 
++net@61[37] net@61[36] net@61[35] net@61[34] net@61[33] net@61[51] net@61[32] 
++net@61[31] net@61[30] net@61[29] net@61[28] net@61[27] net@61[26] net@61[25] 
++net@61[24] net@61[23] net@61[50] net@61[22] net@61[21] net@61[20] net@61[19] 
++net@61[18] net@61[17] net@61[16] net@61[15] net@61[49] net@61[48] net@61[47] 
++net@61[46] net@61[45] net@61[44] net@61[43] tOutS scanC1[1] scanInC[2] 
++scanInC[3] scanInC[4] scanInC[5] scanInC[3] scanInC[2] scanInC[8] scanInC[9] 
++scanD1[1] scanD1[2] scanD1[3] scanD1[4] scanD1[5] scanInD[6] scanInD[7] 
++scanInD[8] scanInD[9] scanR2[1] scanInR[2] scanInR[3] scanInR[4] scanInR[5] 
++scanInR[3] scanInR[2] scanR1[8] scanInR[9] scanC3[1] scanD3[1] scanD3[2] 
++scanD3[3] scanD3[4] scanD3[5] scanR3[1] net@63 properStopper
+Xwire90@0 net@0 net@12 wire90-2229_2-layer_1-width_4
+Xwire90@1 net@23 fireM wire90-2229_2-layer_1-width_4
+Xwire90@2 net@2 fireL wire90-2229_2-layer_1-width_4
+.END

diff --git a/testCode/marina.xml b/testCode/marina.xml
index 3661097..1242d8c 100644 (file)
--- a/testCode/marina.xml
+++ b/testCode/marina.xml
@@ -8,159 +8,475 @@
 
 
 <!DOCTYPE ChainG SYSTEM "file:ChainG.dtd" [
-<!ENTITY marina_jtag_dockTest_control_dataNets '
-  <datanet name="ps1.aFillSta@0.gaspPlai@0.scanFx2v@0.scanCell@2" net="xps1.xaFillSta@0.xgaspPlai@0.block(R)" net2="xps1.xaFillSta@0.xgaspPlai@0.xscanFx2v@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
-  <datanet name="ps1.aFillSta@0.gaspPlai@0.scanFx2v@0.scanCell@1" net="xps1.xaFillSta@0.xgaspPlai@0.fill(R)" net2="xps1.xaFillSta@0.xgaspPlai@0.xscanFx2v@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
-  <datanet name="ps1.aDrainSt@0.gaspPlai@0.scanFx3h@0.scanCell@2" net="xps1.xaDrainSt@0.xgaspPlai@0.go(R)" net2="xps1.xaDrainSt@0.xgaspPlai@0.xscanFx3h@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
-  <datanet name="ps1.aDrainSt@0.gaspPlai@0.scanFx3h@0.scanCell@1" net="xps1.xaDrainSt@0.xgaspPlai@0.silent(R)" net2="xps1.xaDrainSt@0.xgaspPlai@0.xscanFx3h@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
-  <datanet name="ps1.aDrainSt@0.gaspPlai@0.scanFx3h@0.scanCell@3" net="xps1.xaDrainSt@0.xgaspPlai@0.clear(R)" net2="xps1.xaDrainSt@0.xgaspPlai@0.xscanFx3h@0.xscanCell@3.xlatch2in@1.dataBar(WI)" />
-  <datanet name="ps2.aFillSta@0.gaspPlai@0.scanFx2v@0.scanCell@2" net="xps2.xaFillSta@0.xgaspPlai@0.block(R)" net2="xps2.xaFillSta@0.xgaspPlai@0.xscanFx2v@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
-  <datanet name="ps2.aFillSta@0.gaspPlai@0.scanFx2v@0.scanCell@1" net="xps2.xaFillSta@0.xgaspPlai@0.fill(R)" net2="xps2.xaFillSta@0.xgaspPlai@0.xscanFx2v@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
-  <datanet name="ps2.aDrainSt@0.gaspPlai@0.scanFx3h@0.scanCell@2" net="xps2.xaDrainSt@0.xgaspPlai@0.go(R)" net2="xps2.xaDrainSt@0.xgaspPlai@0.xscanFx3h@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
-  <datanet name="ps2.aDrainSt@0.gaspPlai@0.scanFx3h@0.scanCell@1" net="xps2.xaDrainSt@0.xgaspPlai@0.silent(R)" net2="xps2.xaDrainSt@0.xgaspPlai@0.xscanFx3h@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
-  <datanet name="ps2.aDrainSt@0.gaspPlai@0.scanFx3h@0.scanCell@3" net="xps2.xaDrainSt@0.xgaspPlai@0.clear(R)" net2="xps2.xaDrainSt@0.xgaspPlai@0.xscanFx3h@0.xscanCell@3.xlatch2in@1.dataBar(WI)" />
-'>
-<!ENTITY marina_jtag_dockTest_data_dataNets '
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.scanCell@0" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.scanCell@0_dIn[1](R)" net2="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xscanCell@0.xlatch2in@0.dataBar(WI)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.scanCell@1" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.scanCell@1_dIn[1](R)" net2="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xscanCell@1.xlatch2in@0.dataBar(WI)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[1]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[1].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[51](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[2]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[2].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[50](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[3]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[3].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[49](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[4]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[4].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[48](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[5]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[5].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[47](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[6]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[6].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[46](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[7]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[7].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[45](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[8]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[8].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[44](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[9]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[9].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[43](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[10]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[10].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[42](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[11]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[11].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[41](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[12]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[12].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[40](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[13]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[13].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[39](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[14]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[14].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[38](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[15]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[15].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[37](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[16]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[16].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[36](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[17]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[17].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[35](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[18]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[18].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[34](R)" />
-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[19]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[19].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[33](R)" />
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-  <datanet name="ps1.aFillSta@0.all1in52@1.data1in3@0.ls[21]" net="xps1.xaFillSta@0.xall1in52@1.xdata1in3@0.xls[21].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps1.net@1[31](R)" />
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-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[5]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[5].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[9](R)" />
-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[6]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[6].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[8](R)" />
-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[7]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[7].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[7](R)" />
-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[8]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[8].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[6](R)" />
-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[9]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[9].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[5](R)" />
-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[10]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[10].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[4](R)" />
-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[11]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[11].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[3](R)" />
-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[12]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[12].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[2](R)" />
-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[13]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[13].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[1](R)" />
-  <datanet name="ps2.aFillSta@0.all1in52@1.addr1in1@0.ls[14]" net="xps2.xaFillSta@0.xall1in52@1.xaddr1in1@0.xls[14].xscanCell@2.xlatch2in@0.dataBar(WI)" net2="xps2.net@1[0](R)" />
-'>
-<!ENTITY marina_jtag_dockTest_report_dataNets '
-  <datanet name="ps1.aFillSta@0.gaspPlai@0.scanEx2v@2.scanCell@1" net="net@19(R)" net2="xps1.xaFillSta@0.xgaspPlai@0.xscanEx2v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
-  <datanet name="ps1.aFillSta@0.gaspPlai@0.scanEx2v@2.scanCell@2" net="xps1.xaFillSta@0.xgaspPlai@0.fill(R)" net2="xps1.xaFillSta@0.xgaspPlai@0.xscanEx2v@2.xscanCell@2.xlatch2in@0.dataBar(WI)" />
-  <datanet name="ps1.aDrainSt@0.gaspPlai@0.scanEx2v@1.scanCell@1" net="xps1.net@13(R)" net2="xps1.xaDrainSt@0.xgaspPlai@0.xscanEx2v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
-  <datanet name="ps1.aDrainSt@0.gaspPlai@0.scanEx2v@1.scanCell@2" net="xps1.xaDrainSt@0.xgaspPlai@0.stopped(R)" net2="xps1.xaDrainSt@0.xgaspPlai@0.xscanEx2v@1.xscanCell@2.xlatch2in@0.dataBar(WI)" />
-  <datanet name="plainSta@0.stg[1].gaspPlai@0.scanEx1v@0.scanCell@1" net="net@17(R)" net2="xplainSta@0.xstg[1].xgaspPlai@0.xscanEx1v@0.xscanCell@1.xlatch2in@0.dataBar(WI)" />
-  <datanet name="plainSta@0.stg[2].gaspPlai@0.scanEx1v@0.scanCell@1" net="xplainSta@0.net@55(R)" net2="xplainSta@0.xstg[2].xgaspPlai@0.xscanEx1v@0.xscanCell@1.xlatch2in@0.dataBar(WI)" />
-  <datanet name="plainSta@0.stg[3].gaspPlai@0.scanEx1v@0.scanCell@1" net="xplainSta@0.net@56(R)" net2="xplainSta@0.xstg[3].xgaspPlai@0.xscanEx1v@0.xscanCell@1.xlatch2in@0.dataBar(WI)" />
-  <datanet name="plainSta@0.stg[4].gaspPlai@0.scanEx1v@0.scanCell@1" net="xplainSta@0.net@57(R)" net2="xplainSta@0.xstg[4].xgaspPlai@0.xscanEx1v@0.xscanCell@1.xlatch2in@0.dataBar(WI)" />
-  <datanet name="ps2.aFillSta@0.gaspPlai@0.scanEx2v@2.scanCell@1" net="net@18(R)" net2="xps2.xaFillSta@0.xgaspPlai@0.xscanEx2v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
-  <datanet name="ps2.aFillSta@0.gaspPlai@0.scanEx2v@2.scanCell@2" net="xps2.xaFillSta@0.xgaspPlai@0.fill(R)" net2="xps2.xaFillSta@0.xgaspPlai@0.xscanEx2v@2.xscanCell@2.xlatch2in@0.dataBar(WI)" />
-  <datanet name="ps2.aDrainSt@0.gaspPlai@0.scanEx2v@1.scanCell@1" net="xps2.net@13(R)" net2="xps2.xaDrainSt@0.xgaspPlai@0.xscanEx2v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
-  <datanet name="ps2.aDrainSt@0.gaspPlai@0.scanEx2v@1.scanCell@2" net="xps2.xaDrainSt@0.xgaspPlai@0.stopped(R)" net2="xps2.xaDrainSt@0.xgaspPlai@0.xscanEx2v@1.xscanCell@2.xlatch2in@0.dataBar(WI)" />
-'>
-<!ENTITY gaspJ_gaspDrain_sic_1_ '
+<!ENTITY marina_marina_control_dataNets '
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.gaspFill@0.scanFx2v@0.scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xgaspFill@0.block(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xgaspFill@0.xscanFx2v@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.gaspFill@0.scanFx2v@0.scanCell@1" net="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xgaspFill@0.fill(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xgaspFill@0.xscanFx2v@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.drainSta@0.gaspDrai@0.scanFx3h@0.scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.go(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanFx3h@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.drainSta@0.gaspDrai@0.scanFx3h@0.scanCell@1" net="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.silent(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanFx3h@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.drainSta@0.gaspDrai@0.scanFx3h@0.scanCell@3" net="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.clear(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanFx3h@0.xscanCell@3.xlatch2in@1.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.drainSta@0.gaspDrai@0.scanFx1v@0.scanCell@2" net="xinstrIn.xtapPropS@0.net@90(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanFx1v@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.tapStage@1.gaspSwit@0.scanFx1v@0.scanCell@2" net="xinstrIn.xtapPropS@0.xtapStage@1.xgaspSwit@0.net@405(R)" net2="xinstrIn.xtapPropS@0.xtapStage@1.xgaspSwit@0.xscanFx1v@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+  <datanet name="tokOut.fillStag@0.gaspFill@0.scanFx2v@0.scanCell@2" net="xtokOut.xfillStag@0.xgaspFill@0.block(R)" net2="xtokOut.xfillStag@0.xgaspFill@0.xscanFx2v@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+  <datanet name="tokOut.fillStag@0.gaspFill@0.scanFx2v@0.scanCell@1" net="xtokOut.xfillStag@0.xgaspFill@0.fill(R)" net2="xtokOut.xfillStag@0.xgaspFill@0.xscanFx2v@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
+  <datanet name="tokOut.drainSta@0.gaspDrai@0.scanFx3h@0.scanCell@2" net="xtokOut.xdrainSta@0.xgaspDrai@0.go(R)" net2="xtokOut.xdrainSta@0.xgaspDrai@0.xscanFx3h@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+  <datanet name="tokOut.drainSta@0.gaspDrai@0.scanFx3h@0.scanCell@1" net="xtokOut.xdrainSta@0.xgaspDrai@0.silent(R)" net2="xtokOut.xdrainSta@0.xgaspDrai@0.xscanFx3h@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
+  <datanet name="tokOut.drainSta@0.gaspDrai@0.scanFx3h@0.scanCell@3" net="xtokOut.xdrainSta@0.xgaspDrai@0.clear(R)" net2="xtokOut.xdrainSta@0.xgaspDrai@0.xscanFx3h@0.xscanCell@3.xlatch2in@1.dataBar(WI)" />
+  <datanet name="tokOut.drainSta@0.gaspDrai@0.scanFx1v@0.scanCell@2" net="net@62(R)" net2="xtokOut.xdrainSta@0.xgaspDrai@0.xscanFx1v@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.fillStag@0.gaspFill@0.scanFx2v@0.scanCell@2" net="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xgaspFill@0.block(R)" net2="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xgaspFill@0.xscanFx2v@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.fillStag@0.gaspFill@0.scanFx2v@0.scanCell@1" net="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xgaspFill@0.fill(R)" net2="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xgaspFill@0.xscanFx2v@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.drainSta@0.gaspDrai@0.scanFx3h@0.scanCell@2" net="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.go(R)" net2="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanFx3h@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.drainSta@0.gaspDrai@0.scanFx3h@0.scanCell@1" net="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.silent(R)" net2="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanFx3h@0.xscanCell@1.xlatch2in@1.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.drainSta@0.gaspDrai@0.scanFx3h@0.scanCell@3" net="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.clear(R)" net2="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanFx3h@0.xscanCell@3.xlatch2in@1.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.drainSta@0.gaspDrai@0.scanFx1v@0.scanCell@2" net="xdata.xfillDrai@0.net@48(R)" net2="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanFx1v@0.xscanCell@2.xlatch2in@1.dataBar(WI)" />
+'>
+<!ENTITY marina_marina_data_dataNets '
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.scanCell@0" net="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.scanCell@0_dIn[1](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xscanCell@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.scanCell@1" net="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.scanCell@1_dIn[1](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[1].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[51](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[1].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[2].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[50](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[2].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[3].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[49](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[3].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[4].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[48](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[4].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[5].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[47](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[5].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[6].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[46](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[6].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[7].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[45](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[7].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[8].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[44](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[8].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[9].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[43](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[9].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[10].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[42](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[10].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[11].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[41](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[11].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[12].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[40](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[12].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[13].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[39](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[13].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[14].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[38](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[14].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[15].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[37](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[15].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[16].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[36](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[16].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[17].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[35](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[17].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[18].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[34](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[18].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[19].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[33](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[19].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[20].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[32](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[20].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[21].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[31](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[21].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[22].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[30](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[22].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[23].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[29](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[23].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[24].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[28](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[24].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[25].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[27](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[25].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[26].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[26](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[26].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[27].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[25](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[27].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[28].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[24](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[28].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[29].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[23](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[29].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[30].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[22](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[30].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[31].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[21](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[31].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[32].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[20](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[32].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[33].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[19](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[33].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[34].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[18](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[34].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[35].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[17](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[35].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[36].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[16](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[36].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.ls[37].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[15](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xls[37].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.data1in3@0.latchWsc@1.scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[14](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xdata1in3@0.xlatchWsc@1.xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[1].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[13](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[1].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[2].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[12](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[2].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[3].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[11](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[3].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[4].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[10](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[4].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[5].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[9](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[5].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[6].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[8](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[6].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[7].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[7](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[7].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[8].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[6](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[8].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[9].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[5](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[9].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[10].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[4](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[10].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[11].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[3](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[11].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[12].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[2](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[12].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[13].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[1](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[13].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[14].scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.net@1[0](R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[14].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnOn@2" net="xinstrIn.xtapPropS@0.xinstruct@0.net@1(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@1.cntScnOn@1" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.net@43(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@1.cntScnOn@2" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.net@46(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@1.cntScnOn@0" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.net@40(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@1.cntScnOn@3" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.net@43(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@2.cntScnOn@1" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.net@43(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@2.cntScnOn@2" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.net@46(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@2.cntScnOn@0" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.net@40(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@2.cntScnOn@3" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.net@46(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@0.cntScnOn@1" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.net@43(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@0.cntScnOn@2" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.net@46(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@0.cntScnOn@0" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.net@40(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@3.cntScnFo@0.cntScnOn@3" net="xinstrIn.xtapPropS@0.xinstruct@0.net@3(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@4.cntScnFo@1.cntScnOn@1" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.net@43(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@4.cntScnFo@1.cntScnOn@2" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.net@46(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@4.cntScnFo@1.cntScnOn@0" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.net@40(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@4.cntScnFo@1.cntScnOn@3" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.net@43(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@4.cntScnFo@2.cntScnOn@1" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.net@43(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@4.cntScnFo@2.cntScnOn@2" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.net@46(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.instruct@0.cntScnTw@4.cntScnFo@2.cntScnOn@0" net="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.net@40(R)" net2="xinstrIn.xtapPropS@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
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+  <datanet name="tokOut.fillStag@0.all1in52@1.data1in3@0.ls[20].scanCell@2" net="xtokOut.net@1[32](R)" net2="xtokOut.xfillStag@0.xall1in52@1.xdata1in3@0.xls[20].xscanCell@2.xlatch2in@0.dataBar(WI)" />
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+  <datanet name="tokOut.fillStag@0.all1in52@1.data1in3@0.ls[27].scanCell@2" net="xtokOut.net@1[25](R)" net2="xtokOut.xfillStag@0.xall1in52@1.xdata1in3@0.xls[27].xscanCell@2.xlatch2in@0.dataBar(WI)" />
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+  <datanet name="data.fillDrai@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[11].scanCell@2" net="xdata.xfillDrai@0.xproperSt@0.net@1[3](R)" net2="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[11].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[12].scanCell@2" net="xdata.xfillDrai@0.xproperSt@0.net@1[2](R)" net2="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[12].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[13].scanCell@2" net="xdata.xfillDrai@0.xproperSt@0.net@1[1](R)" net2="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[13].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.fillStag@0.all1in52@1.addr1in1@0.ls[14].scanCell@2" net="xdata.xfillDrai@0.xproperSt@0.net@1[0](R)" net2="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xall1in52@1.xaddr1in1@0.xls[14].xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.net@1(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@1.cntScnOn@1" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@1.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@1.cntScnOn@0" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.net@40(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@1.cntScnOn@3" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@1.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@2.cntScnOn@1" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@2.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@2.cntScnOn@0" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.net@40(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@2.cntScnOn@3" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@2.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@0.cntScnOn@1" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@0.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@0.cntScnOn@0" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.net@40(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@3.cntScnFo@0.cntScnOn@3" net="xdata.xfillDrai@0.xinstruct@0.net@3(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@3.xcntScnFo@0.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@1.cntScnOn@1" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@1.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@1.cntScnOn@0" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.net@40(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@1.cntScnOn@3" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@1.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@2.cntScnOn@1" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@2.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@2.cntScnOn@0" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.net@40(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@2.cntScnOn@3" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@2.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@0.cntScnOn@1" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@0.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@0.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@0.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@0.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@0.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@0.cntScnOn@0" net="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@0.net@40(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@0.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnTw@4.cntScnFo@0.cntScnOn@3" net="xdata.xfillDrai@0.xinstruct@0.net@42(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnTw@4.xcntScnFo@0.xcntScnOn@3.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnNi@2.cntScnTh@1.cntScnOn@1" net="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@1.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@1.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnNi@2.cntScnTh@1.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@1.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@1.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnNi@2.cntScnTh@1.cntScnOn@0" net="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@1.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnNi@2.cntScnTh@2.cntScnOn@1" net="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@2.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@2.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnNi@2.cntScnTh@2.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@2.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@2.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnNi@2.cntScnTh@2.cntScnOn@0" net="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@2.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnNi@2.cntScnTh@0.cntScnOn@1" net="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@0.net@43(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@0.xcntScnOn@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnNi@2.cntScnTh@0.cntScnOn@2" net="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@0.net@46(R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@0.xcntScnOn@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.instruct@0.cntScnNi@2.cntScnTh@0.cntScnOn@0" net="scanInD[8](R)" net2="xdata.xfillDrai@0.xinstruct@0.xcntScnNi@2.xcntScnTh@0.xcntScnOn@0.xlatch2in@0.dataBar(WI)" />
+'>
+<!ENTITY marina_marina_report_dataNets '
+  <datanet name="instrIn.upDown8w@0.weakStag@10.gaspPlai@1.scanEx1v@2.scanCell@1" net="xinstrIn.net@58(R)" net2="xinstrIn.xupDown8w@0.xweakStag@10.xgaspPlai@1.xscanEx1v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.upDown8w@0.weakStag@11.gaspPlai@1.scanEx1v@2.scanCell@1" net="xinstrIn.xupDown8w@0.net@28(R)" net2="xinstrIn.xupDown8w@0.xweakStag@11.xgaspPlai@1.xscanEx1v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.upDown8w@0.weakStag@12.gaspPlai@1.scanEx1v@2.scanCell@1" net="xinstrIn.xupDown8w@0.net@62(R)" net2="xinstrIn.xupDown8w@0.xweakStag@12.xgaspPlai@1.xscanEx1v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.upDown8w@0.weakStag@13.gaspPlai@1.scanEx1v@2.scanCell@1" net="xinstrIn.xupDown8w@0.net@64(R)" net2="xinstrIn.xupDown8w@0.xweakStag@13.xgaspPlai@1.xscanEx1v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.gaspFill@0.scanEx2v@2.scanCell@1" net="xinstrIn.net@61(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xgaspFill@0.xscanEx2v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.fillStag@0.gaspFill@0.scanEx2v@2.scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xgaspFill@0.fill(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xfillStag@0.xgaspFill@0.xscanEx2v@2.xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.drainSta@0.gaspDrai@0.scanEx2v@1.scanCell@1" net="xinstrIn.xtapPropS@0.xproperSt@0.net@41(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanEx2v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.properSt@0.drainSta@0.gaspDrai@0.scanEx2v@1.scanCell@2" net="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.stopped(R)" net2="xinstrIn.xtapPropS@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanEx2v@1.xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.tapPropS@0.tapStage@1.gaspSwit@0.scanEx1v@0.scanCell@1" net="xinstrIn.xtapPropS@0.net@85(R)" net2="xinstrIn.xtapPropS@0.xtapStage@1.xgaspSwit@0.xscanEx1v@0.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="epiFifo@0.epiFifoC@0.anEpiSta@0.scanKhx1@0.scanCell@1" net="xepiFifo@0.xepiFifoC@0.xanEpiSta@0.s[1](R)" />
+  <datanet name="epiFifo@0.epiFifoC@0.aStageS@0.scanKhx1@0.scanCell@1" net="xepiFifo@0.xepiFifoC@0.xaStageS@0.s[1](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.odRQstag@0.scanKhx5@0.scanCell@4" net="xringSkip@0.xringFIFO@0.xodRQstag@0.s[1](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.odRQstag@0.scanKhx5@0.scanCell@5" net="xringSkip@0.xringFIFO@0.xodRQstag@0.s[2](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.odRQstag@0.scanKhx5@0.scanCell@6" net="xringSkip@0.xringFIFO@0.xodRQstag@0.s[3](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.odRQstag@0.scanKhx5@0.scanCell@7" net="xringSkip@0.xringFIFO@0.xodRQstag@0.s[4](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.odRQstag@0.scanKhx5@0.scanCell@8" net="xringSkip@0.xringFIFO@0.xodRQstag@0.s[5](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@0.anAltSta@0.scanKhx2@0.scanCell@1" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@0.xanAltSta@0.s[1](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@0.anAltSta@0.scanKhx2@0.scanCell@2" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@0.xanAltSta@0.s[2](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@1.splitSta@4.scanKhx2@0.scanCell@1" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@1.xsplitSta@4.s[1](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@1.splitSta@4.scanKhx2@0.scanCell@2" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@1.xsplitSta@4.s[2](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@2.splitSta@4.scanKhx2@0.scanCell@1" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@2.xsplitSta@4.s[1](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@2.splitSta@4.scanKhx2@0.scanCell@2" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@2.xsplitSta@4.s[2](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@2.splitSta@5.scanKhx2@0.scanCell@1" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@2.xsplitSta@5.s[1](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@2.splitSta@5.scanKhx2@0.scanCell@2" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@2.xsplitSta@5.s[2](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@1.splitSta@5.scanKhx2@0.scanCell@1" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@1.xsplitSta@5.s[1](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitSta@1.splitSta@5.scanKhx2@0.scanCell@2" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitSta@1.xsplitSta@5.s[2](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitEnd@0.anAltEnd@1.scanKhx3@0.scanCell@4" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitEnd@0.xanAltEnd@1.ss[1](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitEnd@0.anAltEnd@1.scanKhx3@0.scanCell@5" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitEnd@0.xanAltEnd@1.ss[2](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.split10@0.splitEnd@0.anAltEnd@1.scanKhx3@0.scanCell@6" net="xringSkip@0.xringFIFO@0.xsplit10@0.xsplitEnd@0.xanAltEnd@1.ss[3](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.m12stage@0.m1stageD@1.scanKhx2@0.scanCell@1" net="xringSkip@0.xringFIFO@0.xm12stage@0.s[m2](R)" />
+  <datanet name="ringSkip@0.ringFIFO@0.m12stage@0.m1stageD@1.scanKhx2@0.scanCell@2" net="xringSkip@0.xringFIFO@0.xm12stage@0.xm1stageD@1.s[m1](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx7@0.scanCell@4" net="xringSkip@0.xskipCoun@0.net@129[6](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx7@0.scanCell@5" net="xringSkip@0.xskipCoun@0.net@129[5](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx7@0.scanCell@6" net="xringSkip@0.xskipCoun@0.net@129[4](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx7@0.scanCell@7" net="xringSkip@0.xskipCoun@0.net@129[3](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx7@0.scanCell@8" net="xringSkip@0.xskipCoun@0.net@129[2](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx7@0.scanCell@9" net="xringSkip@0.xskipCoun@0.net@129[1](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx7@0.scanCell@10" net="xringSkip@0.xskipCoun@0.net@129[0](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx6@0.scanCell@4" net="xringSkip@0.xskipCoun@0.net@130[5](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx6@0.scanCell@5" net="xringSkip@0.xskipCoun@0.net@130[4](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx6@0.scanCell@6" net="xringSkip@0.xskipCoun@0.net@130[3](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx6@0.scanCell@7" net="xringSkip@0.xskipCoun@0.net@130[2](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx6@0.scanCell@8" net="xringSkip@0.xskipCoun@0.net@130[1](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx6@0.scanCell@9" net="xringSkip@0.xskipCoun@0.net@130[0](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx3@0.scanCell@4" net="xringSkip@0.xskipCoun@0.flag[C](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx3@0.scanCell@5" net="xringSkip@0.xskipCoun@0.flag[B](R)" />
+  <datanet name="ringSkip@0.skipCoun@0.scanKx3@0.scanCell@6" net="xringSkip@0.xskipCoun@0.flag[A](R)" />
+  <datanet name="ringSkip@0.moveLit@0.dStates@0.scanKhx5@2.scanCell@4" net="xringSkip@0.xmoveLit@0.s[1](R)" />
+  <datanet name="ringSkip@0.moveLit@0.dStates@0.scanKhx5@2.scanCell@5" net="xringSkip@0.do[M](R)" />
+  <datanet name="ringSkip@0.moveLit@0.dStates@0.scanKhx5@2.scanCell@6" net="dInS(R)" />
+  <datanet name="ringSkip@0.moveLit@0.dStates@0.scanKhx5@2.scanCell@7" net="tInS(R)" />
+  <datanet name="ringSkip@0.moveLit@0.dStates@0.scanKhx5@2.scanCell@8" net="torpS(R)" />
+  <datanet name="tokOut.fillStag@0.gaspFill@0.scanEx2v@2.scanCell@1" net="tOutS(R)" net2="xtokOut.xfillStag@0.xgaspFill@0.xscanEx2v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="tokOut.fillStag@0.gaspFill@0.scanEx2v@2.scanCell@2" net="xtokOut.xfillStag@0.xgaspFill@0.fill(R)" net2="xtokOut.xfillStag@0.xgaspFill@0.xscanEx2v@2.xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="tokOut.drainSta@0.gaspDrai@0.scanEx2v@1.scanCell@1" net="xtokOut.net@41(R)" net2="xtokOut.xdrainSta@0.xgaspDrai@0.xscanEx2v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="tokOut.drainSta@0.gaspDrai@0.scanEx2v@1.scanCell@2" net="xtokOut.xdrainSta@0.xgaspDrai@0.stopped(R)" net2="xtokOut.xdrainSta@0.xgaspDrai@0.xscanEx2v@1.xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.upDown8w@1.weakStag@10.gaspPlai@1.scanEx1v@2.scanCell@1" net="dOutS(R)" net2="xdata.xupDown8w@1.xweakStag@10.xgaspPlai@1.xscanEx1v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.upDown8w@1.weakStag@11.gaspPlai@1.scanEx1v@2.scanCell@1" net="xdata.xupDown8w@1.net@28(R)" net2="xdata.xupDown8w@1.xweakStag@11.xgaspPlai@1.xscanEx1v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.upDown8w@1.weakStag@12.gaspPlai@1.scanEx1v@2.scanCell@1" net="xdata.xupDown8w@1.net@62(R)" net2="xdata.xupDown8w@1.xweakStag@12.xgaspPlai@1.xscanEx1v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.upDown8w@1.weakStag@13.gaspPlai@1.scanEx1v@2.scanCell@1" net="xdata.xupDown8w@1.net@64(R)" net2="xdata.xupDown8w@1.xweakStag@13.xgaspPlai@1.xscanEx1v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.fillStag@0.gaspFill@0.scanEx2v@2.scanCell@1" net="xdata.net@263(R)" net2="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xgaspFill@0.xscanEx2v@2.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.fillStag@0.gaspFill@0.scanEx2v@2.scanCell@2" net="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xgaspFill@0.fill(R)" net2="xdata.xfillDrai@0.xproperSt@0.xfillStag@0.xgaspFill@0.xscanEx2v@2.xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.drainSta@0.gaspDrai@0.scanEx2v@1.scanCell@1" net="xdata.xfillDrai@0.xproperSt@0.net@41(R)" net2="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanEx2v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.fillDrai@0.properSt@0.drainSta@0.gaspDrai@0.scanEx2v@1.scanCell@2" net="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.stopped(R)" net2="xdata.xfillDrai@0.xproperSt@0.xdrainSta@0.xgaspDrai@0.xscanEx2v@1.xscanCell@2.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.upDown8w@1.weakStag@17.gaspWeak@0.scanEx1v@1.scanCell@1" net="xdata.net@229(R)" net2="xdata.xupDown8w@1.xweakStag@17.xgaspWeak@0.xscanEx1v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.upDown8w@1.weakStag@16.gaspWeak@0.scanEx1v@1.scanCell@1" net="xdata.xupDown8w@1.net@52(R)" net2="xdata.xupDown8w@1.xweakStag@16.xgaspWeak@0.xscanEx1v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.upDown8w@1.weakStag@15.gaspWeak@0.scanEx1v@1.scanCell@1" net="xdata.xupDown8w@1.net@43(R)" net2="xdata.xupDown8w@1.xweakStag@15.xgaspWeak@0.xscanEx1v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="data.upDown8w@1.weakStag@14.gaspWeak@0.scanEx1v@1.scanCell@1" net="xdata.xupDown8w@1.net@50(R)" net2="xdata.xupDown8w@1.xweakStag@14.xgaspWeak@0.xscanEx1v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.upDown8w@0.weakStag@17.gaspWeak@0.scanEx1v@1.scanCell@1" net="gnd(R)" net2="xinstrIn.xupDown8w@0.xweakStag@17.xgaspWeak@0.xscanEx1v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.upDown8w@0.weakStag@16.gaspWeak@0.scanEx1v@1.scanCell@1" net="xinstrIn.xupDown8w@0.net@52(R)" net2="xinstrIn.xupDown8w@0.xweakStag@16.xgaspWeak@0.xscanEx1v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.upDown8w@0.weakStag@15.gaspWeak@0.scanEx1v@1.scanCell@1" net="xinstrIn.xupDown8w@0.net@43(R)" net2="xinstrIn.xupDown8w@0.xweakStag@15.xgaspWeak@0.xscanEx1v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+  <datanet name="instrIn.upDown8w@0.weakStag@14.gaspWeak@0.scanEx1v@1.scanCell@1" net="xinstrIn.xupDown8w@0.net@50(R)" net2="xinstrIn.xupDown8w@0.xweakStag@14.xgaspWeak@0.xscanEx1v@1.xscanCell@1.xlatch2in@0.dataBar(WI)" />
+'>
+<!ENTITY countersL_cntScnFour_sin '
+       <subchain name="cntScnOn@1" length="1" access="RW" clears="-" />
+       <subchain name="cntScnOn@2" length="1" access="RW" clears="-" />
+       <subchain name="cntScnOn@0" length="1" access="RW" clears="-" />
+       <subchain name="cntScnOn@3" length="1" access="RW" clears="-" />
+'>
+<!ENTITY countersL_cntScnNine_sin '
+       <subchain name="cntScnTh@1"> &countersL_cntScnThree_sin; </subchain>
+       <subchain name="cntScnTh@2"> &countersL_cntScnThree_sin; </subchain>
+       <subchain name="cntScnTh@0"> &countersL_cntScnThree_sin; </subchain>
+'>
+<!ENTITY countersL_cntScnThree_sin '
+       <subchain name="cntScnOn@1" length="1" access="RW" clears="-" />
+       <subchain name="cntScnOn@2" length="1" access="RW" clears="-" />
+       <subchain name="cntScnOn@0" length="1" access="RW" clears="-" />
+'>
+<!ENTITY countersL_cntScnTwelve_sin '
+       <subchain name="cntScnFo@1"> &countersL_cntScnFour_sin; </subchain>
+       <subchain name="cntScnFo@2"> &countersL_cntScnFour_sin; </subchain>
+       <subchain name="cntScnFo@0"> &countersL_cntScnFour_sin; </subchain>
+'>
+<!ENTITY countersL_instructionCount_sid_1_ '
+       <subchain name="cntScnOn@2" length="1" access="RW" clears="-" />
+       <subchain name="cntScnTw@3"> &countersL_cntScnTwelve_sin; </subchain>
+       <subchain name="cntScnTw@4"> &countersL_cntScnTwelve_sin; </subchain>
+       <subchain name="cntScnNi@2"> &countersL_cntScnNine_sin; </subchain>
+'>
+<!ENTITY dockPartOD_ringSkipMoveLit_sin '
+       <subchain name="ringFIFO@0"> &fifoL_ringFIFO_sin; </subchain>
+       <subchain name="skipCoun@0"> &dockPartOD_skipCount_sin; </subchain>
+       <subchain name="moveLit@0"> &dockPartsK_moveLit_sin; </subchain>
+'>
+<!ENTITY dockPartOD_skipCount_sin '
+       <subchain name="scanKx7@0"> &scanK_scanKx7_sin; </subchain>
+       <subchain name="scanKx6@0"> &scanK_scanKx6_sin; </subchain>
+       <subchain name="scanKx3@0"> &scanK_scanKx3_sin; </subchain>
+'>
+<!ENTITY dockPartsK_moveD_sin '
+       <subchain name="scanKhx5@2"> &scanK_scanKhx5_sin; </subchain>
+'>
+<!ENTITY dockPartsK_moveLit_sin '
+       <subchain name="dStates@0"> &dockPartsK_moveD_sin; </subchain>
+'>
+<!ENTITY fifoL_epiFifoCont_sin '
+       <subchain name="anEpiSta@0"> &gaspL_anEpiStartS_sin; </subchain>
+       <subchain name="aStageS@0"> &gaspL_aStageS_sin; </subchain>
+'>
+<!ENTITY fifoL_epiFifo_sin '
+       <subchain name="epiFifoC@0"> &fifoL_epiFifoCont_sin; </subchain>
+'>
+<!ENTITY fifoL_m12stageD_sin '
+       <subchain name="m1stageD@1"> &fifoL_m1stageD_sin; </subchain>
+'>
+<!ENTITY fifoL_m1stageD_sin '
+       <subchain name="scanKhx2@0"> &scanK_scanKhx2_sin; </subchain>
+'>
+<!ENTITY fifoL_odRQstageD_sin '
+       <subchain name="scanKhx5@0"> &scanK_scanKhx5_sin; </subchain>
+'>
+<!ENTITY fifoL_ringFIFO_sin '
+       <subchain name="odRQstag@0"> &fifoL_odRQstageD_sin; </subchain>
+       <subchain name="split10@0"> &fifoL_split10_sin; </subchain>
+       <subchain name="m12stage@0"> &fifoL_m12stageD_sin; </subchain>
+'>
+<!ENTITY fifoL_split10_sin '
+       <subchain name="splitSta@0"> &fifoL_splitStart_sin; </subchain>
+       <subchain name="splitSta@1"> &fifoL_splitStageDx4_sin_1_; </subchain>
+       <subchain name="splitSta@2"> &fifoL_splitStageDx4_sin_1_; </subchain>
+       <subchain name="splitSta@2_sin[2]"> &fifoL_splitStageDx4_sin_2_; </subchain>
+       <subchain name="splitSta@1_sin[2]"> &fifoL_splitStageDx4_sin_2_; </subchain>
+       <subchain name="splitEnd@0"> &fifoL_splitEnd_sin; </subchain>
+'>
+<!ENTITY fifoL_splitEnd_sin '
+       <subchain name="anAltEnd@1"> &gaspL_anAltEndS_sin; </subchain>
+'>
+<!ENTITY fifoL_splitStageDx2_sin '
+       <subchain name="scanKhx2@0"> &scanK_scanKhx2_sin; </subchain>
+'>
+<!ENTITY fifoL_splitStageDx4_sin_1_ '
+       <subchain name="splitSta@4"> &fifoL_splitStageDx2_sin; </subchain>
+'>
+<!ENTITY fifoL_splitStageDx4_sin_2_ '
+       <subchain name="splitSta@5"> &fifoL_splitStageDx2_sin; </subchain>
+'>
+<!ENTITY fifoL_splitStart_sin '
+       <subchain name="anAltSta@0"> &gaspL_anAltStartS_sin; </subchain>
+'>
+<!ENTITY gaspL_aStageS_sin '
+       <subchain name="scanKhx1@0"> &scanK_scanKhx1_sin; </subchain>
+'>
+<!ENTITY gaspL_anAltEndS_sin '
+       <subchain name="scanKhx3@0"> &scanK_scanKhx3_sin; </subchain>
+'>
+<!ENTITY gaspL_anAltStartS_sin '
+       <subchain name="scanKhx2@0"> &scanK_scanKhx2_sin; </subchain>
+'>
+<!ENTITY gaspL_anEpiStartS_sin '
+       <subchain name="scanKhx1@0"> &scanK_scanKhx1_sin; </subchain>
+'>
+<!ENTITY gaspL_gaspDrain_sic_1_ '
        <subchain name="scanFx3h@0"> &scanJ_scanFx3hor_sic_1_; </subchain>
+       <subchain name="scanFx1v@0"> &scanJ_scanFx1vert_sic_1_; </subchain>
 '>
-<!ENTITY gaspJ_gaspDrain_sir_1_ '
+<!ENTITY gaspL_gaspDrain_sir_1_ '
        <subchain name="scanEx2v@1"> &scanJ_scanEx2vert_sir_1_; </subchain>
 '>
-<!ENTITY gaspJ_gaspFill_sic_1_ '
+<!ENTITY gaspL_gaspFill_sic_1_ '
        <subchain name="scanFx2v@0"> &scanJ_scanFx2vert_sic_1_; </subchain>
 '>
-<!ENTITY gaspJ_gaspFill_sir_1_ '
+<!ENTITY gaspL_gaspFill_sir_1_ '
        <subchain name="scanEx2v@2"> &scanJ_scanEx2vert_sir_1_; </subchain>
 '>
-<!ENTITY gaspJ_gaspPlain_sir_1_ '
+<!ENTITY gaspL_gaspTap_sic_1_ '
+       <subchain name="scanFx1v@0"> &scanJ_scanFx1vert_sic_1_; </subchain>
+'>
+<!ENTITY gaspL_gaspTap_sir_1_ '
        <subchain name="scanEx1v@0"> &scanJ_scanEx1vertA_sir_1_; </subchain>
 '>
+<!ENTITY gaspL_gaspWeakDn_sor_8_ '
+       <subchain name="scanEx1v@1"> &scanK_scanEx1vertFdn_sor_8_; </subchain>
+'>
+<!ENTITY gaspL_gaspWeakUp_sir_1_ '
+       <subchain name="scanEx1v@2"> &scanK_scanEx1vertFup_sir_1_; </subchain>
+'>
+<!ENTITY latchGroupsK_latchWscan_sin '
+       <subchain name="scanCell@2" length="1" access="RW" clears="-" />
+'>
 <!ENTITY registersJ_addr1in14scan_sin '
-       <subchain name="ls[1:14]" length="14" access="RW" clears="-" />
+       <subchain name="ls[1]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[2]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[3]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[4]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[5]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[6]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[7]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[8]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[9]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[10]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[11]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[12]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[13]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[14]"> &latchGroupsK_latchWscan_sin; </subchain>
 '>
 <!ENTITY registersJ_all1in52scan_sid_1_ '
        <subchain name="data1in3@0"> &registersJ_data1in38scan_sid_1_; </subchain>
@@ -169,8 +485,44 @@
 <!ENTITY registersJ_data1in38scan_sid_1_ '
        <subchain name="scanCell@0" length="1" access="RW" clears="-" />
        <subchain name="scanCell@1" length="1" access="RW" clears="-" />
-       <subchain name="ls[1:37]" length="37" access="RW" clears="-" />
-       <subchain name="latchWsc@1" length="1" access="RW" clears="-" />
+       <subchain name="ls[1]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[2]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[3]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[4]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[5]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[6]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[7]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[8]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[9]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[10]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[11]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[12]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[13]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[14]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[15]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[16]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[17]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[18]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[19]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[20]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[21]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[22]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[23]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[24]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[25]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[26]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[27]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[28]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[29]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[30]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[31]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[32]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[33]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[34]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[35]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[36]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="ls[37]"> &latchGroupsK_latchWscan_sin; </subchain>
+       <subchain name="latchWsc@1"> &latchGroupsK_latchWscan_sin; </subchain>
 '>
 <!ENTITY scanJ_scanEx1vertA_sir_1_ '
        <subchain name="scanCell@1" length="1" access="RW" clears="-" />
@@ -179,6 +531,9 @@
        <subchain name="scanCell@1" length="1" access="RW" clears="-" />
        <subchain name="scanCell@2" length="1" access="RW" clears="-" />
 '>
+<!ENTITY scanJ_scanFx1vert_sic_1_ '
+       <subchain name="scanCell@2" length="1" access="RW" clears="L" />
+'>
 <!ENTITY scanJ_scanFx2vert_sic_1_ '
        <subchain name="scanCell@2" length="1" access="RW" clears="L" />
        <subchain name="scanCell@1" length="1" access="RW" clears="L" />
@@ -188,64 +543,180 @@
        <subchain name="scanCell@1" length="1" access="RW" clears="L" />
        <subchain name="scanCell@3" length="1" access="RW" clears="L" />
 '>
-<!ENTITY stageGroupsJ_plainStageFour_rscanIn_1_ '
-       <subchain name="stg[1]"> &stagesJ_plainStage_sir_1_; </subchain>
-       <subchain name="stg[2]"> &stagesJ_plainStage_sir_1_; </subchain>
-       <subchain name="stg[3]"> &stagesJ_plainStage_sir_1_; </subchain>
-       <subchain name="stg[4]"> &stagesJ_plainStage_sir_1_; </subchain>
+<!ENTITY scanK_scanEx1vertFdn_sor_8_ '
+       <subchain name="scanCell@1" length="1" access="RW" clears="-" />
+'>
+<!ENTITY scanK_scanEx1vertFup_sir_1_ '
+       <subchain name="scanCell@1" length="1" access="RW" clears="-" />
+'>
+<!ENTITY scanK_scanKhx1_sin '
+       <subchain name="scanCell@1" length="1" access="R" clears="-" />
+'>
+<!ENTITY scanK_scanKhx2_sin '
+       <subchain name="scanCell@1" length="1" access="R" clears="-" />
+       <subchain name="scanCell@2" length="1" access="R" clears="-" />
+'>
+<!ENTITY scanK_scanKhx3_sin '
+       <subchain name="scanCell@4" length="1" access="R" clears="-" />
+       <subchain name="scanCell@5" length="1" access="R" clears="-" />
+       <subchain name="scanCell@6" length="1" access="R" clears="-" />
+'>
+<!ENTITY scanK_scanKhx5_sin '
+       <subchain name="scanCell@4" length="1" access="R" clears="-" />
+       <subchain name="scanCell@5" length="1" access="R" clears="-" />
+       <subchain name="scanCell@6" length="1" access="R" clears="-" />
+       <subchain name="scanCell@7" length="1" access="R" clears="-" />
+       <subchain name="scanCell@8" length="1" access="R" clears="-" />
+'>
+<!ENTITY scanK_scanKx3_sin '
+       <subchain name="scanCell@4" length="1" access="R" clears="-" />
+       <subchain name="scanCell@5" length="1" access="R" clears="-" />
+       <subchain name="scanCell@6" length="1" access="R" clears="-" />
+'>
+<!ENTITY scanK_scanKx6_sin '
+       <subchain name="scanCell@4" length="1" access="R" clears="-" />
+       <subchain name="scanCell@5" length="1" access="R" clears="-" />
+       <subchain name="scanCell@6" length="1" access="R" clears="-" />
+       <subchain name="scanCell@7" length="1" access="R" clears="-" />
+       <subchain name="scanCell@8" length="1" access="R" clears="-" />
+       <subchain name="scanCell@9" length="1" access="R" clears="-" />
+'>
+<!ENTITY scanK_scanKx7_sin '
+       <subchain name="scanCell@4" length="1" access="R" clears="-" />
+       <subchain name="scanCell@5" length="1" access="R" clears="-" />
+       <subchain name="scanCell@6" length="1" access="R" clears="-" />
+       <subchain name="scanCell@7" length="1" access="R" clears="-" />
+       <subchain name="scanCell@8" length="1" access="R" clears="-" />
+       <subchain name="scanCell@9" length="1" access="R" clears="-" />
+       <subchain name="scanCell@10" length="1" access="R" clears="-" />
+'>
+<!ENTITY stageGroupsL_fillDrainCount_sic_1_ '
+       <subchain name="properSt@0"> &stageGroupsL_properStopper_sic_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_fillDrainCount_sid_1_ '
+       <subchain name="properSt@0"> &stageGroupsL_properStopper_sid_1_; </subchain>
+       <subchain name="instruct@0"> &countersL_instructionCount_sid_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_fillDrainCount_sir_1_ '
+       <subchain name="properSt@0"> &stageGroupsL_properStopper_sir_1_; </subchain>
 '>
-<!ENTITY stageGroupsJ_properStopper_sic_1_ '
-       <subchain name="aFillSta@0"> &stagesJ_fillStage_sic_1_; </subchain>
-       <subchain name="aDrainSt@0"> &stagesJ_drainStage_sic_1_; </subchain>
+<!ENTITY stageGroupsL_northFifo_sic_1_ '
+       <subchain name="fillDrai@0"> &stageGroupsL_fillDrainCount_sic_1_; </subchain>
 '>
-<!ENTITY stageGroupsJ_properStopper_sid_1_ '
-       <subchain name="aFillSta@0"> &stagesJ_fillStage_sid_1_; </subchain>
+<!ENTITY stageGroupsL_northFifo_sid_1_ '
+       <subchain name="fillDrai@0"> &stageGroupsL_fillDrainCount_sid_1_; </subchain>
 '>
-<!ENTITY stageGroupsJ_properStopper_sir_1_ '
-       <subchain name="aFillSta@0"> &stagesJ_fillStage_sir_1_; </subchain>
-       <subchain name="aDrainSt@0"> &stagesJ_drainStage_sir_1_; </subchain>
+<!ENTITY stageGroupsL_northFifo_sir_1_ '
+       <subchain name="upDown8w@1"> &stageGroupsL_upDown8weak_sir_1_; </subchain>
+       <subchain name="fillDrai@0"> &stageGroupsL_fillDrainCount_sir_1_; </subchain>
 '>
-<!ENTITY stagesJ_drainStage_sic_1_ '
-       <subchain name="gaspPlai@0"> &gaspJ_gaspDrain_sic_1_; </subchain>
+<!ENTITY stageGroupsL_northFifo_sor_8_ '
+       <subchain name="upDown8w@1"> &stageGroupsL_upDown8weak_sor_8_; </subchain>
 '>
-<!ENTITY stagesJ_drainStage_sir_1_ '
-       <subchain name="gaspPlai@0"> &gaspJ_gaspDrain_sir_1_; </subchain>
+<!ENTITY stageGroupsL_properStopper_sic_1_ '
+       <subchain name="fillStag@0"> &stagesL_fillStage_sic_1_; </subchain>
+       <subchain name="drainSta@0"> &stagesL_drainStage_sic_1_; </subchain>
 '>
-<!ENTITY stagesJ_fillStage_sic_1_ '
-       <subchain name="gaspPlai@0"> &gaspJ_gaspFill_sic_1_; </subchain>
+<!ENTITY stageGroupsL_properStopper_sid_1_ '
+       <subchain name="fillStag@0"> &stagesL_fillStage_sid_1_; </subchain>
 '>
-<!ENTITY stagesJ_fillStage_sid_1_ '
+<!ENTITY stageGroupsL_properStopper_sir_1_ '
+       <subchain name="fillStag@0"> &stagesL_fillStage_sir_1_; </subchain>
+       <subchain name="drainSta@0"> &stagesL_drainStage_sir_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_southFifo_sic_1_ '
+       <subchain name="tapPropS@0"> &stageGroupsL_tapPropStop_sic_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_southFifo_sid_1_ '
+       <subchain name="tapPropS@0"> &stageGroupsL_tapPropStop_sid_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_southFifo_sir_1_ '
+       <subchain name="upDown8w@0"> &stageGroupsL_upDown8weak_sir_1_; </subchain>
+       <subchain name="tapPropS@0"> &stageGroupsL_tapPropStop_sir_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_southFifo_sor_8_ '
+       <subchain name="upDown8w@0"> &stageGroupsL_upDown8weak_sor_8_; </subchain>
+'>
+<!ENTITY stageGroupsL_tapPropStop_sic_1_ '
+       <subchain name="properSt@0"> &stageGroupsL_properStopper_sic_1_; </subchain>
+       <subchain name="tapStage@1"> &stagesL_tapStage_sic_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_tapPropStop_sid_1_ '
+       <subchain name="properSt@0"> &stageGroupsL_properStopper_sid_1_; </subchain>
+       <subchain name="instruct@0"> &countersL_instructionCount_sid_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_tapPropStop_sir_1_ '
+       <subchain name="properSt@0"> &stageGroupsL_properStopper_sir_1_; </subchain>
+       <subchain name="tapStage@1"> &stagesL_tapStage_sir_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_upDown8weak_sir_1_ '
+       <subchain name="weakStag@10"> &stagesL_weakStageUp_sir_1_; </subchain>
+       <subchain name="weakStag@11"> &stagesL_weakStageUp_sir_1_; </subchain>
+       <subchain name="weakStag@12"> &stagesL_weakStageUp_sir_1_; </subchain>
+       <subchain name="weakStag@13"> &stagesL_weakStageUp_sir_1_; </subchain>
+'>
+<!ENTITY stageGroupsL_upDown8weak_sor_8_ '
+       <subchain name="weakStag@17"> &stagesL_weakStageDn_sor_8_; </subchain>
+       <subchain name="weakStag@16"> &stagesL_weakStageDn_sor_8_; </subchain>
+       <subchain name="weakStag@15"> &stagesL_weakStageDn_sor_8_; </subchain>
+       <subchain name="weakStag@14"> &stagesL_weakStageDn_sor_8_; </subchain>
+'>
+<!ENTITY stagesL_drainStage_sic_1_ '
+       <subchain name="gaspDrai@0"> &gaspL_gaspDrain_sic_1_; </subchain>
+'>
+<!ENTITY stagesL_drainStage_sir_1_ '
+       <subchain name="gaspDrai@0"> &gaspL_gaspDrain_sir_1_; </subchain>
+'>
+<!ENTITY stagesL_fillStage_sic_1_ '
+       <subchain name="gaspFill@0"> &gaspL_gaspFill_sic_1_; </subchain>
+'>
+<!ENTITY stagesL_fillStage_sid_1_ '
        <subchain name="all1in52@1"> &registersJ_all1in52scan_sid_1_; </subchain>
 '>
-<!ENTITY stagesJ_fillStage_sir_1_ '
-       <subchain name="gaspPlai@0"> &gaspJ_gaspFill_sir_1_; </subchain>
+<!ENTITY stagesL_fillStage_sir_1_ '
+       <subchain name="gaspFill@0"> &gaspL_gaspFill_sir_1_; </subchain>
+'>
+<!ENTITY stagesL_tapStage_sic_1_ '
+       <subchain name="gaspSwit@0"> &gaspL_gaspTap_sic_1_; </subchain>
+'>
+<!ENTITY stagesL_tapStage_sir_1_ '
+       <subchain name="gaspSwit@0"> &gaspL_gaspTap_sir_1_; </subchain>
+'>
+<!ENTITY stagesL_weakStageDn_sor_8_ '
+       <subchain name="gaspWeak@0"> &gaspL_gaspWeakDn_sor_8_; </subchain>
 '>
-<!ENTITY stagesJ_plainStage_sir_1_ '
-       <subchain name="gaspPlai@0"> &gaspJ_gaspPlain_sir_1_; </subchain>
+<!ENTITY stagesL_weakStageUp_sir_1_ '
+       <subchain name="gaspPlai@1"> &gaspL_gaspWeakUp_sir_1_; </subchain>
 '>
 ]>
 
 <ChainG>
        <system>
                <chip name="marina" lengthIR="8">
-                       <chain name="jtag_dockTest_control" opcode="0">
-                               <subchain name="ps1"> &stageGroupsJ_properStopper_sic_1_; </subchain>
-                               <subchain name="ps2"> &stageGroupsJ_properStopper_sic_1_; </subchain>
+                       <chain name="marina_control" opcode="0">
+                               <subchain name="instrIn"> &stageGroupsL_southFifo_sic_1_; </subchain>
+                               <subchain name="tokOut"> &stageGroupsL_properStopper_sic_1_; </subchain>
+                               <subchain name="data"> &stageGroupsL_northFifo_sic_1_; </subchain>
                        </chain>
-                       <chain name="jtag_dockTest_data" opcode="0">
-                               <subchain name="ps1"> &stageGroupsJ_properStopper_sid_1_; </subchain>
-                               <subchain name="ps2"> &stageGroupsJ_properStopper_sid_1_; </subchain>
+                       <chain name="marina_data" opcode="0">
+                               <subchain name="instrIn"> &stageGroupsL_southFifo_sid_1_; </subchain>
+                               <subchain name="tokOut"> &stageGroupsL_properStopper_sid_1_; </subchain>
+                               <subchain name="data"> &stageGroupsL_northFifo_sid_1_; </subchain>
                        </chain>
-                       <chain name="jtag_dockTest_report" opcode="0">
-                               <subchain name="ps1"> &stageGroupsJ_properStopper_sir_1_; </subchain>
-                               <subchain name="plainSta@0"> &stageGroupsJ_plainStageFour_rscanIn_1_; </subchain>
-                               <subchain name="ps2"> &stageGroupsJ_properStopper_sir_1_; </subchain>
+                       <chain name="marina_report" opcode="0">
+                               <subchain name="instrIn"> &stageGroupsL_southFifo_sir_1_; </subchain>
+                               <subchain name="epiFifo@0"> &fifoL_epiFifo_sin; </subchain>
+                               <subchain name="ringSkip@0"> &dockPartOD_ringSkipMoveLit_sin; </subchain>
+                               <subchain name="tokOut"> &stageGroupsL_properStopper_sir_1_; </subchain>
+                               <subchain name="data"> &stageGroupsL_northFifo_sir_1_; </subchain>
+                               <subchain name="data_sor[8]"> &stageGroupsL_northFifo_sor_8_; </subchain>
+                               <subchain name="instrIn_sor[8]"> &stageGroupsL_southFifo_sor_8_; </subchain>
                        </chain>
                </chip>
                <scandatanets>
-                       <datachain name="marina_jtag_dockTest_control"> &marina_jtag_dockTest_control_dataNets; </datachain>
-                       <datachain name="marina_jtag_dockTest_data"> &marina_jtag_dockTest_data_dataNets; </datachain>
-                       <datachain name="marina_jtag_dockTest_report"> &marina_jtag_dockTest_report_dataNets; </datachain>
+                       <datachain name="marina_marina_control"> &marina_marina_control_dataNets; </datachain>
+                       <datachain name="marina_marina_data"> &marina_marina_data_dataNets; </datachain>
+                       <datachain name="marina_marina_report"> &marina_marina_report_dataNets; </datachain>
                </scandatanets>
        </system>
 </ChainG>