public Ship getShip(String type, int ordinal) {
for(Ship s : this)
if (s.getType().equals(type))
- if (ordinal-- < 0)
+ if (--ordinal < 0)
return s;
return null;
}
this.top = top;
debugShip = createShip("Debug", "debug");
- int LANES = 12;
- //int LANES = 1;
+ int LANES = 5;
+ //int LANES = 2;
createShip("Memory", "memory1");
- createShip("CarrySaveAdder", "csa1");
- if (LANES>1)
- createShip("Memory", "memory2");
+ if (LANES>2) {
+ //createShip("Memory", "memory2");
+ //createShip("Memory", "memory3");
+ }
- for(int i=0; i<LANES; i++) {
- createShip("Fifo", "fifo"+i);
+ for(int i=0; i<LANES; i++)
createShip("Alu", "alu"+i);
- }
- createShip("Rotator", "rotator");
- createShip("Lut3", "lut");
+
+ for(int i=0; i<2; i++)
+ createShip("Fifo", "fifo"+i);
+
+ for(int i=0; i<13; i++)
+ createShip("Counter", "counter"+i);
+
/*
- createShip("Rotator", "rotator_");
- createShip("Lut3", "lut_");
+ if (LANES < 15) {
+ createShip("CarrySaveAdder", "csa1");
+ createShip("Rotator", "rotator");
+ createShip("Lut3", "lut");
+ }
*/
if (LANES<=1)
createShip("Fifo", "fifo_extra");
createShip("DRAM", "dram");
+ //createShip("DDR2", "ddr2");
createShip("Video", "video");
//Module.SourcePort debug_in = top.createWireSourcePort("debug_in", WIDTH_PACKET);
Module.SourcePort in = top.createInputPort("in", 8);
Module.SinkPort out = top.createOutputPort("out", 8, "");
- Module.Latch temp_in = top.new Latch("temp", WIDTH_PACKET) { public String doReset() { return name+"=0;"; } };
+ Module.Latch temp_in = top.new Latch("temp", WIDTH_PACKET);
Module.Latch count = top.new Latch("count", 8);
Module.Latch count_out = top.new Latch("count_out", 8);
//Module.SourcePort debug_in = top.createWireSourcePort("debug_in", WIDTH_PACKET);
Module.SinkPort debug_in = top_funnel.getInputPort("in1");
- top.new Event(new Object[] { in, debug_in },
- new Object[] { new SimpleAction(temp_in.getVerilogName()+" = ("+temp_in.getVerilogName()+" << 8) | in;"),
- new SimpleAction("if (count >= 5) begin"+
- " count <= 0; "+
- " `packet_token("+debug_in.getVerilogName()+") <= 0;"+
- " `packet_data("+debug_in.getVerilogName()+") <= "+temp_in.getVerilogName()+";"+
- " `packet_dest("+debug_in.getVerilogName()+") <= `instruction_dest("+temp_in.getVerilogName()+");"+
- " "+debug_in.getVerilogName()+"_r <= 1; "+
- "end else count <= count+1; "),
+ top.new Event(new Object[] { in, "count<=7" },
+ new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], in[7:0] };"),
+ new SimpleAction("count <= count+1;"),
in
- });
+ });
+ top.new Event(new Object[] { debug_in, "count>7" },
+ new Object[] { new SimpleAction(" count <= 0; "),
+ new AssignAction(debug_in, temp_in),
+ debug_in
+ });
top.new Event(new Object[] { out, debug_out },
new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
new SimpleAction("if (count_out >= 5) begin "+
FileOutputStream out = new FileOutputStream(outf);
PrintWriter pw = new PrintWriter(out);
- boolean auto = !"debug".equals(filename);
+ boolean debug = "debug".equals(filename);
pw.println("`include \"bitfields.v\"");
- pw.println("`define defreg(signame,width,regname) reg width regname; wire width signame; assign signame = regname; initial regname = 0;");
- pw.println("`define input(r, a, a_, w, d) input r; output a_; reg a; assign a_=a; input w d; initial a=0;");
- pw.println("`define output(r, r_, a, w, d) output r_; input a; reg r; assign r_=r; output w d; initial r=0;");
- pw.println("`define onread(req, ack) if (!req && ack) ack <= 0; else if (req && !ack) begin ack <=1;");
- pw.println("`define onwrite(req, ack) if (!req && !ack) req <= 1; else if (req && ack) begin req <= 0;");
pw.println();
- if (auto) {
- pw.print("`define reset ");
- for(DockDescription bb : sd) {
- String bb_name = bb.getName();
- if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; ");
- else pw.print(bb_name+"_r <= 0; ");
- }
- pw.println();
+ pw.print("`define reset ");
+ for(DockDescription bb : sd) {
+ String bb_name = bb.getName();
+ if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
+ else pw.print(bb_name+"_r <= 0; ");
+ }
+ pw.println();
- pw.println("module " + filename + "( clk, rst ");
- for(DockDescription bb : sd) {
- String bb_name = bb.getName();
- pw.print(" ");
- if (bb.isInputDock()) {
- pw.print(", " + bb_name+"_r");
- pw.print(", " + bb_name+"_a_");
- pw.print(", " + bb_name+"_d");
- } else {
- pw.print(", " + bb_name+"_r_");
- pw.print(", " + bb_name+"_a");
- pw.print(", " + bb_name+"_d_");
- }
- pw.println();
+ pw.print("`define flush ");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" if (!"+bb.getName()+"_r_) "+bb.getName()+"_f <= 0; ");
+ pw.print("if (1");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a");
+ pw.print(") begin ");
+ if (true) {
+ pw.print("if (1");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" && "+bb.getName()+"_d["+WIDTH_WORD+"] ");
+ pw.print(") begin ");
+ if (true) {
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(bb.getName()+"_f <= 1; ");
}
- if (filename.equals("dram")) {
- pw.println(" , dram_addr_");
- pw.println(" , dram_addr_r_");
- pw.println(" , dram_addr_a");
- pw.println(" , dram_isread_");
- pw.println(" , dram_write_data_");
- pw.println(" , dram_write_data_push_");
- pw.println(" , dram_write_data_full");
- pw.println(" , dram_read_data");
- pw.println(" , dram_read_data_pop_");
- pw.println(" , dram_read_data_empty");
- pw.println(" , dram_read_data_latency");
+ pw.print(" end else if (0");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" || "+bb.getName()+"_d["+WIDTH_WORD+"] ");
+ pw.print(") begin ");
+ if (true) {
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" if (!"+bb.getName()+"_d["+WIDTH_WORD+"]) "+bb.getName()+"_f <= 1; ");
}
- if (filename.equals("video")) {
- pw.println(" , vga_clk");
- pw.println(" , vga_psave");
- pw.println(" , vga_hsync");
- pw.println(" , vga_vsync");
- pw.println(" , vga_sync");
- pw.println(" , vga_blank");
- pw.println(" , vga_r");
- pw.println(" , vga_g");
- pw.println(" , vga_b");
- pw.println(" , vga_clkout");
+ pw.print(" end ");
+ }
+ pw.print(" end ");
+ pw.println();
+
+ pw.println("module " + filename + "( clk, rst ");
+ for(DockDescription bb : sd) {
+ String bb_name = bb.getName();
+ pw.print(" ");
+ if (bb.isInputDock()) {
+ pw.print(", " + bb_name+"_r_");
+ pw.print(", " + bb_name+"_a_");
+ pw.print(", " + bb_name+"_d");
+ } else {
+ pw.print(", " + bb_name+"_r_");
+ pw.print(", " + bb_name+"_a");
+ pw.print(", " + bb_name+"_d_");
}
- pw.println(" );");
pw.println();
- pw.println(" input clk;");
- pw.println(" input rst;");
- if (filename.equals("dram")) {
- pw.println("output [31:0] dram_addr_;");
- pw.println("output dram_addr_r_;");
- pw.println("input dram_addr_a;");
- pw.println("output dram_isread_;");
- pw.println("output [63:0] dram_write_data_;");
- pw.println("output dram_write_data_push_;");
- pw.println("input dram_write_data_full;");
- pw.println("input [63:0] dram_read_data;");
- pw.println("output dram_read_data_pop_;");
- pw.println("input dram_read_data_empty;");
- pw.println("input [1:0] dram_read_data_latency;");
- }
- if (filename.equals("video")) {
- pw.println("input vga_clk;");
- pw.println("output vga_psave;");
- pw.println("output vga_hsync;");
- pw.println("output vga_vsync;");
- pw.println("output vga_sync;");
- pw.println("output vga_blank;");
- pw.println("output [7:0] vga_r;");
- pw.println("output [7:0] vga_g;");
- pw.println("output [7:0] vga_b;");
- pw.println("output vga_clkout;");
- }
- for(DockDescription bb : sd) {
- String bb_name = bb.getName();
- pw.print(" ");
- if ("fifo".equals(filename)) continue;
- if (bb.isInputDock()) {
- pw.println("`input(" +
- bb_name+"_r, "+
- bb_name+"_a, "+
- bb_name+"_a_, "+
- "[("+WIDTH_WORD+"-1):0],"+
- bb_name+"_d)"
- );
- } else {
- pw.println("`output(" +
- bb_name+"_r, "+
- bb_name+"_r_, "+
- bb_name+"_a, "+
- "[("+WIDTH_WORD+"):0],"+
- bb_name+"_d_)"
- );
- /*
- if (!bb_name.equals("out") || !"memory".equals(filename))
- pw.println("`defreg(" +
- bb_name+"_d_, "+
- "[("+WIDTH_WORD+"-1):0],"+
- bb_name+"_d)"
- );
- */
- }
- pw.println();
+ }
+ if (filename.equals("debug")) {
+ pw.println(" , out_r_");
+ pw.println(" , out_a");
+ pw.println(" , out_d_");
+ }
+ if (filename.equals("dram")) {
+ pw.println(" , dram_addr_");
+ pw.println(" , dram_addr_r_");
+ pw.println(" , dram_addr_a");
+ pw.println(" , dram_isread_");
+ pw.println(" , dram_write_data_");
+ pw.println(" , dram_write_data_push_");
+ pw.println(" , dram_write_data_full");
+ pw.println(" , dram_read_data");
+ pw.println(" , dram_read_data_pop_");
+ pw.println(" , dram_read_data_empty");
+ pw.println(" , dram_read_data_latency");
+ }
+ if (filename.equals("ddr2")) {
+ pw.println(" , ddr2_addr_");
+ pw.println(" , ddr2_addr_r_");
+ pw.println(" , ddr2_addr_a");
+ pw.println(" , ddr2_isread_");
+ pw.println(" , ddr2_write_data_");
+ pw.println(" , ddr2_write_data_push_");
+ pw.println(" , ddr2_write_data_full");
+ pw.println(" , ddr2_read_data");
+ pw.println(" , ddr2_read_data_pop_");
+ pw.println(" , ddr2_read_data_empty");
+ pw.println(" , ddr2_read_data_latency");
+ }
+ if (filename.equals("video")) {
+ pw.println(" , vga_clk");
+ pw.println(" , vga_psave");
+ pw.println(" , vga_hsync");
+ pw.println(" , vga_vsync");
+ pw.println(" , vga_sync");
+ pw.println(" , vga_blank");
+ pw.println(" , vga_r");
+ pw.println(" , vga_g");
+ pw.println(" , vga_b");
+ pw.println(" , vga_clkout");
+ }
+ pw.println(" );");
+ pw.println();
+ pw.println(" input clk;");
+ pw.println(" input rst;");
+ if (filename.equals("debug")) {
+ pw.println(" output ["+WIDTH_WORD+":0] out_d_;");
+ pw.println(" input out_a;");
+ pw.println(" output out_r_;");
+ }
+ if (filename.equals("dram")) {
+ pw.println("output [31:0] dram_addr_;");
+ pw.println("output dram_addr_r_;");
+ pw.println("input dram_addr_a;");
+ pw.println("output dram_isread_;");
+ pw.println("output [63:0] dram_write_data_;");
+ pw.println("output dram_write_data_push_;");
+ pw.println("input dram_write_data_full;");
+ pw.println("input [63:0] dram_read_data;");
+ pw.println("output dram_read_data_pop_;");
+ pw.println("input dram_read_data_empty;");
+ pw.println("input [1:0] dram_read_data_latency;");
+ }
+ if (filename.equals("ddr2")) {
+ pw.println("output [31:0] ddr2_addr_;");
+ pw.println("output ddr2_addr_r_;");
+ pw.println("input ddr2_addr_a;");
+ pw.println("output ddr2_isread_;");
+ pw.println("output [63:0] ddr2_write_data_;");
+ pw.println("output ddr2_write_data_push_;");
+ pw.println("input ddr2_write_data_full;");
+ pw.println("input [63:0] ddr2_read_data;");
+ pw.println("output ddr2_read_data_pop_;");
+ pw.println("input ddr2_read_data_empty;");
+ pw.println("input [1:0] ddr2_read_data_latency;");
+ }
+ if (filename.equals("video")) {
+ pw.println("input vga_clk;");
+ pw.println("output vga_psave;");
+ pw.println("output vga_hsync;");
+ pw.println("output vga_vsync;");
+ pw.println("output vga_sync;");
+ pw.println("output vga_blank;");
+ pw.println("output [7:0] vga_r;");
+ pw.println("output [7:0] vga_g;");
+ pw.println("output [7:0] vga_b;");
+ pw.println("output vga_clkout;");
+ }
+
+ for(DockDescription bb : sd) {
+ String bb_name = bb.getName();
+ if (bb.isInputDock()) {
+ pw.println(" input ["+WIDTH_WORD+":0] "+bb_name+"_d;");
+ pw.println(" input "+bb_name+"_r_;");
+ pw.println(" wire "+bb_name+"_r;");
+ pw.println(" assign "+bb_name+"_r = "+bb_name+"_r_ & ~"+bb_name+"_d["+WIDTH_WORD+"];");
+ pw.println(" output "+bb_name+"_a_;");
+ pw.println(" reg "+bb_name+"_a;");
+ pw.println(" initial "+bb_name+"_a = 0;");
+ pw.println(" reg "+bb_name+"_f;");
+ pw.println(" initial "+bb_name+"_f = 0;");
+ pw.println(" assign "+bb_name+"_a_ = "+bb_name+"_a || "+bb_name+"_f;");
+ } else {
+ pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
+ pw.println(" input "+bb_name+"_a;");
+ pw.println(" output "+bb_name+"_r_;");
+ pw.println(" reg "+bb_name+"_r;");
+ pw.println(" initial "+bb_name+"_r = 0;");
+ pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
}
+ pw.println();
}
pw.println(sd.getSection("fpga"));
- if (auto)
- pw.println("endmodule");
+ pw.println("endmodule");
pw.flush();
pw.close();
/** the pump itself is a */
public class FpgaDock extends FleetTwoDock implements FabricElement {
- private static final int INSTRUCTION_FIFO_SIZE = 12;
+ private static final int INSTRUCTION_FIFO_SIZE = 16;
private static final int EPILOGUE_FIFO_SIZE = 0;
- private static final int DATA_FIFO_SIZE = 12;
+ private static final int DATA_FIFO_SIZE = 16;
private FpgaDestination dataDestination;
private FpgaDestination instructionDestination;
instance.getOutputPort("fabric_out").connect((Module.SinkPort)outPort);
}
+ public static class TorpedoBranchModule extends Module {
+ public TorpedoBranchModule() {
+ super("torpedobranch");
+ Module.SourcePort in = createInputPort ("in", WIDTH_PACKET);
+ // FIXME: assumes DISPATCH_PATH is at top of word!!!
+ Module.SinkPort out = createOutputPort("out", WIDTH_WORD-DISPATCH_PATH.valmaskwidth, "");
+ Module.SinkPort torpedo = createOutputPort("torpedo", 0, "");
+ in.hasLatch = false;
+ out.hasLatch = false;
+ torpedo.hasLatch = false;
+
+ addPreCrap("assign out = `packet_data(in);");
+ addPreCrap("assign out_r = in_r && !("+PACKET_TOKEN.verilogVal("in")+");");
+ addPreCrap("assign torpedo_r = in_r && "+PACKET_TOKEN.verilogVal("in")+";");
+ addPreCrap("assign in_a = out_a || torpedo_a;");
+ }
+ }
+
+ public static class FanoutModule extends Module {
+ public FanoutModule(int width) {
+ super("fanout"+width);
+ Module.SourcePort in = createInputPort ("in", width);
+ Module.SinkPort out0 = createOutputPort("out0", width, "");
+ Module.SinkPort out1 = createOutputPort("out1", width, "");
+ in.hasLatch = false;
+ out0.hasLatch = false;
+ out1.hasLatch = false;
+ addPreCrap("assign out0 = in;");
+ addPreCrap("assign out1 = in;");
+ addPreCrap("assign out0_r = in_r;");
+ addPreCrap("assign out1_r = in_r;");
+ addPreCrap("reg in_a__;");
+ addPreCrap("assign in_a = in_a__;");
+ addPreCrap("always @(posedge clk) begin if (out0_a && out1_a) in_a__ <= 1; if (!out0_a && !out1_a) in_a__ <= 0; end");
+ }
+ }
+
+ public static class RequeueModule extends Module {
+ public RequeueModule() {
+ super("requeue");
+ Module.SourcePort fabric_in = createInputPort ("fabric_in", WIDTH_WORD-DISPATCH_PATH.valmaskwidth);
+ Module.SourcePort ondeck_in = createInputPort ("ondeck_in", WIDTH_WORD-DISPATCH_PATH.valmaskwidth);
+ Module.SourcePort olc_in = createInputPort ("olc_in", SET_OLC_FROM_IMMEDIATE.valmaskwidth);
+ Module.SinkPort out = createOutputPort("out", WIDTH_WORD-DISPATCH_PATH.valmaskwidth, "");
+ out.hasLatch = true;
+
+ Module.StateWire using = new StateWire("using", false);
+ Module.StateWire circulating = new StateWire("circulating", false);
+
+ // always: discard one-shot instructions
+ new Event(new Object[] { ondeck_in, /*olc_in,*/ OS.verilog(ondeck_in.getName()) },
+ new Action[] { ondeck_in, /*olc_in */});
+
+ new Event(new Object[] { circulating.isEmpty(), fabric_in, TAIL.verilog(fabric_in.getName()) },
+ new Action[] { circulating.doFill(), fabric_in });
+ new Event(new Object[] { circulating.isEmpty(), fabric_in, "!("+TAIL.verilog(fabric_in.getName())+")" },
+ new Action[] { fabric_in, out, new AssignAction(out, fabric_in) });
+ new Event(new Object[] { using.isEmpty(), ondeck_in, /*olc_in,*/ "!("+OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
+ new Action[] { ondeck_in, /*olc_in */ });
+ new Event(new Object[] { using.isEmpty(), ondeck_in, /*olc_in,*/ "!("+OS.verilog(ondeck_in.getName())+")", "olc_in!=0" },
+ new Action[] { using.doFill() });
+ new Event(new Object[] { circulating.isFull(), using.isFull(), ondeck_in, /*olc_in,*/ "!("+OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
+ new Action[] { circulating.doDrain(), using.doDrain(), ondeck_in, /*olc_in */});
+ new Event(new Object[] { circulating.isFull(), using.isFull(), ondeck_in, /*olc_in,*/ "!("+OS.verilog(ondeck_in.getName())+")", "olc_in!=0" },
+ new Action[] { ondeck_in, out, /*olc_in,*/ new AssignAction(out, ondeck_in) });
+
+ }
+ }
+
public static class DockModule extends Module {
public DockModule(boolean inbox) {
super(inbox ? "inbox" : "outbox");
- /*
- Module horn = new HornModule();
- Module funnel = new FunnelModule();
- Module.SourcePort instruction = createInputPort("instruction", WIDTH_PACKET);
- Module.SourcePort fabric_in = createInputPort("fabric_in", WIDTH_PACKET);
- Module.SinkPort fabric_out = createOutputPort("fabric_out", WIDTH_PACKET, "");
- if (!inbox) {
- FunnelModule.FunnelInstance f0 = new FunnelModule.FunnelInstance(this, instruction, fabric_in);
- Module.SourcePort ship_out = createInputPort("ship", WIDTH_WORD);
- FunnelModule.FunnelInstance f1 = new FunnelModule.FunnelInstance(this, f0.getOutputPort(), ship_out);
- f1.addOutput(f0, fabric_out);
- } else {
- Module.SinkPort ship_in = createOutputPort("ship", WIDTH_PACKET, "");
- instruction.connect(fabric_out);
- fabric_in.connect(ship_in);
- }
- */
-
int dfifo_width = inbox ? WIDTH_WORD+1 : 1;
// FIXME: assumes DISPATCH_PATH is at top of word!!!
Module ififo_m = new FifoModule(INSTRUCTION_FIFO_SIZE, WIDTH_WORD-DISPATCH_PATH.valmaskwidth);
- Module efifo_m = new FifoModule(EPILOGUE_FIFO_SIZE, WIDTH_WORD-DISPATCH_PATH.valmaskwidth);
Module dfifo_m = new FifoModule(DATA_FIFO_SIZE, dfifo_width);
- Module.SourcePort instruction = createInputPort("instruction", WIDTH_PACKET);
- instruction.hasLatch = true;
+ Module.SourcePort instruction = createInputPort("instruction", WIDTH_PACKET);
Module.SourcePort fabric_in = createInputPort("fabric_in", WIDTH_PACKET);
// FIXME: at inboxes, no need for a full set of latches
Module.SinkPort ship_in = null;
if (inbox) {
- ship_in = createOutputPort("ship", WIDTH_WORD, "");
+ ship_in = createOutputPort("ship", WIDTH_WORD+1, "");
ship_in.hasLatch = true;
}
Module.Latch flag_b = new Latch("flag_b", 1);
Module.Latch flag_c = new Latch("flag_c", 1);
- Module.StateWire isHatchOpen = new StateWire("hatch", true);
- Module.StateWire proceed = new StateWire("proceed", false);
+ Module.StateWire torpedoWaiting = new StateWire("torpedoWaiting", false);
Module.SinkPort token_out = fabric_out;
Module.SourcePort token_in = dfifo_out;
Module.InstantiatedModule ififo = new Module.InstantiatedModule(this, ififo_m);
Module.SinkPort ififo_in = ififo.getInputPort("in");
- ififo_in.hasLatch = false;
- ififo_in.forceNoLatch = true;
-
Module.SourcePort ififo_out = ififo.getOutputPort("out");
- Module.InstantiatedModule efifo = new Module.InstantiatedModule(this, efifo_m);
- Module.SinkPort efifo_in = efifo.getInputPort("in");
- Module.SourcePort efifo_out = efifo.getOutputPort("out");
- efifo_in.hasLatch = false;
- efifo_in.forceNoLatch = true;
+ Module.SinkPort data_latch_output_p = createWirePort("data_latch_output", inbox ? WIDTH_WORD+1 : WIDTH_WORD);
- Module.SinkPort data_latch_output_p = createWirePort("data_latch_output", WIDTH_WORD);
- Module.SinkPort data_latch_input_p = createWirePort("data_latch_input", inbox ? WIDTH_WORD : WIDTH_WORD+1);
+ Module.InstantiatedModule torpedo_branch = new Module.InstantiatedModule(this, new TorpedoBranchModule());
+ instruction.connect(torpedo_branch.getInputPort("in"));
+ Module.SourcePort efifo_out = torpedo_branch.getOutputPort("out");
+ Module.SourcePort torpedo_branch_torpedo = torpedo_branch.getOutputPort("torpedo");
+
+ Module.InstantiatedModule fanout_module = new Module.InstantiatedModule(this, new FanoutModule(WIDTH_WORD-DISPATCH_PATH.valmaskwidth));
+ Module.SinkPort fanout_module_in = fanout_module.getInputPort("in");
+ Module.SourcePort fanout_module_out0 = fanout_module.getOutputPort("out0");
+ Module.SourcePort fanout_module_out1 = fanout_module.getOutputPort("out1");
+
+ Module.InstantiatedModule requeue_module = new Module.InstantiatedModule(this, new RequeueModule());
+ Module.SinkPort requeue_fabric_in = requeue_module.getInputPort("fabric_in");
+ Module.SinkPort requeue_ondeck = requeue_module.getInputPort("ondeck_in");
+ Module.SinkPort requeue_olc_in = requeue_module.getInputPort("olc_in");
+ Module.SourcePort requeue_out = requeue_module.getOutputPort("out");
+
+ efifo_out.connect(requeue_fabric_in);
+ requeue_out.connect(ififo_in);
+ ififo_out.connect(fanout_module_in);
+ fanout_module_out0.connect(requeue_ondeck);
+ Module.SourcePort ondeck = fanout_module_out1;
- // FIXME
- addPreCrap("wire ["+(ififo_out.width-1)+":0] ondeck;");
- addPreCrap("wire ["+(Math.max(repeat_counter.width,loop_counter.width)-1)+":0] decremented;");
addPreCrap("assign data_latch_output = " + (inbox ? data_out.getName() : "`packet_data("+data_out.getName()+")")+";");
- addPreCrap("assign data_latch_input = " + (inbox ? data_in.getName() : data_in.getName())+";");
- addPreCrap("assign "+efifo_in.getName()+" = `packet_data("+instruction.getName()+");");
- addPreCrap("assign "+ififo_in.getName()+" = hatch ? "+efifo_out.getName()+" : ondeck;");
- addPreCrap("assign ondeck = "+ififo_out.getName()+";");
- addPreCrap("assign decremented = ("+SET_OLC_FROM_OLC_MINUS_ONE.verilog("ondeck")+" ? {1'b0, loop_counter} : repeat_counter)-1;");
+ addPreCrap("wire ["+(Math.max(repeat_counter.width,loop_counter.width)-1)+":0] decremented;");
+ addPreCrap("assign decremented = ("+SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName())+" ? {1'b0, loop_counter} : repeat_counter)-1;");
+ addPreCrap("assign "+requeue_olc_in.getName()+" = loop_counter;");
Assignable data_latch = new SimpleAssignable(inbox ? data_out.getName() : "`packet_data("+data_out.getName()+")");
- String data_latch_input = "data_latch_input";
+ String data_latch_input = inbox ? data_in.getName() : data_in.getName();
- // Open the Hatch
- new Event(new Object[] { "loop_counter==0" },
- new Action[] { isHatchOpen.doFill() });
+ String magic_standing_value = "(1<<"+SET_ILC_FROM_IMMEDIATE.valmaskwidth+")";
+ String done_executing = "(repeat_counter==0 || repeat_counter==1 || !"+MOVE.verilog(ondeck.getName())+")";
// Torpedo Arrival
- new Event(new Object[] { instruction,
- PACKET_TOKEN.verilogVal("instruction"),
- ififo_out,
- I.verilog("ondeck") },
- new Action[] { instruction,
- ififo_out,
- new AssignAction(loop_counter, "0"),
- new AssignAction(repeat_counter, "1"),
- isHatchOpen.doFill() });
- // Non-Torpedo Arrival
- new Event(new Object[] { instruction, efifo_in, "!("+PACKET_TOKEN.verilogVal("instruction")+")" },
- new Action[] { efifo_in });
- new Event(new Object[] { efifo_in.getName()+"_a" },
- new Action[] { new SimpleAction(instruction.getName()+"_a <= 1;") });
-
- // Tail
- new Event(new Object[] { efifo_out, ififo_in, isHatchOpen.isFull(), TAIL.verilog(efifo_out.getName()) },
- new Action[] { efifo_out, isHatchOpen.doDrain() } );
- // Enqueue
- new Event(new Object[] { efifo_out, ififo_in, isHatchOpen.isFull(), "!("+TAIL.verilog(efifo_out.getName())+")" },
- new Action[] { efifo_out, ififo_in } );
-
- // Execute
- new Event(new Object[] { ififo_out, ififo_in, proceed.isFull() },
- new Action[] { ififo_out, proceed.doDrain() });
- new Event(
- new Object[] { ififo_out,
+ new Event(new Object[] { torpedo_branch_torpedo, torpedoWaiting.isEmpty() },
+ new Action[] { torpedo_branch_torpedo, torpedoWaiting.doFill() });
+
+ String predicate_met =
+ "("+
+ "("+
+ "!"+MOVE.verilog(ondeck.getName())+" || repeat_counter!=0"+
+ ") && ("+
+ "("+
+ P_ALWAYS.verilog(ondeck.getName())+
+ ") || ("+
+ P_OLC_ZERO.verilog(ondeck.getName())+"==(loop_counter==0)"+
+ ")"+
+ ") && ("+
+ " " + P_A.verilog(ondeck.getName())+" ? flag_a"+
+ ":" + P_B.verilog(ondeck.getName())+" ? flag_b"+
+ ":" + P_NOT_A.verilog(ondeck.getName())+" ? !flag_a"+
+ ":" + P_NOT_B.verilog(ondeck.getName())+" ? !flag_b "+
+ ": 1"+
+ ")"+
+ ")";
+
+ // Torpedo strikes
+ new Event(new Object[] {
+ ondeck,
+ data_out,
+ token_out,
+ predicate_met,
+ MOVE.verilog(ondeck.getName()),
+ I.verilog(ondeck.getName()),
+ torpedoWaiting.isFull()
+ },
+ new Object[] {
+ ondeck,
+ torpedoWaiting.doDrain(),
+ new AssignAction(loop_counter, "0"),
+ new AssignAction(repeat_counter, "1")
+ });
+
+ // Predicate not met
+ new Event(new Object[] { ondeck, "!("+predicate_met+")" },
+ new Action[] { ondeck });
+
+ new Event(new Object[] { ondeck,
data_out,
token_out,
- ififo_in,
- proceed.isEmpty(),
- "(!`predicate_met(ondeck) || "+OS.verilog("ondeck")+" || !hatch)",
- new ConditionalTrigger("(`predicate_met(ondeck) && `instruction_bit_datain(ondeck))", data_in),
- new ConditionalTrigger("(`predicate_met(ondeck) && `instruction_bit_tokenin(ondeck))", token_in)
+ predicate_met,
+ "(!"+MOVE.verilog(ondeck.getName())+" || !"+I.verilog(ondeck.getName())+" || !"+torpedoWaiting.isFull()+")",
+ new ConditionalTrigger(DI.verilog(ondeck.getName()), data_in),
+ new ConditionalTrigger(TI.verilog(ondeck.getName()), token_in)
},
new Action[] {
- new ConditionalAction(" `done_executing(ondeck) && "+MOVE.verilog("ondeck"), new AssignAction(repeat_counter, "1")),
- new ConditionalAction("!`should_requeue(ondeck) && `done_executing(ondeck)", ififo_out),
- new ConditionalAction(" `should_requeue(ondeck) && `done_executing(ondeck)", ififo_in),
- new ConditionalAction(" `should_requeue(ondeck) && `done_executing(ondeck)", proceed.doFill()),
- new ConditionalAction("!`done_executing(ondeck)",
+ new ConditionalAction(done_executing+" && "+MOVE.verilog(ondeck.getName()), new AssignAction(repeat_counter, "1")),
+ new ConditionalAction(done_executing, ondeck),
+ new ConditionalAction("!"+done_executing,
new AssignAction(repeat_counter,
- "repeat_counter==`magic_standing_value?`magic_standing_value:decremented"))
- });
- new Event(
- new Object[] { ififo_out,
- data_out,
- token_out,
- ififo_in,
- proceed.isEmpty(),
- "`predicate_met(ondeck)",
- "("+OS.verilog("ondeck")+" || !hatch)",
- new ConditionalTrigger("`instruction_bit_datain(ondeck)", data_in),
- new ConditionalTrigger("`instruction_bit_tokenin(ondeck)", token_in)
- },
- new Action[] {
- new ConditionalAction(SET_OLC_FROM_DATA_LATCH.verilog("ondeck"), new AssignAction(loop_counter, "data_latch_output")),
- new ConditionalAction(SET_OLC_FROM_IMMEDIATE.verilog("ondeck"),
- new AssignAction(loop_counter, SET_OLC_FROM_IMMEDIATE.verilogVal("ondeck"))),
- new ConditionalAction(SET_OLC_FROM_OLC_MINUS_ONE.verilog("ondeck"),
+ "repeat_counter=="+magic_standing_value+"?"+magic_standing_value+":decremented")),
+
+ new ConditionalAction(SET_OLC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(loop_counter, "data_latch_output")),
+ new ConditionalAction(SET_OLC_FROM_IMMEDIATE.verilog(ondeck.getName()),
+ new AssignAction(loop_counter, SET_OLC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),
+ new ConditionalAction(SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName()),
new AssignAction(loop_counter, "loop_counter==0 ? 0 : decremented")),
- new ConditionalAction(SET_ILC_FROM_DATA_LATCH.verilog("ondeck"), new AssignAction(repeat_counter, "data_latch_output")),
- new ConditionalAction(SET_ILC_FROM_IMMEDIATE.verilog("ondeck"),
- new AssignAction(repeat_counter, SET_ILC_FROM_IMMEDIATE.verilogVal("ondeck"))),
- new ConditionalAction(SET_ILC_FROM_INFINITY.verilog("ondeck"), new AssignAction(repeat_counter, "`magic_standing_value")),
- new ConditionalAction(SHIFT.verilog("ondeck"),
+ new ConditionalAction(SET_ILC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(repeat_counter, "data_latch_output")),
+ new ConditionalAction(SET_ILC_FROM_IMMEDIATE.verilog(ondeck.getName()),
+ new AssignAction(repeat_counter, SET_ILC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),
+ new ConditionalAction(SET_ILC_FROM_INFINITY.verilog(ondeck.getName()), new AssignAction(repeat_counter, magic_standing_value)),
+ new ConditionalAction(SHIFT.verilog(ondeck.getName()),
new AssignAction(data_latch,
"{ data_latch_output["+(WIDTH_WORD-1-SHIFT.valmaskwidth)+":0], "+
- SHIFT.verilogVal("ondeck")+"}")),
- new ConditionalAction(SET_IMMEDIATE.verilog("ondeck"),
+ SHIFT.verilogVal(ondeck.getName())+"}")),
+ new ConditionalAction(SET_IMMEDIATE.verilog(ondeck.getName()),
new AssignAction(data_latch,
"{ {"+(WIDTH_WORD-FleetTwoFleet.DataLatch_WIDTH)+
- "{"+SET_IMMEDIATE_EXTEND.verilogVal("ondeck")+"}}, "+
- SET_IMMEDIATE.verilogVal("ondeck")+" }")),
- new ConditionalAction(SET_FLAGS.verilog("ondeck"), new AssignAction(flag_a, "`new_flag_a(ondeck)")),
- new ConditionalAction(SET_FLAGS.verilog("ondeck"), new AssignAction(flag_b, "`new_flag_b(ondeck)")),
+ "{"+SET_IMMEDIATE_EXTEND.verilogVal(ondeck.getName())+"}}, "+
+ SET_IMMEDIATE.verilogVal(ondeck.getName())+" }")),
+ new ConditionalAction(SET_FLAGS.verilog(ondeck.getName()), new AssignAction(flag_a, "`new_flag_a("+ondeck.getName()+")")),
+ new ConditionalAction(SET_FLAGS.verilog(ondeck.getName()), new AssignAction(flag_b, "`new_flag_b("+ondeck.getName()+")")),
new ConditionalAction(inbox
- ? "(`instruction_bit_datain(ondeck) || `instruction_bit_tokenin(ondeck))"
- : "(!`instruction_bit_datain(ondeck) && `instruction_bit_tokenin(ondeck))",
+ ? "("+DI.verilog(ondeck.getName())+" || "+TI.verilog(ondeck.getName())+")"
+ : "(!"+DI.verilog(ondeck.getName())+" && "+TI.verilog(ondeck.getName())+")",
new AssignAction(flag_c, dfifo_out.getBits(dfifo_width-1, dfifo_width-1))),
- inbox?null:new ConditionalAction("`instruction_bit_datain(ondeck)", new AssignAction(flag_c, "data_latch_input["+WIDTH_WORD+"]")),
- new ConditionalAction("`instruction_bit_datain(ondeck)", data_in),
- new ConditionalAction("`instruction_bit_dataout(ondeck)", data_out),
- new ConditionalAction("`instruction_bit_tokenin(ondeck)", token_in),
- new ConditionalAction("`instruction_bit_tokenout(ondeck)", token_out),
- new ConditionalAction("`instruction_bit_latch(ondeck)", new AssignAction(data_latch, data_latch_input)),
- new AssignAction(new SimpleAssignable("`packet_token("+token_out.getName()+")"), "`instruction_bit_tokenout(ondeck)?1:0"),
- new ConditionalAction("`instruction_path_from_data(ondeck)",
- new AssignAction(new SimpleAssignable("`packet_signal_and_dest("+token_out.getName()+")"),
+ new ConditionalAction(DI.verilog(ondeck.getName()), data_in),
+ new ConditionalAction(DO.verilog(ondeck.getName()), data_out),
+ new ConditionalAction(FLUSH.verilog(ondeck.getName()), data_out),
+ inbox
+ ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+WIDTH_WORD+"]"), FLUSH.verilog(ondeck.getName())+"?1:0")
+ : new ConditionalAction(DI.verilog(ondeck.getName()), new AssignAction(flag_c, data_latch_input+"["+WIDTH_WORD+"]")),
+ new ConditionalAction(TI.verilog(ondeck.getName()), token_in),
+ new ConditionalAction(TO.verilog(ondeck.getName()), token_out),
+ new ConditionalAction(DC.verilog(ondeck.getName()), new AssignAction(data_latch, data_latch_input)),
+ new AssignAction(new SimpleAssignable("`packet_token("+token_out.getName()+")"), "("+TO.verilog(ondeck.getName())+")?1:0"),
+ new ConditionalAction(PATH_DATA.verilog(ondeck.getName()),
+ new AssignAction(new SimpleAssignable("{ "+PACKET_SIGNAL.verilogVal(token_out.getName())+", "+
+ PACKET_DEST.verilogVal(token_out.getName())+" }"),
DISPATCH_PATH.verilogVal(data_latch_input))),
- new ConditionalAction("`instruction_path_from_immediate(ondeck)",
- new AssignAction(new SimpleAssignable("`packet_signal_and_dest("+token_out.getName()+")"),
- "`instruction_path_immediate(ondeck)")),
+ new ConditionalAction(PATH_IMMEDIATE.verilog(ondeck.getName()),
+ new AssignAction(new SimpleAssignable("{ "+PACKET_SIGNAL.verilogVal(token_out.getName())+", "+
+ PACKET_DEST.verilogVal(token_out.getName())+" }"),
+ PATH_IMMEDIATE.verilogVal(ondeck.getName()))),
}
);
-
}
public void dump(PrintWriter pw, boolean fix) {
-
- pw.println("`define packet_signal_and_dest(p) { "+PACKET_SIGNAL.verilogVal("p")+", "+PACKET_DEST.verilogVal("p")+" }");
- pw.println("`define instruction_repeat_count_immediate(i) "+SET_ILC_FROM_IMMEDIATE.verilogVal("i"));
- pw.println("`define instruction_loop_count_immediate(i) "+SET_OLC_FROM_IMMEDIATE.verilogVal("i"));
-
- pw.println("`define instruction_path_immediate(i) "+PATH_IMMEDIATE.verilogVal("i"));
- pw.println("`define instruction_path_from_immediate(i) "+PATH_IMMEDIATE.verilog("i"));
- pw.println("`define instruction_path_from_data(i) "+PATH_DATA.verilog("i"));
-
- pw.println("`define instruction_bit_tokenout(i) ("+MOVE.verilog("i")+" && "+TO.verilog("i")+")");
- pw.println("`define instruction_bit_dataout(i) ("+MOVE.verilog("i")+" && "+DO.verilog("i")+")");
- pw.println("`define instruction_bit_latch(i) ("+MOVE.verilog("i")+" && "+DC.verilog("i")+")");
- pw.println("`define instruction_bit_datain(i) ("+MOVE.verilog("i")+" && "+DI.verilog("i")+")");
- pw.println("`define instruction_bit_tokenin(i) ("+MOVE.verilog("i")+" && "+TI.verilog("i")+")");
- pw.println("`define should_requeue(i) (loop_counter!=0 && !("+OS.verilog("i")+"))");
- pw.println("`define predicate_met(i) ("+
- "("+
- "!"+MOVE.verilog("i")+" || repeat_counter!=0"+
- ") && ("+
- "("+
- P_ALWAYS.verilog("i")+
- ") || ("+
- P_OLC_ZERO.verilog("i")+"==(loop_counter==0)"+
- ")"+
- ") && ("+
- " " + P_A.verilog("i")+" ? flag_a"+
- ":" + P_B.verilog("i")+" ? flag_b"+
- ":" + P_NOT_A.verilog("i")+" ? !flag_a"+
- ":" + P_NOT_B.verilog("i")+" ? !flag_b "+
- ": 1"+
- ")"+
- ")");
pw.println("`define new_flag(x) ("+
"( ((x >> 0) & 1) & !flag_c) |" +
"( ((x >> 1) & 1) & flag_c) |" +
")");
pw.println("`define new_flag_a(i) `new_flag("+SET_FLAGS_A.verilogVal("i")+")");
pw.println("`define new_flag_b(i) `new_flag("+SET_FLAGS_B.verilogVal("i")+")");
- pw.println("`define done_executing(i) (repeat_counter==0 || repeat_counter==1 || !"+MOVE.verilog("i")+")");
-
- pw.println("`define magic_standing_value (1<<"+SET_ILC_FROM_IMMEDIATE.valmaskwidth+")");
-
super.dump(pw,fix);
}
}
this.module = new Module(getType().toLowerCase());
this.instance = new Module.InstantiatedModule(fleet.getVerilogModule(), module);
for(DockDescription sdbb : sd) {
- if (sdbb.isInputDock()) module.createInputPort(sdbb.getName(), WIDTH_WORD);
+ if (sdbb.isInputDock()) module.createInputPort(sdbb.getName(), WIDTH_WORD+1);
else module.createOutputPort(sdbb.getName(), WIDTH_WORD+1, "");
ports.put(sdbb.getName(), new FpgaDock(this, sdbb));
}
#### Module DDR2_SDRAM constraints
-# Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin LOC=AA25;
-# Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<0> LOC=H28;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<0> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<1> LOC=K28;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<1> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<2> LOC=L28;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<2> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<3> LOC=M25;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<3> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<4> LOC=Y24;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<4> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<5> LOC=N27;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<5> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<6> LOC=AD26;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<6> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<7> LOC=AC25;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<7> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<8> LOC=R26;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<8> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<9> LOC=R28;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<9> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<10> LOC=T26;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<10> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<11> LOC=T28;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<11> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<12> LOC=U27;
-# Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<12> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<0> LOC=V28;
-# Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<0> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<1> LOC=W26;
-# Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<1> IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin LOC=R31;
-# Net fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_CE_pin LOC=AJ31;
-# Net fpga_0_DDR2_SDRAM_DDR2_CE_pin IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin LOC=AJ30;
-# Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin LOC=R32;
-# Net fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_WE_n_pin LOC=T31;
-# Net fpga_0_DDR2_SDRAM_DDR2_WE_n_pin IOSTANDARD = SSTL18_I;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=AH30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=M31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> LOC=T30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> LOC=U28;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=AJ32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=AG31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=AG30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=AF29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<0> LOC=F29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<0> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<1> LOC=K29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<1> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<2> LOC=P27;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<2> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<3> LOC=P32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<3> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<4> LOC=W27;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<4> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<5> LOC=W31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<5> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<6> LOC=AG32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<6> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<7> LOC=AE32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS<7> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<0> LOC=E29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<0> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<1> LOC=J29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<1> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<2> LOC=P26;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<2> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<3> LOC=N32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<3> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<4> LOC=V27;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<4> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<5> LOC=W30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<5> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<6> LOC=AH32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<6> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<7> LOC=AE31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQS_n<7> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<0> LOC=C32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<0> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<1> LOC=D32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<1> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<2> LOC=E32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<2> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<3> LOC=G32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<3> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<4> LOC=H32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<4> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<5> LOC=J32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<5> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<6> LOC=K32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<6> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<7> LOC=M32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<7> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<8> LOC=N28;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<8> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<9> LOC=D31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<9> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<10> LOC=E31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<10> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<11> LOC=F31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<11> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<12> LOC=G31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<12> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<13> LOC=J31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<13> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<14> LOC=K31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<14> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<15> LOC=L31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<15> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<16> LOC=C30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<16> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<17> LOC=D30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<17> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<18> LOC=F30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<18> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<19> LOC=G30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<19> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<20> LOC=Y28;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<20> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<21> LOC=Y27;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<21> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<22> LOC=L30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<22> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<23> LOC=M30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<23> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<24> LOC=N30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<24> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<25> LOC=C29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<25> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<26> LOC=D29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<26> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<27> LOC=J30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<27> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<28> LOC=L29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<28> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<29> LOC=N29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<29> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<30> LOC=P29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<30> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<31> LOC=R29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<31> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<32> LOC=T29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<32> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<33> LOC=U32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<33> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<34> LOC=V32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<34> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<35> LOC=W32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<35> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<36> LOC=Y32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<36> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<37> LOC=AB32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<37> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<38> LOC=AC32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<38> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<39> LOC=AD32;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<39> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<40> LOC=AB27;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<40> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<41> LOC=U31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<41> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<42> LOC=W25;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<42> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<43> LOC=Y31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<43> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<44> LOC=AA31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<44> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<45> LOC=AB31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<45> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<46> LOC=AD31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<46> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<47> LOC=AB28;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<47> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<48> LOC=AF31;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<48> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<49> LOC=U30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<49> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<50> LOC=V30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<50> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<51> LOC=Y26;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<51> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<52> LOC=AA30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<52> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<53> LOC=AB30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<53> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<54> LOC=AC30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<54> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<55> LOC=AD30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<55> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<56> LOC=AF30;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<56> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<57> LOC=V29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<57> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<58> LOC=W29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<58> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<59> LOC=Y29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<59> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<60> LOC=AA29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<60> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<61> LOC=AC29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<61> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<62> LOC=AD29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<62> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<63> LOC=AE29;
-# Net fpga_0_DDR2_SDRAM_DDR2_DQ<63> IOSTANDARD = SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin LOC=H30;
-# Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin IOSTANDARD = DIFF_SSTL18_II;
-# Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin LOC=H29;
-# Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin IOSTANDARD = DIFF_SSTL18_II;
+Net ddr2_ODT_pin LOC=AA25;
+Net ddr2_ODT_pin IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<0> LOC=H28;
+Net ddr2_Addr_pin<0> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<1> LOC=K28;
+Net ddr2_Addr_pin<1> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<2> LOC=L28;
+Net ddr2_Addr_pin<2> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<3> LOC=M25;
+Net ddr2_Addr_pin<3> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<4> LOC=Y24;
+Net ddr2_Addr_pin<4> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<5> LOC=N27;
+Net ddr2_Addr_pin<5> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<6> LOC=AD26;
+Net ddr2_Addr_pin<6> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<7> LOC=AC25;
+Net ddr2_Addr_pin<7> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<8> LOC=R26;
+Net ddr2_Addr_pin<8> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<9> LOC=R28;
+Net ddr2_Addr_pin<9> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<10> LOC=T26;
+Net ddr2_Addr_pin<10> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<11> LOC=T28;
+Net ddr2_Addr_pin<11> IOSTANDARD = SSTL18_I;
+Net ddr2_Addr_pin<12> LOC=U27;
+Net ddr2_Addr_pin<12> IOSTANDARD = SSTL18_I;
+Net ddr2_BankAddr_pin<0> LOC=V28;
+Net ddr2_BankAddr_pin<0> IOSTANDARD = SSTL18_I;
+Net ddr2_BankAddr_pin<1> LOC=W26;
+Net ddr2_BankAddr_pin<1> IOSTANDARD = SSTL18_I;
+Net ddr2_CAS_n_pin LOC=R31;
+Net ddr2_CAS_n_pin IOSTANDARD = SSTL18_I;
+Net ddr2_CE_pin LOC=AJ31;
+Net ddr2_CE_pin IOSTANDARD = SSTL18_I;
+Net ddr2_CS_n_pin LOC=AJ30;
+Net ddr2_CS_n_pin IOSTANDARD = SSTL18_I;
+Net ddr2_RAS_n_pin LOC=R32;
+Net ddr2_RAS_n_pin IOSTANDARD = SSTL18_I;
+Net ddr2_WE_n_pin LOC=T31;
+Net ddr2_WE_n_pin IOSTANDARD = SSTL18_I;
+Net ddr2_DM_pin<0> LOC=AH30;
+Net ddr2_DM_pin<0> IOSTANDARD = SSTL18_II;
+Net ddr2_DM_pin<1> LOC=M31;
+Net ddr2_DM_pin<1> IOSTANDARD = SSTL18_II;
+Net ddr2_DM_pin<2> LOC=T30;
+Net ddr2_DM_pin<2> IOSTANDARD = SSTL18_II;
+Net ddr2_DM_pin<3> LOC=U28;
+Net ddr2_DM_pin<3> IOSTANDARD = SSTL18_II;
+Net ddr2_DM_pin<4> LOC=AJ32;
+Net ddr2_DM_pin<4> IOSTANDARD = SSTL18_II;
+Net ddr2_DM_pin<5> LOC=AG31;
+Net ddr2_DM_pin<5> IOSTANDARD = SSTL18_II;
+Net ddr2_DM_pin<6> LOC=AG30;
+Net ddr2_DM_pin<6> IOSTANDARD = SSTL18_II;
+Net ddr2_DM_pin<7> LOC=AF29;
+Net ddr2_DM_pin<7> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS<0> LOC=F29;
+Net ddr2_DQS<0> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS<1> LOC=K29;
+Net ddr2_DQS<1> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS<2> LOC=P27;
+Net ddr2_DQS<2> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS<3> LOC=P32;
+Net ddr2_DQS<3> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS<4> LOC=W27;
+Net ddr2_DQS<4> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS<5> LOC=W31;
+Net ddr2_DQS<5> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS<6> LOC=AG32;
+Net ddr2_DQS<6> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS<7> LOC=AE32;
+Net ddr2_DQS<7> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS_n<0> LOC=E29;
+Net ddr2_DQS_n<0> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS_n<1> LOC=J29;
+Net ddr2_DQS_n<1> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS_n<2> LOC=P26;
+Net ddr2_DQS_n<2> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS_n<3> LOC=N32;
+Net ddr2_DQS_n<3> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS_n<4> LOC=V27;
+Net ddr2_DQS_n<4> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS_n<5> LOC=W30;
+Net ddr2_DQS_n<5> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS_n<6> LOC=AH32;
+Net ddr2_DQS_n<6> IOSTANDARD = SSTL18_II;
+Net ddr2_DQS_n<7> LOC=AE31;
+Net ddr2_DQS_n<7> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<0> LOC=C32;
+Net ddr2_DQ<0> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<1> LOC=D32;
+Net ddr2_DQ<1> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<2> LOC=E32;
+Net ddr2_DQ<2> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<3> LOC=G32;
+Net ddr2_DQ<3> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<4> LOC=H32;
+Net ddr2_DQ<4> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<5> LOC=J32;
+Net ddr2_DQ<5> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<6> LOC=K32;
+Net ddr2_DQ<6> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<7> LOC=M32;
+Net ddr2_DQ<7> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<8> LOC=N28;
+Net ddr2_DQ<8> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<9> LOC=D31;
+Net ddr2_DQ<9> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<10> LOC=E31;
+Net ddr2_DQ<10> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<11> LOC=F31;
+Net ddr2_DQ<11> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<12> LOC=G31;
+Net ddr2_DQ<12> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<13> LOC=J31;
+Net ddr2_DQ<13> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<14> LOC=K31;
+Net ddr2_DQ<14> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<15> LOC=L31;
+Net ddr2_DQ<15> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<16> LOC=C30;
+Net ddr2_DQ<16> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<17> LOC=D30;
+Net ddr2_DQ<17> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<18> LOC=F30;
+Net ddr2_DQ<18> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<19> LOC=G30;
+Net ddr2_DQ<19> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<20> LOC=Y28;
+Net ddr2_DQ<20> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<21> LOC=Y27;
+Net ddr2_DQ<21> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<22> LOC=L30;
+Net ddr2_DQ<22> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<23> LOC=M30;
+Net ddr2_DQ<23> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<24> LOC=N30;
+Net ddr2_DQ<24> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<25> LOC=C29;
+Net ddr2_DQ<25> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<26> LOC=D29;
+Net ddr2_DQ<26> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<27> LOC=J30;
+Net ddr2_DQ<27> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<28> LOC=L29;
+Net ddr2_DQ<28> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<29> LOC=N29;
+Net ddr2_DQ<29> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<30> LOC=P29;
+Net ddr2_DQ<30> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<31> LOC=R29;
+Net ddr2_DQ<31> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<32> LOC=T29;
+Net ddr2_DQ<32> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<33> LOC=U32;
+Net ddr2_DQ<33> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<34> LOC=V32;
+Net ddr2_DQ<34> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<35> LOC=W32;
+Net ddr2_DQ<35> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<36> LOC=Y32;
+Net ddr2_DQ<36> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<37> LOC=AB32;
+Net ddr2_DQ<37> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<38> LOC=AC32;
+Net ddr2_DQ<38> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<39> LOC=AD32;
+Net ddr2_DQ<39> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<40> LOC=AB27;
+Net ddr2_DQ<40> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<41> LOC=U31;
+Net ddr2_DQ<41> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<42> LOC=W25;
+Net ddr2_DQ<42> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<43> LOC=Y31;
+Net ddr2_DQ<43> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<44> LOC=AA31;
+Net ddr2_DQ<44> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<45> LOC=AB31;
+Net ddr2_DQ<45> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<46> LOC=AD31;
+Net ddr2_DQ<46> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<47> LOC=AB28;
+Net ddr2_DQ<47> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<48> LOC=AF31;
+Net ddr2_DQ<48> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<49> LOC=U30;
+Net ddr2_DQ<49> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<50> LOC=V30;
+Net ddr2_DQ<50> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<51> LOC=Y26;
+Net ddr2_DQ<51> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<52> LOC=AA30;
+Net ddr2_DQ<52> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<53> LOC=AB30;
+Net ddr2_DQ<53> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<54> LOC=AC30;
+Net ddr2_DQ<54> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<55> LOC=AD30;
+Net ddr2_DQ<55> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<56> LOC=AF30;
+Net ddr2_DQ<56> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<57> LOC=V29;
+Net ddr2_DQ<57> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<58> LOC=W29;
+Net ddr2_DQ<58> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<59> LOC=Y29;
+Net ddr2_DQ<59> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<60> LOC=AA29;
+Net ddr2_DQ<60> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<61> LOC=AC29;
+Net ddr2_DQ<61> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<62> LOC=AD29;
+Net ddr2_DQ<62> IOSTANDARD = SSTL18_II;
+Net ddr2_DQ<63> LOC=AE29;
+Net ddr2_DQ<63> IOSTANDARD = SSTL18_II;
+Net ddr2_Clk_pin LOC=H30;
+Net ddr2_Clk_pin IOSTANDARD = SSTL18_II;
+Net ddr2_Clk_n_pin LOC=H29;
+Net ddr2_Clk_n_pin IOSTANDARD = SSTL18_II;
#### Module DDR_SDRAM constraints
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> LOC=J24;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> LOC=K26;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> LOC=K24;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> LOC=K23;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> LOC=L26;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> LOC=L25;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> LOC=L24;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> LOC=M23;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> LOC=N24;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> LOC=N23;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> LOC=N22;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> LOC=P22;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> LOC=P24;
-Net fpga_0_DDR_SDRAM_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> LOC=J26;
-Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> LOC=J25;
-Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=D26;
-Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=H14;
-Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=C27;
-Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=D27;
-Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=E27;
-Net fpga_0_DDR_SDRAM_DDR_WE_n_pin IOSTANDARD = SSTL2_I;
-Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> LOC=F21;
-Net fpga_0_DDR_SDRAM_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> LOC=G22;
-Net fpga_0_DDR_SDRAM_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> LOC=E23;
-Net fpga_0_DDR_SDRAM_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> LOC=G23;
-Net fpga_0_DDR_SDRAM_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQS<0> LOC=F20;
-Net fpga_0_DDR_SDRAM_DDR_DQS<0> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQS<1> LOC=G20;
-Net fpga_0_DDR_SDRAM_DDR_DQS<1> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQS<2> LOC=G25;
-Net fpga_0_DDR_SDRAM_DDR_DQS<2> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQS<3> LOC=F25;
-Net fpga_0_DDR_SDRAM_DDR_DQS<3> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<0> LOC=E17;
-Net fpga_0_DDR_SDRAM_DDR_DQ<0> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<1> LOC=E18;
-Net fpga_0_DDR_SDRAM_DDR_DQ<1> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<2> LOC=F18;
-Net fpga_0_DDR_SDRAM_DDR_DQ<2> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<3> LOC=G18;
-Net fpga_0_DDR_SDRAM_DDR_DQ<3> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<4> LOC=F19;
-Net fpga_0_DDR_SDRAM_DDR_DQ<4> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<5> LOC=E19;
-Net fpga_0_DDR_SDRAM_DDR_DQ<5> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<6> LOC=D21;
-Net fpga_0_DDR_SDRAM_DDR_DQ<6> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<7> LOC=E21;
-Net fpga_0_DDR_SDRAM_DDR_DQ<7> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<8> LOC=G21;
-Net fpga_0_DDR_SDRAM_DDR_DQ<8> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<9> LOC=H20;
-Net fpga_0_DDR_SDRAM_DDR_DQ<9> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<10> LOC=J20;
-Net fpga_0_DDR_SDRAM_DDR_DQ<10> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<11> LOC=J21;
-Net fpga_0_DDR_SDRAM_DDR_DQ<11> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<12> LOC=K21;
-Net fpga_0_DDR_SDRAM_DDR_DQ<12> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<13> LOC=L21;
-Net fpga_0_DDR_SDRAM_DDR_DQ<13> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<14> LOC=J22;
-Net fpga_0_DDR_SDRAM_DDR_DQ<14> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<15> LOC=H22;
-Net fpga_0_DDR_SDRAM_DDR_DQ<15> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<16> LOC=C22;
-Net fpga_0_DDR_SDRAM_DDR_DQ<16> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<17> LOC=C23;
-Net fpga_0_DDR_SDRAM_DDR_DQ<17> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<18> LOC=C24;
-Net fpga_0_DDR_SDRAM_DDR_DQ<18> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<19> LOC=C25;
-Net fpga_0_DDR_SDRAM_DDR_DQ<19> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<20> LOC=D22;
-Net fpga_0_DDR_SDRAM_DDR_DQ<20> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<21> LOC=D24;
-Net fpga_0_DDR_SDRAM_DDR_DQ<21> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<22> LOC=D25;
-Net fpga_0_DDR_SDRAM_DDR_DQ<22> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<23> LOC=C28;
-Net fpga_0_DDR_SDRAM_DDR_DQ<23> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<24> LOC=F23;
-Net fpga_0_DDR_SDRAM_DDR_DQ<24> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<25> LOC=F24;
-Net fpga_0_DDR_SDRAM_DDR_DQ<25> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<26> LOC=F26;
-Net fpga_0_DDR_SDRAM_DDR_DQ<26> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<27> LOC=G26;
-Net fpga_0_DDR_SDRAM_DDR_DQ<27> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<28> LOC=H25;
-Net fpga_0_DDR_SDRAM_DDR_DQ<28> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<29> LOC=H24;
-Net fpga_0_DDR_SDRAM_DDR_DQ<29> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<30> LOC=E24;
-Net fpga_0_DDR_SDRAM_DDR_DQ<30> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_DQ<31> LOC=E22;
-Net fpga_0_DDR_SDRAM_DDR_DQ<31> IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=F28;
-Net fpga_0_DDR_SDRAM_DDR_Clk_pin IOSTANDARD = SSTL2_II;
-Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=E28;
-Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin IOSTANDARD = SSTL2_II;
+Net ddr1_Addr_pin<12> LOC=J24;
+Net ddr1_Addr_pin<12> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<11> LOC=K26;
+Net ddr1_Addr_pin<11> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<10> LOC=K24;
+Net ddr1_Addr_pin<10> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<9> LOC=K23;
+Net ddr1_Addr_pin<9> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<8> LOC=L26;
+Net ddr1_Addr_pin<8> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<7> LOC=L25;
+Net ddr1_Addr_pin<7> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<6> LOC=L24;
+Net ddr1_Addr_pin<6> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<5> LOC=M23;
+Net ddr1_Addr_pin<5> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<4> LOC=N24;
+Net ddr1_Addr_pin<4> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<3> LOC=N23;
+Net ddr1_Addr_pin<3> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<2> LOC=N22;
+Net ddr1_Addr_pin<2> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<1> LOC=P22;
+Net ddr1_Addr_pin<1> IOSTANDARD = SSTL2_I;
+Net ddr1_Addr_pin<0> LOC=P24;
+Net ddr1_Addr_pin<0> IOSTANDARD = SSTL2_I;
+Net ddr1_BankAddr_pin<1> LOC=J26;
+Net ddr1_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
+Net ddr1_BankAddr_pin<0> LOC=J25;
+Net ddr1_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
+Net ddr1_CAS_n_pin LOC=D26;
+Net ddr1_CAS_n_pin IOSTANDARD = SSTL2_I;
+Net ddr1_CE_pin LOC=H14;
+Net ddr1_CE_pin IOSTANDARD = SSTL2_I;
+Net ddr1_CS_n_pin LOC=C27;
+Net ddr1_CS_n_pin IOSTANDARD = SSTL2_I;
+Net ddr1_RAS_n_pin LOC=D27;
+Net ddr1_RAS_n_pin IOSTANDARD = SSTL2_I;
+Net ddr1_WE_n_pin LOC=E27;
+Net ddr1_WE_n_pin IOSTANDARD = SSTL2_I;
+Net ddr1_DM_pin<0> LOC=F21;
+Net ddr1_DM_pin<0> IOSTANDARD = SSTL2_II;
+Net ddr1_DM_pin<1> LOC=G22;
+Net ddr1_DM_pin<1> IOSTANDARD = SSTL2_II;
+Net ddr1_DM_pin<2> LOC=E23;
+Net ddr1_DM_pin<2> IOSTANDARD = SSTL2_II;
+Net ddr1_DM_pin<3> LOC=G23;
+Net ddr1_DM_pin<3> IOSTANDARD = SSTL2_II;
+Net ddr1_DQS<0> LOC=F20;
+Net ddr1_DQS<0> IOSTANDARD = SSTL2_II;
+Net ddr1_DQS<1> LOC=G20;
+Net ddr1_DQS<1> IOSTANDARD = SSTL2_II;
+Net ddr1_DQS<2> LOC=G25;
+Net ddr1_DQS<2> IOSTANDARD = SSTL2_II;
+Net ddr1_DQS<3> LOC=F25;
+Net ddr1_DQS<3> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<0> LOC=E17;
+Net ddr1_DQ<0> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<1> LOC=E18;
+Net ddr1_DQ<1> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<2> LOC=F18;
+Net ddr1_DQ<2> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<3> LOC=G18;
+Net ddr1_DQ<3> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<4> LOC=F19;
+Net ddr1_DQ<4> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<5> LOC=E19;
+Net ddr1_DQ<5> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<6> LOC=D21;
+Net ddr1_DQ<6> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<7> LOC=E21;
+Net ddr1_DQ<7> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<8> LOC=G21;
+Net ddr1_DQ<8> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<9> LOC=H20;
+Net ddr1_DQ<9> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<10> LOC=J20;
+Net ddr1_DQ<10> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<11> LOC=J21;
+Net ddr1_DQ<11> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<12> LOC=K21;
+Net ddr1_DQ<12> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<13> LOC=L21;
+Net ddr1_DQ<13> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<14> LOC=J22;
+Net ddr1_DQ<14> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<15> LOC=H22;
+Net ddr1_DQ<15> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<16> LOC=C22;
+Net ddr1_DQ<16> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<17> LOC=C23;
+Net ddr1_DQ<17> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<18> LOC=C24;
+Net ddr1_DQ<18> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<19> LOC=C25;
+Net ddr1_DQ<19> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<20> LOC=D22;
+Net ddr1_DQ<20> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<21> LOC=D24;
+Net ddr1_DQ<21> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<22> LOC=D25;
+Net ddr1_DQ<22> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<23> LOC=C28;
+Net ddr1_DQ<23> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<24> LOC=F23;
+Net ddr1_DQ<24> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<25> LOC=F24;
+Net ddr1_DQ<25> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<26> LOC=F26;
+Net ddr1_DQ<26> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<27> LOC=G26;
+Net ddr1_DQ<27> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<28> LOC=H25;
+Net ddr1_DQ<28> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<29> LOC=H24;
+Net ddr1_DQ<29> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<30> LOC=E24;
+Net ddr1_DQ<30> IOSTANDARD = SSTL2_II;
+Net ddr1_DQ<31> LOC=E22;
+Net ddr1_DQ<31> IOSTANDARD = SSTL2_II;
+Net ddr1_Clk_pin LOC=F28;
+Net ddr1_Clk_pin IOSTANDARD = SSTL2_II;
+Net ddr1_Clk_n_pin LOC=E28;
+Net ddr1_Clk_n_pin IOSTANDARD = SSTL2_II;
fpga_0_RS232_Uart_1_sin_pin,
fpga_0_RS232_Uart_1_sout_pin,
- fpga_0_DDR_SDRAM_DDR_Clk_pin,
- fpga_0_DDR_SDRAM_DDR_Clk_n_pin,
- fpga_0_DDR_SDRAM_DDR_Addr_pin,
- fpga_0_DDR_SDRAM_DDR_BankAddr_pin,
- fpga_0_DDR_SDRAM_DDR_CAS_n_pin,
- fpga_0_DDR_SDRAM_DDR_CE_pin,
- fpga_0_DDR_SDRAM_DDR_CS_n_pin,
- fpga_0_DDR_SDRAM_DDR_RAS_n_pin,
- fpga_0_DDR_SDRAM_DDR_WE_n_pin,
- fpga_0_DDR_SDRAM_DDR_DM_pin,
- fpga_0_DDR_SDRAM_DDR_DQS,
- fpga_0_DDR_SDRAM_DDR_DQ,
+ ddr1_Clk_pin,
+ ddr1_Clk_n_pin,
+ ddr1_Addr_pin,
+ ddr1_BankAddr_pin,
+ ddr1_CAS_n_pin,
+ ddr1_CE_pin,
+ ddr1_CS_n_pin,
+ ddr1_RAS_n_pin,
+ ddr1_WE_n_pin,
+ ddr1_DM_pin,
+ ddr1_DQS,
+ ddr1_DQ,
+
+ ddr2_ODT_pin,
+ ddr2_Clk_pin,
+ ddr2_Clk_n_pin,
+ ddr2_Addr_pin,
+ ddr2_BankAddr_pin,
+ ddr2_CAS_n_pin,
+ ddr2_CE_pin,
+ ddr2_CS_n_pin,
+ ddr2_RAS_n_pin,
+ ddr2_WE_n_pin,
+ ddr2_DM_pin,
+ ddr2_DQS,
+ ddr2_DQS_n,
+ ddr2_DQ,
vga_psave,
vga_hsync,
input fpga_0_RS232_Uart_1_sin_pin;
output fpga_0_RS232_Uart_1_sout_pin;
- output fpga_0_DDR_SDRAM_DDR_Clk_pin;
- output fpga_0_DDR_SDRAM_DDR_Clk_n_pin;
- output [12:0] fpga_0_DDR_SDRAM_DDR_Addr_pin;
- output [1:0] fpga_0_DDR_SDRAM_DDR_BankAddr_pin;
- output fpga_0_DDR_SDRAM_DDR_CAS_n_pin;
- output fpga_0_DDR_SDRAM_DDR_CE_pin;
- output fpga_0_DDR_SDRAM_DDR_CS_n_pin;
- output fpga_0_DDR_SDRAM_DDR_RAS_n_pin;
- output fpga_0_DDR_SDRAM_DDR_WE_n_pin;
- output [3:0] fpga_0_DDR_SDRAM_DDR_DM_pin;
- inout [3:0] fpga_0_DDR_SDRAM_DDR_DQS;
- inout [31:0] fpga_0_DDR_SDRAM_DDR_DQ;
+ output ddr1_Clk_pin;
+ output ddr1_Clk_n_pin;
+ output [12:0] ddr1_Addr_pin;
+ output [1:0] ddr1_BankAddr_pin;
+ output ddr1_CAS_n_pin;
+ output ddr1_CE_pin;
+ output ddr1_CS_n_pin;
+ output ddr1_RAS_n_pin;
+ output ddr1_WE_n_pin;
+ output [3:0] ddr1_DM_pin;
+ inout [3:0] ddr1_DQS;
+ inout [31:0] ddr1_DQ;
+
+ output ddr2_ODT_pin;
+ output ddr2_Clk_pin;
+ output ddr2_Clk_n_pin;
+ output [12:0] ddr2_Addr_pin;
+ output [1:0] ddr2_BankAddr_pin;
+ output ddr2_CAS_n_pin;
+ output ddr2_CE_pin;
+ output ddr2_CS_n_pin;
+ output ddr2_RAS_n_pin;
+ output ddr2_WE_n_pin;
+ output [7:0] ddr2_DM_pin;
+ inout [7:0] ddr2_DQS;
+ inout [7:0] ddr2_DQS_n;
+ inout [63:0] ddr2_DQ;
wire [31:0] dram_addr;
wire dram_addr_r;
wire dram_read_data_empty;
wire [1:0] dram_read_data_latency;
+ wire [31:0] ddr2_addr;
+ wire ddr2_addr_r;
+ wire ddr2_addr_a;
+ wire ddr2_isread;
+ wire [63:0] ddr2_write_data;
+ wire ddr2_write_data_push;
+ wire ddr2_write_data_full;
+ wire [63:0] ddr2_read_data;
+ wire ddr2_read_data_pop;
+ wire ddr2_read_data_empty;
+ wire [1:0] ddr2_read_data_latency;
+
output vga_psave;
output vga_hsync;
output vga_vsync;
.phase_shift( 0 ),
.wait200_init( 26 )
) ddr_ctrl (
- .ddr_a( fpga_0_DDR_SDRAM_DDR_Addr_pin ),
- .ddr_clk( fpga_0_DDR_SDRAM_DDR_Clk_pin ),
- .ddr_clk_n( fpga_0_DDR_SDRAM_DDR_Clk_n_pin ),
- .ddr_ba( fpga_0_DDR_SDRAM_DDR_BankAddr_pin ),
- .ddr_dq( fpga_0_DDR_SDRAM_DDR_DQ ),
- .ddr_dm( fpga_0_DDR_SDRAM_DDR_DM_pin ),
- .ddr_dqs( fpga_0_DDR_SDRAM_DDR_DQS ),
- .ddr_cs_n( fpga_0_DDR_SDRAM_DDR_CS_n_pin ),
- .ddr_ras_n( fpga_0_DDR_SDRAM_DDR_RAS_n_pin ),
- .ddr_cas_n( fpga_0_DDR_SDRAM_DDR_CAS_n_pin ),
- .ddr_we_n( fpga_0_DDR_SDRAM_DDR_WE_n_pin ),
- .ddr_cke( fpga_0_DDR_SDRAM_DDR_CE_pin ),
+ .ddr_a( ddr1_Addr_pin ),
+ .ddr_clk( ddr1_Clk_pin ),
+ .ddr_clk_n( ddr1_Clk_n_pin ),
+ .ddr_ba( ddr1_BankAddr_pin ),
+ .ddr_dq( ddr1_DQ ),
+ .ddr_dm( ddr1_DM_pin ),
+ .ddr_dqs( ddr1_DQS ),
+ .ddr_cs_n( ddr1_CS_n_pin ),
+ .ddr_ras_n( ddr1_RAS_n_pin ),
+ .ddr_cas_n( ddr1_CAS_n_pin ),
+ .ddr_we_n( ddr1_WE_n_pin ),
+ .ddr_cke( ddr1_CE_pin ),
.clk(clk),
.reset(!rst),
- .rot(3'b011),
+ .rot(3'b100),
.fml_wr(!dram_isread && dram_addr_r),
.fml_done(dram_addr_a),
.fml_msk(16'h0)
);
+/*
+ ddr2spa
+ #(
+// fabtech : integer := virtex4;
+// memtech : integer := 0;
+// rskew : integer := 0;
+// hindex : integer := 0;
+// haddr : integer := 0;
+// hmask : integer := 16#f00#;
+// ioaddr : integer := 16#000#;
+// iomask : integer := 16#fff#;
+ .mhz(100),
+ .clkmul(2),
+ .clkdiv(1),
+// col : integer := 9;
+// Mbyte : integer := 16;
+// rstdel : integer := 200;
+ .pwron(1),
+ //oepol : integer := 0;
+ .ddrbits(64),
+ .ahbfreq(50),
+ //readdly : integer := 1; -- 1 added read latency cycle
+ //ddelayb0 : integer := 0; -- Data delay value (0 - 63)
+ //ddelayb1 : integer := 0; -- Data delay value (0 - 63)
+ //ddelayb2 : integer := 0; -- Data delay value (0 - 63)
+ //ddelayb3 : integer := 0; -- Data delay value (0 - 63)
+ //ddelayb4 : integer := 0; -- Data delay value (0 - 63)
+ //ddelayb5 : integer := 0; -- Data delay value (0 - 63)
+ //ddelayb6 : integer := 0; -- Data delay value (0 - 63)
+ //ddelayb7 : integer := 0; -- Data delay value (0 - 63)
+ //numidelctrl : integer := 4;
+ .norefclk(1)
+ //odten : integer := 0
+ ) ddr2_spa (
+ .rst_ddr(sys_rst_pin),
+ .rst_ahb(rst),
+ .clk_ddr(sys_clk_pin),
+ .clk_ahb(clk),
+ //clkref200 : in std_logic;
+ //lock : out std_ulogic; -- DCM locked
+ .clkddro(ddr2_clock),
+ .clkddri(ddr2_clock),
+ //ahbsi : in ahb_slv_in_type;
+ //ahbso : out ahb_slv_out_type;
+ .ddr_clk(ddr2_Clk_pin),
+ .ddr_clkb(ddr2_Clk_n_pin),
+ .ddr_cke(ddr2_CE_pin),
+ .ddr_csb(ddr2_CS_n_pin),
+ .ddr_web(ddr2_WE_n_pin),
+ .ddr_rasb(ddr2_RAS_n_pin),
+ .ddr_casb(ddr2_CAS_n_pin),
+ .ddr_dm(ddr2_DM_pin),
+ .ddr_dqs(ddr2_DQS),
+ .ddr_dqsn(ddr2_DQS_n),
+ .ddr_ad(ddr2_Addr_pin),
+ .ddr_ba(ddr2_BankAddr_pin),
+ .ddr_dq(ddr2_DQ),
+ .ddr_odt(ddr2_ODT_pin)
+ );
+*/
endmodule
set -tmpdir ./tmp
set -xsthdpdir ./xst
+set -xsthdpini main.ini
run
--ifn main.prj -ifmt mixed -ofn main -ofmt NGC -p xc4vfx60-11ff1152 -top main -opt_mode speed -opt_level 1 -iuc NO -lso main.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis YES -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract Yes -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 10000 -bufg 1 -register_duplication YES -register_balancing Yes -slice_packing Yes -optimize_primitives Yes -tristate2logic Yes -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5
+-ifn main.prj -ifmt mixed -ofn main -ofmt NGC -p xc4vfx60-11ff1152 -top main -opt_mode area -opt_level 1 -iuc NO -lso main.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis YES -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract Yes -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 10000 -bufg 1 -register_duplication YES -register_balancing Yes -slice_packing Yes -optimize_primitives Yes -tristate2logic Yes -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5
`define CMD_WIDTH 3
`define A_WIDTH 13
`define BA_WIDTH 2
-`define DQ_WIDTH 16
-`define DQS_WIDTH 2
-`define DM_WIDTH 2
+`define DQ_WIDTH 32
+`define DQS_WIDTH 4
+`define DM_WIDTH 4
`define RFIFO_WIDTH (2 * `DQ_WIDTH )
`define WFIFO_WIDTH (2 * (`DQ_WIDTH + `DM_WIDTH))
pw.println(" , dram_read_data_empty");
pw.println(" , dram_read_data_latency");
}
+ if (module.name.equals("ddr2")) {
+ pw.println(" , ddr2_addr");
+ pw.println(" , ddr2_addr_r");
+ pw.println(" , ddr2_addr_a");
+ pw.println(" , ddr2_isread");
+ pw.println(" , ddr2_write_data");
+ pw.println(" , ddr2_write_data_push");
+ pw.println(" , ddr2_write_data_full");
+ pw.println(" , ddr2_read_data");
+ pw.println(" , ddr2_read_data_pop");
+ pw.println(" , ddr2_read_data_empty");
+ pw.println(" , ddr2_read_data_latency");
+ }
if (module.name.equals("video")) {
pw.println(" , vga_clk");
pw.println(" , vga_psave");
if (external) {
sb.append("input " + name +"_r;\n");
sb.append("output " + name +"_a_;\n");
- sb.append("input ["+(width-1)+":0]" + name +";\n");
+ if (width>0)
+ sb.append("input ["+(width-1)+":0]" + name +";\n");
+ else
+ sb.append("input [0:0]" + name +";\n"); // waste a bit, I guess
} else {
sb.append("wire " + name +"_r;\n");
- sb.append("wire ["+(width-1)+":0]" + name +";\n");
+ if (width>0)
+ sb.append("wire ["+(width-1)+":0]" + name +";\n");
}
if (!hasLatch) {
sb.append("wire " + name +"_a;\n");
if (external) {
sb.append("output " + name +"_r_;\n");
sb.append("input " + name +"_a;\n");
- sb.append("output ["+(width-1)+":0]" + name +"_;\n");
+ if (width>0)
+ sb.append("output ["+(width-1)+":0]" + name +"_;\n");
+ else
+ sb.append("output [0:0]" + name +"_;\n"); // waste a bit, I guess
} else {
sb.append("wire " + name +"_a;\n");
}
if (forceNoLatch || latchDriver!=null) {
sb.append("reg " + name +"_r;\n");
sb.append("initial " + name +"_r = 0;\n");
- sb.append("wire ["+(width-1)+":0]" + name +";\n");
+ if (width>0)
+ sb.append("wire ["+(width-1)+":0]" + name +";\n");
} else if (!hasLatch) {
sb.append("wire " + name +"_r;\n");
- sb.append("wire ["+(width-1)+":0]" + name +";\n");
+ if (width>0)
+ sb.append("wire ["+(width-1)+":0]" + name +";\n");
} else {
sb.append("reg " + name +"_r;\n");
sb.append("initial " + name +"_r = 0;\n");
- sb.append("reg ["+(width-1)+":0]" + name +";\n");
- if (!"/*NORESET*/".equals(resetBehavior))
- sb.append("initial " + name +" = 0;\n");
+ if (width>0) {
+ sb.append("reg ["+(width-1)+":0]" + name +";\n");
+ if (!"/*NORESET*/".equals(resetBehavior))
+ sb.append("initial " + name +" = 0;\n");
+ }
}
return sb.toString();
}
StringBuffer sb = new StringBuffer();
if (external) {
sb.append("assign " + name +"_r_ = " + name + "_r;\n");
- sb.append("assign " + name +"_ = " + name + ";\n");
+ if (width>0)
+ sb.append("assign " + name +"_ = " + name + ";\n");
}
if (driven != null) {
sb.append("assign " + driven.name +"_r = " + name + "_r;\n");
sb.append("assign " + name +"_a = " + driven.name + "_a;\n");
- sb.append("assign " + driven.name +" = " + name + ";\n");
+ if (width>0)
+ sb.append("assign " + driven.name +" = " + name + ";\n");
}
if (driver != null) {
sb.append("assign " + name +"_r = " + driver.name + "_r;\n");
sb.append("assign " + driver.name +"_a = " + name + "_a;\n");
- sb.append("assign " + name +" = " + driver.name + ";\n");
+ if (width>0)
+ sb.append("assign " + name +" = " + driver.name + ";\n");
}
if (latchDriver != null) {
- sb.append("assign " + name +" = " + latchDriver.name + ";\n");
+ if (width>0)
+ sb.append("assign " + name +" = " + latchDriver.name + ";\n");
}
return sb.toString();
}
pw.println(" , vga_g");
pw.println(" , vga_b");
pw.println(" , vga_clkout");
+ pw.println(" , ddr2_addr");
+ pw.println(" , ddr2_addr_r");
+ pw.println(" , ddr2_addr_a");
+ pw.println(" , ddr2_isread");
+ pw.println(" , ddr2_write_data");
+ pw.println(" , ddr2_write_data_push");
+ pw.println(" , ddr2_write_data_full");
+ pw.println(" , ddr2_read_data");
+ pw.println(" , ddr2_read_data_pop");
+ pw.println(" , ddr2_read_data_empty");
+ pw.println(" , ddr2_read_data_latency");
}
pw.println(" );");
pw.println();
pw.println("output dram_addr_r;");
pw.println("input dram_addr_a;");
pw.println("output dram_isread;");
- pw.println("output [31:0] dram_write_data;");
+ pw.println("output [63:0] dram_write_data;");
pw.println("output dram_write_data_push;");
pw.println("input dram_write_data_full;");
- pw.println("input [31:0] dram_read_data;");
+ pw.println("input [63:0] dram_read_data;");
pw.println("output dram_read_data_pop;");
pw.println("input dram_read_data_empty;");
pw.println("input [1:0] dram_read_data_latency;");
+ pw.println("output [31:0] ddr2_addr;");
+ pw.println("output ddr2_addr_r;");
+ pw.println("input ddr2_addr_a;");
+ pw.println("output ddr2_isread;");
+ pw.println("output [63:0] ddr2_write_data;");
+ pw.println("output ddr2_write_data_push;");
+ pw.println("input ddr2_write_data_full;");
+ pw.println("input [63:0] ddr2_read_data;");
+ pw.println("output ddr2_read_data_pop;");
+ pw.println("input ddr2_read_data_empty;");
+ pw.println("input [1:0] ddr2_read_data_latency;");
pw.println("input vga_clk;");
pw.println("output vga_psave;");
pw.println("output vga_hsync;");
projects / fleet.git / commitdiff